Resistive random access memory device

Abstract

A resistive random access memory device 8 has a resistance switching layer 9 and a conductive oxide layer 10 stacked between first and second electrodes 3, 5. The resistance switching layer may be si

Description

Field of the invention The present invention relates to new structures of resistive random access memory devices. The present invention also relates to methods of manufacturing, and operating, the resistive random access memory devices. Background Existing non-volatile memory technologies face scalability challenges, particularly for embedded applications such as embedded Flash. These challenges may be compounded by demands on programming and read speeds, programming endurance and so forth. As the demand grows for memory devices that are faster, smaller, and more energy-efficient, for example for applications in mobile computing and the Internet of Things (loT), the shortcomings of current memory solutions have become evident. Consequently, there has been a drive to create new types of memory technology that can overcome the technological shortfalls of existing memory devices. One emerging technology is Resistive Random Access Memory (RRAM), which appears favourable due to a potential combination of cost-effectiveness, simplicity, and efficiency, especially in embedded memory applications. RRAM has potential as an alternative to traditional embedded Flash memory. The principle of RRAM is to transform typically insulating materials, such as metal or semiconducting oxides, into materials capable of resistance switching. This is achieved by applying voltage pulses that reversibly induce multiple conductance states. In the context of digital memory, one conductance state is used to represent logic state "1" and another conductance state is used to represent the logic state "0". Without wishing to be bound by theory, the present understanding is that the applied voltage pulses generate one or more conductive filaments within the (otherwise dielectric) resistance switching material. Typically a single filament is considered to dominate device behaviour. The conductive filament can be electrically modified to either form a fully connected conductive path between two electrodes or remain only partially connected. The formation of conductive filaments in RRAM devices is influenced by a large number of factors including, but not limited to, defects in the resistance switching oxide material, the generation of oxygen vacancies, and the movement of oxygen ions. In valence change, or intrinsic, RRAM devices, these filaments are understood to be primarily composed of oxygen vacancies. An electroforming process is thought to initiate these filaments, which allows their electronic states to be reversibly changed, in particular to be: • 'reset' to a high resistance state (HRS) or • 'set' to a low resistance state (LRS). This effect is referred to as resistance switching. This process depends on the precise application of specific voltages and currents, and there is a stochastic element which has remained a significant challenge in the prior art to control sufficiently to permit reliable operation across a large enough number of set / reset cycles. One direction of development has been the investigation of oxide bilayers in RRAM devices. Work has been conducted to explore configurations of either two distinct oxides, or the same oxides with different stoichiometries. One strategy involves employing two chemically different oxides with similar resistivity, in which both oxide layers are weakly conductive insulators in their pristine state (i.e. prior to electroforming). Using this approach, a higher contrast in resistance has been reported in Basnet, P. et al. "Asymmetric Resistive Switching of Bilayer HfOx / AIOy and AIOy / HfOx Memristors: The Oxide Layer Characteristics and Performance Optimization for Digital Set and Analog Reset Switching." ACS Appl. Electron. Mater. 5, 1859-1865 (2023), referred to hereinafter as "BASNET". Also using this approach, multiple stable resistance states for muti-bit RRAM cells have been reported by Stathopoulos, S. et al. "Multibit memory operation of metal-oxide bilayer memristors.", Sci Rep 7, 17532 (2017), referred to hereinafter as "STATHOPOULOS". The use of oxides with significantly different pristine resistances has also been explored. It has been considered that the layer with a higher proportion of oxygen relative to other elements provides the site for conductive filament formation. This approach leverages the unique properties of each layer. Lee, M.-J. et al. "A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2Os-x / TaO2-x bilayer structures", Nature Mater 10, 625-630 (2011), referred to hereinafter as "LEE". Integration of a conductive TaOx layer with HfOx-based RRAM devices has been reported in Falcone, D. F. et al. "Physical modeling and design rules of analog Conductive Metal Oxide-HfO2 RRAM.", in 2023 IEEE International Memory Workshop (IMW) 1-4 (2023), doi: 10.1109 / IMW56887.2023.10145936, referred to hereinafter as "FALCONE", and also explored in Stecconi, T. et al. "Filamentary TaOx / HfOz RRAM Devices for Neural Networks Training with Analog In-Memory Computing.", Advanced Electronic Materials 8, 2200448 (2022), referred to hereinafter as "STECCONI". It was reported in FALCONE that incorporating a TaOx layer results in a more gradual resistance transition both for the set and the reset processes. It was postulated that this, in turn, may allow for more non-volatile memory states to be achieved. However, this approach appears to lead to a significantly reduced resistance contrast window for such a device. The authors of the paper propose that the resistance switching takes place within the TaOx layer, rather than the more resistive HfOx layer. Sekar, D. C. et al. "Technology and circuit optimization of resistive RAM for low-power, reproducible operation", in 2014 IEEE International Electron Devices Meeting 28.3.1-28.3.4 (IEEE, San Francisco, CA, USA, 2014), doi: 10.1109 / IEDM.2014.7047125, describes a TiN / conductive TaOx / HfO2 / TiN RRAM with a built-in surge current reduction layer. The authors report that this reduces worst case write current by 33% and fail bit count by 23x compared to conventional RRAM. A circuit to control surge current also described which is reported to improve write current by 40% and endurance by 63%. Switching, endurance and retention data for a 256kb chip with these concepts is presented. Summary According to a first aspect of the invention there is provided a resistive random access memory device including a first electrode and a second electrode. The resistive random access memory device also includes, stacked between the first electrode and the second electrode: a resistance switching layer formed from one or more of silicon oxide, silicon dioxide, silicon nitride, silicon carbide and silicon oxynitride; and a conductive oxide layer. The conductive oxide layer has a resistivity of less than or equal to 5 mQ.cm. The layers of the resistive random access memory device may be deposited in the order (without excluding one or more additional, intermediate layers): first electrode, resistance switching layer, conductive oxide layer, and second electrode. The resistance switching layer may consist of a single listed compound. The resistance switching layer may take the form of a mixture, blend or alloy of two or more of the listed compounds. The first electrode may include two or more layers. One, some or all of the layers of the first electrode may be metallic. The second electrode may include two or more layers. One, some or all of the layers of the second electrode may be metallic. The resistance switching layer may be disposed (or formed) directly on the first electrode. Alternatively, one or more first intermediate layers may separate the resistance switching layer from the first electrode. At least one first intermediate layer may function to modify a chemical potential difference between the first electrode and the resistance switching layer. At least one first intermediate layer may function as a diffusion-barrier layer between the first electrode and the resistance switching layer. At least one first intermediate layer may function to reduce interfacial straining between the first electrode and the resistance switching layer. At least one first intermediate layer may function to reduce lattice mis-match between the first electrode and the resistance switching layer. At least one first intermediate layer may function as an oxygen scavenging layer. The conductive oxide layer may be disposed (or formed) directly on the resistance switching layer. Alternatively, one or more second intermediate layers may separate the conductive oxide layer from the resistance switching layer. Second intermediate layers may be provided to fulfil any functions described in relation to the first intermediate layers, except between the conductive oxide layer and the resistance switching layer instead of between the first electrode and the resistance switching layer. The second electrode may be disposed (or formed) directly on the conductive oxide layer. Alternatively, one or more third intermediate layers may separate the second electrode from the conductive oxide layer. Third intermediate layers may be provided to fulfil any functions described in relation to the first intermediate layers, except between the second electrode and the conductive oxide layer instead of between the first electrode and the resistance switching layer. Alternatively, the layers of the resistive random access memory device may be deposited in the order (without excluding one or more additional, intermediate layers): second electrode, conductive oxide layer, resistance switching layer, and first electrode. The conductive oxide layer may be disposed (or formed) directly on the second electrode. Alternatively, one or more third intermediate layers (already described) may separate the conductive oxide layer from the second electrode. The resistance switching layer may be disposed (or formed) directly on conductive oxide layer. Alternatively, one or more second intermediate layers (already described) may separate the resistance switching layer from the conductive oxide layer. The first electrode may be disposed (or formed) directly on the resistance switching layer. Alternatively, one or more first intermediate layers (already described) may separate the first electrode from the resistance switching layer. The conductive oxide layer may have a resistivity of less than or equal to 4 mQ.cm. The conductive oxide layer may have a resistivity of less than or equal to 3 mQ.cm. The conductive oxide layer may have a resistivity of less than or equal to 2 mQ.cm. The conductive oxide layer may have a resistivity of less than or equal to 1.5 mQ.cm. The conductive oxide layer may have a resistivity of less than or equal to 1.0 mQ.cm, The conductive oxide layer may have a resistivity of less than or equal to 0.5 mQ.cm. The resistivity of the conductive oxide layer may be measured using a four-point probe measurement. The resistivity of the conductive oxide layer may be measured using a reference conductive oxide layer deposited on an insulating substrate under the same conditions and to the same thickness. The conductive oxide layer may take the form of a metal oxide layer. The conductive oxide layer may take the form of a metal oxynitride layer. The conductive oxide layer may function as an oxygen scavenging layer. The resistive random access memory device may be operable using a magnitude of set voltage pulses which is less than or equal to 3 V. Set voltage pulses may be applied to set the resistance switching layer to a low-resistance state. The magnitude of set voltage pulses may be set to equal or exceed a mean set voltage threshold plus three sigma. The magnitude of set voltage pulses may correspond to a voltage value which permits correct switching of all resistive random access memory devices (following quality control checks for fabrication yield) for at least 10,000 switching cycles with a resistance contrast between high and low resistance states of at least 10 times (i.e. the low resistance state is at least 10 times lower than the high resistance state). Quality control checks for fabrication yield may involve identifying and excluding any resistive random access memory devices which are not demonstrating the correct initial behaviours: for example, any resistive random access memory devices which do not exhibit electroforming or which have an initial conductance which is too high (e.g. 10 times a mean conductance of fabricated resistive random access memory devices). Switching cycles for determining whether this condition on the magnitude of set voltage pulses is met may be performed using a write-and-verify approach in which: • A set voltage pulse is applied to the resistive random access memory device in the high resistance state; • The resistance of the resistive random access memory device is measured; • If the resistance corresponds to the low resistance state, the resistive random access memory device has been set; • If the resistance does not correspond to the low resistance state, the preceding steps are repeated, up to a threshold number of pulses, for example between 10 and 20; • If the threshold number of pulses is exceeded without obtaining the low-resistance state, the set operation has failed. The magnitude of set voltage pulses may be less than or equal to 2 V. The magnitude of set voltage pulses may be less than or equal to 1.8 V. A set voltage threshold may correspond to the voltage at which the gradient (or equally derivative) of the current-voltage characteristic sharply rises, leading to a change in the resistance of the resistive random access memory device. The set voltage threshold may change between different resistive random access memory devices, and for each cycle of a given resistive random access memory devices. The set voltage threshold is not equivalent to the magnitude of set voltage pulses used to operate the resistive random access memory device, and may typically be less. The resistive random access memory device may be configured such that for a given resistance cycle (less than 10,000), the probability of the magnitude of the set voltage threshold being less than or equal to the magnitude of set voltage pulses is (1 - 10 6) or greater. The set voltage threshold may be measured by applying a voltage sweep across the resistive random access memory device, and measuring the resulting current through the resistive random access memory device. If the applied voltage equals or exceeds the set voltage threshold, then forward (from 0 V to |Vmax|) and backward (IVmaxl to 0 V) sweeps will exhibit a permanent current-voltage hysteresis. Conversely, if the voltage sweep remains below the set voltage threshold, then the forward and backward sweeps will not demonstrate hysteresis in the current-voltage curve. The sign of the sweep maximum Vmax may be positive or negative. In this way, the set voltage threshold may be measured by performing multiple sweeps and iteratively increasing the sweep maximum Vmax until current-voltage hysteresis is observed. The corresponding sweep maximum Vmax may be taken as the measurement of set voltage threshold. The sweeps may be conducted at a voltage ramp rate corresponding to a controller intended for use to control the resistive random access memory device. The sweeps may be conducted at a voltage ramp rate of 0.1 V.s1. The resistive random access memory device may be operable using a magnitude of reset voltage pulses which is less than or equal to 3 V. Reset voltage pulses may be applied to set the resistance switching layer to the high-resistance state. The magnitude of reset voltage pulses may be set to equal or exceed a mean reset voltage threshold plus three sigma. The magnitude of reset voltage pulses may correspond to a voltage value which permits correct switching of all the resistive random access memory devices (following quality control checks for fabrication yield, as described hereinbefore) for at least 10,000 switching cycles with a resistance contrast between high and low resistance states of at least 10 times (i.e. the high resistance state is at least 10 times larger than the high resistance state). Switching cycles for determining whether this condition on the magnitude of reset voltage pulses is met may be performed using a write-and-verify approach in which: • A reset voltage pulse is applied to the resistive random access memory device in the low resistance state; • The resistance of the resistive random access memory device is measured; • If the resistance corresponds to the high resistance state, the resistive random access memory device has been reset; • If the resistance does not correspond to the high resistance state, the preceding steps are repeated, up to a threshold number of pulses, for example between 10 and 20; • If the threshold number of pulses is exceeded without obtaining the high-resistance state, the reset operation has failed. The magnitude of reset voltage pulses magnitude may be less than or equal to 1.4 V. The magnitude of reset voltage pulses may be less than or equal to 1.2 V. The reset threshold voltage is characterised as the voltage at which the resistance of the resistive random access memory device starting in the low resistance state starts to increase. The reset voltage threshold may change between different resistive random access memory devices, and for each cycle of a given resistive random access memory devices. The reset voltage threshold is not equivalent to the magnitude of reset voltage pulses used to operate the resistive random access memory device, and may typically be less. The resistive random access memory device may be configured such that for a given resistance cycle (less than 10,000), the probability of the magnitude of the reset voltage threshold being less than or equal to the magnitude of set voltage pulses is (1 - 10 6) or greater. The resistive random access memory device may be placed in the low resistance state by applying one or more set voltage pulses. Once in the low-resistance state, the reset threshold voltage may be measured using current-voltage sweeps in the same way as the set threshold voltage, by increasing the maximum sweep voltage Vmax (positive or negative, but opposite to the set voltage Vset) until hysteresis is observed in the current-voltage plot of the sweep. A median switching time for the resistance switching layer to transition from a high resistance state to a low resistance state in response to application of the set threshold voltage may be a fraction of half or less than a median reference switching time which corresponds to a reference device which is identical to the resistance random access memory device except that the conductive oxide layer is replaced with a layer formed from the respective unoxidized material. For example, if the conductive oxide is an oxide of a metal, the reference device will have a layer of that metal having the same thickness as the conductive metal oxide layer of the resistive random access memory device. Of course, it may not be excluded (and is likely) that the reference device may include a thin oxide at the interface with the resistance switching layer when this includes silicon oxide / silicon dioxide. Similarly, thin nitrides / carbides may form at the interface of the reference device metal layer with resistance switching layers in the form of silicon nitride / carbide / oxynitride. The median switching time of the resistance random access memory device may be less than or equal to 1 ps. The median switching time of the resistance random access memory device may be less than or equal to one tenth the median switching time of the reference device. The switching time has a stochastic aspect. Let the set probability, Pset, be the probability of the resistive random access memory device being in the low-resistance state following application between the first and second electrodes of a voltage pulse (which voltage pulse is used to measure the switching time and is not equivalent the set pulses used to operate the device) having a magnitude equal to the set threshold voltage and a duration of Atset. The switching time may be the duration Atset of voltage pulse required so that the complement of the set probability (1-Pset) is less than or equal to 1x10 6. The set probability Pset may be evaluated based on a plurality of repeated set-reset cycles using one or more nominally identical resistance random access memory devices, using the wrlte-and-verify set and reset processes described herein. Nominally identical may mean identical to within manufacturing tolerances. The duration of set voltage pulses may be set to equal or exceed a mean switching time. The duration of set voltage pulses may be set to equal or exceed a mean switching time plus three sigma. The duration of set voltage pulses may be set to permit correct switching of all resistive random access memory devices (following quality control checks for fabrication yield, as described hereinbefore) for at least 10,000 switching cycles with a resistance contrast between high and low resistance states of at least 10 times. Switching cycles for determining whether this condition on the duration of set voltage pulses is met may be performed using the write-and-verify approach described hereinbefore in relation to the magnitude of set voltage pulses. The conductive oxide may have 20% or more excess metal compared to a stoichiometric conductive oxide. The conductive oxide may have 25% or more excess metal compared to a stoichiometric conductive oxide. The conductive oxide may have 30% or more excess metal compared to a stoichiometric conductive oxide. The specified percentages of excess metal may correspond to feedstock ratios during formation of the conductive oxide layer. The specified percentages of excess metal may be determined using laser-ablation mass-spectrometry. The high resistance branch of the current-voltage characteristic of the resistance random access memory device may not exhibit rectifying behaviour. Rectifying behaviour of the high resistance branch may mean that 11(101 * 1 / (-1 / )1- The resistive random access memory device may be considered to not exhibit rectifying behaviour provided that: i / cni-1 / (-^)1 m + ioi The current-voltage characteristic of the resistive random access memory device may not exhibit self-saturation of the current. Self-saturation of the current may mean that the current through the device, I, tends towards a plateau as the magnitude of the voltage V is increased in the polarity corresponding to setting the low-resistance state. Consequently, the resistive random access memory device may require current limitation provided by an external circuit. For example, the resistive random access memory device may be connected in series with a field-effect transistor, and the saturated channel current through the field-effect transistor may be controlled via a voltage applied to a gate of the field-effect transistor. The current-voltage characteristic of the resistive random access memory may exhibit a step change in current in response to a voltage ramp spanning the set threshold voltage. The step change in current may corresponding a shift in the gradient (resistance) of 100 pA.V 1 in 0.1 V or less. The rate of the voltage ramp for measuring the step change may be ~0.1 V.s1. The resistance switching oxide layer may include, or be formed of, Silicon oxide. The resistance switching layer may be formed from SiOx. The value of x may be between 0.5 and 2 (inclusive of endpoints). The resistance switching layer may be formed of Silicon dioxide. The conductive oxide layer may include, or be formed of, one or more of tantalum oxide, hafnium oxide, molybdenum oxide, aluminium oxide, tungsten oxide, gallium oxide, silicon oxide and germanium oxide. The conductive oxide layer may be formed of tantalum oxide. The conductive oxide layer may be formed of a single compound. The conductive oxide may be formed of a mixture, blend or alloy of two or more compounds. The conductive oxide layer may include, or be formed from, an oxynitride corresponding to one, some or all of the specifically listed conductive metal oxides. The resistance switching layer may be formed of silicon oxide, SiOx, and the conductive oxide layer may be formed of tantalum oxide. The resistance switching layer may be formed of silicon oxide, SiOx, and the conductive oxide layer may be formed of hafnium oxide. The resistance switching layer may be formed of silicon oxide, SiOx, and the conductive oxide layer may be formed of molybdenum oxide. The resistance switching layer may be formed of silicon oxide, SiOx, and the conductive oxide layer may be formed of aluminium oxide. The resistance switching layer may be formed of silicon oxide, SiOx, and the conductive oxide layer may be formed of tungsten oxide. The resistance switching layer may be formed of silicon oxide, SiOx, and the conductive oxide layer may be formed of gallium oxide. The resistance switching layer may be formed of silicon oxide, SiOx, and the conductive oxide layer may be formed of silicon oxide. The resistance switching layer may be formed of silicon oxide, SiOx, and the conductive oxide layer may be formed of germanium oxide. The resistance switching layer may be formed of silicon dioxide, and the conductive oxide layer may be formed of tantalum oxide. The resistance switching layer may be formed of silicon dioxide, and the conductive oxide layer may be formed of hafnium oxide. The resistance switching layer may be formed of silicon dioxide, and the conductive oxide layer may be formed of molybdenum oxide. The resistance switching layer may be formed of silicon dioxide, and the conductive oxide layer may be formed of aluminium oxide. The resistance switching layer may be formed of silicon dioxide, and the conductive oxide layer may be formed of tungsten oxide. The resistance switching layer may be formed of silicon dioxide, and the conductive oxide layer may be formed of gallium oxide. The resistance switching layer may be formed of silicon dioxide, and the conductive oxide layer may be formed of silicon oxide. The resistance switching layer may be formed of silicon dioxide, and the conductive oxide layer may be formed of germanium oxide. The resistance switching layer may be formed of silicon nitride, and the conductive oxide layer may be formed of tantalum oxide. The resistance switching layer may be formed of silicon nitride, and the conductive oxide layer may be formed of hafnium oxide. The resistance switching layer may be formed of silicon nitride, and the conductive oxide layer may be formed of molybdenum oxide. The resistance switching layer may be formed of silicon nitride, and the conductive oxide layer may be formed of aluminium oxide. The resistance switching layer may be formed of silicon nitride, and the conductive oxide layer may be formed of tungsten oxide. The resistance switching layer may be formed of silicon nitride, and the conductive oxide layer may be formed of gallium oxide. The resistance switching layer may be formed of silicon nitride, and the conductive oxide layer may be formed of silicon oxide. The resistance switching layer may be formed of silicon nitride, and the conductive oxide layer may be formed of germanium oxide. The resistance switching layer may be formed of silicon carbide, and the conductive oxide layer may be formed of tantalum oxide. The resistance switching layer may be formed of silicon carbide, and the conductive oxide layer may be formed of hafnium oxide. The resistance switching layer may be formed of silicon carbide, and the conductive oxide layer may be formed of molybdenum oxide. The resistance switching layer may be formed of silicon carbide, and the conductive oxide layer may be formed of aluminium oxide. The resistance switching layer may be formed of silicon carbide, and the conductive oxide layer may be formed of tungsten oxide. The resistance switching layer may be formed of silicon carbide, and the conductive oxide layer may be formed of gallium oxide. The resistance switching layer may be formed of silicon carbide, and the conductive oxide layer may be formed of silicon oxide. The resistance switching layer may be formed of silicon carbide, and the conductive oxide layer may be formed of germanium oxide. The resistance switching layer may be formed of silicon oxynitride, and the conductive oxide layer may be formed of tantalum oxide. The resistance switching layer may be formed of silicon oxynitride, and the conductive oxide layer may be formed of hafnium oxide. The resistance switching layer may be formed of silicon oxynitride, and the conductive oxide layer may be formed of molybdenum oxide. The resistance switching layer may be formed of silicon oxynitride, and the conductive oxide layer may be formed of aluminium oxide. The resistance switching layer may be formed of silicon oxynitride, and the conductive oxide layer may be formed of tungsten oxide. The resistance switching layer may be formed of silicon oxynitride, and the conductive oxide layer may be formed of gallium oxide. The resistance switching layer may be formed of silicon oxynitride, and the conductive oxide layer may be formed of silicon oxide. The resistance switching layer may be formed of silicon oxynitride, and the conductive oxide layer may be formed of germanium oxide.> The resistance switching layer may be amorphous. Alternatively, the resistance switching layer may be crystalline or polycrystalline. The conductive oxide layer may be amorphous. Alternatively, the conductive oxide layer may be crystalline or polycrystalline. The resistance switching layer may have a thickness of between 0.5 nm and 20 nm. The thickness range for the resistance switching layer may be inclusive of endpoints. The thickness of the resistance switching layer may be between 1 nm and 10 nm. The thickness of the resistance switching layer may be between 2 and 4 nm. The conductive oxide layer may have a thickness of between 1 nm and 40 nm. The thickness range for the conductive oxide layer may be inclusive of endpoints. The thickness of the conductive oxide layer is between 2 nm and 20 nm. The thickness of the conductive oxide layer is between 3 nm and 10 nm. An oxygen affinity of the conductive oxide layer may be greater than or equal to 2 times an oxygen affinity of the resistance switching layer. The oxygen affinity of the conductive oxide layer may be greater than or equal to 3 times an oxygen affinity of the resistance switching layer. The oxygen affinity of the conductive oxide layer may be greater than or equal to 4 times an oxygen affinity of the resistance switching layer. The oxygen affinity of the conductive oxide layer may be greater than or equal to 5 times an oxygen affinity of the resistance switching layer. The oxygen affinity of the conductive oxide layer may be greater than or equal to 10 times an oxygen affinity of the resistance switching layer. The oxygen affinity of the conductive oxide layer may be greater than or equal to 15 times an oxygen affinity of the resistance switching layer. The oxygen affinity of the conductive oxide layer may be greater than or equal to 20 times an oxygen affinity of the resistance switching layer. An apparatus may include the resistive random access memory device and a controller. The controller may be configured, in response to a command to set the resistive random access memory device, to apply a set voltage pulse between the first and second electrodes such that the first electrode is negative relative to the second electrode. The controller may be configured, in response to a command to reset the resistive random access memory device, to apply a reset voltage pulse between the first and second electrodes such that the first electrode is positive relative to the second electrode. The controller may be configured to use write-and-verify methods to set the resistive random access memory device to a low resistance state. A maximum number of attempts may be 20. The controller may be configured to use write-and-verify methods to reset the resistive random access memory device to a low resistance state. A maximum number of attempts may be 20. In response to a command to read the state of the resistive random access memory device, the controller may apply a voltage having a magnitude which is less than the set threshold (for example one tenth of the magnitude of the set voltage pulse) between the first and second electrodes such that the first electrode negative relative to the second electrode. Alternatively, in response to a command to read the state of the resistive random access memory device, the controller may apply a voltage having a magnitude which is less than the reset threshold (for example one tenth of the magnitude of the reset voltage pulse) between the first and second electrodes such that the first electrode is positive relative to the second electrode. The apparatus may include a number of resistive random access memory devices disposed in an array. Each resistive random access memory device may be as defined hereinbefore. The controller may be configured, for each given resistive random access memory device, in response to a command to set the given resistive random access memory device, to apply a set voltage pulse between the first and second electrodes such that the first electrode is negative relative to the second electrode. The controller may be configured, for each given resistive random access memory device, in response to a command to reset the given resistive random access memory device, to apply a reset voltage pulse between the first and second electrodes such that the first electrode is positive relative to the second electrode. Each of the plurality of resistive random access memory devices may be identical. The controller may be configured to perform the same operations to set, reset and / or read each of the resistive random access memory devices. A memory device may include a number of resistive random access memory devices. A system may include the memory device and a controller. The controller may be configured, for each given resistive random access memory device, in response to a command to set the given resistive random access memory device, to apply a set voltage pulse between the first and second electrodes such that the first electrode Is negative relative to the second electrode. The controller may be configured, for each given resistive random access memory device, in response to a command to reset the given resistive random access memory device, to apply a reset voltage pulse between the first and second electrodes such that the first electrode is positive relative to the second electrode. A neuromorphlc computing device may include a number of resistive random access memory devices, the apparatus, the memory device, or the system. Weights of a neural network may be encoded in the resistances of at least a subset of the resistive random access memory devices. According to a second aspect of the invention there is provided a method of fabricating a resistive random access memory device. The method Includes depositing a first electrode. The method also includes depositing a resistance switching layer over the first electrode. The resistance switching oxide layer is formed from one or more of silicon oxide, silicon dioxide, silicon nitride, silicon carbide and silicon oxynitride. The method also includes depositing a conductive oxide layer over the resistance switching layer. The conductive oxide layer has a resistivity of less than or equal to 5 mfl.cm. The method also includes depositing a second electrode over the conductive oxide layer. The method of the second aspect may include features corresponding to any features of the resistive random access memory device of the first aspect (or an apparatus / memory device / system containing the resistive random access memory device of the first aspect). Definitions applicable to the resistive random access memory device / apparatus / memory device / system of the first aspect (or features thereof) may be equally applicable to the method of the second aspect (or features thereof). According to a third aspect of the invention, there is provided a method of fabricating a resistive random access memory device. The method includes depositing a second electrode. The method also includes depositing a conductive oxide layer over the second electrode. The conductive oxide layer has a resistivity of less than or equal to 5 mQ.cm. The method also includes depositing a resistance switching layer over the conductive oxide layer. The resistance switching oxide layer is formed from one or more of silicon oxide, silicon dioxide, silicon nitride, silicon carbide and silicon oxynitride. The method also includes depositing a first electrode over the resistance switching layer. The method of the third aspect may include features corresponding to any features of the resistive random access memory device of the first aspect (or an apparatus / device / system containing the resistive random access memory device of the first aspect). Definitions applicable to the resistive random access memory device / apparatus / memory device / system of the first aspect (or features thereof) may be equally applicable to the method of the third aspect (or features thereof). The following features are equally applicable to the methods of the second and third aspects. The conductive oxide may have 20% or more excess metal compared to a stoichiometric conductive oxide. The resistance switching layer may take the form of Silicon oxide. The conductive oxide layer may include one or more of tantalum oxide, hafnium oxide, molybdenum oxide, aluminium oxide, tungsten oxide, gallium oxide, silicon oxide and germanium oxide. According to a fourth aspect of the Invention, there is provided a method including use of a number of resistive random access memory devices according to the first aspect, or an the apparatus, memory device or the system including the resistive random access memory devices, to store Information in the resistance states of the number of resistive random access memory devices. The method of the fourth aspect may Include features corresponding to any features of the resistive random access memory device of the first aspect (or an apparatus / device / system containing the resistive random access memory device of the first aspect). Definitions applicable to the resistive random access memory device / apparatus / memory device / system of the first aspect (or features thereof) may be equally applicable to the method of the third aspect (or features thereof). Storing information in the resistance states of the plurality of resistive random access memory devices may include, for each given resistive random access memory device, in response to a command to set the given resistive random access memory device, applying a set voltage pulse between the first and second electrodes such that the first electrode is negative relative to the second electrode. Storing information in the resistance states of the plurality of resistive random access memory devices may include, for each given resistive random access memory device, in response to a command to reset the given resistive random access memory device, applying a reset voltage pulse between the first and second electrodes such that the first electrode is positive relative to the second electrode. Set and reset pulse may have magnitudes determined as described in relation to the first aspect. Brief description of the drawings Certain embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings in which: Figure 1 is a schematic cross-section of a prior art RRAM device; Figure 2 is a schematic cross-section of an improved RRAM device; Figure 3A plots the median I-V characteristic for examples of a prior art RRAM device including a silicon oxide resistance switching layer and a tantalum metal layer; Figure 3B plots the median I-V characteristic for examples of an improved RRAM device including a silicon oxide resistance switching layer and a tantalum oxide conductive oxide layer; Figure 4A plots mean currents following set and reset processes for prior art RRAM devices having the same structure as for Figure 3A; Figure 4B plots mean currents following set and reset processes for improved RRAM devices having the same structure as for Figure 3B; Figure 5A plots maximum currents following reset and minimum currents following set for prior art RRAM devices having the same structure as for Figure 3A; Figure 5B plots maximum currents following reset and minimum currents following set for improved RRAM devices having the same structure as for Figure 3B; Figure 6A plots a section of an I-V characteristic illustrating an undesired set event, for a prior art RRAM device having the same structure as for Figure 3A; Figure 6B plots a section of an I-V characteristic illustrating an undesired set event, for an improved RRAM device having the same structure as for Figure 3B; Figure 7 A plots histograms of voltages for reset and undesired set for prior art RRAM devices having the same structure as for Figure 3A; and Figure 7B plots histograms of voltages for reset and undesired set for prior art RRAM devices having the same structure as for Figure 3B. Detailed Description of Certain Embodiments In the following description, like elements are denoted by like reference numerals. Precise control of resistance switching requires careful consideration of the electrical, chemical, and thermal properties of the layers comprising a RRAM device. The present invention is based, at least in part, on the inventors' insight that employing electrically conductive but thermally insulating oxides, instead of more conventional metallic scavenging layers, offers excellent control in a system using a silicon-based resistance switching layer. For example, a resistance switching layer formed from one or more of silicon oxide, silicon dioxide, silicon nitride, silicon carbide and silicon oxynitride. As shall be explained further hereinafter, the resulting RRAM devices may offer advantages including more consistent switching, lower variability, enhanced resistance contrast, and shorter switching times. There has been previous interest in two-layer metal oxide devices (see for example the "Background" section hereinbefore). However, to the best of the inventors' knowledge a combination of a silicon-based resistance switching layer with a metal oxide layer has not previously been reported. The reason for this is believed to reside in the large disparity in breakdown fields between silicon-based resistance switching layers and metal oxide layers. In particular, it would previously have been considered that a dual-layer structure of a silicon-based resistance switching layer and a conductive oxide layer would undergo at most a single breakdown of the silicon-based resistance switching layer, and that thereafter the behaviour would be dominated by resistance switching of the metal oxide layer. However, the inventors have surprisingly discovered that, with careful control of the metal oxide layer conductance (via the composition thereof), repeated and reliable switching of the silicon-based resistance switching layer is possible. Indeed, as shall be explained hereinafter (see also Figures 4A to 5B), the use of a conductive oxide layer with excess metal as an oxygen scavenging layer can, against expectations, actually improve the switching behaviour when compared to a metal scavenging layer of the type which would previously have been used in a RRAM device having a silicon-based resistance switching layer. As shall be discussed hereinafter with relation to Figures 3A through 7B, experiments using RRAM devices according to the present specification demonstrate that for silicon-based resistance switching layers, replacing prior art metallic scavenging layers with conductive oxides could provide advantages including more consistent switching, reduced cycle-to-cycle variability, and enhancements in both resistance contrast and switching speed. Moreover, in devices according to the present specification, undesirable behaviour in the set and reset processes appears to be suppressed. As discussed hereinafter in relation specifically to Figures 6A through 7B, the combination of a conductive oxide layer with a silicon based resistance switching layer appears to reduce the occurrence of undesired set processes while the devices are biased with a voltage polarity that is intended to only trigger a reset process. Devices according to the present specification also appear to suppress the unwanted occurrence of a reset process while the devices are biased with a voltage polarity that is intended to only trigger the set process. Prior art RRAM device Referring also to Figure 1, a schematic cross-section of a prior art RRAM device 1 including a metal scavenging layer 2 is shown. The prior art RRAM device 1 is an example of a type of metal-insulator-metal (MIM) stack which has been used previously. The prior art RRAM device 1 includes, In order, a first metallic electrode 3, a resistance switching layer 4, the metal scavenging layer 2, and a second metallic electrode 5. The relative thicknesses of layers are not shown to scale in Figure 1. The materials of the first 3 and second 5 electrodes are selected for use with the material of the resistance switching layer 4 on the basis of a variety of factors including (but not limited to) chemical compatibility, work function and so forth. One example of a material useable for the first 3 and second 5 electrodes is titanium nitride TIN. Either or both of the first electrode 3 and the second electrode 5 may be formed as multilayer structures. The prior art RRAM device 1 stack may also incorporate additional layers (not shown) disposed between any of the illustrated layers to perform functions including, but not limited to, adjustment of the local stoichiometry, adjustment of the density of oxygen vacancies, improving interface matching and so forth. The prior art RRAM device 1 can be used to switch between two resistance states, representing logic '1' or logic '0', and it represents a single-bit of data. Typically, a large number prior art RRAM devices 1 are arranged and interconnected in an array to form a memory. This is represented in Figure 1 by the connection of the first electrode 3 to a first metallised layer / trace 6 and the connection of the second electrode 5 to a second metallised layer / trace 7. For example, if the prior art RRAM device 1 was used in a memory array (not shown) configured using conventional 1-Transistor-l-Resistor (1T1R) memory cells, then the first metallised layer / trace 6 would be connected to the drain terminal (not shown) of a corresponding access transistor (not shown), whilst the second metallised layer / trace 7 would be connecting to a bit line (not shown) of the memory array (not shown), or vice versa. The ordering of the resistance switching layer 4 and metal scavenging layer 2 between the first 3 and second 5 electrodes may be reversed. The metal scavenging layer 2 is included between an electrode 3, 5 and the resistance switching layer 4 to facilitate electroforming. However, such metal scavenging layers 2 may not be ideal due to their poor thermal insulation (high thermal conductance), leading to relatively rapid dissipation of thermal energy from Joule heating. Joule heating is believed to be important because a localised elevation of temperature will which promote ion movement (diffusion and drift). While such ion movement is presently understood to be needed to enable both formation of the conductive filament in the set process and also dissolution of the conductive filament in the reset process. Dissipation of the Joule heating means that, in order to allow movement of the comparatively small number of ions required to modulate the filament, excess heating must be supplied to compensate for the dissipation, and therefore this leads to increased programming current and programming time. In this way, the metal scavenging layer 2 may serve to increase an amount of Joule heating required for the set and reset processes. Additionally, too great a contrast in oxygen affinity between the resistance-switching layer 4 and the metal scavenging layer 2 could lead to less controlled oxygen exchange, resulting in more significant variability observed between different set-reset cycles. The prior art RRAM device 1 illustrated in Figure 1 may be implemented using a range of different materials for each layer, including using silicon-based materials for the resistance switching layer 4. The first electrode 3 typically has a thickness in the range between 10 nm and 100 nm (inclusive of end points), for example 60 nm. Similarly, the second electrode 3 typically has a thickness in the range between 10 and 100 nm (inclusive of end points), for example 60 nm. Examples of materials used for the electrodes 3, 4 include, without being limited to, titanium nitride, titanium Ti, tungsten W, gold Au, molybdenum Mo, nickel Ni and so forth. Either or both of the first 3 and second 5 electrodes may take the form of a multilayer-electrode. For example, the first electrode 3 be formed as a stack of two or more layers and / or the second electrode 5 be formed as a stack of two or more layers The resistance switching layer 4 typically has a thickness in the range between 1 nm and 50 nm (inclusive of endpoints), more preferably between 1 nm and 15 nm (inclusive of endpoints), for example 3 nm. Examples of materials which can be used for the resistance switching layer 4 of the prior art RRAM device 1 include silicon oxide SiOx (0.5 <x <2) or other suitable silicon-based dielectrics for memory resistors, such as silicon nitride, silicon carbide, or silicon oxynitride. However, non-silicon-based materials like oxides of hafnium, tantalum, titanium, zinc, aluminium, niobium, among others, may also be utilized. The metallic scavenging layer 2 typically has a thickness in the range between 1 nm and 30 nm (inclusive of endpoints), for example 10 nm. Examples of materials which can be used for the metallic scavenging layer include titanium Ti, Molybdenum Mo, Hafnium Hf, tantalum Ta, tungsten W, and so forth. Improved RRAM device Referring also to Figure 2, a schematic cross-section of an improved resistive random access memory (RRAM) device 8 is shown. The improved RRAM device 8 includes the first metallic electrode 3 and the second metallic electrode 5. A silicon-based resistance switching layer 9 and a conductive oxide layer 10 are stacked between the first 3 and second 5 electrodes. The conductive oxide layer 10 has a resistivity of less than or equal to 5 mQ.cm. Lower resistivity of the conductive oxide layer 10 is preferred, in order to minimise a voltage drop across the conductive oxide layer 10 between a filament formed through the silicon-based resistance switching layer 9 and the second electrode 5. In the example shown in Figure 2, the silicon-based resistance switching layer 9 is disposed between the first electrode 3 and the conductive oxide layer 10. However, the improved RRAM device 8 may instead have the silicon-based resistance switching layer 9 disposed between the second electrode 5 and the conductive oxide layer 10. The improved RRAM device 8 differs from the prior art RRAM device 1 in that the metallic scavenging layer 2 is replaced with the conductive oxide layer 10, and in that the resistance switching layer 4 is specifically a silicon-based resistance switching layer 9. The first 3 and second 5 electrodes may be formed using any materials described in relation to the prior art RRAM device 1, and may be formed to thicknesses within the same ranges. The silicon-based resistance switching layer 9 is formed from one or more of silicon oxide SiOx with 0.5 <x< 2 (or 1 <x <2), silicon dioxide, silicon nitride, silicon carbide and silicon oxynitride. The silicon-based resistance switching layer 9 may consist of a single material, or may take the form of a mixture, blend or alloy of two or more materials. The silicon-based resistance switching layer 9 has a thickness typically in the range between 0.5 nm and 50 nm (inclusive of endpoints), preferably between 0.5 nm and 20 nm (inclusive of endpoints), more preferably between 1 nm and 10 nm (inclusive of endpoints). For practical memory applications, a thickness of between 2 nm and 4 nm has been found to be useful for silicon-based resistance switching layers 9 formed from SiOx. Typically the silicon-based resistance switching layer 9 will have an amorphous structure, though the improved RRAM device 8 could alternatively include a crystalline or poly-crystalline resistance switching layer 9. A large range of conductive oxides may be used, including but not limited to metal oxides, and semiconductor oxides. For example, the conductive oxide layer 10 may be formed from one or more of tantalum oxide, hafnium oxide, molybdenum oxide, aluminium oxide, tungsten oxide, gallium oxide, silicon oxide and germanium oxide. Additionally or alternatively, the conductive oxide layer 10 may include oxynitrides, for example of the metals / semiconductors mentioned hereinbefore. The conductive oxide layer may consist of a single material, or may take the form of a mixture, blend or alloy of two or more materials. The selection of the material(s) (single material, blend, alloy and so forth) to form the conductive oxide layer 10 has two important design rules. The first is required and is that the conductive oxide layer 10 should have a resistivity less than or equal to 5 mQ.cm, preferably less than or equal to 2 mQ.cm or lower. This is in contrast to prior works concerning oxide bi-layers, and follows from the fact that in prior works concerning oxide bi-layers both oxide layers contribute to the resistance switching. In contrast to this, the conductive oxide layer 10 of the present specification is not thought to be directly involved in resistance switching, and is instead intended to serve two primary purposes. Firstly, to reduce the variability arising from oxygen exchange between the resistance switching layer 4 and the metal scavenging layer 2 in prior art RRAM devices 1. Secondly, to produce reduced heat dissipation compared to a metal scavenging layer 2, so as to reduce the power requirements for switching of the silicon-based resistance switching layer 9. The resistivity of the conductive oxide layer 10 may be measured using a four-point probe measurement, by forming long thin layers of varying length, or any other standard technique known for resistivity measurements. The resistivity of the conductive oxide layer 10 may be measured using a reference conductive oxide layer with the same composition, deposited on an insulating substrate under the same conditions and to the same thickness as are intended for use. Control of the resistivity of the conductive oxide layer 10 is obtained by controlling the stoichiometry of the material so that the concentration of oxygen is lower than the stoichiometric ratio. Without wishing to be bound by theory, it is believed that this increases electronic conductivity while retaining thermal insulation. In order to obtain the desired resistivity of less than or equal to 5 mQ.cm, in the improved RRAM device 8 the material of the conductive oxide layer 10 will typically be heavily reduced compared to the ideal stoichiometry of the oxide / oxynitride. For example, the material of the conductive oxide layer 10 may include 20% or more excess metal or semiconductor compared to the stoichiometric conductive oxide / oxynitride. The percentage of excess metal may be controlled by varying feedstock ratios during formation of the conductive oxide layer 10. The composition of a deposited conductive oxide layer 10 may be checked / tested using any suitable technique for compositions analysis such as, for example, SEM / EDX (for a quick check), laser-ablation mass-spectrometry (for more accurate analysis), and so forth. The second design rule is preferable rather than essential, and is that an oxygen affinity of the conductive oxide layer 10 should be greater than an oxygen affinity of the silicon-based resistance switching layer 9. For example, greater than or equal to twice the oxygen affinity of the silicon-based resistance switching layer 9. Whilst the oxygen affinity of the conductive oxide layer 10 is preferably greater than that of the silicon-based resistance switching layer 9, it should still be balanced to avoid uncontrollable oxygen exchange that would worsen the long-term stability of the RRAM device 8. In this way, the conductive oxide layer 10 may function as an oxygen scavenging layer whilst avoiding the issues of reliability experienced with the uncontrolled oxygen exchange experienced with a metal scavenging layer 2. The control of excess metal / semiconductor content which is used to tune resistivity may also be used to influence oxygen affinity. The conductive oxide layer 10 has a thickness typically in the range between 1 nm and 40 nm (inclusive of endpoints). The thickness may be varied depending on the materials used, for example using tantalum oxide a thickness in the range of 5 nm to 30 nm has been found to be useful. Typically the conductive oxide layer 10 will have an amorphous structure, though the improved RRAM device 8 could alternatively use a crystalline or polycrystalline conductive oxide layer 10. The improved RRAM device 8 stack may also incorporate additional layers (not shown) disposed between any of the illustrated layers to perform functions including, but not limited to, adjustment of the local stoichiometry, adjustment of the density of oxygen vacancies, improving interface matching (e.g. reducing interfacial straining and / or lattice mismatches), modifying a chemical potential difference, providing a diffusion barrier, reducing interfacial straining and so forth. Whilst there has been previous interest in two-layer metal oxide devices, see for example BASNET, STATHOPOULOS, LEE, FALCONE and STECCONI, previously the additional oxide layers used have not been passive components (in relation to resistance switching); rather, the second oxide layers previously reported have been included and configured to interact more extensively with the other oxide layer (beyond charge transfer), so as to play an active role in the memory switching process by modifying device resistance or in regulating the operational current by providing a series resistance. Moreover and to the best of the inventors' knowledge a combination of a silicon-based resistance switching layer with a metal oxide layer has not previously been investigated. The reason for this is believed to reside in the disparity in breakdown fields between silicon-based resistance switching layers (for example silicon oxide SiOx) and metal oxide layers. In particular, it would previously have been considered that a dual-layer structure of a silicon-based resistance switching layer and a conductive oxide layer would undergo at most a single breakdown of the silicon-based resistance switching layer, and that thereafter the behaviour would be dominated by resistance switching of the metal oxide layer. In this specification the inventors discuss their surprising results that, by controlling the resistivity of the metal oxide layer 10 (via the composition thereof), repeated and reliable switching of the silicon-based resistance switching layer 9 is possible. Indeed, as shall be explained hereinafter with reference to comparative experimental studies, improved RRAM devices in accordance with the present specification may provide one or more of more reliable set / reset processes, increased switching speeds, improved cycling endurance and enhanced resistance contrast between the low resistance state (LRS) and the high resistance state (HRS). Operation of the resistive random access memory device Referring still to Figure 2, operation of the improved RRAM device 8 to store a logical state shall be described in relation to a schematic control circuit comprising a controller 11, a switch SW, a set bias source VPset and a reset bias source VPreset. The first electrode 3 is coupled to system ground. In order to set the improved RRAM device 8 to the low-resistance state (LRS), the controller 11 sends a control signal 12 which causes the switch SW to temporarily connect the set bias source VPset to the second electrode 5 so as to apply a set voltage pulse exceeding (with high probability as discussed hereinafter), a set threshold voltage Vset between the first 3 and second 5 electrodes. In the example illustrated in Figure 2, the bias source VPset has polarity such that the first electrode 3 is negative relative to the second electrode 5. However, if the order of the silicon-based resistance switching layer 9 and conductive oxide layer 10 were reversed, then the polarity of each of bias sources VPset, VPreset would also be reversed. In order to reset the improved RRAM device 8 to the high-resistance state (HRS), the controller 11 sends a control signal 12 which causes the switch SW to temporarily connect the reset bias source VPreset to the second electrode 5 so as to apply a voltage pulse exceeding (with high probability as discussed hereinafter) a reset threshold voltage Vreset between the first 3 and second 5 electrodes. In the example illustrated in Figure 2, the bias source VPreset has polarity such that the first electrode 3 is positive relative to the second electrode 5. Again, if the order of the silicon-based resistance switching layer 9 and conductive oxide layer 10 were reversed, then the polarity of each of bias sources VPset, VPreset would also be reversed. Compared to previously studied bi-layer oxide RRAM devices (see for example STATHOPOULOS), the polarities of set and reset operations using the improved RRAM device 8 are reversed. In order to read the state of the improved RRAM device 8, the controller 11 applies a voltage Vread which is less (with high probability, as discussed hereinafter) than a set threshold Vset between the first 3 and second electrodes 5, with a polarity such that the first electrode 3 is negative relative to the second electrode 5. Alternatively, the controller 11 may apply a voltage which is less (with high probability, as discussed hereinafter) than a reset threshold Vreset between the first 3 and second 5 electrodes such that the first electrode 3 is positive relative to the second electrode 5. In other words, the read operation should not cause a change between the HRS and LRS. The controller 11 measures the current Iread which flows in response to the read voltage Vread, and from ratio Vread / Iread it is determined whether the improved RRAM device 8 is in the HRS or the LRS. The mapping of HRS and LRS to binary 1 and 0 is not critical, for example the HRS may represent 1 and the LRS 0, or vice versa. In some devices the improved RRAM device 8 may be controlled between three or more distinct resistances states, but unless clearly specified to the contrary, a two-state system (HRS and LRS) may be presumed in the discussions hereinafter. A single RRAM device is not particularly useful, and in general a larger number of improved RRAM devices 8 may be disposed in an array (not shown), with each providing one "cell" of a memory. In this case, each improved RRAM device 8 will be coupled to the control 11, the set bias source VPset and the reset bias source VP^set to allow each Improved RRAM device 8 to be individually addressed to be set, reset or read out as required. For example, each improved RRAM device 8 may be controlled by a corresponding cell of a conventional 1-Transistor-l-Reslstor (1T1R) memory array (not shown), in which case the controller 11 would encompass the transistors, addressing lines and other components for implementing and controlling the 1T1R memory array. Comparative study of metal scavenging layers vs conductive oxide layers Referring also to Figure 3A and 3B, median current-voltage characteristics are shown for prior art RRAM devices 1 using a metal scavenging layer 2 and for improved RRAM devices 8 using a conductive oxide layer 10. The experimental data shown in Figure 3A were obtained as median current-voltage characteristics obtained by testing 50 prior art RRAM devices 1. Testing of each prior art RRAM device 1 was repeated 5 times. Each prior art RRAM device 1 was produced with: • a 60 nm thick first electrode 3 formed of titanium nitride TiN; • a 3 nm thick resistance switching layer 4 formed of silicon oxide SiOx; • a 4 nm thick metal scavenging layer 2 formed of tantalum Ta; and • a 60 nm thick first electrode 3 formed of titanium nitride TiN. The experimental data shown in Figure 3B were obtained as median current-voltage characteristics obtained by testing 50 improved art RRAM devices 8. Testing of each improved art RRAM device 1 was repeated 5 times. Each Improved art RRAM device 8 was produced with: • a 60 nm thick first electrode 3 formed of titanium nitride TiN; • a 3 nm thick silicon-based resistance switching layer 9 formed of silicon oxide SiOx; • a 30 nm thick conductive oxide layer 10 formed of Tantalum oxide TaOx; and • a 60 nm thick first electrode 3 formed of titanium nitride TiN. The Tantalum oxide TaOx conductive oxide layers 10 of the improved RRAM devices 8 produced and tested for the data shown in Figure 3B have a resistivity of less than 1 mQ.cm. For both Figure 3A and 3B, data were obtained using a sweep rate of ~0.1 V.s1. Arrows indicate the sweep direction relative to the plotted data. For both Figure 3A and 3B, the RRAM device 1, 8 under test was connected in series with the drain of a field-effect transistor (FET). The gate voltage of the FET was controlled to limit the currents passing through the RRAM device 1, 8. External limitation of currents was used because, as described hereinafter, the improved art RRAM devices 8 do not exhibit self-limitation of the current in the low-resistance state. The set voltage threshold Vset corresponds to the voltage at which the gradient of the current-voltage (I-V) characteristic sharply rises. The set voltage threshold Vset has a stochastic element, and is a function of, amongst other factors the materials, the structure and the history of an RRAM device 1, 8. In general, the set voltage threshold Vset will vary both between nominally identical (to within fabrication tolerances) RRAM devices 1, 8, and also between different switching cycles of setting and resetting for each individual RRAM device 1, 8. Consequently, discussions of the set voltage threshold Vset shall refer to statistical measures thereof. The determination of an appropriate magnitude VPset for set pulses, taking into consideration the variability of the set voltage threshold Vset, is discussed hereinafter For the prior art RRAM devices 1 (Figure 3A) the median set voltage threshold Vset is about 0.5 V, and for the improved RRAM device 1 (Figure 3B) the median set voltage threshold Vset is about 0.6 V. However, the transition may be observed to be considerably sharper (on average) for the improved RRAM device 1, and a step change in current I is observed. An I-V characteristic of a RRAM device 1, 8 may be considered to represent a "step change" if the gradient 5IsteP / 5VsteP exhibits a jump of 100 pA.V1 within a 0.1 V range at a predetermined ramp rate (for example ~0.1 V.s1). Although the set voltage threshold Vset is clearly defined in an I-V characteristic, and may be simply read by inspection for the improved RRAM device 1, for completeness a method of defining and measuring the set voltage threshold Vset is described. The set voltage threshold Vset may be measured by applying voltage sweeps across a RRAM device 1, 8 to an amplitude Vmax, and measuring the resulting current to obtain I-V characteristics as presented in Figures 3A and 3B. If the applied voltage equals or exceeds the set voltage threshold Vset, then forward (from 0 V to | Vmax|) and backward (IVmaxl to 0 V) sweeps will exhibit a permanent current-voltage hysteresis (as shown in both Figures 3A and 3B). Conversely, if the voltage sweep remains below the set voltage threshold, i.e. |Vmax| <Vset, then the forward and backward sweeps will not demonstrate hysteresis in the current-voltage curve. In other words, when the voltage is ramped back down to 0 V, the current will follow the same path on the I-V plot as it did when the voltage was ramped up to | Vmax\. The sign of the sweep upper bound Vmax may be positive or negative depending on the polarity for the set operation. In this way, the set voltage threshold Vset can be determined by performing multiple sweeps and iteratively increasing the sweep upper bound |l / max| until I-V hysteresis is observed. The corresponding sweep upper bound | Vmaxl for which I-V hysteresis is first observed corresponds to the set voltage threshold Vset. The sweeps may be conducted at a voltage ramp rate corresponding to a controller 11 intended for use to control the RRAM device 1, 8. Alternatively, the sweeps may be conducted at a predetermined reference voltage ramp rate, for example ~0.1 V.s1. The reset threshold voltage Vreset Is characterised as the voltage at which the resistance of a RRAM device 1, 8 starts to increase. On the I-V characteristics, this shows as a point where the current I stops increasing with increasing amplitude of applied voltage V, and instead starts to decrease. The reset voltage threshold Vreset has a stochastic element, and Is a function of, amongst other factors the materials, the structure and the history of an RRAM device 1, 8. In general, the reset voltage threshold Vreset will vary both between nominally identical (to within fabrication tolerances) RRAM devices 1, 8, and also between different switching cycles of setting and resetting for each individual RRAM device 1, 8. Consequently, discussions of the reset voltage threshold Vreset shall refer to statistical measures thereof. The determination of an appropriate magnitude VPredet for reset pulses, taking into consideration the variability of the set voltage threshold Vset, is discussed hereinafter For both the prior art RRAM device 1 (Figure 3A) and for the improved RRAM device 8 (Figure 3B) the median reset voltage thresholds Vset are similar at about -0.6 V. However, for the improved RRAM device 8 this occurs at a reduced current I compared to the prior art RRAM device 1. Without wishing to be bound by theory, it is believed that the reset process is driven by Joule heating in the conductive filament of the LRS, which is speculated to thermally activate diffusion processes which partially or fully "heal" the conductive filament. Again without wishing to be bound by theory, the reduced reset current Ireset for the improved RRAM device 8 is believed to arise from a lower thermal conductance of the conductive oxide layer 10 compared to the metal scavenging layer 2, keeping heat localised so that a critical temperature to activate the reset process may be reached at a lower level of input energy from Joule heating. A reduced power requirement for operating a memory formed using Improved RRAM devices 8 is evidently beneficial. The reset threshold voltage Vreset may be measured in a similar way to the set voltage threshold Vset, using iterative sweeps to an upper bound Vmax which is positive or negative depending on the polarity for the reset operation, until I-V hysteresis Is observed. The relatively low set voltage threshold Vset and reset voltage threshold Vreset for the improved RRAM device 1 allows setting operating magnitudes VPset, VPreset of 1.8 V and -1.4 V respectively for set and reset pulses used to operate the experimentally characterised improved RRAM devices 8. The operating magnitude for switching pulses are not based on median values, since this would only switch 50% of devices. Instead, the operating magnitudes VPset, VPreset for set and reset pulses should be set to ensure that the probability of the set / reset pulse exceeding the respective threshold Vset, Vrest is as high as possible. Setting the operating magnitudes VPset, VPreset arbitrarily high is not viable though, since excessive potentials may lead to undesired reset under polarity intended for setting and / or undesired set under polarity intended for resetting. Such factors are discussed hereinafter in relation to Figure 6A through 7B. For example, the operating magnitudes VPset, VPreset may each be set to ensure that the probability of exceeding the respective threshold Vset, Vreset for a given device and cycle (below the 10,000th cycle) Is (1 - 10-6) or greater. This may be determined using measurements of the thresholds Vset and Vreset across a large number of improved RRAM devices 8 and cycles. Whilst laborious, this is readily automated so as to not present an undue burden. An alternative which is more closely related to typical operating conditions is to set the magnitudes VPset, VP of set and reset voltage pulses to correspond to voltage values which permit correct switching of all the improved RRAM devices 8 (following quality control checks for fabrication yield) for at least 10,000 switching cycles with a resistance contrast between high and low resistance states of at least 10 times (i.e. the low resistance state is at least 10 times lower than the high resistance state). Quality control checks for fabrication yield involve identifying and excluding any improved RRAM device(s) 8 which are not demonstrating the correct initial behaviours: for example, any improved RRAM device(s) 8 which do not exhibit electroforming or which have an initial conductance which is too high (e.g. 10 times the mean). One example of switching cycles for determining whether this condition on the magnitudes of set / reset voltage pulses is met may be performed using a write-and-verify approach in which a set operation is applied by: a) Applying a set voltage pulse to the improved RRAM device 8 in the high resistance state; b) Measuring the resistance of the improved RRAM device 8. The read potential Vmad magnitude is controlled to be less than lower bounds of the distributions of switching threshold Vset, Vreset f c) If the resistance corresponds to the low resistance state, the improved RRAM device 8 has been set, and a reset operation is then applied to complete the present switching cycle; d) If the resistance does not correspond to the low resistance state, the preceding steps a) to c) are repeated, up to a threshold number of pulses, for example between 10 and 20; e) If the threshold number of pulses is exceeded without obtaining the low-resistance state, the set operation has failed and that improved RRAM device 8 is no longer usable. Similarly, a reset operation for determining whether the condition on the magnitudes of set / reset voltage pulses is met may be performed by: f) Applying a reset voltage pulse to the improved RRAM device 8 in the low resistance state; g) Measuring the resistance of the improved RRAM device 8; h) If the resistance corresponds to the high resistance state, the improved RRAM device 8 has been reset, and the next switching cycle is then started by applying the set operation; i) If the resistance does not correspond to the high resistance state, the preceding steps are repeated, up to a threshold number of pulses, for example between 10 and 20. The threshold number of pulses need not be the same for set and reset operations; j) If the threshold number of pulses is exceeded without obtaining the high-resistance state, the reset operation has failed and the improved RRAM device 8 is no longer usable. Whilst this process will require large numbers of switching cycles, and a reasonable number of improved RRAM devices 8 to be tested, this is not unduly burdensome due to the ease of automating the measurements. For example, this discussion concerns improved RRAM devices 8 which in the primary use case are formed into memory arrays for switching at high bandwidths. Thus, the measurements necessary to determine suitable operating voltages VPset, VP reset may be conducted rapidly and using only the standard operations of a RRAM memory controller. For example, this type of data is presented hereinafter in relation to Figures 4A through 5B. In practical devices the switching cycle preferably utilises some form of write-and-verify process for both set and reset pulses. As explained hereinbefore, write-and-verify refers to reading the resistance of the improved RRAM device 8 after each set or reset pulse to verify whether the device 8 is in the intended resistance state. If it is not, then a further set or reset pulse is applied and the resistance re-measured. This cycle may be repeated until the intended resistance state is obtained, or until a threshold maximum number of pulses have been applied, for example 10 or 20. These operating voltages VPset, VPreset compare favourably with previous studies using bi-layer oxide structures and permit integration in small processing nodes (for example <22 nm), for example in contrast to set and reset pulses of 6 V and 4.5 V respectively reported in LEE. An aspect of RRAM device 1, 8 which is less frequently discussed is the phenomena of "undesired" sets. The voltage applied to reset to the high resistance state needs to exceed the reset voltage threshold Vreset to cause a sufficient current Ireset to flow to thermally activate the physical mechanisms that cause the reset. However, at too large an amplitude of applied voltage Vund, the resistance switching layer 4, 9 may undergo breakdown in the reverse direction, generating a new conductive filament instead. This is referred to as an "undesired" set, and would leave the affected RRAM device 1, 8 in the opposite resistance state to what is intended. All processes of set, reset and undesired set in a RRAM device have a stochastic element, so that the distribution widths can be equally Important as the median (or mode) average values describing the relative location of the distribution (or peak thereof). However, because the reset and undesired set processes occur for the same polarity, reliable operation requires that the distribution of reset voltages Vreset be clearly separated from the distribution of undesired set voltages Vund, so that an operating voltage VPreset for reset pulses may be selected for which there is a sufficiently high probability of triggering the reset process whilst the probability of an undesired set remains acceptably low. As shall be explained hereinafter with reference to Figures 4A through 5B, the improved RRAM device 8 has a greatly improved cycling endurance compared to the prior art RRAM device 1, and this is believed to result, at least in part, from reduced overlap between the distributions of reset voltages V^set and undesired set voltages Vund. Before discussing cycling endurance, certain other features of I-V characteristics of improved RRAM devices 8 shall be discussed. It may be observed that the high resistance branch of the I-V characteristic of the improved RRAM 8 does not exhibit rectifying behaviour (or equivalently, exhibits "nonrectifying" behaviour). Rectifying behaviour of the high resistance branch mean that |I(I / )| * \I{-V)|. A RRAM device may be considered as exhibiting non-rectifying behaviour, provided that the condition is met: mi-i / mi mi + i / mi < 0.01 (1) The non-rectifying behaviour may only apply to a central range of voltages, for example between -0.5 V to 0.5 V. Without wishing to be bound by theory, the nonrectifying behaviour of the improved RRAM device 8 is considered to be representative of the more passive role of the conductive oxide layer 10 In the silicon-based Improved RRAM device 8, as compared to prior art bi-layer oxide devices (not using silicon) in which both oxide layers actively participate in the resistance switching mechanism and which often exhibit pronounced rectifying behaviour. As described hereinbefore, the median I-V characteristic of the improved RRAM devices 8 shown in Figure 3B corresponds to the improved RRAM device 8 connected to the drain of the external FET. The effects of any external FET (or similar current limiting external circuit), and any rectifying behaviour thereof (typically small or negligible for a FET), should be taken into account when evaluating the extent or otherwise of rectifying behaviour of an RRAM device. Another difference compared to many bi-layer oxide devices reported previously may be observed from the I-V characteristic (Figure 3B) of the improved RRAM device 8. Namely that the I-V characteristic of the resistive random access memory device does not exhibit self-saturation of the I{V). Self-saturation of the current I(V) refers to the current I(V) through a RRAM device tending towards a current I(V) plateau as the magnitude of the voltage V is increased in the polarity corresponding to setting the low-resistance state. Again, the median I-V characteristic of the improved RRAM devices 8 shown in Figure 3B corresponds to the improved RRAM device 8 connected to the drain of the external FET for the purpose of limiting the current through the improved RRAM device 8. Thus the apparent plateau in Figure 3B results from the external current limiting FET, which was included in the measurement circuitry precisely because the current I through the improved RRAM devices 8 is not self-limiting (and some control of runaway current is necessary to prevent excessive energy discharge which could permanently damage the RRAM device). Prior art dual-oxide layer devices have instead relied on self-saturation by the RRAM device itself. The contrast of this to the improved RRAM devices 8 which use external current I control is further evidence that such devices do not operate in the same way as the improved RRAM devices 8 of the present specification. Another benefit observed for the improved RRAM device 8 compared to the prior art RRAM device 1 was a reduction of the switching time for the resistance switching layer 4, 9 to transition from the high resistance state (HRS) to the low resistance state (LRS) in response to application of the set threshold voltage Vset. The improved RRAM devices 8 were switchable using set and reset pulses of shorter duration than the prior art RRAM devices 1. For example, set and result pulses of 1 ps duration were used to obtain the data for improved RRAM devices shown in Figures 4B and 5B hereinafter, whereas set and reset pulse of 10 ps duration were used for the prior art RRAM device 1 data shown in Figures 4A and 5B hereinafter. The switching time also has a stochastic element, and is not the same as a duration of a set / reset pulse. For the purposes of discussion, a set probability may be defined, Pset, to be the probability of a RRAM device 1, 8 being In the LRS following application between the first 3 and second 5 electrodes of a set pulse having a magnitude equal to the VPset and a duration of Atset. The switching time may be the duration Atset required so that the complement of the set probability (1-Pset) is less than or equal to a threshold, for example lx 10-6 or lower. The duration of Atset is not necessarily equivalent to, and ideally is significantly shorter than, the duration of set pulses used to operate the RRAM device 1, 8.Suitable durations of set and reset pulses may be determined so as to exceed with high probability the distribution of switching times (and set and reset pulses may have different durations). For example, using the same conditions described hereinbefore In relation to the magnitudes VPset, VPreset of set and reset pulses. For instance, after optimising the magnitudes VPset, VPreset of set and reset pulses, the durations of each pulse type may be progressively reduced until they are as short as possible whilst retaining correct switching of all the improved RRAM devices 8 (following quality control checks for fabrication yield as described hereinbefore) over at least 10,000 switching cycles (including write-and-verify) with a resistance contrast between high and low resistance states of at least 10 times. In the general case, the switching time, for the sake of definiteness the median switching time, of an improved RRAM device 8 including a conductive oxide layer 10 formed of a metal / semiconductor is expected to be less than or equal to half that of a reference device (e.g. prior art RRAM device 1). Without wishing to be bound by theory, this is believed to result from the thermal energy from Joule heating being confined within the switching site for longer as a result of the relatively lower thermal conductance of the conductive oxide layer 10. The reference device should be Identical to the improved RRAM device 8, except that the conductive oxide layer is replaced with a layer formed from the respective unoxidized metal / semiconductor. In other words, compared to a prior art RRAM device 1 having a metal scavenging layer 2 formed of the same metal or semiconductor used in the oxide or oxynitride of the improved RRAM device 8. Preferably, the median switching time of the improved RRAM device 8 is less than or equal to 1 ps, and more preferably the median switching time of the improved RRAM device 8 is less than or equal to one tenth the switching time of the reference device. For example, if the conductive oxide layer 10 of the improved RRAM device 8 is an oxide of a metal, the reference device (prior art RRAM device 1) will have a metal scavenging layer 2 formed of that metal and having the same thickness as the conductive metal oxide layer 10 of the improved RRAM device 8. Of course, it is not excluded (and likely) that the reference device (prior art RRAM device 1) may include a thin oxide at the interface with the resistance switching layer 4 when this includes silicon oxide / dioxide. Similarly, thin nitrides / carbides may form at the interface of the reference device metal layer with resistance switching layers in the form of silicon nitride / carbide / oxynitride. Cycling endurance testing Referring also to Figures 4A to 5B, results of endurance testing are shown for prior art RRAM devices 1 and improved RRAM devices 8 having the same structure as those described in relation to Figures 3A and 3B respectively. Figures 4A and 5A show results for endurance testing of 16 prior art RRAM devices 1. The set was triggered by applying one or more set pulses of 10 ps duration at +1.8 V, and the reset was triggered by applying one or more result pulses of 10 ps duration at -1.2 V. Both set and reset operations used write-and-verify methods as described hereinbefore. The read potential was -0.2 V. Standard errors calculated for the currents I following reset operations 13 are indicated by the solid lines, and standard errors calculated for the currents following set operations 14 are indicated by the dashed lines. Figure 5A shows a comparison, for the prior art RRAM devices 1, between the maximum current following a reset operation 17 (solid line) and the minimum current following a set operation 18 (dashed line). Figures 4B and 5B show results for endurance testing of 14 improved RRAM devices 8. The set was triggered by applying one or more set pulses of 1 ps duration at +1.8 V, and the reset was triggered by applying one or more result pulses of 1 ps duration at -1.4 V. Both set and reset operations used write-and-verify methods as described hereinbefore. The read potential was -0.2 V. The faster switching of the improved RRAM devices 8 permitted set and reset pulses to be set an order or magnitude shorter compared to the prior art RRAM devices 1. For the improved RRAM devices 8 tested, the numbers of set / reset pulses needed to obtain the desired resistance state rarely exceeded 1 or 2 below 10,000 cycles. Figure 4B shows, for the improved RRAM devices 8, the mean current following a reset operation 15 (solid circles) and the mean current following a set pulse 16. Standard errors calculated for the currents following reset operations 15 are indicated by the solid lines, and standard errors calculated for the currents following set operations 16 are indicated by the dashed lines. Figure 5B shows a comparison, for the prior art RRAM devices 1, between the maximum current following a reset operation 19 (solid line) and the minimum current following a set operation 20 (dashed line). Comparing Figures 4A and 4B, it may be observed that the resistance contrast, namely the difference in resistance between the HRS following a reset pulse and a LRS following a set pulse, is increased in the improved RRAM device 8 using conductive oxide layer 10 when compared to the prior art RRAM device 1 using a metal scavenging layer 2. The variability of resistance states may also be observed to have been reduced for the improved RRAM device 8. Referring in particular to Figures 5A and 5B, once the distributions of resistance after a set / reset operation start to overlap, i.e. once the minimum resistance after a reset operation crosses a maximum resistance after a set process, it is no longer possible to refer to well-defined LRS and HRS. This may be observed to occur after a relatively small number of cycles, fewer than ten, for the prior art RRAM devices 1 (Figure 5A). However, for the improved RRAM devices 8, a collapse of resistance contrast was not observed to occur until over 10,000 cycles. As shown in Figures 4A through 5B, the improved RRAM devices 8 represent an improvement of multiple orders of magnitude in the endurance of a RRAM device 8 incorporating a silicon-based resistance switching layer 9. Not only is this compatible with common CMOS material systems, but the set and reset pulses at 1.8 and -1.4 V respectively are also compatible for ready integration with smaller (feature size) CMOS processing nodes. Without wishing to be bound by theory, the greatly improved consistency and endurance cycling of the improved RRAM devices 8 is currently attributed to an observed increased in the polarity dependence for the set and reset processes compared to prior art devices 1 with conventional metal scavenging layers 2. For example, the improved RRAM devices 8 devices were not observed to exhibit distributions of unexpected set and reset voltages (when a voltage of the opposite polarity, from what would typically Induce a set / reset process was applied) which overlapped with the distributions of the intended reset and set voltages. Referring also to Figure 6A and 6B, median I-V characteristics for resets interrupted by undesired sets are respectively shown for prior art RRAM devices 1 and improved RRAM devices 8 having the same structure as those described in relation to Figures 3A and 3B. The measurements providing the data shown in Figures 6A and 6B was obtained by testing 50 prior art RRAM devices 1 and 50 improved RRAM devices 8 to destruction. Specifically, for the destructive testing cycle each device 1, 8 was set by ramping up the voltage until the set voltage Vset was observed. Subsequently, the voltage polarity was reversed to initiate the reset process. However, the magnitude of the voltage applied continued to be ramped until undesired set was observed. In these experiments, undesired set was accompanied by current runaway, leading to damage rendering each device no longer usable. Figure 6A shows the median I-V characteristic of the 50 prior art RRAM devices 1 tested in this way, and Figure 6B shows the median I-V characteristic of the 50 improved art RRAM devices 8 tested. The reset distribution is defined by the onset of the reset process at the reset threshold voltage Vreset (for that device and cycle). However, the reset process Is not immediate, and it is instead progressive. To fully reset RRAM devices 1, 8, it is necessary to further stress them by applying a lower voltage (a higher negative voltage In this example) than the reset voltage threshold Vreset. For example, the operating voltage VPreset for reset pulses is set to a magnitude exceeding that of the reset voltage threshold Vreset as described hereinbefore. As described hereinbefore, the magnitude of reset pulses is also set to encompass almost the entire distribution of reset threshold voltages Vreset. However, there is a limitation, defined by the distribution of undesired set voltages Vund. The undesired set voltages Vund represent the voltages at which, after having transitioned from the LRS to the HRS, the current starts to rise again (HRS to LRS transition). An undesired set transition causes the resistance state of the device to differ from the state which was intended to be set, and forces careful tuning of the operating voltage VPreset of reset pulses to maximise the probability of completing the reset process to the HRS without interruption by an unintended set. Of course, the extent to which this is possible depends on the degree of separation between the distribution of reset voltages Vreset and the distribution of undesired set voltages Vund, for example as represented by the relative peak positions. Referring also to Figure 7A, histograms are shown for the reset voltages Vreset and undesired set voltages Vund, obtained from one destructive switching cycle each (as described in relation to Figures 6A and 6B) of 50 prior art RRAM devices 1 having the same structure as those described in relation to Figure 3A. For the distributions shown in Figure 7A, the mean reset voltage Vreset is -0.699 V and the standard error was 0.092 V, whilst the mean undesired set voltage Vund is -1.300 V with standard error 0.106 V. Referring also to Figure 7B, histograms are shown for the reset voltages Vreset and undesired set voltages Vund, obtained from one destructive switching cycle each (as described in relation to Figures 6A and 6B) of 50 improved RRAM devices 8 having the same structure as those described in relation to Figure 3B. For the distributions shown in Figure 7B, the mean reset voltage Vreset is -0.739 V and the standard error was 0.062 V, whilst the mean undesired set voltage Vund is -1.609 V with standard error 0.202 V. Overall, in Figure 7A the separation of mean reset Vreset and undesired set Vund voltages is 0.601 V, whilst in Figure 7B the separation Is Increased to 0.870 V, an increase of around 300 mV in the "window" for the magnitude VPreset of reset pulses. Whilst experimental data has been presented for examples of improved RRAM devices 8 fabricated using tantalum oxide, the performance of improved RRAM devices 8 using other materials (for example as described herein) for the conductive oxide layer 10 are expected to behave similarly provided that the resistivity is maintained to the specified range at or below 5 mQ.cm. This is because, as explained herein, the conductive oxide layer 10 of the improved RRAM devices 8 does not actively participate in the resistance switching mechanism of the silicon-based resistance switching layer 9. This is in contrast to previous dual-layer oxide devices in which both layers Interact for resistance switching, see for example BASNET, STATHOPOULOS, LEE, FALCONE, STECCONI and SEKAR. Applications of the improved RRAM devices The improved RRAM devices 8 may be used to replace other memory cell elements. For example, any application in which non-volatile memory such is presently used. Depending on the switching speeds achieved, the improved RRAM devices 8 could for some applications compete with volatile memory, which could be advantageous in some fields. For example, a device using a memory based on the improved RRAM devices 8 might be easier to rapidly suspend (switch off or sleep mode) and then resume. The improved RRAM devices 8 may also be used to construct an analogue computing architecture. For example, an Improved RRAM device 8 could be set to the LRS, then variable length and / or magnitude reset pulses could be applied to allow the reset process be competed to different extents to provide a range of resistance values. Additionally or alternatively, an external current limitation circuit may be used to curtail filament formation during the set process. The resistance following a set operation may be reliably controlled in dependence on the current I limitation during that set operation. This may be used control the improved RRAM device 8 to more than two resistance states, either separately from or in combination with truncation of the reset process. Alternatively, a number of improved RRAM devices 8 may be connected in series and / or In a network mixing series and parallel connections, and operated between binary high and low resistance states. With the inclusion of additional switching transistors to allow isolating and setting / resetting each improved RRAM device 8 individually, the overall effective resistance of the series / network of improved RRAM devices 8 could then be controlled by setting different permutations of the improved RRAM devices 8 to the HRS and LRS. This approach suffers from a reduced density compared to directing setting individual improved RRAM devices 8 to three of more resistances states. However, this approach may be useful If it is desired to maximum endurance (number of cycles before resistance contrast Is lost). Modifications It will be appreciated that various modifications may be made to the embodiments hereinbefore described. Such modifications may involve equivalent and other features which are already known in the design, configuration, manufacture and / or use of resistive random access memory device and memories formed thereof, and which may be used Instead of or in addition to features already described herein. Features of one embodiment may be replaced or supplemented by features of another embodiment. As described hereinbefore, the improved RRAM device 8 stack may also incorporate additional layers (not shown) disposed between any of the illustrated layers 3, 5, 6, 7, 8, 9, 10. For example one or more first intermediate layers may separate the silicon-based resistance switching layer 9 from the first electrode 3, each first intermediate layer selected to perform one of more functions of adjustment of the local stoichiometry, adjustment of the density of oxygen vacancies, improving interface matching (e.g. reducing interfacial straining and / or lattice mismatches), modifying a chemical potential difference, providing a diffusion barrier, reducing interfacial straining and so forth. Alternatively, when the ordering of the silicon-based resistance switching layer 9 and the conductive oxide layer 10 is reversed, the one or more first intermediate layers may separate the silicon-based resistance switching layer 9 from the second electrode 5 However, in some examples, the silicon based resistance switching layer 9 may be disposed (or formed) directly on the first electrode 3 (or vice versa, depending on the order of forming the stack). As another example, one or more second intermediate layers may separate the conductive oxide layer 10 from the silicon-based resistance switching layer 9, each second intermediate layer selected to perform one or more functions of adjustment of the local stoichiometry, adjustment of the density of oxygen vacancies, improving interface matching (e.g. reducing Interfacial straining and / or lattice mismatches), modifying a chemical potential difference, providing a diffusion barrier, reducing interfacial straining and so forth. However, in some examples, the conductive oxide layer 10 may be disposed (or formed) directly on the silicon-based resistance switching layer 9 (or vice versa, depending on the order of forming the stack). As another example, one or more third intermediate layers may separate the second electrode 5 from the conductive oxide layer 10, each third intermediate layer selected to perform one of more functions of adjustment of the local stoichiometry, adjustment of the density of oxygen vacancies, improving interface matching (e.g. reducing interfacial straining and / or lattice mismatches), modifying a chemical potential difference, providing a diffusion barrier, reducing interfacial straining and so forth. Alternatively, when the ordering of the silicon-based resistance switching layer 9 and the conductive oxide layer 10 is reversed, the one or more third intermediate layers may separate the conductive oxide layer 10 from the first electrode 3 However, In some examples, the second electrode 5 may be disposed (or formed) directly on the conductive oxide layer 10 (or vice versa, depending on the order of forming the stack). As described hereinbefore, the selection of materials for the silicon-based resistance switching layer 9 and the conductive oxide layer 10 follows a first (essential) design rule that the resistivity be less than or equal to 5 mQ.cm, and second (optional but preferred) design rule that an oxygen affinity of the conductive oxide layer 10 should be greater than or equal to twice an oxygen affinity of the silicon-based resistance switching layer 9. One specific combination of materials is to form the silicon-based 5 resistance switching layer 9 from SIOX with the conductive oxide layer 10 formed as tantalum oxide, as for the improved RRAM devices 8 measured to obtain the data shown In Figures 3B, 4B, 5B, 6B and 7B. Further specific combinations which are expected to function similarly are set out in 10 Table 1: Table 1 Silicon-based resistance switching layer material Conductive oxide layer material silicon oxide tantalum oxide (TaOx) silicon oxide hafnium oxide all (HfOx) silicon oxide molybdenum oxide (MoOx) silicon oxide aluminium oxide (AIOx) silicon oxide tungsten oxide (WOX) silicon oxide titanium oxide (TiOx) silicon oxide gallium oxide (GaOx) silicon oxide silicon oxide (SiOx) silicon oxide germanium oxide (GeOx) silicon dioxide tantalum oxide (TaOx) silicon dioxide hafnium oxide all (HfOx) silicon dioxide molybdenum oxide (MoOx) silicon dioxide aluminium oxide (AIOX) silicon dioxide tungsten oxide (WOX) silicon dioxide titanium oxide (TiOx) silicon dioxide gallium oxide (GaOx) silicon dioxide silicon oxide (SiOx) silicon dioxide germanium oxide (GeOx) silicon nitride tantalum oxide (TaOx) silicon nitride hafnium oxide all (HfOx) silicon nitride molybdenum oxide (MoOx) silicon nitride aluminium oxide (AIOx) silicon nitride tungsten oxide (WOx) silicon nitride titanium oxide (TiOx) silicon nitride gallium oxide (GaOx) silicon nitride silicon oxide (SIOX) silicon nitride germanium oxide (GeOx) silicon carbide tantalum oxide (TaOx) silicon carbide hafnium oxide all (HfOx) silicon carbide molybdenum oxide (MoOx) silicon carbide aluminium oxide (AIOX) silicon carbide tungsten oxide (WOX) silicon carbide titanium oxide (TIOx) silicon carbide gallium oxide (GaOx) silicon carbide silicon oxide (SiOx) silicon carbide germanium oxide (GeOx) silicon oxynitride tantalum oxide (TaOx) silicon oxynitride hafnium oxide all (HfOx) silicon oxynitride molybdenum oxide (MoOx) silicon oxynitride aluminium oxide (AIOx) silicon oxynitride tungsten oxide (WOx) silicon oxynitride titanium oxide (TIOx) silicon oxynitride gallium oxide (GaOx) silicon oxynitride silicon oxide (SiOx) silicon oxynitride germanium oxide (GeOx) Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel features or any novel combination of features 5 disclosed herein either explicitly or implicitly or any generalization thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to such features and / or combinations of such features during the prosecution of the 10 present application or of any further application derived therefrom.

Claims

1. A resistive random access memory device, comprising:a first electrode;a second electrode; andstacked between the first electrode and the second electrode:a resistance switching layer formed from one or more of silicon oxide, silicon dioxide, silicon nitride, silicon carbide and silicon oxynitride; anda conductive oxide layer;wherein the conductive oxide layer has a resistivity of less than or equal to 5 mQ.cm.

2. The resistive random access memory device of claim 1, operable using a magnitude of set voltage pulses which is less than or equal to 3 V.

3. Theresistive random access memory device of claims 1 or 2, operable using a magnitude of reset voltage pulses which is less than or equal to 3 V.

4. The resistive random access memory device of any one of claims 1 to 3, wherein a median switching time for the resistance switching layer to transition from a high resistance state to a low resistance state in response to application of the set threshold voltage is a fraction of half or less than a median reference switching time which corresponds to a reference device which is identical to the resistance random access memory device except that the conductive oxide layer is replaced with a layer formed from the respective unoxidized material.

5. The resistive random access memory device of any one of claims 1 to 4, wherein the conductive oxide has 20% or more excess metal compared to a stoichiometric conductive oxide.

6. The resistive random access memory device of any one of claims 1 to 5, wherein the high resistance branch of the current-voltage characteristic of the resistance random access memory device does not exhibit rectifying behaviour.

7. The resistive random access memory device of any one of claims 1 to 6, wherein the current-voltage characteristic of the resistive random access memory device does not exhibit self-saturation of the current.

8. The resistive random access memory device of any one of claims 1 to 7, wherein the current-voltage characteristic of the resistive random access memory exhibits a step change in current in response to a voltage ramp spanning the set threshold voltage.

9. The resistive random access memory device of any one of claims 1 to 8, wherein the resistance switching oxide layer is Silicon oxide.

10. The resistive random access memory device of any one of claims 1 to 9, wherein the conductive oxide layer comprises one or more of tantalum oxide, hafnium oxide, molybdenum oxide, aluminium oxide, tungsten oxide, gallium oxide, silicon oxide and germanium oxide.

11. The resistive random access memory device of any one of claims 1 to 10, wherein the resistance switching layer is amorphous.

12. The resistive random access memory device of any one of claims 1 to 11, wherein the conductive oxide layer is amorphous.

13. The resistive random access memory device of any one of claims 1 to 12, wherein the resistance switching layer has a thickness of between 0.5 nm and 20 nm.

14. The resistive random access memory device of any one of claims 1 to 13, wherein the conductive oxide layer has a thickness of between 1 nm and 40 nm.

15. The resistive random access memory device of any one of claims 1 to 14, wherein an oxygen affinity of the conductive oxide layer is greater than or equal to 2 times an oxygen affinity of the resistance switching layer.

16. An apparatus comprising:the resistive random access memory device of any one of claims 1 to 15;a controller configured:in response to a command to set the resistive random access memory device, to apply a set voltage pulse between the first and second electrodes such that the first electrode is negative relative to the second electrode;in response to a command to reset the resistive random access memory device, to apply a reset voltage pulse between the first and second electrodes such that the first electrode is positive relative to the second electrode.

17. The apparatus of claim 16, comprising a plurality of resistive random access memory devices disposed in an array, each resistive random access memory device according to any one of claims 1 to 15;wherein the controller is configured, for each given resistive random access memory device:in response to a command to set the given resistive random access memory device, to apply a set voltage pulse between the first and second electrodes such that the first electrode is negative relative to the second electrode;in response to a command to reset the given resistive random access memory device, to apply a reset voltage pulse between the first and second electrodes such that the first electrode is positive relative to the second electrode.

18. A memory device comprising a plurality of resistive random access memory device according to any one of claims 1 to 15.

19. A system comprising:the memory device of claim 18; anda controller configured, for each given resistive random access memory device: in response to a command to set the given resistive random accessmemory device, to apply a set voltage pulse between the first and second electrodes such that the first electrode is negative relative to the second electrode;in response to a command to reset the given resistive random access memory device, to apply a reset voltage pulse between the first and second electrodes such that the first electrode is positive relative to the second electrode.

20. A neuromorphic computing device comprising a plurality of resistive random access memory devices according to any one of claims 1 to 15, the apparatus of claims 16 or 17, the memory device of claim 18 or the system of claim 19, wherein weights of a neural network are encoded in the resistances of at least a subset of the resistive random access memory devices.

21. A method of fabricating a resistive random access memory device, comprising: depositing a first electrode;depositing a resistance switching layer over the first electrode, the resistance switching oxide layer formed from one or more of silicon oxide, silicon dioxide, silicon nitride, silicon carbide and silicon oxynitride;depositing a conductive oxide layer over the resistance switching layer, wherein the conductive oxide layer has a resistivity of less than or equal to 5 mQ.cm; and depositing a second electrode over the conductive oxide layer.

22. A method of fabricating a resistive random access memory device, comprising: depositing a second electrode;depositing a conductive oxide layer over the second electrode, wherein the conductive oxide layer has a resistivity of less than or equal to 5 mQ.cm;depositing a resistance switching layer over the conductive oxide layer, the resistance switching oxide layer formed from one or more of silicon oxide, silicon dioxide, silicon nitride, silicon carbide and silicon oxynitride; anddepositing a first electrode over the resistance switching layer.

23. The method of claims 21 or 22, wherein the conductive oxide has 20% or more excess metal compared to a stoichiometric conductive oxide.

24. A method comprising use of a plurality of resistive random access memory devices according to any one of claims 1 to 15, the apparatus of claims 16 or 17, the memory device of claim 18 or the system of claim 19, to store information in the resistance states of the plurality of resistive random access memory devices.

25. The method of claim 24, wherein storing information in the resistance states of the plurality of resistive random access memory devices comprises, for each given resistive random access memory device:in response to a command to set the given resistive random access memory device, applying a set voltage pulse between the first and second electrodes such that the first electrode is negative relative to the second electrode;in response to a command to reset the given resistive random access memory device, applying a reset voltage pulse between the first and second electrodes such that the first electrode is positive relative to the second electrode.

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