Gate driver circuit and driving method therefor, and display panel and display apparatus

Abstract

A gate driver circuit and a driving method therefor, and a display panel and a display apparatus. The gate driver circuit comprises a multi-stage cascaded shift register unit, which comprises a shift

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of display technology and, in particular, to a gate driving circuit and a driving method therefor, a display panel, and a display device. BACKGROUND

[0002] In the related art, the display panel may only regulate the refresh frequency of all the pixel driving circuits, and when, in an image displayed on the display panel, a partial area requires a relatively high refresh frequency and another partial area requires a relatively low refresh frequency, the display panel may only increase the refresh frequency of all pixel driving circuits to meet the requirements of the image. However, such a setting results in relatively high power consumption of the display panel.

[0003] It should be noted that the information disclosed in the background section above is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those skilled m the art. SUMMARY

[0004] According to an aspect of the present disclosure, the gate driving circuit is provided, and a shift register unit includes:

[0005] a shift output circuit, configured to convert an input signal into a shift-output output signal, where the shift output circuit includes a plurality of signal tenninals; and

[0006] a control circuit, connected to at least part of the signal terminals in the at least one shift output circuit, to a gating signal terminal and to a driving signal terminal;

[0007] where the signal tenninals connected to the control circuit and located in the shift output circuit include one or a plurality of control signal terminals, where the control circuit is configured to input a first driving signal or a second driving signal to the driving signal terminal in response to a signal on the gating signal terminal and a signal on the control signal terminal, where the first driving signal is the same as the output signal, and the second driving signal is an invalid level signal.

[0008] In an embodiment of the present disclosure, the signal on the control signal terminal and the output signal output by the shift output circuit in a current stage have pulse signals that are at least partially overlapped.

[0009] In an embodiment of the present disclosure, the control signal terminal includes one or a plurality of first control signal terminals;

[0010] the control circuit includes:

[0011] a gating circuit, connected to the gating signal terminal and a first node, where the gating circuit is configured to transmit a signal from the gating signal terminal to the first node in response to a control signal; and

[0012] a regulating circuit, connected to the first node, the first control signal terminal and the driving signal terminal, where the regulating circuit is configured to input the first driving signal or the second driving signal to the driving signal terminal in response to signals from the first node and the first control signal terminal.

[0013] In an embodiment of the present disclosure, the control signal terminals further include one or a plurality of second control signal terminals;

[0014] where the gating circuit is connected to the second control signal terminal and is configured to transmit a signal from the gating signal terminal to the first node in response to a signal on the second control signal terminal.

[0015] In an embodiment of the present disclosure, the first control signal terminal is formed by a signal terminal in the shift output circuit in a current stage;

[0016] and / or, the gating circuit is connected to the plurality of second control signal terminals, and the plurality of second control signal terminals connected to the gating circuit are formed by signal terminals of shift output circuits in two adjacent stages.

[0017] In an embodiment of the present disclosure, the shift output circuit includes a signal output terminal, and the signal output terminal is configured to output the output signal;

[0018] where the gating circuit is connected to the plurality of second control signal terminals, the plurality of second control signal tenninals connected to the gating circuit include a first control signal sub-terminal and a second control signal sub-terminal, the first control signal sub-terminal is formed by the signal output terminal of the shift output circuit in the current stage, and the second control signal sub-terminal is formed by the signal output terminal of the shift output circuit in an adjacent stage; and

[0019] where the gating circuit is configured to transmit the signal from the gating signal terminal to the first node in response to a signal on the first control signal sub-terminal and a signal on the second control signal sub-terminal.

[0020] In an embodiment of the present disclosure, the first control signal terminal is formed by a signal output terminal in the shift output circuit in a current stage;

[0021] the regulating circuit includes:

[0022] a NAND gate, where a first input terminal of the NAND gate is connected to the first control signal terminal, and a second input terminal of the NAND gate is connected to the first node; and

[0023] a first inverter, where an input terminal of the first inverter is connected to an output terminal of the NAND gate, and an output terminal of the first inverter is connected to the driving signal terminal.

[0024] In an embodiment of the present disclosure, tire second control signal sub-terminal is formed by the signal output terminal of the shift output circuit in an adjacent previous stage; or,

[0025] the second control signal sub-terminal is formed by the signal output terminal of the shift output circuit in an adjacent next stage.

[0026] In an embodiment of the present disclosure, the gate driving circuit is used for a display panel, and the display panel includes a plurality of rows of pixel driving circuits;

[0027] when the second control signal sub-terminal is formed by the signal output terminal of the shift output circuit in the adjacent previous stage, the driving signal terminal of the shift register unit in a first stage is not connected to the pixel driving circuit; and

[0028] when the second control signal sub-terminal is formed by the signal output terminal of the shift output circuit in the adjacent next stage, the driving signal terminal of the shift register unit in a last stage is not connected to the pixel driving circuit.

[0029] In an embodiment of the present disclosure, the regulating circuit includes:

[0030] a latch circuit, connected to the first node and configured to latch a voltage input from the gating signal terminal to the first node.

[0031] In an embodiment of the present disclosure, the regulating circuit further includes:

[0032] a first reset circuit, connected to the first node, a reset signal terminal and a first power supply terminal and configured to transmit a signal from the first power supply terminal to the first node in response to a signal on the reset signal terminal.

[0033] In an embodiment of the present disclosure, when the second control signal sub-terminal is formed by the signal output terminal of the shift output circuit in the adjacent previous stage, the gating circuit includes:

[0034] a first transistor, where a first electrode of the first transistor is connected to the gating signal terminal, a gate electrode of the first transistor is connected to the first control signal sub-terminal, and a polarity of a turn-on level of the first transistor is opposite to a polarity of an active level of the signal output terminal;

[0035] a second transistor, where a first electrode of the second transistor is connected to a second electrode of the first transistor, a second electrode of the second transistor is connected to the first node, a gate electrode of the second transistor is connected to the second control signal sub-terminal, and a polarity of a turn-on level of the second transistor and the polarity of the active level of the signal output terminal are identical;

[0036] a first capacitor, a first electrode of the first capacitor is connected to the first node, and a second electrode of the first capacitor is connected to a stable voltage terminal;

[0037] where when the second control signal sub-terminal is formed by the signal output terminal of the shift output circuit in the adjacent next stage, the gating circuit includes:

[0038] a first transistor, a first electrode of the first transistor is connected to the gating signal terminal, a gate electrode of the first transistor is connected to the second control signal sub-terminal, and the polarity of the turn-on level of the first transistor is opposite to the polarity of the active level of the signal output terminal;

[0039] a second transistor, a first electrode of the second transistor is connected to a second electrode of the first transistor, a second electrode of the second transistor is connected to the first node, a gate electrode of the second transistor is connected to the first control signal sub-terminal, and the polarity of the turn-on level of the second transistor and the polarity of the active level of the signal output terminal are identical; and

[0040] a first capacitor, a first electrode of the first capacitor is connected to the first node, and a second electrode of the first capacitor is connected to a stable voltage terminal.

[0041] In an embodiment of the present disclosure, the regulating circuit further includes:

[0042] a latch circuit, connected to the first node and configured to latch a voltage input from the gating signal terminal to the first node;

[0043] where the latch circuit includes:

[0044] a second inverter, where an input terminal of the second inverter is connected to the first node;

[0045] a third inverter, where an input terminal of the third inverter is connected to an output terminal of the second inverter, and an output terminal of the third inverter is connected to the second input terminal of the NAND gate; and

[0046] a fourth switching circuit, connected to the first node and the output terminal of the third inverter, configured to turn off the first node and the output terminal of the third inverter during at least part of a time period in which the gating signal terminal inputs the signal to the first node, and configured to turn on the first node and the output terminal of the third inverter during at least another part of the time period in which the gating signal terminal inputs the signal to the first node.

[0047] In an embodiment of the present disclosure, the second inverter includes:

[0048] a third P-type transistor, where a first electrode of the third P-type transistor is connected to a first power supply terminal at a high level, a second electrode of the third P-type transistor is connected to a second node, and a gate electrode of the third P-type transistor is connected to the first node; and

[0049] a fourth N-typc transistor, where a first electrode of the fourth N-typc transistor is connected to a second power supply terminal at a low level, a second electrode of the fourth N-type transistor is connected to the second node, and a gate electrode of the fourth N-type transistor is connected to the first node;

[0050] where the third inverter includes:

[0051] a fifth P-type transistor, where a first electrode of the fifth P-type transistor is connected to the first power supply terminal, a second electrode of the fifth P-type transistor is connected to the second input terminal of the NAND gate, and a gate electrode of the fifth P-type transistor is connected to the second node;

[0052] a sixth N-type transistor, where a first electrode of the sixth N-type transistor is connected to the second power supply terminal, a second electrode of the sixth N-type transistor is connected to the second input terminal of the NAND gate, and a gate electrode of the sixth N-type transistor is connected to the second node;

[0053] where when the second control signal sub-terminal is formed by the signal output terminal of the shift output circuit m the adjacent previous stage, the fourth switching circuit includes:

[0054] a seventh transistor, where a first electrode of the seventh transistor is connected to the second input terminal of the NAND gate, a second electrode of the seventh transistor is connected to the first node, and a gate electrode of the seventh transistor is connected to the signal output terminal of the shift output circuit in the adjacent previous stage;

[0055] an eighth transistor, where a first electrode of the eighth transistor is connected to the second input terminal of the NAND gate, a second electrode of the eighth transistor is connected to the first node, and a gate electrode of the eighth transistor is connected to a first clock signal terminal;

[0056] where when the second control signal sub-terminal is formed by the signal output terminal of the shift output circuit in the adjacent next stage, the fourth switching circuit includes:

[0057] a seventh transistor, where a first electrode of the seventh transistor is connected to the second input tenninal of the NAND gate, a second electrode of the seventh transistor is connected to the first node, and a gate electrode of the seventh transistor is connected to the signal output terminal of the shift output circuit in the current stage; and

[0058] an eighth transistor, where a first electrode of the eighth transistor is connected to the second input terminal of the NAND gate, a second electrode of the eighth transistor is connected to the first node, and a gate electrode of the eighth transistor is connected to the first clock signal terminal.

[0059] In an embodiment of the present disclosure, the NAND gate includes:

[0060] a ninth P-typc transistor, where a first electrode of the ninth P-typc transistor is connected to a first power supply terminal, a second electrode of the ninth P-type transistor is connected to a third node, and a gate electrode of the ninth P-type transistor is connected to the first input terminal of the NAND gate;

[0061] a tenth P-type transistor, where a first electrode of the tenth P-type transistor is connected to the first power supply terminal, a second electrode of the tenth P-type transistor is connected to the third node, and a gate electrode of the tenth P-type transistor is connected to the second input terminal of the NAND gate;

[0062] an eleventh N-type transistor, where a first electrode of the eleventh N-type transistor is connected to the third node, and a gate electrode of the eleventh N-type transistor is connected to the first input terminal of the NAND gate; and

[0063] a twelfth N-type transistor, where a first electrode of the twelfth N-type transistor is connected to a second electrode of the eleventh N-type transistor, a second electrode of the twelfth N-type transistor is connected to a second power supply terminal, and a gate electrode of the twelfth N-type transistor is connected to the second input terminal of the NAND gate;

[0064] where the first inverter includes:

[0065] a thirteenth P-type transistor, where a first electrode of the thirteenth P-type transistor is connected to the first power supply terminal, a second electrode of the thirteenth P-type transistor is connected to the driving signal terminal, and a gate electrode of the thirteenth P-type transistor is connected to the output tenninal of the NAND gate; and

[0066] a fourteenth N-type transistor, where a first electrode of the fourteenth N-type transistor is connected to the second power supply terminal, a second electrode of the fourteenth N-type transistor is connected to the driving signal terminal, and agate electrode of the fourteenth N-type transistor is connected to the output tenninal of the NAND gate.

[0067] In an embodiment of the present disclosure, the first reset circuit includes:

[0068] a fifteenth transistor, where a first electrode of the fifteenth transistor is connected to the first power supply terminal, a second electrode of the fifteenth transistor is connected to the first node, and a gate electrode of the fifteenth transistor is connected to the reset signal terminal.

[0069] In an embodiment of the present disclosure, the shift output circuit includes:

[0070] a first output circuit, connected to a fourth node, a first power supply terminal, and a signal output terminal of the shift output circuit, where the first output circuit is configured to transmit a signal of the first power supply terminal to the signal output terminal in response to a signal of the fourth node;

[0071] a second output circuit, connected to a fifth node, a second power supply terminal, and the signal output terminal of the shift output circuit, where the second output circuit is configured to transmit a signal of the second power supply terminal to the signal output terminal in response to a signal of the fifth node, and the signal output terminal is configured to output tire output signal;

[0072] where the gating circuit is connected to the plurality of second control signal terminals, the plurality of second control signal terminals connected to the gating circuit include a third control signal sub-terminal and a fourth control signal sub-terminal, the fourth node of the shift output circuit in the current stage forms the third control signal sub-terminal, and the fifth node of the shift output circuit in the adjacent next stage forms the fourth control signal sub-terminal;

[0073] where the gating circuit is connected to a plurality of gating signal terminals, the plurality of gating signal terminals connected to the gating circuit include a first gating signal terminal and a second gating signal terminal;

[0074] where the gating circuit is further connected to a third control signal terminal, and is configured to transmit a signal of the first gating signal terminal to the first node in response to signals of the third control signal terminal and the third control signal sub-terminal, and to transmit a signal of the second gating signal terminal to the first node in response to signals of the third control signal terminal and the fourth control signal sub-terminal.

[0075] In an embodiment of the present disclosure, the regulating circuit is connected to a plurality of first control signal terminals, the plurality of first control signal terminals connected to the regulating circuit include a fifth control signal sub-terminal and a sixth control signal sub-terminal, the fifth control signal sub-terminal being formed by the fourth node in the shift output circuit in the current stage, and the sixth control signal sub-terminal being formed by the fifth node in the shift output circuit in the current stage;

[0076] where the regulating circuit includes:

[0077] a first switching circuit, connected to the sixth control signal sub-terminal, the first node, and a sixth node, and configured to transmit a signal of the sixth control signal sub-terminal to the sixth node in response to a signal of the first node;

[0078] a second switching circuit, connected to the fifth control signal sub-terminal, the first node, and a seventh node, and configured to transmit a signal of the fifth control signal sub-terminal to the seventh node in response to the signal of the first node;

[0079] a third output circuit, connected to the sixth node, the seventh node, the first power supply terminal, and the second power supply terminal, and configured to transmit a power supply signal of the second power supply terminal to the driving signal terminal in response to a signal of the sixth node, and to transmit a power supply signal of the first power supply terminal to the driving signal terminal in response to a signal of the seventh node.

[0080] In an embodiment of the present disclosure, the second output circuit is further connected to an eighth node, and is further configured to transmit a signal of the eighth node to the fifth node in response to a signal of the eighth node;

[0081] where the regulating circuit further includes:

[0082] a third switching circuit, connected to the sixth node and the eighth node, and configured to transmit a signal of the eighth node to the sixth node in response to a signal of the eighth node.

[0083] In an embodiment of the present disclosure, the gating circuit includes:

[0084] a sixteenth transistor, where a first electrode of the sixteenth transistor is connected to the first gating signal terminal, and a gate electrode of the sixteenth transistor is connected to the third control signal terminal;

[0085] a seventeenth transistor, where a first electrode of the seventeenth transistor is connected to a second electrode of the sixteenth transistor, a second electrode of the seventeenth transistor is connected to the first node, and a gate electrode of the seventeenth transistor is connected to the third control signal sub-terminal;

[0086] an eighteenth transistor, where a first electrode of the eighteenth transistor is connected to the second gating signal terminal, and a gate electrode of the eighteenth transistor is connected to the third control signal terminal;

[0087] a nineteenth transistor, where a first electrode of the nineteenth transistor is connected to a second electrode of the eighteenth transistor, a second electrode of the nineteenth transistor is connected to the first node, and a gate electrode of the nineteenth transistor is connected to the fourth control signal sub-terminal;

[0088] a second capacitor, where a first electrode of the second capacitor is connected to the first node, and a second electrode of the second capacitor is connected to the seventh node;

[0089] where the first switching circuit includes:

[0090] a twentieth transistor, where a first electrode of the twentieth transistor is connected to the sixth control signal sub-terminal, a second electrode of the twentieth transistor is connected to the sixth node, and a gate electrode of the twentieth transistor is connected to the first node;

[0091] where the second switching circuit includes:

[0092] a twenty-first transistor, where a first electrode of the twenty-first transistor is connected to the fifth control signal sub-terminal, a second electrode of the twenty-first transistor is connected to the seventh node, and a gate electrode of the twenty-first transistor is connected to the first node;

[0093] where the third switching circuit includes:

[0094] a twenty-fourth transistor, where a first electrode of the twenty-fourth transistor is connected to the eighth node, a second electrode of the twenty-fourth transistor is connected to the sixth node, and a gate electrode of the twenty-fourth transistor is connected to the eighth node;

[0095] where the third output circuit includes:

[0096] a twenty-second transistor, where a first electrode of the twenty-second transistor is connected to the first power supply terminal, a second electrode of the twenty-second transistor is connected to the driving signal terminal, and agate electrode of the twenty-second transistor is connected to the seventh node;

[0097] a twenty-third transistor, where a first electrode of the twenty-third transistor is connected to the second power supply terminal, a second electrode of the twenty-third transistor is connected to the driving signal terminal, and a gate electrode of the twenty-third transistor is connected to the sixth node; and

[0098] a third capacitor, where a first electrode of the third capacitor is connected to the seventh node, and a second electrode of the third capacitor is connected to the first power supply terminal.

[0099] In an embodiment of the present disclosure, the shift output circuit includes:

[00100] a first input circuit, connected to a second power supply terminal, a first clock signal terminal, and a ninth node, and configured to transmit a signal of the second power supply terminal to the ninth node in response to a signal of the first clock signal terminal;

[00101] a second input circuit, connected to a signal input terminal, the first clock signal terminal, a tenth node, and an eleventh node, and configured to transmit a signal of the signal input terminal to the tenth node and the eleventh node in response to a signal of the first clock signal terminal;

[00102] a first output circuit, connected to a twelfth node, a thirteenth node, a fourth node, a second clock signal terminal, a first power supply terminal, and a signal output terminal, where the first output circuit is configured to transmit a signal of the second clock signal terminal to the thirteenth node in response to a signal of the twelfth node, to transmit a signal of the thirteenth node to the fourth node in response to a signal of the second clock signal terminal, and to transmit a power supply signal of the first power supply terminal to the signal output terminal in response to a signal of the fourth node, where the twelfth node is connected to the ninth node;

[00103] a second output circuit, connected to an eighth node, a fifth node, the second power supply terminal, and the signal output terminal, where the second output circuit is configured to transmit a signal of the eighth node to the fifth node in response to a signal of the eighth node, and to transmit the signal of the second power supply terminal to the signal output terminal in response to a signal of the fifth node, where the eighth node is connected to the eleventh node, and the tenth node is connected to the fifth node;

[00104] a first pull-up circuit, connected to the tenth node, the first power supply terminal, and the fourth node, and configured to transmit a signal of the first power supply terminal to the fourth node in response to a signal of the tenth node;

[00105] a second pull-up circuit, connected to the tenth node, the first clock signal terminal, and the ninth node, and configured to transmit a signal of the first clock signal terminal to the ninth node in response to a signal of the tenth node;

[00106] a coupling circuit, connected to the ninth node, the first power supply terminal, a fourteenth node, the eighth node, and the second clock signal terminal, and configured to transmit the signal of the first power supply terminal to the fourteenth node in response to a signal of the ninth node, to transmit the signal of the second clock signal terminal to the fourteenth node in response to the signal of the eighth node, and to couple a signal on the fourteenth node to the eighth node;

[00107] where the signal input terminal of the shift output circuit in a first stage is connected to an initial signal, and the signal input terminal of another shift output circuit is connected to the signal output terminal of the shift output circuit in an adjacent previous stage.

[00108] In an embodiment of the present disclosure, the shift output circuit further includes:

[00109] a first isolation circuit, connected to the ninth node, the twelfth node and the second power supply tenninaL and configured to communicate the ninth node with the twelfth node in response to the signal of the second power supply terminal;

[00110] a second isolation circuit connected to the tenth node, the eleventh node, the second power supply terminal, the fifth node and the eighth node, and configured to communicate the tenth node with the fifth node, and to communicate the eleventh node with the eighth node, in response to the signal of the second power supply terminal; and [OOlllJa second reset circuit, connected to the first power supply terminal, a reset signal terminal, and the tenth node, and configured to transmit a signal of the first power supply terminal to the tenth node in response to a signal of the reset signal terminal.

[00112] In an embodiment of the present disclosure, the first input circuit includes:

[00113] a twenty-fifth transistor, where a first electrode of the twenty-fifth transistor is connected to the second power supply terminal, a second electrode of the twenty-fifth transistor is connected to the ninth node, and a gate electrode of the twenty-fifth transistor is connected to the first clock signal tenninal;

[00114] where the second input circuit includes:

[00115] a twenty-sixth transistor, where a first electrode of the twenty-sixth transistor is connected to the signal input terminal, a second electrode of the twenty-sixth transistor is connected to the tenth node, and a gate electrode of the twenty-sixth transistor is connected to the first clock signal terminal; [ 001161 a twenty-seventh transistor, where a first electrode of the twenty-seventh transistor is connected to the signal input terminal, a second electrode of the twenty-seventh transistor is connected to the eleventh node, and a gate electrode of the twenty-seventh transistor is connected to the first clock signal terminal;

[00117] where the first output circuit includes:

[00118] a twenty-eighth transistor, where a first electrode of the twenty-eighth transistor is connected to the second clock signal tenninal, a second electrode of the twenty-eighth transistor is connected to the thirteenth node, and a gate electrode of the twenty-eighth transistor is connected to the twelfth node;

[00119] a twenty-ninth transistor, where a first electrode of the twenty-ninth transistor is connected to the thirteenth node, a second electrode of the twenty-ninth transistor is connected to the fourth node, and a gate electrode of the twenty-ninth transistor is connected to the second clock signal terminal;

[00120] a thirtieth transistor, where a first electrode of the thi rtietli transistor is connected to the first power supply terminal, a second electrode of the thirtieth transistor is connected to the signal output tenninal, and a gate electrode of the thirtieth transistor is connected to the fourth node;

[00121] a fourth capacitor, where a first electrode of the fourth capacitor is connected to the twelfth node, and a second electrode of the fourth capacitor is connected to the thirteenth node;

[00122] a fifth capacitor, where a first electrode of the fifth capacitor is connected to the fourth node, and a second electrode of the fifth capacitor is connected to the first power supply terminal;

[00123] where the second output circuit includes:

[00124] a thirty-first transistor, where a first electrode of the thirty-first transistor is connected to the fifth node, a second electrode of the thirty-first transistor is connected to the eighth node, and a gate electrode of the thirty-first transistor is connected to the eighth node;

[00125] a thirty-second transistor, where a first electrode of the thirty-second transistor is connected to the second power supply terminal, a second electrode of the thirty-second transistor is connected to the signal output terminal, and a gate electrode of the thirty-second transistor is connected to the fifth node;

[00126] a sixth capacitor, where a first electrode of the sixth capacitor is connected to the signal output terminal, and a second electrode of the sixth capacitor is connected to the second power supply terminal;

[00127] where the first pull-up circuit includes:

[00128] a thirty-third transistor, where a first electrode of the thirty-third transistor is connected to the first power supply terminal, a second electrode of the thirty-third transistor is connected to the fourth node, and a gate electrode of the thirty-third transistor is connected to the tenth node;

[00129] where the second pull-up circuit includes:

[00130] a thirty-fourth transistor, where a first electrode of the thirty-fourth transistor is connected to the first clock signal terminal, a second electrode of the thirty-fourth transistor is connected to the ninth node, and a gate electrode of the thirty-fourth transistor is connected to the tenth node;

[00131] where the coupling circuit includes:

[00132] a thirty-fifth transistor, where a first electrode of the thirty-fifth transistor is connected to the first power supply terminal, a second electrode of the thirty-fifth transistor is connected to the fourteenth node, and a gate electrode of the thirty-fifth transistor is connected to the ninth node;

[00133] a thirty-sixth transistor, where a first electrode of the thirty-sixth transistor is connected to the second clock signal terminal, a second electrode of the thirty-sixth transistor is connected to the fourteenth node, and a gate electrode of the thirty-sixth transistor is connected to the eighth node;

[00134] a seventh capacitor, where a first electrode of the seventh capacitor is connected to the fourteenth node, and a second electrode of the seventh capacitor is connected to the eighth node;

[00135] where the first isolation circuit includes:

[00136] a thirty-seventh transistor, where a first electrode of the thirty-seventh transistor is connected to the ninth node, a second electrode of the thirty-seventh transistor is connected to the twelfth node, and a gate electrode of the thirty-seventh transistor is connected to the second power supply terminal;

[00137] where the second isolation circuit includes:

[00138] a thirty-eighth transistor, where a first electrode of the thirty-eighth transistor is connected to the tenth node, a second electrode of the thirty-eighth transistor is connected to the fifth node, and a gate electrode of the thirty-eighth transistor is connected to the second power supply terminal;

[00139] a thirty-ninth transistor, where a first electrode of the thirty-ninth transistor is connected to the eleventh node, a second electrode of the thirty-ninth transistor is connected to the eighth node, and a gate electrode of the tlurh -ninth transistor is connected to the second power supply terminal;

[00140] where the second reset circuit includes:

[00141] a fortieth transistor, where a first electrode of the fortieth transistor is connected to the first power supply terminal, a second electrode of the fortieth transistor is connected to the tenth node, and a gate electrode of the fortieth transistor is connected to the reset signal terminal.

[00142] According to an aspect of the present disclosure, a method for driving a gate driving circuit is provided, where the method is configured to drive the above gate driving circuit, and the method includes:

[00143] shifting and outputting an output signal by using the shift output circuit; and

[00144] controlling the control circuit to output a first driving signal or a second driving signal by using a gating signal, where the first driving signal and the output signal are identical, and the second driving signal is an invalid level signal.

[00145] According to an aspect of the present disclosure, a display panel is provided, where the display panel includes the above gate driving circuit.

[00146] According to an aspect of the present disclosure, a display device is provided, where the display-device includes the above display panel.

[00147] It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and not for limiting the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[00148] The accompanying drawings herein, which are incorporated m the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and are used to explain the principles of the present disclosure together with the specification. It is apparent that the accompanying drawings described below are only some embodiments of the present disclosure, and other accompanying drawings may also be obtained according to these accompanying drawings without any creative efforts by those skilled in the art.

[00149] FIG. 1 is a schematic structural diagram of an exemplary- embodiment of a pixel driving circuit according to the present disclosure;

[00150] FIG. 2 is a timing diagram of a part of nodes in an exemplary embodiment of the pixel driving circuit shown in FIG. 1; [00151JFIG. 3 is a schematic structural diagram of another exemplary embodiment of the pixel driving circuit according to the present disclosure;

[00152] FIG. 4 is a schematic structural diagram of an exemplary embodiment of the shift register unit according to the present disclosure; [00153JFIG. 5 is a schematic structural diagram of an exemplary embodiment of the shift register unit according to the present disclosure;

[00154] FIG. 6 is a schematic structural diagram of an exemplary embodiment of the shift register unit according to the present disclosure; [00155JFIG. 7 is a timing diagram of the signal output terminal of the shift output circuit in an exemplary embodiment of the gate driving circuit according to the present disclosure;

[00156] FIG. 8 is a timing diagram of each node in a driving method of the shift register unit according to the present disclosure; [00157JFIG. 9 is a schematic structural diagram of another exemplary' embodiment of the shift register unit according to the present disclosure; [00158JFIG. 10 is a schematic structural diagram of another exemplary embodiment of the shift register unit according to the present disclosure; |OO159|F1G. 11 is a timing diagram of each node m a driving method of the shift register unit shown in FIG. 10. DETAILED DESCRIPTION

[00160] Exemplary embodiments will now be described more comprehensively with reference to the accompanying drawings. However, the exemplary embodiments may be implemented in various forms, and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided to make the present disclosure be more comprehensive and complete, and the concepts of tire exemplary' embodiments will be comprehensively communicated to those skilled in the art. The same reference numerals in the accompanying drawings denote the same or similar structures, and thus detailed description thereof will be omitted.

[00161] The terms “a”, “an”, and “the” are used to represent the presence of one or a plurality of elements / components / etc.; the terms “including” and “having” are used to represent the meaning of openness and means that there may be additional elements / components / etc. in addition to the listed elements / components / etc..

[00162] The exemplary embodiment first provides a pixel driving circuit, as shown in Figs. 1 and 2, FIG. 1 is a schematic structural diagram of an exemplary embodiment of a pixel driving circuit according to the present disclosure, and FIG. 2 is a timing diagram of a part of nodes m an exemplary embodiment of the pixel driving circuit shown in FIG. 1.

[00163] The pixel driving circuit may include: a driving transistor T3, a first transistor Tl, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. Where a first electrode of the fourth transistor T4 is connected to the data signal terminal Da, a second electrode of the fourth transistor T4 is connected to the first electrode of the driving transistor T3, and a gate electrode of the fourth transistor T4 is connected to the first gate driving signal terminal Gl; a first electrode of the fifth transistor T5 is connected to a first power supply terminal VDD, a second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T3, and a gate electrode of the fifth transistor T5 is connected to the enable signal terminal EM; the gate electrode of the driving transistor T3 is connected to the node N; a first electrode of the second transistor T2 is connected to the node N, a second electrode of the second transistor T2 is connected to a second electrode of the driving transistor T3, and a gate electrode of the second transistor T2 is connected to the second gate driving signal terminal G2; a first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, a second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7, a gate electrode of the sixth transistor T6 is connected to the enable signal terminal EM, a first electrode of the seventh transistor T7 is connected to a second initial signal terminal Vinit2, and a gate electrode of the seventh transistor T7 is connected to a second reset signal terminal Re2; a second electrode of the first transistor Tl is connected to the node N, a first electrode of the first transistor Tl is connected to a first initial signal terminal Vinit 1, and a gate electrode of the first transistor Tl is connected to a first reset signal terminal Rei; a first electrode of the capacitor C is connected to the node N, and a second electrode of the capacitor C is connected to the first power supply terminal VDD. The pixel driving circuit may be connected to a light emitting unit OLED, the pixel driving circuit is configured to drive the light emitting unit OLED to emit light, a first electrode of the light emitting unit OLED may be connected to the second electrode of the sixth transistor T6, a second electrode of the light emitting unit may be connected to a second power supply terminal VSS, the first electrode of the light emitting unit may be an anode of the light emitting unit, and the second electrode of the light emitting unit may be a cathode of the light emitting unit. Where tire first transistor Tl and the second transistor T2 may be N-type transistors, for example, the first transistor Tl and the second transistor T2 may be N-type metal oxide transistors, and the N-type transistors have smaller leakage current, so that the electricity leakage of the node N through the first transistor Tl and the second transistor T2 in the light emitting stage may be avoided. Meanwhile, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 may be P-type transistors, for example, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 may be P-type low-temperature polycrystalline silicon transistors, and the P-type transistors have higher carrier mobility, which is beneficial to achieve a display panel with high resolution, high response speed, high pixel density and high aperture ratio. The first initial signal terminal and the second initial signal terminal may output the same or different voltage signals according to actual conditions.

[00164] As shown in FIG. 2, in which G1 represents a timing of the first gate driving signal terminal Gl, G2 represents a timing of the second gate driving signal tenninal G2, Rei represents a timing of the first reset signal terminal Rei, Re2 represents a timing of the second reset signal terminal Re2, EM represents a timing of the enable signal terminal EM, and Da represents a timing of the data signal tenninal Da. The driving method of the pixel driving circuit may include a reset stage tl, a data writing stage t2, and a light emitting stage t3. At reset stage tl: the first reset signal terminal Re 1 outputs a high-level signal, the second reset signal terminal Re2 outputs a low-level signal, the first transistor Tl and the seventh transistor T7 are turned on, the first initial signal terminal Vinitl inputs the first initial signal to the node N, and the second initial signal terminal Vinit2 inputs the second initial signal to the first electrode of the light emitting unit OLED. At data writing stage t2: the second gate driving signal terminal G2 outputs a high-level signal, the first gate driving signal terminal Gl outputs a low-level signal, the fourth transistor T4 and the second transistor T2 are turned on, meanwhile, the data signal terminal Da outputs a data signal to write a compensation voltage Vdata+Vth to the node N, where Vdata is a voltage of the data signal and Vth is a threshold voltage of the driving transistor T3. At the light emitting stage t3: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in the capacitor C. The driving transistor output current fonnula is as follows: I=(pWCox / 2L)(Vgs-Vth): Where I is the driving transistor output current; p is the carrier mobility; Cox is the gate electrode capacitance per unit area, W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, Vgs is gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. The output current of the driving transistor in the above pixel driving circuit is I=(pWCox / 2L)(Vdata+Vth-Vdd-Vth)2. The pixel driving circuit may avoid the influence of the threshold value of the driving transistor on the output current thereof.

[00165] It should be understood that, in other exemplary embodiments, tire second reset signal terminal Re2 and the first gate driving signal terminal G1 may also be shared as the same signal terminal, and the seventh transistor T7 may write the second initial signal to the first electrode of the light emitting unit OLED at the data writing stage T2.

[00166] FIG. 3 is a schematic structural diagram of another exemplary embodiment of the pixel driving circuit according to the present disclosure. The difference between this pixel driving circuit and the pixel driving circuit shown in FIG. 1 is that the first transistor T1 is connected to the output terminal of the driving transistor T3. The driving method of the pixel driving circuit may also include: a reset stage tl, a data writing stage t2, and a light emitting stage t3. At the reset stage tl: the first reset signal terminal Rei and the second gate driving signal terminal G2 output high-level signals, the second reset signal terminal Re2 outputs a low-level signal, the first transistor Tl, the seventh transistor T7, and the second transistor T2 are turned on, the first initial signal terminal Vinitl inputs the first initial signal to the node N through the first transistor Tl and the second transistor T2, and the second initial signal terminal Vinit2 inputs the second initial signal to the first electrode of the light emitting unit OLED. At the data writing stage t2: the second gate driving signal terminal G2 outputs a high-level signal, the first gate driving signal terminal G1 and the first reset signal terminal Rei output low-level signals, the fourth transistor T4 and the second transistor T2 are turned on, the first transistor Tl is turned off, and the data signal terminal Da outputs a data signal to write a compensation voltage Vdata+Vth to the node N, where Vdata is a voltage of the data signal and Vth is a threshold voltage of the driving transistor T3. At the light emitting stage t3: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in the capacitor C.

[00167] As seen from the pixel driving circuit shown in FIG. 1, if the first transistor Tl and the second transistor T2 are not turned on at the reset stage tl and data writing stage t2, the voltage on the node N is not refreshed, and the node N maintains the voltage of the previous frame. As may be seen from the pixel driving circuit shown in FIG. 2, if the second transistor T2 is not turned on at the reset stage tl and the data writing stage t2, the voltage on the node N is not refreshed, and the node N maintains the voltage of the previous frame. The exemplary embodiment may implement the refresh frequency of the pixel driving circuit in the local area of the display panel local area by controlling the gate driving signals of the first and second transistors Tl and T2.

[00168] Accordingly, the exemplary embodiment provides a gate driving circuit that may provide a gate driving signal to the first transistor T1 or the second transistor T2 described above.

[00169] In the exemplary embodiment, the gate driving circuit includes a plurality of stages of cascaded shift register units. FIG. 4 is a schematic structural diagram of an exemplary embodiment of the shift register unit according to the present disclosure. The shift register unit includes: a shift output circuit 1 and a control circuit 2, where the shift output circuit 1 is configured to convert an input signal into a shift-output output signal, and the shift output circuit 1 includes a plurality of signal terminals; the control circuit 2 is connected to at least part of signal terminals in the at least one shift output circuit 1, a gating signal terminal SM and a driving signal terminal Gate; where the signal terminals connected to the control circuit 2 and located in the shift output circuit 1 include one or a plurality of control signal terminals CN, and the control circuit 2 is configured to input a first driving signal or a second driving signal to the driving signal terminal Gate in response to signals on the gating signal terminal SM and the control signal terminal CN, where the first driving signal is the same as the output signal, and the second driving signal is an invalid level signal.

[00170] The gate driving circuit provided in the exemplary embodiment drives the control circuit to output the first driving signal or the second driving signal under different requirements by using the gating signal terminal SM and the control signal terminal CN. The first driving signal may control the pixel driving circuit to scan normally, and the second driving signal may control the pixel driving circuit not to scan. The gate driving circuit may thus control the refresh frequency of the local pixel driving circuits in the display panel.

[00171] In the exemplary embodiment, the signal on the control signal terminal CN and the output signal output by the shift output circuit 1 in a current stage have pulse signals which are at least partially overlapped. The control signal terminal CN may drive the control circuit 2 to output the above first driving signal or second driving signal in time when the shift output circuit in the current stage outputs a valid pulse signal. The shift register unit may output a corresponding driving signal in a scanning time period of the pixel driving circuit according to the scanning requirement of the pixel driving circuit. The polarity of the pulse signal on the control signal terminal CN may be the same as or opposite to that of the output signal output by the shift output circuit 1 in a current stage.

[00172] In the exemplary' embodiment, FIG. 5 is a schematic structural diagram of an exemplary embodiment of the shift register unit according to the present disclosure. The control signal terminals CN include one or a plurality-’ of first control signal terminals CN1; the control circuit 2 includes: a gating circuit 21 and a regulating circuit 22, where the gating circuit 21 is connected to the gating signal terminal SM and the first node N1, the gating circuit 21 is configured to transmit a signal from the gating signal terminal SM to the first node N1 in response to a control signal; the regulating circuit 22 is connected to the first node N1, the first control signal terminal CN1 and the driving signal terminal Gate, and the regulating circuit 22 is configured to input the first or second driving signal to the driving signal terminal Gate in response to signals from the first node N1 and the first control signal terminal CN1.

[00173] In the exemplary embodiment, as shown in FIG. 5, the first control signal terminal CN1 may be formed by a signal terminal in the shift output circuit 1 in the current stage. For example, the first control signal terminal CN 1 may be formed by the signal output terminal of the shift output circuit 1. In addition, the first control signal terminal CN 1 may also be formed by other signal terminals in the shift output circuit 1 in tire current stage.

[00174] In the exemplary- embodiment, as shown in FIG. 5, the control signal terminal CN further includes one or a plurality of second control signal terminals CN 2; the gating circuit 21 is connected to the second control signal terminal CN2 and is configured to transmit a signal from the gating signal terminal SM to the first node N1 in response to the signal on the second control signal terminal CN2.

[00175] In the exemplary embodiment, as shown in FIG. 5, the gating circuit 21 may be connected to the plurality of second control signal terminals CN2, and the plurality of second control signal terminals CN2 connected to the gating circuit 21 may be formed by signal tenninals in the shift output circuit 1 in two adjacent stages.

[00176] In the exemplary' embodiment, FIG. 6 is a schematic structural diagram of an exemplary embodiment of the shift register unit according to the present disclosure. Hie shift output circuit 1 includes a signal output terminal OUT(n), and the signal output terminal OUT(n) is configured to output the output signal; the gating circuit 21 is connected to the plurality of second control signal terminals CN2, the plurality of second control signal terminals CN2 connected to the gating circuit 21 include a first control signal sub-terminal CN21 and a second control signal sub-tenninal CN22, the first control signal subterminal CN21 is formed by the signal output terminal OUT(n) of the shift output circuit 1 in the current stage, and the second control signal sub-terminal CN22 is formed by the signal output terminal OUT(n-l) of the shift output circuit 1 in the adjacent previous stage; the first control signal terminal CN1 is formed by the signal output terminal OUT(n) of the shift output circuit 1 in the current stage. The gating circuit 21 is configured to transmit a signal from the gating signal terminal SM to the first node N1 in response to signals on the first control signal sub-terminal CN21 and the second control signal sub-terminal CN22; the regulating circuit 22 includes: a NAND gate 222 and a first inverter 223, a first input terminal ini of the NAND gate 222 is connected to the first control signal terminal CN1, and a second input terminal in2 is connected to the first node Nl; the first inverter 223 has a signal input terminal connected to the output terminal of the NAND gate 222, and an output terminal connected to the driving signal terminal Gate.

[00177] In the exemplary embodiment, as shown in FIG. 6, the regulating circuit 22 may also include: a latch circuit 221 connected to the first node N1 and is configured to latch the voltage input to the first node N1 from the gating signal terminal MS.

[00178] In the exemplary embodiment, as shown in FIG. 6, the regulating circuit 22 may also include: a first reset circuit 224 connected to the first node Nl, a reset signal terminal Re and a first power supply terminal VGH and configured to transmit a signal from the first power supply terminal VGH to the first node N1 in response to a signal of the reset signal terminal Re.

[00179] In the exemplary embodiment, as shown in FIG. 6, the gating circuit 21 includes: a first transistor Tl, a second transistor T2, and a first capacitor Cl, where the first transistor T1 has a first electrode connected to the gating signal terminal SM, a gate electrode connected to the first control signal subterminal CN21, and the polarity of a turn-on level of the first transistor Tl is opposite to that of an active level of the signal output terminal OUT(n); the second transistor T2 has a first electrode connected to a second electrode of the first transistor T1, a second electrode connected to the first node N1, a gate electrode connected to tire second control signal sub-terminal CN22, and the polarity of a turn-on level of the second transistor T2 is the same as that of the active level of the signal output terminal OUT(n); a first electrode of the first capacitor Cl is connected to the first node Nl, and a second electrode of the first capacitor Cl is connected to a stable voltage terminal. For example, a second electrode of the first capacitor Cl may be connected to the second power supply temiinal VGL. In the exemplary embodiment, the active level may be understood as a level for turning on a target circuit, for example, the shift output circuit is used for turning on an N-type transistor of the pixel driving circuit by a high-level signal, the active level of the signal output terminal is a high level, accordingly, tire first power supply terminal VGH may be a high-level power supply terminal, the second power supply temiinal VGL may be a low-level power supply temiinal, the first transistor Tl may be a P-type transistor, and the second transistor T2 may be an N-type transistor.

[00180] Inthe exemplary embodiment, as shown in FIG. 6, the latch circuit 221 includes: a second inverter PI2, a third inverter PI3, and a fourth switching circuit K4, an input terminal of the second inverter PI2 being connected to the first node N1; an input temiinal of the third inverter PI3 being connected to an output terminal of the second inverter PI2, and an output terminal of the third inverter PI3 being connected to a second input terminal in2 of the NAND gate 222; the fourth switching circuit K4 being connected between the first node N1 and the output terminal of the third inverter PI3, and being configured to turn off the first node N1 and the output terminal of the third inverter PI3 during at least part of a time period in which the gating signal terminal MS inputs a signal to the first node Nl, and to turn on the first node Nl and the output terminal of the third inverter PI3 during at least part of another time period in which the gating signal terminal inputs a signal to the first node N1. The fourth switching circuit K4 may avoid the voltage at the output terminal of the third inverter PI3 from affecting the voltage at the first node Nl when the gating signal terminal MS inputs a signal to the first node Nl, and may maintain the voltage at the first node Nl through the output terminal of the third inverter PI3 during other time periods.

[00181] In the exemplary embodiment, as shown in FIG. 6, the second inverter PI2 may include: a third P-type transistor T3 and a fourth N-type transistor T4, the third P-type transistor T3 having a first electrode connected to the first power supply terminal VGH at a high level, a second electrode connected to a second node N2, and a gate electrode connected to the first node Nl; and the fourth N-type transistor T4 having a first electrode connected to the second power supply terminal VGL at a low level, a second electrode connected to the second node N2, and a gate electrode connected to the first node N1. The third inverter PI3 may include: a fifth P-type transistor T5 and a sixth N-type transistor T6, the fifth P-type transistor T5 having a first electrode connected to the first power supply terminal VGH, a second electrode connected to the second input terminal in2 of the NAND gate 222, and a gate electrode connected to the second node N2; and the sixth N-type transistor T6 having a first electrode connected to the second power supply terminal VGL, a second electrode connected to the second input terminal in2 of the NAND gate 222, and a gate electrode connected to the second node N2. The fourth switching circuit K4 may include: a seventh transistor T7 and an eighth transistor T8, the seventh transistor T7 having a first electrode connected to the second input terminal in2 of the NAND gate 222, a second electrode connected to the first node N1, and a gate electrode connected to the signal output terminal OUT(n-l) of the shift output circuit 1 in an adjacent previous stage; and the eighth transistor T8 having a first electrode connected to the second input terminal m2 of the NAND gate 222, a second electrode connected to the first node N1, and a gate electrode connected to the first clock signal terminal CLK.

[00182] In the exemplary embodiment, as shown in FIG. 6, the NAND gate 222 includes: a ninth P-type transistor T9, a tenth P-type transistor T10, an eleventh N-type transistor Til, and a twelfth N-type transistor T12, the ninth P-type transistor T9 having a first electrode connected to the first power supply terminal VGH, a second electrode connected to a third node N3, and a gate electrode connected to a first input terminal ini of the NAND gate 222; the tenth P-type transistor T10 having a first electrode connected to the first power supply terminal VGH, a second electrode connected to the third node N3, and a gate electrode connected to a second input terminal in2 of the NAND gate 222; the eleventh N-type transistor T11 having a first electrode connected to the third node N3, and a gate electrode connected to the first input terminal ini of the NAND gate 222; the twelfth N-type transistor T12 having a first electrode connected to a second electrode of the eleventh N-type transistor Tl 1, a second electrode connected to the second power supply terminal VGL, and a gate electrode connected to the second input terminal in2 of the NAND gate 222. The first inverter 223 includes: a thirteenth P-type transistor T13 and a fourteenth N-type transistor T14, the thirteenth P-typc transistor T13 having a first electrode connected to tire first power supply terminal VGH, a second electrode connected to the driving signal terminal Gate, and a gate electrode connected to an output terminal of the NAND gate 222; the fourteenth N-type transistor T14 having a first electrode connected to the second power supply terminal VGL, a second electrode connected to the driving signal terminal Gate, and a gate electrode connected to an output terminal OUT of the NAND gate 222. The first reset circuit 224 includes: a fifteenth transistor T15, the fifteenth transistor T15 having a first electrode connected to the first power supply terminal VGH, a second electrode connected to the first node Nl, and a gate electrode connected to the reset signal terminal Re. [001831 As shown m FIG. 7, a timing diagram of a signal output terminal of the shift output circuit in an exemplary embodiment of the gate driving circuit according to the present disclosure is illustrated. OUT(n) represents a timing of a signal output terminal in the shift output circuit in the current stage, and OUT(n-l) represents a timing of a signal output terminal in the shift output circuit in an adjacent previous stage.

[00184] As shown in FIGS. 6 and 7, in a first time period tl, OUT(n-l) outputs a high-level signal, OUT(n) outputs a low-level signal, the first transistor Tl and the second transistor T2 are turned on, and the gating signal terminal SM may input a gating signal to the first node Nl in the first time period 11. When a pixel driving circuit connected to the driving signal terminal Gate needs to maintain a high refresh frequency, the gating signal terminal SM inputs a high-level signal to the first node Nl in the first time period tl; when the signal output terminal OUT(n) outputs a high-level signal, an output terminal of the NAND gate outputs a low-level signal, and an output terminal of the first inverter outputs a high-level signal; when the signal output terminal OUT(n) outputs a low-level signal, the output terminal of the NAND gate outputs a high-level signal, and the output terminal of the first inverter normally outputs a low-level signal. When a pixel driving circuit connected to tire driving signal terminal Gate needs to be switched to a low refresh frequency, the gating signal terminal SM inputs a low-level signal to the first node Nl in the first time period tl; regardless of whether the signal output terminal OUT(n) outputs a high-level signal or a low-level signal, the output terminal of the NAND gate outputs a high-level signal, and the output terminal of the first inverter outputs a low-level signal. The exemplary embodiment may control a refresh frequency of the pixel driving circuit by controlling a polarity of a signal input from the gating signal terminal SM to the first node N1.

[00185] It should be understood that, in other exemplary embodiments, the regulating circuit 22 may also have other structures. For example, the regulating circuit 22 may replace the NAND gate and the first inverter in the shift register unit shown in FIG. 6 with an AND gate, a first input terminal of the AND gate being connected to the signal output terminal OUT(n), a second input terminal being connected to the first node Nl, and an output terminal being connected to the driving signal terminal Gate. When a pixel driving circuit connected to the driving signal terminal needs to maintain a high refresh frequency, a high-level signal is written to the first node Nl; when the signal output terminal OUT(n) outputs a high-level signal, the driving signal terminal Gate outputs a high-level signal; when the signal output terminal OUT(n) outputs a low-level signal, the driving signal terminal Gate normally outputs a low-level signal. When a pixel driving circuit connected to the driving signal terminal Gate needs to be switched to a low refresh frequency, a low-level signal is written to the first node N1; regardless of whether the signal output terminal OUT(n) outputs a high-level signal or a low-level signal, the driving signal terminal Gate outputs a low-level signal.

[00186] In the exemplary embodiment, the driving signal terminal Gate may be connected to one or a plurality of rows of pixel driving circuits. A plurality of cascaded shift register units may provide a gating signal terminal through the same signal line. Since the gating circuit is used for writing the signal of the gating signal terminal to the first node Nl in response to the first control signal sub-terminal CN21 and the second control signal sub-tenninal CN22, the gating signals input to shift register units of different rows through the same signal line do not interfere with each other.

[00187] In the exemplary embodiment, the driving signal terminal of the first-stage shift register unit may not be connected to the pixel driving circuit. This arrangement may make the driving capability of the gate driving signal received by each row of pixel driving circuits relatively uniform, thereby improving the display uniformity of the display panel.

[00188] In the exemplary embodiment, as shown in FIG. 6, the shift output circuit 1 may include: a first input circuit 13, a second input circuit 14, a first output circuit 11, a second output circuit 12, a first pull-up circuit 15, a second pull-up circuit 16, and a coupling circuit 17. The first input circuit 13 is connected to the second power supply terminal VGL, the first clock signal terminal CLK, and a ninth node N9, and is configured to transmit a signal from the second power supply terminal VGL to the ninth node N9 in response to a signal from the first clock signal terminal CLK. The second input circuit 14 is connected to a signal input terminal IN, the first clock signal terminal CLK, a tenth node N10, and an eleventh node Nil, and is configured to transmit a signal from the signal input terminal IN to the tenth node N10 and the eleventh node N11 in response to a signal from the first clock signal terminal CLK. The first output circuit 11 is connected to a twelfth node N12, a thirteenth node N13, a fourth node N4, a second clock signal terminal CLB, a first power supply terminal VGH, and a signal output terminal OUT(n), and is configured to transmit a signal from the second clock signal terminal CLB to the thirteenth node N13 in response to a signal from the twelfth node N12, to transmit a signal from the thirteenth node N13 to the fourth node N4 in response to a signal from the second clock signal terminal CLB, and to transmit a power supply signal from the first power supply terminal VGH to the signal output terminal OUT(n) in response to a signal from the fourth node N4, where the twelfth node N12 is connected to the ninth node N9. The second output circuit 12 is connected to an eighth node N8, a fifth node N5, the second power supply terminal VGL, and the signal output terminal OUT(n), and is configured to transmit a signal from the eighth node N8 to the fifth node N5 in response to a signal from the eighth node N8, and to transmit a signal from the second power supply terminal VGL to the signal output terminal OUT(n) in response to a signal from the fifth node N5, where the eighth node N8 is connected to the eleventh node Nil, and the tenth node N10 is connected to the fifth node N5. The first pull-up circuit 15 is connected to the tenth node N10, the first power supply terminal VGH, and the fourth node N4, and is configured to transmit a signal from the first power supply terminal VGH to the fourth node N4 in response to a signal from the tenth node N10. The second pull-up circuit 16 is connected to the tenth node N10, the first clock signal terminal CLK, and the ninth node N9, and is configured to transmit a signal from the first clock signal terminal CLK to the ninth node N9 in response to a signal from the tenth node N10. The coupling circuit 17 is connected to the ninth node N9, the first power supply terminal VGH, a fourteenth node N14, the eighth node N8, and the second clock signal terminal CLB, and is configured to transmit a signal from the first power supply terminal VGH to the fourteenth node N14 in response to a signal from the ninth node N9, to transmit a signal from the second clock signal terminal CLB to the fourteenth node N14 in response to a signal from the eighth node N8, and to couple a signal on the fourteenth node N14 to the eighth node N8.

[00189] In the exemplary embodiment, the signal input terminal IN of the first-stage shift output circuit 1 may be connected to an initial signal terminal, and the signal input terminal IN of other shift output circuits 1 is connected to the signal output terminal OUT(n) of the shift output circuit 1 in an adjacent previous stage.

[00190] In the exemplary embodiment, as shown in FIG. 6, the shift output circuit 1 further includes: a first isolation circuit 18, a second isolation circuit 19, and a second reset circuit 110. The first isolation circuit 18 is connected to the ninth node N9, the twelfth node N12, and the second power supply terminal VGL, and is configured to communicate the ninth node N9 with the twelfth node N12 in response to a signal from the second power supply terminal VGL. The second isolation circuit 19 is connected to the tenth node N10, the eleventh node Nil, the second power supply terminal VGL, the fifth node N5, and the eighth node N8, and is configured to communicate the tenth node N10 with the fifth node N5, and communicate the eleventh node Nil with the eighth node N8, in response to a signal from the second power supply terminal VGL. The second reset circuit 110 is connected to the first power supply terminal VGH, the reset signal terminal Re, and the tenth node N10, and is configured to transmit a signal from the first power supply terminal VGH to the tenth node N10 in response to a signal from the reset signal terminal Re.

[00191] In the exemplary embodiment, as shown m FIG. 6, the first input circuit 13 includes: a twenty-fifth transistor T25, having a first electrode connected to the second power supply terminal VGL, a second electrode connected to the ninth node N9, and a gate electrode connected to the first clock signal terminal CLK. The second input circuit 14 includes: a twenty-sixth transistor T26 and a twenty-seventh transistor T27, where the twenty-sixth transistor T26 has the first electrode connected to the signal input terminal IN, the second electrode connected to the tenth node N10, and the gate electrode connected to the first clock signal terminal CLK; the twenty-seventh transistor T27 has the first electrode connected to the signal input terminal IN, the second electrode connected to the eleventh node Nil, and the gate electrode connected to the first clock signal terminal CLK. |00192|In the exemplary embodiment, as shown in FIG. 6, the first output circuit 11 includes: a twentyeighth transistor T28, a twenty-ninth transistor T29, a thirtieth transistor T30, a fourth capacitor C4, and a fifth capacitor C5, where the twenty-eighth transistor T28 has the first electrode connected to the second clock signal terminal CLB, the second electrode connected to the thirteenth node N13, and the gate electrode connected to the twelfth node N12; the twenty-ninth transistor T29 has the first electrode connected to the thirteenth node N13, the second electrode connected to the fourth node N4, and the gate electrode connected to the second clock signal terminal CLB; the thirtieth transistor T30 has the first electrode connected to the first power supply terminal VGH, the second electrode connected to the signal output terminal OUT(n), and the gate electrode connected to the fourth node N4; the fourth capacitor C4 has the first electrode connected to the twelfth node N12, and the second electrode connected to the thirteenth node N13; the fifth capacitor C5 has the first electrode connected to the fourth node N4, and the second electrode connected to the first pow er supply terminal VGH.

[00193] In the exemplary embodiment, as shown in FIG. 6, the second output circuit 12 includes: a thirty- first transistor T31, a thirty-second transistor T32, and a sixth capacitor C6, where the thirty-first transistor T31 has the first electrode connected to the fifth node N5, the second electrode connected to the eighth node N8, and the gate electrode connected to the eighth node N8; the thirty-second transistor T32 has the first electrode connected to the second power supply terminal VGL, the second electrode connected to the signal output terminal OUT(n), and the gate electrode connected to the fifth node N5; the first electrode of the sixth capacitor C6 is connected to the signal output terminal OUT(n), and the second electrode of the sixth capacitor C6 is connected to the second power supply terminal VGL.

[00194] In the exemplary embodiment, as shown in FIG. 6, the first pull-up circuit 15 includes: a thirty-third transistor T33, having a first electrode connected to the first power supply terminal VGH, a second electrode connected to the fourth node N4, and a gate electrode connected to the tenth node N10. The second pull-up circuit 16 includes: a thirty-fourth transistor T34, having a first electrode connected to the first clock signal terminal CLK, a second electrode connected to the ninth node N9, and a gate electrode connected to the tenth node N10. The coupling circuit 17 includes: a thirty-fifth transistor T35, a thirtysixth transistor T36, and a seventh capacitor C7, where the thirty-fifth transistor T35 has the first electrode connected to the first power supply terminal VGH, the second electrode connected to the fourteenth node N14, and the gate electrode connected to the ninth node N9; the thirty-sixth transistor T36 has the first electrode connected to the second clock signal terminal CLB, the second electrode connected to the fourteenth node N14, and the gate electrode connected to the eighth node N8; the seventh capacitor C7 has the first electrode connected to the fourteenth node N14, and the second electrode connected to the eighth node N8. The first isolation circuit 18 includes: a thirty-seventh transistor T37, having a first electrode connected to the ninth node N9, a second electrode connected to the twelfth node N12, and a gate electrode connected to the second power supply terminal VGL. The second isolation circuit 19 includes: a thirtyeighth transistor T38 and a thirty-ninth transistor T39, where the thirty-eighth transistor T38 has the first electrode connected to the tenth node N10, the second electrode connected to the fifth node N5, and the gate electrode connected to the second power supply terminal VGL; the thirty-ninth transistor T39 has the first electrode connected to the eleventh node Nil, the second electrode connected to the eighth node N8, and the gate electrode connected to the second power supply terminal VGL. The second reset circuit 110 includes: a fortieth transistor T40, having a first electrode connected to the first power supply terminal VGH, a second electrode connected to the tenth node N10, and a gate electrode connected to the reset signal terminal Re.

[00195] As shown in FIG. 8, it is a timing diagram of each node in a driving method of the shift register unit according to the present disclosure. CLK is the timing diagram at the first clock signal terminal, CLB is the timing diagram at the second clock signal terminal, IN is the timing diagram at the signal input terminal, and OUT(n) is the timing diagram at the signal output terminal.

[00196] In the exemplary embodiment, the twenty-fifth transistor to the fortieth transistor may be P-typc transistors, the first power supply terminal VGH is a high-level signal temiinal, and the second power supply terminal VGL is a low-level signal terminal. The first isolation circuit and the second isolation circuit arc normally turned on.

[00197] The driving method of the shift register unit may include eight stages: a first stage 11, a second stage t2, a third stage t3, a fourth stage t4, a fifth stage t5, a sixth stage t6, a seventh stage t7, and an eighth stage t8. In the first stage tl: the first clock signal temiinal CLK outputs a low-level signal, the second clock signal terminal CLB outputs a high-level signal, the signal input temiinal IN outputs a high-level signal, the twenty-fifth transistor T25 and the twenty-eighth transistor T28 are turned on, the twelfth node N12 and the thirteenth node N13 are written with the low-level signal, the twenty-ninth transistor T29 is turned off under the action of the second clock signal temiinal CLB, the fourth node N4 maintains the high-level signal of the previous stage, the thirtieth transistor T30 is turned off, meanwhile, the twenty-sixth transistor T26 and the twenty-seventh transistor T27 are turned on, the fifth node N5 and the eighth node N8 are written with the high-level signal from the signal input terminal IN, the thirty-second transistor T32 is turned off, and the signal output terminal OUT(n) maintains the low level of the previous stage under the action of the sixth capacitor C6. In the second stage t2: the first clock signal terminal CLK and the signal input terminal IN output a high-level signal, the second clock signal terminal CLB outputs a low-level signal, the twelfth node N12 maintains the low level of the previous stage under the action of the fourth capacitor C4 so as to turn on the twenty-eighth transistor T28, thereby transmitting the low-level signal of the second clock signal temiinal CLB to the fourth node N4, and the thirtieth transistor T30 is turned on under the action of the fourth node N4 so as to transmit the high-level signal of the first power supply terminal VGH to the signal output terminal OUT(n). In the third stage t3: the first clock signal terminal CLK outputs a low-level signal, the second clock signal terminal CLB outputs a high-level signal, the signal input terminal IN outputs a high-level signal, the fourth node N4 maintains the low level of the previous stage, the thirtieth transistor T30 is turned on, and the first power supply terminal VGH inputs a high-level signal to the signal output terminal OUT(n). Hie fourth stage t4, the sixth stage t6. and the second stage t2 have the same driving condition, and the fifth stage t5 and the third stage t3 have the same driving condition. In the seventh stage t7: the first clock signal terminal CLK outputs a low-level signal, the second clock signal terminal CLB outputs a high-level signal, the signal input terminal IN outputs a low-level signal, the fifth node N5 and the eighth node N8 are written with the low-level signal from the signal input terminal IN, the ninth node N9 is written with the low-level signal from the second power supply terminal VGL, the thirty-fourth transistor T34, the thirty-fifth transistor T35, and the thirty-sixth transistor T36 are turned on, the fourteenth node N14 is written with a high-level signal, and under the coupling action of the seventh capacitor C7, the eighth node N8 and the fifth node N5 are pulled high, the fifth node N5 cannot fully turn on the thirty-second transistor T32, such that the signal output terminal OUT(n) maintains the high level of the previous stage. In the eighth stage t8: the first clock signal terminal CLK outputs a high-level signal, the second clock signal terminal CLB outputs a low-level signal, the signal input terminal IN outputs a low-level signal, the second clock signal terminal CLB changes from high level to low level, and correspondingly, the fourteenth node N14 changes from high level to low level, and under the coupling action of the seventh capacitor C7, the eighth node N8 and the fifth node N5 are pulled low, the thirty-second transistor T32 is turned on, the signal output terminal OUT(n) outputs a low-level signal, and meanwhile, under the action of the first pull-up circuit and the second pull-up circuit, the ninth node N9 and the fourth node N4 are pulled high.

[00198] The reset signal terminal Re may input an active signal when the display panel is powered on to turn on the second reset circuit 110 and the first reset circuit 224 so as to respectively reset the tenth node N10 and the first node N1. |00199| In the exemplary embodiment, the gate electrode of the seventh transistor T7 in the fourth switching circuit K4 is connected to the signal output terminal OUT(n^l) of the shift output circuit I in the adjacent previous stage, and the gate electrode of the eighth transistor T8 in the fourth switching circuit K4 is connected to the first clock signal terminal CLK in the shift output circuit 1, such that the latch circuit may turn off the first node and the output terminal of the third inverter during at least a part of the time period in which the gating signal terminal inputs a signal to the first node, and may turn on the first node and the output terminal of the third inverter during at least another part of the time period in which the gating signal terminal inputs a signal to the first node.

[00200] As shown in FIG. 9, it is a schematic structural diagram of another exemplary embodiment of the shift register unit according to the present disclosure. The second control signal sub-terminal CN22 may also be formed by the signal output terminal OUT(n+1) of the shift output circuit 1 in an adjacent next stage. The gating circuit 21 includes a first transistor Tl, a second transistor T2, and a first capacitor Cl, the first transistor Tl having a first electrode connected to the gating signal terminal SM, a gate electrode connected to the second control signal sub-terminal CN22, and a polarity of a turn-on level of the first transistor T1 is opposite to a polarity of an active level of the signal output terminal OUT(n); the second transistor T2 having a first electrode connected to a second electrode of the first transistor Tl, a second electrode connected to the first node Nl, a gate electrode connected to the first control signal sub-terminal CN21, and a polarity of a tum-on level of the second transistor T2 is identical to a polarity of the active level of the signal output terminal OUT(n); the first capacitor C1 having a first electrode connected to the first node Nl and a second electrode connected to a stable voltage terminal, for example, the second electrode of the first capacitor Cl may be connected to the second power supply terminal VGL. The active level of the signal output terminal OUT(n) may be a high level, the first transistor Tl may be a P-type transistor, and the second transistor T2 may be an N-type transistor.

[00201] In this exemplary embodiment, as shown in FIG. 9, the gate driving circuit is for a display panel, the display panel includes a plurality of rows of pixel driving circuits; the driving signal terminal of a last stage shift register unit may not be connected to the pixel driving circuit. This arrangement may allow the gate driving signals received by the pixel driving circuits to have relatively uniform driving capability’, thereby improving display uniformity of the display panel.

[00202] In this exemplary embodiment, as shown in FIG. 9, the fourth switching circuit includes a seventh transistor T7 and an eighth transistor T8, the seventh transistor T7 having a first electrode connected to an output terminal of the third inverter, a second electrode connected to the first node, and a gate electrode connected to the signal output terminal OUT(n) of the current stage shift output circuit; the eighth transistor T8 having a first electrode connected to the output terminal of the third inverter, a second electrode connected to the first node, and a gate electrode connected to the first clock signal terminal CLK. This arrangement likewise allows the latch circuit to turn off the first node and the output terminal of the third inverter during at least a part of a period in which the gating signal terminal inputs a signal to the first node, and to turn on the first node and the output terminal of the third inverter during at least another part of a period in which the gating signal terminal inputs a signal to the first node.

[00203] As shown in FIG. 10, it is a schematic structural diagram of another exemplary embodiment of the shift register unit according to the present disclosure. In this exemplary embodiment, the shift output circuit 1 includes a first output circuit 11 and a second output circuit 12. The first output circuit 11 is connected to the fourth node N4, the first power supply terminal VGH, and the signal output terminal OUT(n) of the shift output circuit 1, and is configured to transmit a signal of the first power supply terminal VGH to the signal output terminal OUT(n) in response to a signal of the fourth node N4. The second output circuit 12 is connected to the fifth node N5, the second power supply terminal VGL, and the signal output terminal OUT(n) of the shift output circuit 1, and is configured to transmit a signal of the second power supply terminal VGL to the signal output terminal OUT(n) in response to a signal of the fifth node N5. The signal output terminal OUT(n) is configured to output the output signal. The gating circuit 21 is connected to a plurality of the second control signal terminals CN2, among which are included a third control signal subterminal CN23 and a fourth control signal sub-terminal CN24. where the fourth node N4 of the shift output circuit 1 in the current stage forms the third control signal sub-terminal CN23, and the fifth node N5(n+1) of a shift output circuit 1 in an adjacent next stage forms the fourth control signal sub-terminal CN24. The gating circuit 21 is connected to a plurality of gating signal terminals SM, among which are included a first gating signal terminal SM 1 and a second gating signal terminal SM2. The gating circuit 21 is also connected to a third control signal terminal CN3, and is configured to transmit a signal of the first gating signal terminal SMI to the first node N1 in response to signals of the third control signal terminal CN3 and the third control signal sub-terminal CN23, and to transmit a signal of the second gating signal terminal SM2 to the first node N1 in response to signals of the third control signal terminal CN3 and the fourth control signal sub-terminal CN24.

[00204] In this exemplary embodiment, as shown in FIG. 10, the regulating circuit 22 is connected to a plurality of the first control signal terminals CN1, the plurality of the first control signal terminals CN1 connected to the regulating circuit 22 include a fifth control signal sub-terminal CN15 and a sixth control signal sub-terminal CN16, where the fifth control signal sub-terminal CN15 is formed by the fourth node N4 of the shift output circuit 1 in the current stage, and the sixth control signal sub-terminal CNI6 is formed by the fifth node N5 of the shift output circuit 1 in the current stage. The regulating circuit 22 includes a first switching circuit 225, a second switching circuit 226, and athird output circuit 227. The first switching circuit 225 is connected to the sixth control signal sub-terminal CN16, the first node N1, and the sixth node N6, and is configured to transmit a signal of the sixth control signal sub-terminal CN16 to the sixth node N6 in response to a signal of the first node N1. The second switching circuit 226 is connected to the fifth control signal sub-terminal CN15, the first node Nl, and the seventh node N7, and is configured to transmit a signal of the fifth control signal sub-terminal CN 15 to the seventh node N7 in response to a signal of the first node N1. The third output circuit 227 is connected to the sixth node N6, the seventh node N7, the first power supply terminal VGH. and the second power supply terminal VGL, and is configured to transmit a power supply signal of the second power supply terminal VGL to the driving signal terminal Gate in response to a signal of the sixth node N6, and to transmit a power supply signal of the first power supply terminal VGH to the driving signal terminal Gate in response to a signal of the seventh node N7.

[00205] In the present exemplary embodiment, the second output circuit 12 is further connected to an eighth node N8, and the second output circuit 12 is further configured to transmit a signal of the eighth node N8 to the fifth node N5 in response to a signal of the eighth node N8. The regulating circuit 22 further includes: a third switching circuit 228, the third switching circuit 228 being connected to the sixth node N6 and the eighth node N8, and configured to transmit a signal of the eighth node N8 to the sixth node N6 in response to a signal of the eighth node N8.

[00206] In the present exemplary embodiment, the gating circuit 21 includes: a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19, and a second capacitor C2, where the sixteenth transistor T16 has a first electrode connected to the first gating signal terminal SMI, and a gate electrode connected to the third control signal terminal CN3; the seventeenth transistor T17 has a first electrode connected to a second electrode of the sixteenth transistor T16, a second electrode connected to the first node N1, and a gate electrode connected to the third control signal sub-terminal CN23; the eighteenth transistor T18 has a first electrode connected to the second gating signal terminal SM2, and a gate electrode connected to the third control signal terminal CN3; the nineteenth transistor T19 has a first electrode connected to a second electrode of the eighteenth transistor T18, a second electrode connected to the first node N1, and a gate electrode connected to the fourth control signal sub-terminal CN24; the second capacitor C2 has a first electrode connected to the first node N1, and a second electrode connected to the seventh node N7. The first switching circuit 225 includes: a twentieth transistor T20, where the twentieth transistor T20 has a first electrode connected to the sixth control signal sub-terminal CN16, a second electrode connected to the sixth node N6, and a gate electrode connected to the first node Nl. The second switching circuit 226 includes: a twenty-first transistor T21, where the twenty-first transistor T21 lias a first electrode connected to the fifth control signal sub-terminal CN15, a second electrode connected to the seventh node N7, and a gate electrode connected to the first node N1. The third switching circuit 228 includes: a twenty-fourth transistor T24, the twenty-fourth transistor T24 has a first electrode connected to the eighth node N8, a second electrode connected to the sixth node N6, and a gate electrode connected to the eighth node N8. The third output circuit 227 includes: a twenty-second transistor T22, a twenty-third transistor T23, and a third capacitor C3, where the twenty-second transistor T22 has a first electrode connected to the first power supply terminal VGH, a second electrode connected to the driving signal terminal Gate, and a gate electrode connected to the seventh node N7; the twenty-third transistor T23 has a first electrode connected to the second power supply terminal VGL, a second electrode connected to the driving signal terminal Gate, and a gate electrode connected to the sixth node N6; the third capacitor C3 has a first electrode connected to the seventh node N7, and a second electrode connected to the first power supply terminal VGH.

[00207] In the present exemplary embodiment, the multi-stage cascaded shift register units may provide the first gating signal terminal via a first signal line, provide the second gating signal terminal via a second signal line, and provide the third control signal terminal via a third signal line.

[00208] In the present exemplary embodiment, the sixteenth transistor through the twenty-fourth transistor may be P-type transistors, the first power supply terminal VGH is a high-level signal terminal, and the second power supply terminal VGL is a low-level signal terminal.

[00209] As shown m FIG. 11, FIG. 11 is a timing diagram of each node in a driving method of the shift register unit shown in FIG. 10. In the timing diagram, N4 is a timing diagram of the fourth node, N5(n+1) is a timing diagram of the fifth node in shift output circuit in an adjacent previous stage, CN3 is a timing diagram of the third control signal terminal, MSI is a timing diagram of tire first gating signal terminal, MS2 is a timing diagram of the second gating signal terminal, and OUT(n) is a timing diagram of the signal output terminal in the shift output circuit in the current stage.

[00210] When the display panel does not switch the refresh frequency, the display panel may output a valid pulse signal via the third control signal terminal CN3 in a first stage tl before the start of a frame refresh, at this time, the fifth node N5 in all the shift register units is at a low level, the fourth node N4 is at a high level, the nineteenth transistor T19 and the eighteenth transistor T18 are turned on, the first node N1 is written with a low-level signal from the second gating signal terminal MS2, the twenty-first transistor T21 and the twentieth transistor T20 are turned on, the fifth node N5 and the sixth node N6 are connected, the fourth node N4 and the seventh node N7 are connected, and the driving signal terminal Gate outputs the same signal as the signal output terminal OUT(n). In the present exemplary embodiment, the first stage tl may be located at a last period of a blank period between frames.

[00211] When a partial area of the display panel needs to switch from a high refresh frequency to a low refresh frequency, the display panel may output a second valid level pulse via the third control signal terminal CN3 in a second stage t2 at the end of a high refresh period. For the shift register unit in the current stage, at this time, the signal output terminal of the shift output circuit outputs a low-level signal, the fourth node N4 is at a high level, the fifth node N5(n+1) in an adjacent next stage shift output circuit is at a low level, the eighteenth transistor T18 and the nineteenth transistor T19 are turned on, the first node N1 is written with a high-level signal from the second gating signal terminal, the twentieth transistor T20 and the twenty-first transistor T21 are turned off, the sixth node N6 maintains the low level of the previous stage, the seventh node N7 maintains the high level of the previous stage, and the driving signal terminal Gate continues to output a low-level signal, thereby switching the pixel driving circuit connected to the shift register unit in the current stage to a low refresh frequency. For other shift register units, if at this time the signal output terminal of the shift output circuit outputs a high-level signal, the fourth node N4 is at a low level, the fifth node N5(n+1) in an adjacent next stage shift output circuit is at a high level, the sixteenth transistor T16 and the seventeenth transistor T17 arc turned on, the first node N1 is written with a low-level signal from the first gating signal terminal MSI, the twentieth transistor T20 and the twenty-first transistor T21 are turned on, the sixth node N6 is written with a high-level signal, the seventh node N7 is written with a low-level signal, and the driving signal terminal Gate outputs a high-level signal, such that other shift register units may normally output. In addition, when the signal output terminal switches from the high level to the low level, the driving signal terminal Gate may also switch to output a low-level signal, that is, the driving method does not affect other shift register units outputting driving signals for maintaining a high refresh frequency. |00212|When a partial area of the display panel needs to switch from a low refresh frequency to a high refresh frequency, the display panel may output a third valid level pulse via the third control signal terminal CN3 in a third stage t3 at the end of a low refresh period. For the shift register unit in the current stage, at this time, the signal output terminal of the shift output circuit outputs a low-level signal, the fourth node N4 is at a high level, the fifth node N5(n+1) in an adjacent next stage shift output circuit is at a low level, the eighteenth transistor T18 and the nineteenth transistor T19 are turned on, the first node N I is written with a low-level signal from the second gating signal terminal, the twentieth transistor T20 and the twenty-first transistor T21 are turned on, the sixth node N6 is connected to the fifth node N5, the fourth node N4 is connected to the seventh node N7, and the driving signal terminal Gate outputs the same signal as the signal output terminal, thereby switching the pixel driving circuit connected to the shift register unit in the current stage to a high refresh frequency. For other shift register units, if at this time the signal output terminal of the shift output circuit outputs a high-level signal, the fourth node N4 is at a low level, the fifth node N5(n+1) in an adjacent next stage shift output circuit is at a high level, the sixteenth transistor T16 and the seventeenth transistor T17 are turned on, the first node N1 is written with a high-level signal from the first gating signal terminal MSI, the twentieth transistor T20 and the twenty-first transistor T21 are turned off, the sixth node N6 maintains the low level of the previous stage, the seventh node N7 maintains the high level of the previous stage, and the driving signal terminal Gate outputs a low-level signal, that is, the driving method does not affect other shift register units outputting driving signals for maintaining a low refresh frequency.

[00213] As shown in FIG. 10, the structure of the shift output circuit 1 may be the same as the structure of the shift output circuit shown in FIG. 6, and details are omitted herein.

[00214] According to one aspect of the present disclosure, a driving method of a gate electrode driving circuit is provided, the driving method including:

[00215] shifting and outputting an output signal by using the shift output circuit;

[00216] controlling the control circuit to output a first driving signal or a second driving signal by using a gating signal, where the first driving signal is the same as the output signal, and the second driving signal is an invalid level signal.

[00217] According to one aspect of the present disclosure, a display panel is provided, the display panel including the above gate electrode driving circuit.

[00218] The present exemplary embodiment further provides a display device including the above display panel. The display device may be a mobile phone, atablet computer, a television, or another display device.

[00219] Those skilled m the art, after considering the specification and practicing the disclosure herein, will readily conceive of other embodiments of the present disclosure. Tire present application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common general knowledge or conventional technical means in the art that are not disclosed herein. Hie specification and embodiments should be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.

[00220] The drawings in the present disclosure only relate to the structures involved in the present disclosure, and other structures may refer to conventional designs. Where there is no conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other to obtain new embodiments. Those of ordinary skill in the art should understand that modifications or equivalent substitutions may be made to the technical solutions of the present disclosure without departing from the spirit and scope of the technical solutions of the present disclosure, and such modifications or equivalent substitutions should be included within the scope of the claims of the present disclosure.

[00221] It should be understood that the present disclosure is not limited to the precise structures described above and shown in the drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is only defined by the appended claims.

Claims

1. A gate driving circuit, comprising a plurality of stages of cascaded shift register units, wherein the shift register unit comprises:a shift output circuit, configured to convert an input signal into a shift-output output signal, wherein the shift output circuit comprises a plurality of signal terminals; anda control circuit, connected to at least part of the signal terminals in the at least one shift output circuit, to a gating signal terminal and to a driving signal terminal;wherein the signal terminals connected to the control circuit and located in the shift output circuit comprise one or a plurality of control signal terminals, wherein the control circuit is configured to input a first driving signal or a second driving signal to the driving signal terminal in response to a signal on the gating signal terminal and a signal on the control signal terminal, wherein the first driving signal is the same as the output signal, and the second driving signal is an invalid level signal.

2. The gate driving circuit according to claim 1, wherein the signal on the control signal terminal and the output signal output by the shift output circuit in a current stage have pulse signals that are at least partially overlapped.

3. The gate driving circuit according to claim 1, wherein the control signal terminal comprises one or a plurality of first control signal terminals;the control circuit comprises:a gating circuit, connected to the gating signal terminal and a first node, wherein the gating circuit is configured to transmit a signal from the gating signal terminal to the first node in response to a control signal; anda regulating circuit, connected to the first node, the first control signal terminal and the driving signal terminal, wherein the regulating circuit is configured to input the first driving signal or the second driving signal to the driving signal terminal in response to signals from the first node and the first control signal terminal.

4. The gate driving circuit according to claim 3, wherein the control signal terminals further comprise one or a plurality of second control signal terminals;wherein the gating circuit is connected to the second control signal terminal and is configured to transmit a signal from the gating signal terminal to the first node in response to a signal on the second control signal terminal.

5. The gate driving circuit according to claim 4, wherein the first control signal terminal is formed by a signal terminal in the shift output circuit in a current stage; and / or,the gating circuit is connected to the plurality of second control signal terminals, and the plurality of second control signal terminals connected to the gating circuit are formed by signal terminals of shift output circuits in two adjacent stages.

6. The gate driving circuit according to claim 4 or 5, wherein the shift output circuit comprises a signal output terminal, and the signal output terminal is configured to output the output signal;wherein the gating circuit is connected to the plurality of second control signal terminals, the plurality of second control signal terminals connected to the gating circuit comprise a first control signal sub-terminal and a second control signal sub-terminal, the first control signal sub-terminal is formed by the signal output terminal of the shift output circuit in the current stage, and the second control signal sub-tenninal is formed by the signal output terminal of the shift output circuit in an adjacent stage; andwherein the gating circuit is configured to transmit the signal from the gating signal terminal to the first node in response to a signal on the first control signal sub-tenninal and a signal on the second control signal sub-terminal.

7. The gate driving circuit according to any one of claims 3-6, wherein the first control signal terminal is formed by a signal output terminal in the shift output circuit in a current stage;the regulating circuit comprises:a NAND gate, wherein a first input terminal of the NAND gate is connected to the first control signal terminal, and a second input terminal of the NAND gate is connected to the first node; anda first inverter, wherein an input terminal of the first inverter is connected to an output terminal of the NAND gate, and an output terminal of the first inverter is connected to the driving signal terminal.

8. The gate driving circuit according to claim 6, wherein the second control signal sub-terminal is formed by the signal output terminal of the shift output circuit in an adjacent previous stage; or,the second control signal sub-terminal is formed by the signal output terminal of the shift output circuitin an adjacent next stage.

9. The gate driving circuit according to claim 8, wherein the gate driving circuit is used for a display panel, and the display panel comprises a plurality of rows of pixel driving circuits;when the second control signal sub-terminal is formed by the signal output terminal of the shift output circuit in the adjacent previous stage, the driving signal terminal of the shift register unit in a first stage is not connected to the pixel driving circuit; andwhen the second control signal sub-terminal is formed by the signal output terminal of the shift output circuit in the adjacent next stage, the driving signal terminal of the shift register unit in a last stage is not connected to the pixel driving circuit.

10. The gate driving circuit according to any one of claims 3-9, wherein the regulating circuit comprises:a latch circuit, connected to the first node and configured to latch a voltage input from the gating signal terminal to the first node.

11. The gate driving circuit according to any one of claims 3-10, wherein the regulating circuit further comprises:a first reset circuit, connected to the first node, a reset signal terminal and a first power supply terminal and configured to transmit a signal from the first power supply terminal to the first node in response to a signal on the reset signal terminal.

12. The gate driving circuit according to claim 8 or 9, wherein when the second control signal subterminal is formed by the signal output terminal of the shift output circuit in the adjacent previous stage, the gating circuit comprises:a first transistor, wherein a first electrode of the first transistor is connected to the gating signal terminal, a gate electrode of the first transistor is connected to the first control signal sub-terminal, and a polarity of a turn-on level of the first transistor is opposite to a polarity of an active level of the signal output terminal;a second transistor, wherein a first electrode of the second transistor is connected to a second electrode of the first transistor, a second electrode of the second transistor is connected to the first node, a gateelectrode of the second transistor is connected to the second control signal sub-terminal, and a polarity of a turn-on level of the second transistor and the polarity of the active level of the signal output terminal are identical;a first capacitor, a first electrode of the first capacitor is connected to the first node, and a second electrode of the first capacitor is connected to a stable voltage terminal;wherein when the second control signal sub-terminal is formed by the signal output terminal of the shift output circuit in the adjacent next stage, the gating circuit comprises:a first transistor, a first electrode of the first transistor is connected to the gating signal terminal, a gate electrode of the first transistor is connected to the second control signal sub-terminal, and the polarity of the turn-on level of the first transistor is opposite to the polarity of the active level of the signal output terminal;a second transistor, a first electrode of the second transistor is connected to a second electrode of the first transistor, a second electrode of the second transistor is connected to the first node, a gate electrode of the second transistor is connected to the first control signal sub-terminal, and the polarity of the turn-on level of the second transistor and the polarity of the active level of the signal output terminal are identical; anda first capacitor, a first electrode of the first capacitor is connected to the first node, and a second electrode of the first capacitor is connected to a stable voltage terminal.

13. The gate driving circuit according to any one of claims 8, 9 or 12. wherein the first control signal terminal is formed by the signal output terminal in the shift output circuit in the current stage;the regulating circuit comprises:a NAND gate, wherein a first input terminal of the NAND gate is connected to the first control signal tenninaL and a second input terminal of the NAND gate is connected to the first node;a first inverter, wherein an input terminal of the first inverter is connected to an output terminal of the NAND gate, and an output terminal of the first inverter is connected to the driving signal terminal; anda latch circuit, connected to the first node and configured to latch a voltage input from the gating signal terminal to the first node;wherein the latch circuit comprises:a second inverter, wherein an input terminal of the second inverter is connected to the first node;a third inverter, wherein an input terminal of the third inverter is connected to an output terminal ofthe second inverter, and an output terminal of the third inverter is connected to the second input terminal of the NAND gate; anda fourth switching circuit, connected to the first node and the output terminal of the third inverter, configured to turn off the first node and the output terminal of the third inverter during at least part of a time period in which the gating signal terminal inputs the signal to the first node, and configured to turn on the first node and the output terminal of the third inverter during at least another part of the time period in which the gating signal terminal inputs the signal to the first node.

14. The gate driving circuit according to claim 13, wherein the second inverter comprises:a third P-type transistor, wherein a first electrode of the third P-type transistor is connected to a first power supply terminal at a high level, a second electrode of the third P-type transistor is connected to a second node, and a gate electrode of the third P-type transistor is connected to the first node; anda fourth N-type transistor, wherein a first electrode of the fourth N-type transistor is connected to a second power supply terminal at a low level, a second electrode of the fourth N-type transistor is connected to the second node, and a gate electrode of the fourth N-type transistor is connected to the first node;wherein the third inverter comprises:a fifth P-type transistor, wherein a first electrode of the fifth P-type transistor is connected to the first power supply terminal, a second electrode of the fifth P-type transistor is connected to the second input terminal of the NAND gate, and a gate electrode of the fifth P-type transistor is connected to the second node;a sixth N-type transistor, wherein a first electrode of the sixth N-type transistor is connected to the second power supply terminal, a second electrode of the sixth N-type transistor is connected to the second input terminal of the NAND gate, and a gate electrode of the sixth N-type transistor is connected to the second node;wherein when the second control signal sub-terminal is formed by the signal output terminal of the shift output circuit in the adjacent previous stage, the fourth switching circuit comprises:a seventh transistor, wherein a first electrode of the seventh transistor is connected to the second input terminal of the NAND gate, a second electrode of the seventh transistor is connected to the first node, and a gate electrode of the seventh transistor is connected to the signal output terminal of the shift output circuit in the adjacent previous stage;an eighth transistor, wherein a first electrode of the eighth transistor is connected to the second inputterminal of the NAND gate, a second electrode of the eighth transistor is connected to the first node, and a gate electrode of the eighth transistor is connected to a first clock signal terminal;wherein when the second control signal sub-terminal is formed by the signal output terminal of the shift output circuit in the adjacent next stage, the fourth switching circuit comprises:a seventh transistor, wherein a first electrode of the seventh transistor is connected to the second input terminal of the NAND gate, a second electrode of the seventh transistor is connected to the first node, and a gate electrode of the seventh transistor is connected to the signal output terminal of the shift output circuit in the current stage; andan eighth transistor, wherein a first electrode of the eighth transistor is connected to the second input terminal of the NAND gate, a second electrode of the eighth transistor is connected to the first node, and a gate electrode of the eighth transistor is connected to the first clock signal terminal.

15. The gate driving circuit according to claim 7, wherein the NAND gate comprises:a ninth P-type transistor, wherein a first electrode of the ninth P-type transistor is connected to a first power supply terminal, a second electrode of the ninth P-type transistor is connected to a third node, and a gate electrode of the ninth P-typc transistor is connected to the first input terminal of the NAND gate;a tenth P-type transistor, wherein a first electrode of the tenth P-type transistor is connected to the first power supply terminal, a second electrode of the tenth P-type transistor is connected to the third node, and a gate electrode of the tenth P-type transistor is connected to the second input terminal of the NAND gate;an eleventh N-type transistor, wherein a first electrode of the eleventh N-type transistor is connected to the third node, and a gate electrode of the eleventh N-type transistor is connected to the first input terminal of the NAND gate; anda twelfth N-type transistor, wherein a first electrode of the twelfth N-type transistor is connected to a second electrode of the eleventh N-type transistor, a second electrode of the twelfth N-type transistor is connected to a second power supply terminal, and a gate electrode of the twelfth N-type transistor is connected to the second input terminal of the NAND gate;wherein the first inverter comprises:a thirteenth P-type transistor, wherein a first electrode of the thirteenth P-type transistor is connected to the first power supply terminal, a second electrode of the thirteenth P-type transistor is connected to the driving signal terminal, and a gate electrode of the thirteenth P-type transistor is connected to the output tenninal of the NAND gate; anda fourteenth N-type transistor, wherein a first electrode of the fourteenth N-type transistor is connected to the second power supply terminal, a second electrode of the fourteenth N-type transistor is connected to the driving signal terminal, and a gate electrode of the fourteenth N-type transistor is connected to the output terminal of the NAND gate.

16. The gate driving circuit according to claim 11, wherein the first reset circuit comprises:a fifteenth transistor, wherein a first electrode of the fifteenth transistor is connected to the first power supply terminal, a second electrode of the fifteenth transistor is connected to the first node, and a gate electrode of the fifteenth transistor is connected to the reset signal terminal.

17. The gate driving circuit according to any one of claims 4-6, wherein the shift output circuit comprises:a first output circuit, connected to a fourth node, a first power supply terminal, and a signal output terminal of the shift output circuit, wherein the first output circuit is configured to transmit a signal of the first power supply terminal to the signal output terminal in response to a signal of the fourth node;a second output circuit, connected to a fifth node, a second power supply terminal, and the signal output terminal of the shift output circuit, wherein the second output circuit is configured to transmit a signal of the second power supply terminal to the signal output terminal in response to a signal of the fifth node, and the signal output terminal is configured to output the output signal;wherein the gating circuit is connected to the plurality of second control signal terminals, the plurality of second control signal terminals connected to the gating circuit comprise a third control signal subterminal and a fourth control signal sub-terminal, the fourth node of the shift output circuit in the current stage forms the third control signal sub-terminal, and the fifth node of the shift output circuit in the adjacent next stage forms the fourth control signal sub-tenninahwherein the gating circuit is connected to a plurality of gating signal terminals, the plurality of gating signal terminals connected to the gating circuit comprise a first gating signal terminal and a second gating signal terminal;wherein the gating circuit is further connected to a third control signal terminal, and is configured to transmit a signal of the first gating signal terminal to the first node in response to signals of the third control signal terminal and the third control signal sub-terminal, and to transmit a signal of the second gating signal terminal to the first node in response to signals of the third control signal terminal and the fourth controlsignal sub-terminal.

18. The gate driving circuit according to claim 17, wherein the regulating circuit is connected to a plurality of first control signal terminals, the plurality of first control signal terminals connected to the regulating circuit comprise a fifth control signal sub-terminal and a sixth control signal sub-terminal, the fifth control signal sub-terminal being formed by the fourth node in the shift output circuit in the current stage, and the sixth control signal sub-terminal being formed by the fifth node in the shift output circuit in the current stage;wherein the regulating circuit comprises:a first switching circuit, connected to the sixth control signal sub-tenninal, the first node, and a sixth node, and configured to transmit a signal of the sixth control signal sub-terminal to the sixth node in response to a signal of the first node;a second switching circuit, connected to the fifth control signal sub-terminal, the first node, and a seventh node, and configured to transmit a signal of the fifth control signal sub-tenninal to the seventh node in response to the signal of the first node;a third output circuit, connected to the sixth node, the seventh node, the first power supply terminal, and the second power supply terminal, and configured to transmit a power supply signal of the second power supply terminal to the driving signal terminal in response to a signal of the sixth node, and to transmit a power supply signal of the first power supply terminal to the driving signal terminal in response to a signal of the seventh node.

19. The gate driving circuit according to claim 18, wherein the second output circuit is further connected to an eighth node, and is further configured to transmit a signal of the eighth node to the fifth node in response to a signal of the eighth node;wherein the regulating circuit further comprises:a third switching circuit, connected to the sixth node and the eighth node, and configured to transmit a signal of the eighth node to the sixth node in response to a signal of the eighth node.

20. The gate driving circuit according to claim 19, wherein the gating circuit comprises:a sixteenth transistor, wherein a first electrode of the sixteenth transistor is connected to the first gating signal terminal, and a gate electrode of the sixteenth transistor is connected to the third control signalterminal;a seventeenth transistor, wherein a first electrode of the seventeenth transistor is connected to a second electrode of the sixteenth transistor, a second electrode of the seventeenth transistor is connected to the first node, and a gate electrode of the seventeenth transistor is connected to the third control signal sub-tenninal;an eighteenth transistor, wherein a first electrode of the eighteenth transistor is connected to the second gating signal terminal, and a gate electrode of the eighteenth transistor is connected to the third control signal terminal;a nineteenth transistor, wherein a first electrode of the nineteenth transistor is connected to a second electrode of the eighteenth transistor, a second electrode of the nineteenth transistor is connected to the first node, and a gate electrode of the nineteenth transistor is connected to the fourth control signal sub-terminal;a second capacitor, wherein a first electrode of the second capacitor is connected to the first node, and a second electrode of the second capacitor is connected to the seventh node;wherein the first switching circuit comprises:a twentieth transistor, wherein a first electrode of the twentieth transistor is connected to the sixth control signal sub-terminal, a second electrode of the twentieth transistor is connected to the sixth node, and a gate electrode of the twentieth transistor is connected to the first node;wherein the second switching circuit comprises:a twenty-first transistor, wherein a first electrode of the twenty-first transistor is connected to the fifth control signal sub-tenninal, a second electrode of the twenty-first transistor is connected to the seventh node, and a gate electrode of the twenty-first transistor is connected to the first node;wherein the third switching circuit comprises:a twenty-fourth transistor, wherein a first electrode of the twenty-fourth transistor is connected to the eighth node, a second electrode of the twenty-fourth transistor is connected to the sixth node, and a gate electrode of the twenty-fourth transistor is connected to the eighth node;wherein the third output circuit comprises:a twenty-second transistor, wherein a first electrode of the twenty-second transistor is connected to the first power supply terminal, a second electrode of the twenty-second transistor is connected to the driving signal terminal, and agate electrode of the twenty-second transistor is connected to the seventh node;a twenty-third transistor, wherein a first electrode of the twenty-third transistor is connected to the second power supply terminal, a second electrode of the twenty-third transistor is connected to the driving signal terminal, and a gate electrode of the twenty-third transistor is connected to the sixth node; anda third capacitor, wherein a first electrode of the third capacitor is connected to the seventh node, and a second electrode of the third capacitor is connected to the first power supply terminal.

21. The gate driving circuit according to any one of claims 1-20, wherein the shift output circuit comprises:a first input circuit, connected to a second power supply terminal, a first clock signal terminal, and a ninth node, and configured to transmit a signal of the second power supply terminal to the ninth node in response to a signal of the first clock signal terminal;a second input circuit, connected to a signal input terminal, the first clock signal terminal, a tenth node, and an eleventh node, and configured to transmit a signal of the signal input terminal to the tenth node and the eleventh node in response to a signal of the first clock signal terminal;a first output circuit, connected to a twelfth node, a thirteenth node, a fourth node, a second clock signal terminal, a first power supply terminal, and a signal output terminal, wherein the first output circuit is configured to transmit a signal of the second clock signal terminal to the thirteenth node in response to a signal of the twelfth node, to transmit a signal of the thirteenth node to the fourth node in response to a signal of the second clock signal terminal, and to transmit a power supply signal of the first power supply terminal to the signal output terminal in response to a signal of the fourth node, wherein the twelfth node is connected to the ninth node;a second output circuit, connected to an eighth node, a fifth node, the second power supply terminal, and the signal output terminal, wherein the second output circuit is configured to transmit a signal of the eighth node to the fifth node in response to a signal of the eighth node, and to transmit the signal of the second power supply terminal to the signal output terminal in response to a signal of the fifth node, wherein the eighth node is connected to the eleventh node, and the tenth node is connected to the fifth node;a first pull-up circuit, connected to the tenth node, the first power supply terminal, and the fourth node, and configured to transmit a signal of the first power supply terminal to the fourth node in response to a signal of the tenth node;a second pull-up circuit, connected to the tenth node, the first clock signal terminal, and the ninth node, and configured to transmit a signal of the first clock signal terminal to the ninth node in response to a signal of the tenth node;a coupling circuit, connected to the ninth node, the first power supply terminal, a fourteenth node, the eighth node, and the second clock signal terminal, and configured to transmit the signal of the first powersupply terminal to the fourteenth node in response to a signal of the ninth node, to transmit the signal of the second clock signal terminal to the fourteenth node in response to the signal of the eighth node, and to couple a signal on the fourteenth node to the eighth node;wherein the signal input terminal of the shift output circuit in a first stage is connected to an initial signal, and the signal input terminal of another shift output circuit is connected to the signal output terminal of the shift output circuit in an adjacent previous stage.

22. The gate driving circuit according to claim 21, wherein the shift output circuit further comprises:a first isolation circuit, connected to the ninth node, the twelfth node and the second power supply terminal, and configured to communicate the ninth node with the twelfth node in response to the signal of the second power supply terminal;a second isolation circuit connected to the tenth node, the eleventh node, the second power supply terminal, the fifth node and the eighth node, and configured to communicate the tenth node with the fifth node, and to communicate the eleventh node with the eighth node, in response to the signal of the second power supply terminal; anda second reset circuit, connected to the first power supply terminal, a reset signal terminal, and the tenth node, and configured to transmit a signal of the first power supply terminal to the tenth node in response to a signal of the reset signal terminal.

23. The gate driving circuit according to claim 22, wherein the first input circuit comprises:a twenty-fifth transistor, wherein a first electrode of the twenty-fifth transistor is connected to the second power supply terminal, a second electrode of the twenty-fifth transistor is connected to the ninth node, and a gate electrode of the twenty-fifth transistor is connected to the first clock signal terminal;wherein the second input circuit comprises:a twenty-sixth transistor, wherein a first electrode of the twenty-sixth transistor is connected to the signal input terminal, a second electrode of the twenty-sixth transistor is connected to the tenth node, and a gate electrode of the twenty-sixth transistor is connected to the first clock signal terminal;a twenty-seventh transistor, wherein a first electrode of the twenty-seventh transistor is connected to the signal input terminal, a second electrode of the twenty-seventh transistor is connected to the eleventh node, and a gate electrode of the twenty-seventh transistor is connected to the first clock signal terminal;wherein the first output circuit comprises:a twenty-eighth transistor, wherein a first electrode of the twenty-eighth transistor is connected to the second clock signal terminal, a second electrode of the twenty-eighth transistor is connected to the thirteenth node, and a gate electrode of the twenty-eighth transistor is connected to the twelfth node;a twenty-ninth transistor, wherein a first electrode of the twenty-ninth transistor is connected to the thirteenth node, a second electrode of the twenty-ninth transistor is connected to the fourth node, and a gate electrode of the twenty-ninth transistor is connected to the second clock signal terminal;a thirtieth transistor, wherein a first electrode of the thirtieth transistor is connected to the first power supply terminal, a second electrode of the thirtieth transistor is connected to the signal output terminal, and a gate electrode of the thirtieth transistor is connected to the fourth node;a fourth capacitor, wherein a first electrode of the fourth capacitor is connected to the twelfth node, and a second electrode of the fourth capacitor is connected to the thirteenth node;a fifth capacitor, wherein a first electrode of the fifth capacitor is connected to the fourth node, and a second electrode of the fifth capacitor is connected to the first power supply terminal;wherein the second output circuit comprises:a thirty-first transistor, wherein a first electrode of the thirty-first transistor is connected to the fifth node, a second electrode of the thirty-first transistor is connected to the eighth node, and a gate electrode of the thirty-first transistor is connected to the eighth node;a thirty-second transistor, wherein a first electrode of the thirty-second transistor is connected to the second power supply terminal, a second electrode of the thirty-second transistor is connected to the signal output terminal, and a gate electrode of the thirty-second transistor is connected to the fifth node;a sixth capacitor, wherein a first electrode of the sixth capacitor is connected to the signal output terminal, and a second electrode of the sixth capacitor is connected to the second power supply terminal;wherein the first pull-up circuit comprises:a thirty-third transistor, wherein a first electrode of the thirty-third transistor is connected to the first power supply terminal, a second electrode of the thirty-third transistor is connected to the fourth node, and a gate electrode of the thirty -third transistor is connected to the tenth node;wherein the second pull-up circuit comprises:a thirty-fourth transistor, wherein a first electrode of the thirty-fourth transistor is connected to the first clock signal terminal, a second electrode of the thirty-fourth transistor is connected to the ninth node, and a gate electrode of the thirty-fourth transistor is connected to the tenth node;wherein the coupling circuit comprises:a thirty-fifth transistor, wherein a first electrode of the thirty-fifth transistor is connected to the first power supply terminal, a second electrode of the thirty-fifth transistor is connected to the fourteenth node, and a gate electrode of the thirty-fifth transistor is connected to the ninth node;a thirty-sixth transistor, wherein a first electrode of the thirty-sixth transistor is connected to the second clock signal terminal, a second electrode of the thirty-sixth transistor is connected to the fourteenth node, and a gate electrode of the thirty-sixth transistor is connected to the eighth node;a seventh capacitor, wherein a first electrode of the seventh capacitor is connected to the fourteenth node, and a second electrode of the seventh capacitor is connected to the eighth node;wherein the first isolation circuit comprises:a thirty-seventh transistor, wherein a first electrode of the thirty-seventh transistor is connected to the ninth node, a second electrode of the thirty-seventh transistor is connected to the twelfth node, and a gate electrode of the thirty-seventh transistor is connected to the second power supply terminal;wherein the second isolation circuit comprises:a thirty-eighth transistor, wherein a first electrode of the thirty-eighth transistor is connected to the tenth node, a second electrode of the thirty-eighth transistor is connected to the fifth node, and a gate electrode of the thirty-eighth transistor is connected to the second power supply terminal;a thirty-ninth transistor, wherein a first electrode of the thirty-ninth transistor is connected to the eleventh node, a second electrode of the thirty-ninth transistor is connected to the eighth node, and a gate electrode of the thirty-nmth transistor is connected to the second power supply terminal;wherein the second reset circuit comprises:a fortieth transistor, wherein a first electrode of the fortieth transistor is connected to the first power supply terminal, a second electrode of the fortieth transistor is connected to the tenth node, and a gate electrode of the fortieth transistor is connected to the reset signal terminal.

24. A method for driving a gate driving circuit, wherein the method is configured to drive the gate driving circuit according to any one of claims 1-23, the method comprises: shifting and outputting an output signal by using the shift output circuit; andcontrolling the control circuit to output a first driving signal or a second driving signal by using a gating signal, wherein the first driving signal and the output signal are identical, and the second driving signal is an invalid level signal.

25. A display panel, wherein the display panel comprises the gate driving circuit according to any oneof claims 1-23.

26. A display device, wherein the display device comprises the display panel according to claim 25.PCT / CN2023 / 122265A. CLASSIFICATION OF SUBJECT MATTER G09G3 / 3266(2016.01)i; G09G3 / 3208(2016.01)i; G06F9 / 30(2018.01)i According to International Patent Classification (IPC) or to both national classification and IPC B. FIELDS SEARCHED Minimum documentation searched (classification system followed by classification symbols) IPC:G09G G06F Documentation searched other than minimum documentation to the extent that such documents are included in the fields searched Electronic data base consulted during the international search (name of data base and, where practicable, search terms used) CNABS; CNTXT; CNKI; VEN; WOTXT; USTXT; EPTXT: EM EM iztifiL shift register, grid drive, scan drive, control, reverse phase, latch C. DOCUMENTS CONSIDERED TO BE RELEVANT Category* Citation of document, with indication, where appropriate, of the relevant passages Relevant to claim No. X CN 113793570 A (HEFEI BOE JOINT TECHNOLOGY CO., LTD. et al.) 14 December 2021 (2021-12-14) description, paragraphs [0079]-[0371], and figures 1-29 1-6, 10, 11,24-26 X v A. CN 114464133 A (HEFEI BOE JOINT TECHNOLOGY CO., LTD. et al.) 10 May 2022 (2022-05-10) description, paragraphs [0077]-[0274], and figures 1A-12 CN 115050412 A (BOE TECHNOLOGY GROUP CO., LTD. et al.) 13 September 2022 (2022-09-13) description, paragraphs [0030]-[0087], and figures 1-11 1-6, 10, 11,24-26 1-6, 10, 11,24-26 A CN 104900268 A (SHANGHAI TIANMA AM-OLED CO., LTD. et al.) 09 September 2015 (2015-09-09) entire document 1-26 A CN 112802423 A (XIAMEN TIANMA MICRO-ELECTRONICS CO., LTD.) 14 May 2021 (2021-05-14) entire document 1-26 | | Further documents are listed in the continuation of Box C. | J | See patent family annex. * Special categories of cited documents: “T” later document published after the international filing date or priority “A” document defining the general state of the art which is not considered date and not in conflict with the application but cited to understand the to be of particular- relevance principle or theory underlying the invention “D” document cited by the applicant in the international application “X” document of particular- relevance; the claimed invention cannot be “E” earlier application orpatent but published on or after the international considered novel or cannot be considered to involve an inventive step filing date when the document is taken alone “L” document which may throw doubts on priority claim(s) or which is “Y” document of particular relevance; the claimed invention cannot be cited to establish the publication date of another citation or other considered to involve an inventive step when the document is special reason (as specified) combined with one or more other such documents, such combination “O” document referring to an oral disclosure, use, exhibition or other being obvious to a person skilled in the art means document member of the same patent family “P” document published prior to the international filing date but later than the priority date claimed Date of the actual completion of the international search 04 December 2023 Date of mailing of the international search report 11 December 2023 Name and mailing address of the ISA / CN China National Intellectual Property Administration (ISA / CN) China No. 6, Xitucheng Road, Jimenqiao, Haidian District, Beijing 100088 Authorized officer Telephone No.PCT / CN2023 / 122265C. DOCUMENTS CONSIDERED TO BE RELEVANTCategory* Citation of document, with indication, where appropriate, of the relevant passages Relevant to claim No. A CN 104700799 A (SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. et al.) 10 June 2015 (2015-06-10) entire document 1-26 A CN 104269145 A (BOE TECHNOLOGY GROUP CO., LTD. et al.) 07 January 2015 (2015-01-07) entire document 1-26INTERNATIONAL SEARCH REPORT Information on patent family membersInternational application No.PCT / CN2023 / 122265Patent document cited in search report Publication date (day / month / year) Patent family member, s) Publication date (day / month / year) CN 113793570 A 14 December 2021 None CN 114464133 A 10 May 2022 None CN 115050412 A 13 September 2022 None CN 104900268 A 09 September 2015 None CN 112802423 A 14 May 2021 None CN 104700799 A 10 June 2015 None CN 104269145 A 07 January 2015 None

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