Power supply control method and apparatus, and device and storage medium

Abstract

Provided in the embodiments of the present application are a power supply control method and apparatus, and a device and a storage medium. The method is applied to an electronic device. The electronic

Description

[0002] The present disclosure belongs to the technical field of mobile terminals, and in particular, relates to a power control method and apparatus, a device and a storage medium. BACKGROUND

[0003] In order to save circuit space, some electronic devices uses a two-in-one or three-in-one card slot for a Subscriber Identity Module (SIM) card and a Secure Digital (SD) card. The SD card may be inserted outside the card slot, and the SIM card may be inserted inside the card slot.

[0004] When the card is removed quickly, if power-down time of the SD card and / or the SIM card is slow (such as at a millisecond level), a spring contact of a power supply pin of the card slot of the SIM card or the SD card may form a loop with two pins of the SIM card, resulting in burnout of the SIM card. In order to avoid burnout of the SIM card, it is necessary to perform fast powerdown operation on the SD card and / or the SIM card. SUMMARY

[0005] The present disclosure relates to a power control method and apparatus, a device and a storage medium, which can perform fast power-down operation on a Secure Digital (SD) card and / or a Subscriber Identity Module (SIM) card.

[0006] In a first aspect, an embodiment of the present disclosure provides a power control method, which is applied to an electronic device, where the electronic device is provided with a card slot, a System on Chip (SOC) chip, and a Power Management Integrated Circuit (PMIC) chip, the card slot is separately connected to the SOC chip and the PMIC chip, an SD card and an SIM card are inserted into the card slot, the method includes:

[0007] acquiring a status signal of the card slot through the PMIC chip and the SOC chip, where the status signal is used to indicate whether the SD card and / or the SIM card are removed; and

[0008] when the status signal indicates that the SD card and / or the SIM card are removed, i performing a power-down preparation operation through the SOC chip, and controlling the card slot to be powered down through the PMIC chip.

[0009] In one possible implementation, the PMIC chip includes a first detection pin and a first interrupt circuit; and acquiring a status signal of the card slot through the PMIC chip includes:

[0010] determining a preset level signal detected by the first detection pin according to a level state of the first detection pin; and

[0011] performing de-jittering processing and conversion processing on the preset level signal through the first interrupt circuit to obtain the status signal.

[0012] In one possible implementation, the preset level signal is a falling edge signal; and determining a preset level signal detected by the first detection pin according to a level state of the first detection pin includes:

[0013] determining that the first detection pin detects the preset level signal when the level state of the first detection pin changes from a high level state to a low level state.

[0014] In one possible implementation, the preset level signal is a rising edge signal; and determining a preset level signal detected by the first detection pin according to a level state of the first detection pin includes:

[0015] determining that the first detection pin detects the preset level signal when the level state of the first detection pin changes from a low level state to a high level state.

[0016] In one possible implementation, controlling the card slot to be powered down through the PMIC chip includes:

[0017] controlling the card slot to be powered down through the PMIC chip after the SOC chip completes the power-down preparation operation.

[0018] In one possible implementation, controlling the card slot to be powered down through the PMIC chip includes:

[0019] performing power-down processing on the card slot through the PMIC chip according to a preset power binding relationship; where

[0020] the preset power binding relationship is used to indicate a binding relationship between the status signal and the SD card as well as the SIM card.

[0021] In a second aspect, an embodiment of the present disclosure provides a power control apparatus, which is applied to an electronic device, where the electronic device is provided with a card slot, a System on Chip (SOC) chip, and a Power Management Integrated Circuit (PMIC) chip, the card slot is separately connected to the SOC chip and the PMIC chip, a Secure Digital (SD) card and a Subscriber Identity Module (SIM) card are inserted into the card slot, the apparatus includes an acquisition module and a processing module, where

[0022] the acquisition module is configured to acquire a status signal of the card slot through the PMIC chip and the SOC chip, where the status signal is used to indicate whether the SD card and / or the SIM card are removed; and

[0023] the processing module is configured to, when the status signal indicates that the SD card and / or the SIM card are removed, perform a power-down preparation operation through the SOC chip, and control the card slot to be powered down through the PMIC chip.

[0024] In one possible implementation, the PMIC chip includes a first detection pin and a first interrupt circuit; and the acquisition module is specifically configured to:

[0025] determine a preset level signal detected by the first detection pin according to a level state of the first detection pin; and

[0026] perform de-jittering processing and conversion processing on the preset level signal through the first interrupt circuit to obtain the status signal.

[0027] In one possible implementation, the preset level signal is a falling edge signal; and the acquisition module is specifically configured to:

[0028] determine that the first detection pin detects the preset level signal when the level state of the first detection pin changes from a high level state to a low level state.

[0029] In one possible implementation, the preset level signal is a rising edge signal; and the acquisition module is specifically configured to:

[0030] determine that the first detection pin detects the preset level signal when the level state of the first detection pin changes from a low level state to a high level state.

[0031] In a possible implementation, the processing module is specifically configured to:

[0032] control the card slot to be powered down through the PMIC chip after the SOC chip completes the power-down preparation operation.

[0033] In a possible implementation, the processing module is specifically configured to:

[0034] perform power-down processing on the card slot through the PMIC chip according to a preset power binding relationship; where

[0035] the preset power binding relationship is used to indicate a binding relationship between the status signal and the SD card as well as the SIM card.

[0036] In a third aspect, an embodiment of the present disclosure provides an electronic device, including: a processor and a memory; where

[0037] the memory stores computer-executable instructions; and

[0038] the processor executes the computer-executable instructions stored in the memory, so that the processor implements the power control method according to the first aspect.

[0039] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium, where computer-executable instructions are stored in the computer-readable storage medium, and the computer-executable instructions, when executed by a processor, are used to implement the power control method according to the first aspect.

[0040] In a fifth aspect, an embodiment of the present disclosure provides a computer program product, including a computer program, where the computer program, when executed by a processor, implements the power control method according to the first aspect.

[0041] In a sixth aspect, an embodiment of the present disclosure provides a chip on which a computer program is stored, where the computer program, when executed by the chip, implements the power control method according to the first aspect.

[0042] In one possible implementation, the chip is a chip in a chip module.

[0043] An embodiment of the present disclosure provides a power control method and apparatus, a device and a storage medium. The method is applied to an electronic device. The electronic device is provided with a card slot, an SOC chip, and a PMIC chip. The card slot is separately connected to the SOC chip and the PMIC chip. An SD card and an SIM card are inserted into the card slot. The method includes: acquiring a status signal of the card slot through the PMIC chip and the SOC chip, where the status signal is used to indicate whether the SD card and / or the SIM card are removed; and when the status signal indicates that the SD card and / or the SIM card are removed, performing a power-down preparation operation through the SOC chip, and controlling the card slot to be powered down through the PMIC chip. The SOC chip and the PMIC chip detects the presence state of the SD card and / or the SIM card in real time, so that when the SD card and / or the SIM card are removed, the SOC chip and the PMIC chip may separately perform the powerdown preparation operation, thus achieving the fast power-down effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure, and together with the description, serve to explain the principles of the present disclosure.

[0045] FIG. lisa schematic flowchart of a first fast power-down solution in the related art;

[0046] FIG. 2 is a schematic flowchart of a second fast power-down solution in the related art;

[0047] FIG. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure;

[0048] FIG. 4 is a schematic structural diagram of another electronic device according to an embodiment of the present disclosure;

[0049] FIG. 5 is a schematic flowchart of a power control method according to an embodiment of the present disclosure;

[0050] FIG. 6A is a schematic diagram of a level state of a detection pin according to an embodiment of the present disclosure;

[0051] FIG. 6B is a schematic diagram of a level state of another detection pin according to an embodiment of the present disclosure;

[0052] FIG. 7 is a schematic structural diagram of a power control apparatus according to an embodiment of the present disclosure;

[0053] FIG. 8 is a schematic structural diagram of still another electronic device according to an embodiment of the present disclosure.

[0054] Through the above accompanying drawings, a clear embodiment of the present disclosure has been shown, which will be described in more detail hereinafter. These accompanying drawings and written descriptions are not intended to limit the scope of the concept of the present disclosure in any way, but to explain the concept of the present disclosure to those skilled in the art with reference to specific embodiments. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0055] In order to make the objective, the technical solution and the advantage of the embodiment of the present disclosure clearer, the technical solution in the embodiment of the present disclosure will be described clearly and completely with reference to the accompanying drawings. Obviously, the described embodiments are some of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without paying creative labor belong to the protection scope of the present disclosure.

[0056] The term "and / or" in the embodiment of the present disclosure describes a relationship between related objects, indicating that there may be three relationships. For example, A and / or B may indicate that A exists alone, A and B exist at the same time, and B exists alone. The character " / "generally indicates that the related objects before and after the character have an "or" relationship.

[0057] It should be understood that although terms "first", "second", and the like may be used in the present disclosure to describe various objects, these objects should not be limited to these terms. These terms are only used to distinguish objects of the same type from each other. For example, the description of the first detection pin and the second detection pin is only used to distinguish different detection pins, and does not indicate the difference in priority or importance of the two detection pins. Optionally, the first detection pin may also be referred to as the second detection pin without departing from the scope of the present disclosure. Similarly, the second detection pin may also be referred to as the first detection pin.

[0058] It should be further understood that terms "including" and "comprising" indicate the presence of the foregoing features, steps, operations, elements, components, types, and / or groups, but do not exclude the presence, appearance, or addition of one or at least one other feature, step, operation, element, component, type, and / or group.

[0059] In the present disclosure, "for example", "in some embodiments", "in other embodiments", and the like are used as examples, illustrations or explanations. Any embodiment or design solution described as an "example" in the present disclosure should not be interpreted as being more preferred or advantageous than other embodiments or design solutions. To be exact, a term using the example is used to present the concept in a specific manner.

[0060] It should be understood that although each step in the flowchart in the embodiment of the present disclosure is shown in sequence as indicated by the arrow, these steps are not necessarily executed in sequence as indicated by the arrow. Unless explicitly stated herein, the execution of these steps is not limited in a strict order, and these steps may be executed in other orders. Moreover, at least a part of the steps in the diagram may include at least one sub-step or at least one stage, which may not necessarily be completed at the same time, but may be executed at different times. The execution order of the steps may not necessarily be sequential, but may be alternately or alternatively executed with at least a part of other steps or sub-steps or stages of other steps.

[0061] The technical solution of the embodiment of the present disclosure is applicable to all electronic devices with a Subscriber Identity Module (SIM) card and a Secure Digital (SD) card sharing the same card slot.

[0062] The application scenario of the embodiment of the present disclosure may refer to the process of inserting and removing the SIM card and / or the SD card in an electronic device.

[0063] When the card is removed quickly, if power-down time of the SD card and / or the SIM card is slow (such as at a millisecond level), a spring contact of a power supply pin of the card slot of the SIM card or the SD card may form a loop with two pins of the SIM card, resulting in burnout of the SIM card. The spring contact of the power supply pin of the card slot of the SIM card or the SD card may also be in contact with the same pin of the SIM card, and result in a short circuit. This may damage a Low Dropout Linear Regulator (LDO) of a Power Management Integrated Circuit (PMIC) chip, and as a result, there will be a probability of burning out the SIM card.

[0064] In order to avoid the foregoing problems, it is necessary to perform fast power-down operation on the SD card and / or the SIM card. At present, the following two solutions are proposed.

[0065] First solution

[0066] As shown in FIG. 1, the presence state of the SIM card and / or the SD card may be detected by the SIMDET signal. After the card is removed, the SOC chip first performs the power-down preparation operation, and then the PMIC synchronously powers down the SIM card and / or the SD card through a dedicated Analog Digital Interface (ADI).

[0067] In the first solution, the SIM DET signal needs to be judged and processed by the SOC chip before using the dedicated ADI interface to synchronize the PMIC to power down the SIM card and / or the SD card. Because the signal needs to be processed and transmitted by the SOC chip, a time delay is significant.

[0068] There are many paths to process and transmit the signal, so that the time delay is significant. In addition, in a sleep scenario, the corresponding SIM module needs to be awakened before synchronizing the PMIC to be powered down through ADI interface, and the fast power-down effect cannot be achieved.

[0069] Second solution

[0070] As shown in FIG. 2, the SOC chip can detect the presence status of the SIM card and / or the SD card through the SIM DET signal. After the card is removed, the SOC chip first performs the power-down preparation operation, and then sends the SIMJNT signal to the PMIC chip through the dedicated Input / Output (IO) pin, so that the PMIC chip powers down the SIM card and / or the SD card.

[0071] In the second solution, the SIMDET signal needs to be judged and processed by the SOC chip before using the IO pin to synchronize the PMIC to power down the SIM card and / or the SD card. Because the signal needs to be transmitted by the SOC chip, a time delay is increased. In addition, the SOC chip may use more IO pins, which may increase the cost of the chip.

[0072] In order to solve the above technical problems, an embodiment of the present disclosure provides a power control method. The SOC chip and the PMIC chip detects the presence state of the SD card and / or the SIM card in real time, so that when the SD card and / or the SIM card are removed, the SOC chip and the PMIC chip may separately perform the power-down preparation operation, thus achieving the fast power-down effect.

[0073] The technical solution of the present disclosure and the manner in which the technical solution of the present disclosure solves the foregoing technical problems may be described in detail using specific embodiments. The following specific embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. The embodiment of the present disclosure may be described below with reference to the accompanying drawings.

[0074] FIG. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure. Referring to FIG. 3, the electronic device is provided with an SOC chip 10, a PMIC chip 20 and a card slot 30. The SOC chip 10 is provided with a second detection pin 11 and a second interrupt circuit 12. The second detection pin 11 is separately connected to the card slot 30 and the second interrupt circuit 12. The SOC chip 10 is connected to the PMIC chip 20. The card slot 30 is connected to the PMIC chip 20.

[0075] An SD card and an SIM card may be inserted into the card slot 30.

[0076] The SOC chip 10 may be used to control the SD card and / or the SIM card inserted in the card slot 30.

[0077] The PMIC chip 20 may control the power supply of each component in the electronic device.

[0078] The SOC chip 10 and the PMIC chip 20 may also acquire a status signal of the card slot. The status signal may be used to indicate whether the SD card and / or the SIM card are removed. When the status signal indicates that the SD card and / or the SIM card are removed, the SOC chip 10 may perform a power-down preparation operation. The PMIC chip 20 may power down the SD card and / or the SIM card after the SOC chip completes the power-down preparation operation.

[0079] Specifically, the second detection pin 11 in the SOC chip 10 may be used to detect a preset level signal, and the preset level signal may be used to indicate whether the SD card and / or the SIM card are removed.

[0080] There may be one or a plurality of second detection pins 11.

[0081] The second interrupt circuit 12 may be used to convert the preset level signal into the status signal.

[0082] The second interrupt circuit 12 may be an Electronic Integrated Circuit (EIC).

[0083] In one possible implementation, the PMIC chip 20 may include a first detection pin 21 and a first interrupt circuit 22. As shown in FIG. 4, the first detection pin 21 may be separately connected to the card slot 30 and the first interrupt circuit 22.

[0084] Specifically, the first detection pin 21 in the PMIC chip 20 may be used to detect a preset level signal, and the preset level signal may be used to indicate whether the SD card and / or the SIM card are removed.

[0085] There may be one or a plurality of first detection pins 21.

[0086] The first interrupt circuit 22 may be used to convert the preset level signal into the status signal.

[0087] The first interrupt circuit 22 may be an EIC.

[0088] In one possible implementation, the SOC chip 10 may include a pin 13 and an SIM / SD control circuit 14. The pin 13 is separately connected to the card slot 30 and the SIM / SD control circuit 14. The SD card and / or the SIM card inserted in the card slot 30 may be controlled in the SOC chip 10 through the SIM / SD control circuit 14.

[0089] The descriptions of "controlling the card slot to be powered down", "powering down the SD card and / or the SIM card" and "powering down the card slot" involved in the embodiment of the present disclosure are equivalent to powering down each pin in the card slot.

[0090] On the basis of the foregoing electronic device structure, how to control the power supply through the foregoing electronic device will be described in detail below.

[0091] FIG. 5 is a flowchart of a power control method according to an embodiment of the present disclosure. Referring to FIG. 5, the method includes the following steps.

[0092] S501, a status signal of the card slot is acquired through the PMIC chip and the SOC chip, where the status signal is used to indicate whether the SD card and / or the SIM card are removed.

[0093] The executive body of the embodiment of the present disclosure may be an electronic device or a power control apparatus arranged in the electronic device. The power control apparatus may be achieved by software or a combination of software and hardware.

[0094] When the status signal indicates that the SD card and / or the SIM card are removed, the status signal may also be referred to as an interrupt signal.

[0095] In one possible implementation, a status signal of the card slot may be acquired through the PMIC chip in the following manner: determining a preset level signal detected by the first detection pin according to a level state of the first detection pin; and performing de-jittering processing and conversion processing on the preset level signal through the first interrupt circuit to obtain the status signal.

[0096] In one possible implementation, a status signal of the card slot may be acquired through the SOC chip in the following manner: determining a preset level signal detected by the second detection pin according to a level state of the second detection pin; and performing de-jittering processing and conversion processing on the preset level signal through the second interrupt circuit to obtain the status signal.

[0097] The preset level signal may include a falling edge signal or a rising edge signal.

[0098] In one possible implementation, it is assumed that the level states of the first detection pin and the second detection pin are high when the SD card and the SIM card are present; the level states of the first detection pin and the second detection pin are low when the SD card and / or the SIM card are removed; and it may be determined that the first detection pin and the second detection pin have detected preset level signals (falling edge signals) when the level states of the first detection pin and the second detection pin change from high level states to low level states.

[0099] For example, as shown in FIG. 6A, before time t, the SD card and the SIM card are present, and at this time, the level states of the first detection pin and the second detection pin are high; at time t, the SD card and / or the SIM card are removed, the level states of the first detection pin and the second detection pin change from high level states to low level states, and it may be determined that the first detection pin and the second detection pin have detected falling edge signals; and after time t, the level states of the first detection pin and the second detection pin are low.

[00100] In one possible implementation, it is assumed that the level states of the first detection pin and the second detection pin are low when the SD card and the SIM card are present; the level states of the first detection pin and the second detection pin are high when the SD card and / or the SIM card are removed; and it may be determined that the first detection pin and the second detection pin have detected preset level signals (rising edge signals) when the level states of the first detection pin and the second detection pin change from low level states to high level states.

[00101] For example, as shown in FIG. 6B, before time t, the SD card and the SIM card are present, and at this time, the level states of the first detection pin and the second detection pin are low; at time t, the SD card and / or the SIM card are removed, the level states of the first detection pin and the second detection pin change from low level states to high level states, and it may be determined that the first detection pin and the second detection pin have detected rising edge signals; and after time t, the level states of the first detection pin and the second detection pin are high.

[00102] In one possible implementation, the preset level signal may be an analog signal, and the status signal of the card slot may be a digital signal.

[00103] The preset level signal may be an SIMDET signal.

[00104] In one possible implementation, the interrupt mode and the de-jittering time of the preset level signals may be configured for the SOC chip and the PMIC chip in advance, so that the SOC chip and the PMIC chip may detect the level change resulted from the insertion and removal of the SIM card and / or the SD card, and have a de-jittering function.

[00105] For example, the de-jittering time may be 200 ps to 300 ps.

[00106] S502, when the status signal indicates that the SD card and / or the SIM card are removed, a power-down preparation operation is performed through the SOC chip, and the card slot is controlled to be powered down through the PMIC chip.

[00107] The power-down preparation operation may refer to the preparation operation before power-down. The power-down preparation operation may ensure that all devices in the circuit may not be damaged during power-down and can work normally at the next power-on. For example, the power-down preparation operation may be the operation such as saving data and releasing resources.

[00108] In one possible implementation, the card slot is controlled to be powered down through the PMIC chip after the SOC chip completes the power-down preparation operation.

[00109] In one possible implementation, power-down processing is performed on the card slot through the PMIC chip according to a preset power binding relationship; where the preset power binding relationship is used to indicate a binding relationship between the status signal and the SD card as well as the SIM card.

[00110] The preset power binding relationship may be the binding relationship between the status signal 1 and the SD card, the binding relationship between the status signal 2 and the SIM card, and the binding relationship between the status signal 3 and the SIM card as well as the SD card.

[00111] After detecting the preset level signal, upon performing de-jittering and judgment confirmation, the PMIC chip may power down the SD card after the SOC chip completes the power-down preparation operation if it is determined that the status signal is the status signal 1; power down the SIM card after the SOC chip completes the power-down preparation operation if it is determined that the status signal is the status signal 2; and power down the SD card and the SIM card after the SOC chip completes the power-down preparation operation if it is determined that the status signal is the status signal 3.

[00112] In the embodiment shown in FIG. 5, the SOC chip and the PMIC chip detect the presence state of the SD card and / or the SIM card in real time through hardware. When the SD card and / or the SIM card are removed, the SOC chip and the PMIC chip may separately perform the powerdown preparation operation, thus achieving the fast power-down effect. In addition, the solution of the present disclosure may save the IO pins of the SOC chip, thereby reducing the cost of the chip.

[00113] FIG. 7 is a schematic structural diagram of a power control apparatus according to an embodiment of the present disclosure. The power control apparatus is applied to an electronic device. The electronic device is provided with a card slot, an SOC chip, and a PMIC chip. The card slot is separately connected to the SOC chip and the PMIC chip. An SD card and an SIM card are inserted into the card slot. Referring to FIG. 7, the power control apparatus includes an acquisition module 701 and a processing module 702, where

[00114] the acquisition module 701 is configured to acquire a status signal of the card slot through the PMIC chip and the SOC chip, where the status signal is used to indicate whether the SD card and / or the SIM card are removed; and

[00115] the processing module 702 is configured to, when the status signal indicates that the SD card and / or the SIM card are removed, perform a power-down preparation operation through the SOC chip, and control the card slot to be powered down through the PMIC chip.

[00116] In one possible implementation, the PMIC chip includes a first detection pin and a first interrupt circuit. The acquisition module 701 is specifically configured to:

[00117] determine a preset level signal detected by the first detection pin according to a level state of the first detection pin; and

[00118] perform de-jittering processing and conversion processing on the preset level signal through the first interrupt circuit to obtain the status signal. [00119JIn one possible implementation, the preset level signal is a falling edge signal; and the acquisition module 701 is specifically configured to:

[00120] determine that the first detection pin detects the preset level signal when the level state of the first detection pin changes from a high level state to a low level state.

[00121] In one possible implementation, the preset level signal is a rising edge signal; and the acquisition module 701 is specifically configured to:

[00122] determine that the first detection pin detects the preset level signal when the level state of the first detection pin changes from a low level state to a high level state.

[00123] In a possible implementation, the processing module 702 is specifically configured to:

[00124] control the card slot to be powered down through the PMIC chip after the SOC chip completes the power-down preparation operation.

[00125] In a possible implementation, the processing module 702 is specifically configured to:

[00126] perform power-down processing on the card slot through the PMIC chip according to a preset power binding relationship; where

[00127] the preset power binding relationship is used to indicate a binding relationship between the status signal and the SD card as well as the SIM card.

[00128] The power control apparatus according to an embodiment of the present disclosure may implement the technical solution shown in the foregoing method embodiment, and the implementation principle and the beneficial effects are similar, which will not be described in detail this time.

[00129] In addition to the above structure, the electronic device according to an embodiment of the present disclosure may also include other components. FIG. 8 is a schematic structural diagram of still another electronic device according to an embodiment of the present disclosure. Referring to FIG. 8, the electronic device may further include a transceiver 801, a memory 802, and a processor 803. The transceiver 801 may include a transmitter and / or a receiver. The transmitter may also be referred to as a sender, a transmitter, a transmission port, a transmission interface, and the like. The receiver may also be referred to as a receiver, a receiving device, a receiving port, a receiving interface, and the like. For example, the transceiver 801, the memory 802, and the processor 803 are interconnected by a bus 804.

[00130] The memory 802 is configured to store program instructions.

[00131] The processor 803 is configured to execute the program instructions stored in the memory, so that the electronic device implements any of the power control methods shown above.

[00132] The transceiver 801 is configured to execute a transceiver function of the electronic device.

[00133] The electronic device may be a chip, a module, an Integrated Development Environment (IDE), and the like.

[00134] The electronic device shown in the embodiment of FIG. 8 may implement the technical solution shown in the foregoing method embodiment, and the implementation principle and the beneficial effects are similar, which will not be described in detail here.

[00135] An embodiment of the present disclosure provides a computer-readable storage medium, where computer-executable instructions are stored in the computer-readable storage medium, and the computer-executable instructions, when executed by a processor, are used to implement any of the foregoing power control methods.

[00136] An embodiment of the present disclosure provides a computer program product, including a computer program, where the computer program, when executed by a processor, implements any of the foregoing power control methods.

[00137] An embodiment of the present disclosure provides a chip on which a computer program is stored, where the computer program, when executed by the chip, implements the foregoing power control method.

[00138] In one possible implementation, the chip is a chip in a chip module.

[00139] The computer-readable storage medium and the computer program product of the embodiment of the present disclosure may implement the technical solution shown in the foregoing the power control method embodiment, and the implementation principles and the beneficial effects are similar, which will not be described in detail here.

[00140] All or part of the steps for implementing the foregoing method embodiments may be completed by hardware related to program instructions. The foregoing program may be stored in a readable memory. The program, when executed, executes the steps included in the foregoing method embodiments; and the aforementioned memory (storage medium) includes: a Read-Only Memory (ROM), a Random Access Memory (RAM), a flash memory, a hard disk, a solid-state drive, a magnetic tape, a floppy disk, an optical disc, and any combination thereof.

[0100] The embodiment of the present disclosure is described with reference to a flowchart and / or a block diagram of a method, a device (a system), and a computer program product according to the embodiment of the present disclosure. It should be understood that each flow and / or block in the flowchart and / or block diagram, and a combination of the flows and / or blocks in the flowchart and / or the block diagram may be implemented by a computer program instruction. These computer program instructions may be provided to a processing unit of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing devices to produce a machine, so that the instructions which are executed by the processing unit of the computer or other programmable data processing devices produce an apparatus for implementing the functions specified in one or more flows in the flowchart and / or one or more blocks in the block diagram.

[0101] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing devices to work in a particular manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction apparatus, and the instruction apparatus implements the functions specified in one or more flows in the flowchart and / or one or more blocks in the block diagram.

[0102] These computer program instructions may also be loaded onto a computer or other programmable data processing devices, so that a series of operational steps are performed on the computer or other programmable devices to produce a computer-implemented process, so that the instructions executed on the computer or other programmable devices provide steps for implementing the functions specified in one or more flows in the flowchart and / or one or more blocks in the block diagram.

[00141] Obviously, those skilled in the art may make various modifications and variations to the embodiment of the present disclosure without departing from the spirit and scope of the present disclosure. In this way, if these modifications and variations of the embodiment of the present disclosure fall within the scope of the claims of the present disclosure and the equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

WHAT IS CLAIMED IS:

1. A power control method, which is applied to an electronic device, wherein the electronic device is provided with a card slot, a System on Chip (SOC) chip, and a Power Management Integrated Circuit (PMIC) chip, the card slot is separately connected to the SOC chip and the PMIC chip, a Secure Digital (SD) card and a Subscriber Identity Module (SIM) card are inserted into the card slot, the method comprises:acquiring a status signal of the card slot through the PMIC chip and the SOC chip, wherein the status signal is used to indicate whether the SD card and / or the SIM card are removed; andwhen the status signal indicates that the SD card and / or the SIM card are removed, performing a power-down preparation operation through the SOC chip, and controlling the card slot to be powered down through the PMIC chip.

2. The method according to claim 1, wherein the PMIC chip comprises a first detection pin and a first interrupt circuit; and acquiring a status signal of the card slot through the PMIC chip comprises:determining a preset level signal detected by the first detection pin according to a level state of the first detection pin; andperforming de-jittering processing and conversion processing on the preset level signal through the first interrupt circuit to obtain the status signal.

3. The method according to claim 2, wherein the preset level signal is a falling edge signal; and determining a preset level signal detected by the first detection pin according to a level state of the first detection pin comprises:determining that the first detection pin detects the preset level signal when the level state of the first detection pin changes from a high level state to a low level state.

4. The method according to claim 2, wherein the preset level signal is a rising edge signal; and determining a preset level signal detected by the first detection pin according to a level state of the first detection pin comprises:determining that the first detection pin detects the preset level signal when the level state of the first detection pin changes from a low level state to a high level state.

5. The method according to any one of claims 1 to 4, wherein controlling the card slot to be powered down through the PMIC chip comprises:controlling the card slot to be powered down through the PMIC chip after the SOC chip completes the power-down preparation operation.

6. The method according to claim 5, wherein controlling the card slot to be powered down through the PMIC chip comprises:performing power-down processing on the card slot through the PMIC chip according to a preset power binding relationship; whereinthe preset power binding relationship is used to indicate a binding relationship between the status signal and the SD card as well as the SIM card.

7. A power control apparatus, which is applied to an electronic device, wherein the electronic device is provided with a card slot, a System on Chip (SOC) chip, and a Power Management Integrated Circuit (PMIC) chip, the card slot is separately connected to the SOC chip and the PMIC chip, a Secure Digital (SD) card and a Subscriber Identity Module (SIM) card are inserted into the card slot, the apparatus comprises an acquisition module and a processing module, whereinthe acquisition module is configured to acquire a status signal of the card slot through the PMIC chip and the SOC chip, wherein the status signal is used to indicate whether the SD card and / or the SIM card are removed; andthe processing module is configured to, when the status signal indicates that the SD card and / or the SIM card are removed, perform a power-down preparation operation through the SOC chip, and control the card slot to be powered down through the PMIC chip.

8. An electronic device, comprising: a processor and a memory; whereinthe memory stores computer-executable instructions; andthe processor executes the computer-executable instructions stored in the memory, so that the processor implements the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, wherein computer-executable instructions are stored in the computer-readable storage medium, and the computer-executable instructions, when executed by a processor, are used to implement the method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, wherein the computer program, when executed by a processor, implements the method according to any one of claims 1 to 6.PCT / CN2024 / 137641A. CLASSIFICATION OF SUBJECT MATTER G06K19 / 07(2006.01)i According to International Patent Classification (IPC) or to both national classification and IPC B. FIELDS SEARCHED Minimum documentation searched (classification system followed by classification symbols) IPC:G06K Documentation searched other than minimum documentation to the extent that such documents are included in the fields searched Electronic data base consulted during the international search (name of data base and, where practicable, search terms used) CNABS; CNTXT; VEN; USTXT; WOTXT; EPTXT: CNKI: ft®, WrS, “1?, S th, power supply, SOC, PMIC, SIM, SD, state, card, slot, pull out C. DOCUMENTS CONSIDERED TO BE RELEVANT Category* Citation of document, with indication, where appropriate, of the relevant passages Relevant to claim No. PX CN 118821828 A (XIAMEN UNISOC TECHNOLOGIES CO., LTD.) 22 October 2024 (2024-10-22) description, paragraphs 60-141, and figures 1-8 1-10 Y Y CN 107786223 A (GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.) 09 March 2018 (2018-03-09) description, paragraphs 24-116, and figures 1-8 CN 115396255 A (ZEKU TECHNOLOGY (BEIJING) CORP., LTD.) 25 November 2022 (2022-11-25) description, paragraphs 2 and 49-88 1-10 1-10 Y CN 107612571 A (SHENZHEN TINNO WIRELESS TECHNOLOGY CO., LTD. et al.) 19 January 2018 (2018-01-19) description, paragraphs 23-40, and figures 1-3 1-10 A CN 103326149 A (HUIZHOU TCL MOBILE COMMUNICATION CO., LTD.) 25 September 2013 (2013-09-25) entire document 1-10 | Z | Further documents are listed in the continuation of Box C. | f | See patent family annex. * Special categories of cited documents: “T” later document published after the international filing date or priority “A" document defining the general state of the art which is not considered date and not in conflict with the application but cited to understand the to be of particular relevance principle or theory underlying the invention “D" document cited by the applicant in the international application “X” document of particular relevance; the claimed invention cannot be “E" earlier application orpatent but published on or after the international considered novel or cannot be considered to involve an inventive step filing date when the document is taken alone “L" document which may throw doubts on priority claim(s) or which is “Y” document of particular relevance; the claimed invention cannot be cited to establish the publication date of another citation or other considered to involve an inventive step when the document is special reason (as specified) combined with one or more other such documents, such combination “O” document referring to an oral disclosure, use, exhibition or other being obvious to a person skilled in the ait means document member of the same patent family “P” document published prior to the international filing date but later than the priority date claimed Date of the actual completion of the international search 17 February 2025 Date of mailing of the international search report 27 February 2025 Name and mailing address of the ISA / CN China National Intellectual Property Administration (ISA / CN) China No. 6, Xitucheng Road, Jimenqiao, Haidian District, Beijing 100088 Authorized officer Telephone No.PCT / CN2024 / 137641C. DOCUMENTS CONSIDERED TO BE RELEVANTCategory* Citation of document, with indication, where appropriate, of the relevant passages Relevant to claim No. A EP 2648109 Al (BLACKBERRY LTD.) 09 October 2013 (2013-10-09) entire document 1-10PCT / CN2024 / 137641Patent document cited in search report Publication date (day / month / year) Patent family member(s) Publication date (day / month / year) CN 118821828 A 22 October 2024 None CN 107786223 A 09 March 2018 CN 107786223 B 06 September 2019 CN 115396255 A 25 November 2022 None CN 107612571 A 19 January 2018 None CN 103326149 A 25 September 2013 ES 2669514 T3 28 May 2018 WO 2014187030 Al 27 November 2014 US 2015280766 Al 01 October 2015 US 9258024 B2 09 February 2016 EP 2843768 Al 04 March 2015 EP 2843768 Bl 02 May 2018 CN 103326149 B 08 June 2016 EP 2648109 Al 09 October 2013 CA 2809874 Al 02 October 2013 CA 2809874 C 24 January 2017 EP 2648109 Bl 13 August 2014 US 2013262728 Al 03 October 2013 US 8996776 B2 31 March 2015 EP 3197059 Al 26 July 2017 EP 3197059 Bl 18 July 2018 US 10020832 B2 10 July 2018 CN 106990912 A 28 July 2017 CN 106990912 B 28 September 2021

Images