Display substrate and display device

Abstract

A display substrate and a display device. The display substrate has a display area and a non-display area, and comprises a base, and a driving circuit group and a virtual driving circuit group which a

Description

[0001] The present application claims priority of Chinese Patent Application No. 202311499769.8, filed to the CNIPA on November 10, 2023 and entitled “Display Substrate and Display Device’’, the content of which should be regarded as being incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to the field of display technologies, and specifically to a display substrate and a display apparatus. BACKGROUND

[0003] Organic Light Emitting Diodes (OLED's) and Quantum-dot Light Emitting Diodes (QLED's) are active light emitting display devices and have advantages of self-illumination, a wide viewing angle, a high contrast ratio, low power consumption, an extremely high reaction speed, lightness and thinness, flexibility, and low cost, etc. With constant development of display technologies, a flexible display apparatus (Flexible Display) in which an OLED or a QLED is used as a light emitting device and signal control is performed through a Thin Film Transistor (TFT) has become a mainstream product in the field of display at present. SUMMARY

[0004] The following is a summary7 of subject matter described in the present disclosure in detail. This summary is not intended to limit the protection scope of claims.

[0005] In a first aspect, a display substrate is provided in the present disclosure. The display substrate is provided with a display area and a non-display area, and includes a base substrate, a pixel drive circuit located in the display area, a drive circuit group and a dummy drive circuit group, which are located in the non-display area, disposed on the base substrate. The pixel drive circuit is electrically connected with the drive circuit group, the drive circuit group includes at least one shift register, the dummy drive circuit group includes at least one dummy shift register, the dummy shift register includes a plurality of dummy active patterns and a plurality of dummy control electrodes, and the shift register includes a plurality of transistors, wherein a transistor includes an active pattern and a control electrode.

[0006] A shape of at least part of the at least one dummy active pattern is the same as a shape of at least part of an active pattern of at least one transistor, a shape of at least part of at least one dummy control electrode is the same as a shape of at least part of a control electrode of at least one transistor, and an orthographic projection of the at least one dummy active pattern on the base substrate is not overlapped with an orthographic projection of the at least one dummy control electrode on the base substrate.

[0007] In an exemplary implementation, a distance between the orthographic projection of the at least one dummy active pattern on the base substrate and a target dummy control electrode ranges from 0.8 microns to 2 microns;

[0008] the orthographic projection of the dummy active pattern on the base substrate is adjacent to an orthographic projection of the target dummy control electrode on the base substrate.

[0009] In an exemplary implementation, the non-display area comprises at least one comer area and at least one linear bezel area, the drive circuit group comprises a plurality of drive circuits sequentially arranged in a direction close to the display area, the drive circuit comprises a plurality of cascaded shift registers, the dummy drive circuit group comprises a plurality of dummy drive circuits arranged sequentially in a direction close to the display area, and the dummy drive circuit comprises a plurality of cascaded dummy shift registers;

[0010] the dummy drive circuit group is at least partially located in the comer area, the drive circuit group is located in the comer area and the linear bezel area, the drive circuit group and the dummy drive circuit group are located on first and second sides of the display area, wherein the first side and the second side of the display area are opposite to each other.

[0011] In an exemplary' implementation, the display area is provided with a pixel drive circuit and at least one reset signal line, the pixel drive circuit comprises a drive transistor and a reset transistor, the reset transistor is electrically connected with a control electrode of the drive transistor, and the reset signal line is electrically connected with a control electrode of the reset transistor; the plurality of drive circuits include a reset drive circuit located on one of the first side and the second side of the display area, and the plurality of dummy drive circuits include a dummy reset drive circuit;

[0012] a length of the reset drive circuit along a first direction is greater than a length of the dummy reset drive circuit along the first direction, and the first direction is an arrangement direction of the plurality of drive circuits.

[0013] In an exemplary implementation, the reset drive circuit comprises a plurality of cascaded reset shift registers, the dummy reset drive circuit comprises at least one dummy reset shift register located between adjacent reset shift registers.

[0014] The reset shift register includes at least one reset transistor and at least one reset capacitor. At least one dummy drive unit further includes a plurality of dummy source-drain electrodes.

[0015] At least part of at least one dummy active pattern in at least one dummy reset shift register has a same shape as a shape of at least part of an active pattern of the at least one reset transistor. At least part of at least one dummy control electrode in the at least one dummy reset shift register has a same shape as a shape of at least part of a control electrode of the at least one reset transistor or the at least one reset capacitor. At least part of at least one dummy source and drain electrodes in the at least one dummy reset shift register has a same shape as a shape of at least part of at least one electrode of first and second electrodes of the at least one reset transistor.

[0016] In an exemplary implementation, the non-display area is further provided with a reset cascade signal line, a reset initial signal line, a first reset clock signal line, a second reset clock signal line, a first reset power supply line, two second reset power supply lines and a third reset power supply line.

[0017] At least one of the reset initial signal line, the first reset clock signal line, the second reset clock signal line, the first reset power supply line, the second reset power supply lines, tire third reset power supply line and the reset cascade signal line extends along a second direction, the first direction intersects with the second direction.

[0018] Orthographic projections of the reset initial signal line, a first one of second reset power supply lines, the third reset power supply line, the first reset clock signal line, the second reset clock signal line, the first reset power supply line and a second one of second reset power supply lines on the base substrate are sequentially arranged along a direction close to the display area.

[0019] In an exemplary implementation, the non-display area is provided with the reset cascade signal line, the two second reset power supply lines and the third reset power supply line, and the reset shift register comprises an input tenninal and an output terminal.

[0020] The reset cascade signal line is electrically connected with an output terminal of at least one reset shift register and an input terminal of at least one reset shift register, respectively; an orthographic projection of the reset cascade signal line on the base substrate is located between an orthographic projection of the first one of second reset power supply lines on the base substrate and an orthographic projection of the third reset power supply line on the base substrate.

[0021] In an exemplary implementation, the non-display area is provided with the reset cascade signal line and a first reset power supply line.

[0022] The dummy reset shift register is located on a side of the reset cascade signal line close to the display area, and at least one dummy source-drain electrode in the dummy reset shift register is electrically connected with the first reset power supply line.

[0023] In an exemplary implementation, the display substrate further includes a drive structure layer. The drive structure layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer.

[0024] The reset cascade signal line, the reset initial signal line and the two second reset power supply lines are located in the fourth conductive layer, and the first reset clock signal line, the second reset clock signal line, the first reset power supply line and the third reset power supply line are located in the fifth conductive layer.

[0025] In an excmplan implementation, the display area is provided with a pixel drive circuit and at least one light emitting signal line, the pixel drive circuit includes a drive transistor and a light emitting transistor that is electrically connected with at least one of a first electrode and a second electrode of the drive transistor, and the light emitting signal line is electrically connected with a control electrode of the light emitting transistor; the plurality of drive circuits includes a light emitting drive circuit located on the other side of the first side and the second side of the display area, and the plurality7 of dummy drive circuits include a dummy light emitting drive circuit.

[0026] A length of the light emitting drive circuit along a first direction is greater than or equal to a length of the dummy light emitting drive circuit along the first direction, and the first direction is an arrangement direction of a plurality7 of drive circuits.

[0027] In an exemplary implementation, the light emitting drive circuit comprises a plurality of cascaded light emitting shift registers, die dummy7 light emitting drive circuit comprises at least one dummy light emitting shift register located between adjacent light emitting shift registers.

[0028] The light emitting shift registers include at least one light emitting transistor and at least one light emitting capacitor; at least one dummy shift register further comprises a plurality7 of dummy source-drain electrodes.

[0029] At least part of at least one dummy active pattern in at least one dummy reset shift register has a same shape as a shape of at least part of an active pattern of the at least one light emitting transistor. At least part of at least one dummy control electrode in the at least one dummy light emitting shift register has a same shape as a shape of at least part of a control electrode of the at least one light emitting transistor or the at least one light emitting capacitor. At least part of at least one dummy source and drain electrodes in the at least one dummy light emitting shift register has a same shape as a shape of at least part of at least one electrode of first and second electrodes of the at least one light emitting transistor.

[0030] In an exemplary implementation, the non-display area is further provided with a light emitting cascade signal line, a light emitting initial signal line, a first light emitting clock signal line, a second light emitting clock signal line, a first light emitting power supply line, two second light emitting power supply lines and a third light emitting power supply line.

[0031] At least one of the light emitting initial signal line, the first light emitting clock signal line, the second light emitting clock signal line, the first light emitting power supply line, the second light emitting power supply line, the third light emitting power supply line and the light emitting cascade signal line extends along a second direction, wherein the first direction intersects with the second direction.

[0032] Orthographic projections of the light emitting initial signal line, a first one of second light emitting power supply lines, the third light emitting power supply line, the first light emitting clock signal line, the second light emitting clock signal line, the first light emitting power supply line and a second one of first light emitting power supply lines on the base substrate are sequentially arranged along a direction close to the display area.

[0033] In an exemplary implementation, the non-display area is provided with a light emitting cascade signal line, two second light emitting power supply lines and a third light emitting power supply line, and the reset shift register comprises an input terminal and an output terminal.

[0034] The light emitting cascade signal line is electrically connected with an output tenninal of at least one light emitting shift register and an input terminal of at least one light emitting shift register, respectively; an orthographic projection of the light emitting cascade signal line on the base substrate is located between an orthographic projection of the first one of second light emitting power supply lines on the base substrate and an orthographic projection of the third light emitting power supply line on the base substrate.

[0035] In an exemplary implementation, the non-display area is provided with the light emitting cascade signal line and a first light emitting power supply line.

[0036] The dummy light emitting shift register is located on a side of the light emitting cascade signal line close to the display area, and at least one dummy source-drain electrode in the dummy light emitting shift register is electrically connected with the first light emitting power supply line.

[0037] In an exemplary' implementation, the display substrate further includes a drive structure layer. The drive structure layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer.

[0038] The light emitting cascade signal line, the light emitting initial signal line and the two second light emitting power supply lines are located in the fourth conductive layer; the first light emitting clock signal line, the second light emitting clock signal line, the first light emitting power supply line and the third light emitting power supply line are located in the fifth conductive layer.

[0039] In an exemplary implementation, the display area is provided with a pixel drive circuit and at least one control signal line, the pixel drive circuit comprises a drive transistor and a compensation transistor, the compensation transistor is electrically connected with a control electrode and a second electrode of the drive transistor, and the control signal line is electrically connected with a control electrode of the compensation transistor; the plurality of drive circuits include a control drive circuit located on the first side and the second side of the display area, and the plurality of dummy drive circuits include a dummy control drive circuit.

[0040] A length of the control drive circuit along a first direction is greater than or equal to a length of the dummy control drive circuit along the first direction, and the first direction is an arrangement direction of a plurality of drive circuits.

[0041] In an exemplary implementation, the control drive circuit comprises a plurality of cascaded control shift registers, the dummy control drive circuit comprises at least one dummy control shift register located between adjacent control shift registers.

[0042] The control shift registers include at least one control transistor and at least one control capacitor; at least one dummy shift register further comprises a plurality of dummy source-drain electrodes.

[0043] At least part of at least one dummy active pattern in at least one dummy control shift register has a same shape as a shape of at least part of an active pattern of the at least one control transistor. At least part of at least one dummy control electrode in the at least one dummy control shift register has a same shape as a shape of at least part of a control electrode of the at least one control transistor or the at least one control capacitor. At least part of at least one dummy source and drain electrodes in the at least one dummy control shift register has a same shape as a shape of at least part of at least one electrode of first and second electrodes of the at least one control transistor.

[0044] In an exemplary implementation, the non-display area is further provided with a control cascade signal line, two control initial signal lines, a first control clock signal line, a second control clock signal line, three first control power supply lines, two second control power supply lines and a third control power supply line.

[0045] At least one of the control initial signal lines, the first control clock signal line, a second control clock signal line, the first control power supply line, the second control power supply lines, the third control power supply lines and the control cascade signal line extends along a second direction, and the first direction intersects with the second direction.

[0046] A first control initial signal line, a first one of second control power supply lines, a second control initial signal line, the first control clock signal line, the second control clock signal line, a first one of first control power supply lines, the third control power supply line, a second first control power supply line, a third first control power supply line and a second one of second control power supply lines are sequentially arranged along a direction close to the display area.

[0047] In an exemplary implementation, the non-display area is further provided with a control cascade signal line, two control initial signal lines and a first control clock signal line, and the control shift register comprises an input terminal and an output terminal.

[0048] The control cascade signal line is electrically connected with an output terminal of at least one cascaded control shift register and an input terminal of at least one cascaded control shift register, respectively; an orthographic projection of the control cascade signal line on the substrate is located between an orthographic projection of the second control initial signal line on the substrate and an orthographic projection of the first control clock signal line on the substrate.

[0049] In an exemplary implementation, the non-display area is further provided with a control cascade signal line, three first control power supply lines and two second control power supply lines; the control cascade signal line divides a region in which the dummy control shift register is located into a first region and a second region; at least one dummy source-drain electrode located in the first region is connected with the first one of second control power supply lines, and at least one dummy source-drain electrode located in the second region is connected with at least one first control power supply line.

[0050] In an exemplary implementation, the display substrate further includes a drive structure layer. The drive structure layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer.

[0051] The control cascade signal line is located in the fourth conductive layer, and the control initial signal line, the first control clock signal line, the second control clock signal line, the first control power supply line, the two second control power supply lines and the third control power supply line are located in the fifth conductive layer.

[0052] In an exemplary implementation, the display area is provided with a pixel drive circuit and at least one scan signal line, the pixel drive circuit comprises a drive transistor and a write transistor, the write transistor is electrically connected with a control electrode and a first electrode of the drive transistor, and the scan signal line is electrically connected with a control electrode of the write transistor; the plurality of drive circuits include a scan drive circuit located on the first side and the second side of the display area, and the plurality of dummy drive circuits include a dummy scan drive circuit.

[0053] A length of the scan drive circuit along a first direction is greater than or equal to a length of the dummy scan drive circuit along the first direction, and the first direction is an arrangement direction of a plurality of drive circuits.

[0054] In an exemplary implementation, the scan drive circuit comprises a plurality of cascaded scan shift registers, the dummy scan drive circuit comprises at least one dummy scan shift register located between adjacent scan shift registers.

[0055] The scan shift registers include at least one scan transistor and at least one scan capacitor; at least one dummy shift register further comprises a plurality of dummy source-drain electrodes.

[0056] At least part of at least one dummy active pattern in at least one dummy scan shift register has a same shape as a shape of at least part of an active pattern of the at least one scan transistor. At least part of at least one dummy control electrode in the at least one dummy scan shift register has a same shape as a shape of at least part of a control electrode of the at least one scan transistor or die at least one scan capacitor. At least part of at least one dummy source and drain electrodes in the at least one dummy scan shift register has a same shape as a shape of at least part of at least one electrode of first and second electrodes of the at least one scan transistor.

[0057] In an exemplary implementation, the non-display area is further provided with a scan cascade signal line, a scan initial signal line, a first scan clock signal line, a second scan clock signal line, a first scan power supply line and a second scan power supply line.

[0058] At least one of the scan initial signal line, the first scan clock signal line, the second scan clock signal line, the first scan power supply line, the second scan power supply line and the scan cascade signal line extends along a second direction, the first direction intersects with the second direction.

[0059] The second scan power supply line, the first scan clock signal line, the second scan clock signal line, the scan initial signal line and the first scan power supply line are sequentially arranged along a direction close to the display area.

[0060] In an exemplary implementation, the non-display area is further provided with a scan cascade signal line, a scan initial signal line and a second scan clock signal line, the scan shift register comprises an input terminal and an output terminal.

[0061] The scan cascade signal line is electrically connected with an output terminal of the at least one scan shift register and an input terminal of the at least one scan shift register, respectively. An orthographic projection of the scan cascade signal line on the base substrate is located between an orthographic projection of the second scan clock signal line on the base substrate and an orthographic projection of the scan initial signal line on the base substrate.

[0062] In an exemplary' implementation, the non-display area is further provided with a scan cascade signal line, a first scan power supply line and a second scan power supply line.

[0063] The scan cascade signal line divides a region in which the dummy scan shift register is located into a first region and a second region; at least one dummy source-drain electrode located in the first region is connected with the second scan power supply line, and at least one dummy sourcedrain electrode located in the second region is connected with the first scan power supply line.

[0064] In an exemplary- implementation, the display substrate further includes a drive structure layer. The drive structure layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer.

[0065] The scan cascade signal line is located in the fourth conductive layer, the scan initial signal line, the first scan clock signal line, the second scan clock signal line, the first scan power supply line and the second scan power supply line are located in the fifth conductive layer.

[0066] In an exemplary- implementation, the drive circuit group includes a scan drive circuit, a control drive circuit, a light emitting drive circuit and a reset drive circuit.

[0067] The reset drive circuit, the control drive circuit and the scan drive circuit located on the first side of the display area are sequentially arranged in a direction close to the display area, and the light emitting drive circuit, the control drive circuit and the scan drive circuit located on the second side of the display area are sequentially arranged in a direction close to the display area

[0068] The scan drive circuit located on the first side of the display area and the scan drive circuit located on the second side of the display area are symmetrically arranged with respect to a center line extending along the second direction of the display area, the control drive circuit located on the first side of the display area and the control drive circuit located on the second side of the display area are symmetrically arranged with respect to the center line extending along the second direction of the display area, and the reset drive circuit located on the first side of the display area and the light emitting drive circuit located on the second side of the display area are symmetrically arranged with respect to the center line extending along the second direction of the display area.

[0069] In an exemplary implementation, the drive circuit group includes at least one transistor and at least one capacitor. The dummy drive circuit group includes a plurality of dummy active patterns, a plurality of dummy control electrodes and a dummy source-drain electrode. The display substrate further includes a signal output line, at least one cascade signal line and a plurality of signal lines, which are located in the non-display area. The plurality of signal lines are connected with the drive circuit group and the dummy circuit group, respectively. The signal output lines are connected with the drive circuit group.

[0070] The drive structure layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer;

[0071] The semiconductor layer includes, at least, an active pattern of at least one transistor and at least one dummy active pattern of a plurality of dummy active patterns.

[0072] The first conductive layer includes, at least, a control electrode of at least one transistor, one plate of at least one capacitor, and at least one dummy active pattern of a plurality of dummy control electrodes.

[0073] The second conductive layer includes, at least, the other plate of at least one capacitor.

[0074] The third conductive layer includes, at least, a signal output line.

[0075] The fourth conductive layer includes, at least, at least one signal line and cascade signal lines.

[0076] The fifth conductive layer includes, at least, at least one signal line.

[0077] In an exemplary implementation, the display substrate further includes at least one initial signal line located in the non-display area.

[0078] At least one initial signal line is located on a side of at least one of a plurality of signal lines close to the display area and is located in the fifth conductive layer.

[0079] An orthographic projection of the at least one initial signal line on the base substrate is at least partially overlapped with orthographic projections of the drive circuit group and the dummy drive circuit group on the base substrate.

[0080] In a second aspect, a display apparatus is also provided in the present disclosure, including the display substrate described above.

[0081] Other aspects of the present disclosure may be comprehended after the drawings and the detailed descriptions are read and understood. BRIEF DESCRIPTION OF DRAWINGS

[0082] Accompanying drawings are intended to provide an understanding of technical solutions of the present application and form a part of the specification, and are used to explain the technical solutions of the present application together with embodiments of the present application, and do not constitute a limitation on the technical solutions of the present application.

[0083] FIG. 1 is a schematic diagram of a structure of a display substrate.

[0084] FIG. 2 illustrates a part of a bezel area of the display substrate.

[0085] FIG. 3 illustrates schematically a part of a structure of a first side of a display area of a display substrate provided in an embodiment of the present disclosure.

[0086] FIG. 4 illustrates schematically a part of a structure of a second side of the display area of the display substrate provided in the embodiment of the present disclosure.

[0087] FIG. 5 illustrates schematically a part of a film in FIG. 3.

[0088] FIG. 6 illustrates schematically a part of a film in FIG. 4.

[0089] FIG. 7A is an equivalent circuit diagram of a pixel drive circuit.

[0090] FIG. 7B is a timing diagram illustrating operations of the pixel drive circuit provided in FIG. 7A.

[0091] FIG. 8A is an equivalent circuit diagram of a scan shift register according to an exemplary embodiment.

[0092] FIG. 8B is a timing diagram of the scan shift register provided in FIG.9A.

[0093] FIG. 9A is an equivalent circuit diagram of a control shift register provided in an exemplary implementation.

[0094] FIG. 9B is a timing diagram of the control shift register provided in FIG. 9A.

[0095] FIG. 10A is an equivalent circuit diagram of a reset shift register provided in an exemplary embodiment.

[0096] FIG. 10B is a timing diagram of the reset shift register provided in FIG. 10A.

[0097] FIG. 11A is an equivalent circuit diagram of a light emitting shift register provided in an exemplary embodiment.

[0098] FIG. 1 IB is a timing diagram of the light emitting shift register provided in FIG. 11A.

[0099] FIG. 12A is a schematic diagram of a part of a film of a reset shift register and a dummy reset shift register.

[0100] FIG. 12B is a schematic diagram of a part of a film of a reset shift register and a dummy reset shift register.

[0101] FIG. 13A is a schematic diagram of a part of a film of a light emitting shift register and a dummy light emitting shift register.

[0102] FIG. 13B is a schematic diagram of a part of a film of a light emitting shift register and a dummy light emitting shift register.

[0103] FIG. 14A is a schematic diagram of a part of a film of a control shift register and a dummy control shift register.

[0104] FIG. 14B is a schematic diagram of a part of a film of a control shift register and a dummy control shift register.

[0105] FIG. 15A is a schematic diagram of a part of a film of a scan shift register and a dummy scan shift register.

[0106] FIG. 15B is a schematic diagram of a part of a film of a scan shift register and a dummy scan shift register.

[0107] FIG. 16 is a schematic diagram of a scan shift register and a dummy scan shift register after forming a semiconductor layer pattern.

[0108] FIG. 17 is a schematic diagram of a control shift register and a dummy control shift register after forming a semiconductor layer pattern.

[0109] FIG. 18 is a schematic diagram of a reset shift register and a dummy reset shift register after forming a semiconductor layer pattern.

[0110] FIG. 19 is a schematic diagram of the pattern of the first conductive layer in the scan shift register and the dummy scan shift register.

[0111] FIG. 20 is a schematic diagram of the pattern of the first conductive layer after formed by the scan shift register and the virtual scan shift register.

[0112] FIG. 21 is a schematic diagram of a pattern of a first conductive layer in the control shift register and the dummy control shift register.

[0113] FIG. 22 is a schematic diagram of a sequential pattern of the first conductive layer in the control shift register and the dummy control shift register.

[0114] FIG. 23 is a schematic diagram of the pattern of the first conductive layer formed by the reset shift register and the dummy reset shift register.

[0115] FIG. 24 is a schematic diagram of the reset shift register and the dummy reset shift register after the pattern of the first conductive layer is formed.

[0116] FIG. 25 is a schematic diagram of the pattern of the second conductive layer in the scan shift register and the dummy scan shift register.

[0117] FIG. 26 is a schematic diagram of the pattern of the second conductive layer after formed by the scan shift register and the virtual scan shift register.

[0118] FIG. 27 is a schematic diagram of a pattern of a second conductive layer in the control shift register and the dummy control shift register.

[0119] FIG. 28 is a schematic diagram after forming a pattern of the second conductive layer in the control shift register and the dummy control shift register.

[0120] FIG. 29 is a schematic diagram of the pattern of the second conductive layer formed by the reset shift register and the dummy reset shift register.

[0121] FIG. 30 is a schematic diagram of the reset shift register and the dummy reset shift register after the pattern of the second conductive layer is formed.

[0122] FIG. 31 is a schematic diagram of the pattern of the third conductive layer located in the control shift register and the dummy control shift register.

[0123] FIG. 32 is a schematic diagram of the control shift register and the dummy control shift register after the pattern of the third conductive layer is formed.

[0124] FIG. 33 is a schematic diagram of the pattern of the third conductive layer in the reset shift register and the dummy reset shift register.

[0125] FIG. 34 is a schematic diagram of the reset shift register and the dummy reset shift register after the pattern of the third conductive layer is patterned.

[0126] FIG. 35 is a schematic diagram of the scan shift register and the dummy scan sift register after the fourth insulation layer is fonned.

[0127] FIG. 36 is a schematic diagram of the control shift register and the dummy control shift register after the fourth insulation layer is formed.

[0128] FIG. 37 is a schematic diagram of the reset shift register and the dummy reset shift register after the fourth insulation layer is formed.

[0129] FIG. 38 is a schematic diagram of the pattern of the fourth conductive layer in the scan shift register and the dummy scan shift register.

[0130] FIG. 39 is a schematic diagram of the pattern of the fourth conductive layer after formed by the scan shift register and the virtual scan shift register.

[0131] FIG. 40 is a schematic diagram of a pattern of a fourth conductive layer in the control shift register and the dummy control shift register.

[0132] FIG. 41 is a schematic diagram after forming a pattern of the fourth conductive layer in the control shift register and the dummy control shift register.

[0133] FIG. 42 is a schematic diagram of the pattern of the fourth conductive layer in the reset shift register and the dummy reset shift register.

[0134] FIG. 43 is a schematic diagram of the reset shift register and the dummy reset shift register after the pattern of the fourth conductive layer is formed.

[0135] FIG. 44 is a schematic diagram of the scan shift register and the dummy scan sift register after the planarization layer is formed.

[0136] FIG. 45 is a schematic diagram of the control shift register and the dummy control shift register after the planarization layer is formed.

[0137] FIG. 46 is a schematic diagram of the reset shift register and the dummy reset shift register after the planarization layer is formed.

[0138] FIG. 47 is a schematic diagram of the pattern of the fifth conductive layer in the scan shift register and the dummy scan shift register.

[0139] FIG. 48 is a schematic diagram of the pattern of the fifth conductive layer after formed by the scan shift register and the virtual scan shift register.

[0140] FIG. 49 is a schematic diagram of a pattern of a fifth conductive layer in the control shift register and the dummy control shift register.

[0141] FIG. 50 is a schematic diagram after forming a pattern of the fifth conductive layer in the control shift register and the dummy control shift register.

[0142] FIG. 51 is a schematic diagram of the pattern of the fifth conductive layer in the reset shift register and the dummy reset shift register.

[0143] FIG. 52 is a schematic diagram of the reset shift register and the dummy reset shift register after the pattern of the fifth conductive layer is formed. DETAILED DESCRIPTION

[0144] To make objectives, technical solutions, and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It is to be noted that implementations may be implemented in multiple different forms. Those of ordinary skills in the art may easily understand such a fact that implementations and contents may be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be explained as being limited to the contents recorded in the following implementations only. The embodiments and features in the embodiments of the present disclosure may be randomly combined with each other if there is no conflict. In order to keep following description of the embodiments of the present disclosure clear and concise, detailed description of part of known functions and known components are omitted in the present disclosure. The drawings in the embodiments of the present disclosure relate only to the structures involved in the embodiments of the present disclosure, and other structures may be described with reference to conventional designs.

[0145] Scales of the drawings in the present disclosure may be used as a reference in actual processes, but are not limited thereto. For example, a width-length ratio of a channel, a thickness and spacing of each film, and a width and spacing of each signal line may be adjusted according to actual needs. A quantity of pixels in a display substrate and a quantity of sub-pixels in each pixel are not limited to numbers shown in the drawings. The drawings described in the present disclosure are schematic structural diagrams only, and one implementation of the present disclosure is not limited to shapes, numerical values, or the like shown in the drawings.

[0146] Ordinal numerals "first", "second", "third", etc., in the specification are set not to form limits in numbers but only to avoid confusion between constituent elements.

[0147] In the specification, for convenience, expressions "central", "above", "below", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., for indicating directional or positional relationships are used to illustrate positional relationships between the constituent elements with reference to the accompanying drawings, not to indicate or imply that involved devices or elements are required to have specific orientations or are structured and operated in the specific orientations but only to easily describe the present specification and simplify the description, and thus should not be understood as limitations on the present disclosure. The positional relationships between the constituent elements may be changed as appropriate based on a direction according to which each constituent element is described. Therefore, appropriate replacements based on situations are allowed, which is not limited to the expressions in die specification.

[0148] In the specification, unless otherwise explicitly specified and defined, terms "mounting", "coupling", and "connection" should be understood in a broad sense. For example, a connection may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be a direct connection, or an indirect connection through a middleware, or an internal communication between two elements. Those of ordinary skills in the art may understand specific meanings of the above terms in the present disclosure according to specific situations.

[0149] In the specification, a transistor refers to an element that at least includes three terminals, i.e., a control electrode, a drain electrode and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and a current can flow through the dram electrode, the channel region, and the source electrode. It is to be noted that in the specification, tire channel region refers to a region through which a current mainly flows.

[0150] In the specification, a first electrode may be a drain electrode, and a second electrode may be a source electrode. Or, the first electrode may be a source electrode, and the second electrode may be a drain electrode. In a case that transistors with opposite polarities are used, or in a case that a direction of a current changes during operation of a circuit, or the like, functions of the “source electrode” and the “drain electrode” are sometimes interchangeable. Therefore, the "source electrode" and the "drain electrode" are interchangeable in the specification.

[0151] In the specification, an "electrical connection" includes acase that constituent elements are connected together through an element with a certain electrical action. The “element with a certain electrical effect” is not particularly limited as long as electrical signals between the connected constituent elements may be sent and received. Examples of the "element with a certain electrical action" not only include an electrode and a wiring, but also include a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements with various functions, etc.

[0152] In the specification, “parallel” refers to a state in which an angle formed by two straight lines is above -10° and below 10°, and thus may include a state in which the angle is above -5° and below 5°. In addition, “perpendicular” refers to a state in which an angle formed by two straight lines is above 80° and below 100°, and thus may include a state in which the angle is above 85° and below 95°.

[0153] In the specification, a “film” and a “layer” are interchangeable. For example, a “conductive layer” may be replaced with a “conductive film” sometimes. Similarly, an “insulation film” may be replaced with an “insulation layer” sometimes.

[0154] In the specification, “disposed in a same layer” adopted refers to a structure formed by patterning two (or more than two) structures through a same patterning process, and their materials may be the same or different. For example, materials of precursors for forming multiple structures disposed in a same layer are the same, and materials finally formed may be the same or different.

[0155] A triangle, rectangle, trapezoid, pentagon, or hexagon, etc. in the specification is not strictly defined, and it may be an approximate triangle, rectangle, trapezoid, pentagon, or hexagon, etc. There may be some small deformations caused by tolerance, and there may be a chamfer, an arc edge, deformation, etc.

[0156] In the present disclosure, “about” means that a boundary is not defined so strictly and numerical values within process and measurement error ranges are allowed.

[0157] A Low Temperature Poly-Silicon (LTPS for short) technology is used in a display substrate. The LTPS technology has advantages such as a high resolution, a high response speed, high brightness, and a high aperture ratio. Although favored by the market, the LTPS technology also has some defects, such as a relatively high production cost and relatively large power consumption, etc. In this case, a technical solution of Low Temperature Polycrystalline + Oxide (LTPO) formed emerges. Compared with the LTPS technology, in the LTPO technology, a leakage current is smaller, pixel point response is faster, and an additional layer of an oxide is added to a display substrate, which reduces energy consumption required for exciting pixel points, thus reducing power consumption during screen display. However, compared with the display products using the LTPS technology, the display products using the LTPO technology will cause afterimage due to biasing of a threshold voltage of the drive transistor in the pixel circuit, which reduces the display effect of the display products.

[0158] In order to achieve the display, the display product is provided with a variety of gate drivers on array, which are matched according to a pixel design of a display area. Generally, left and right bezels are provided with at least one gate driver on array. Nowadays, special-shaped designs, such as rounded comers, are applied to most display products, such as mobile phones, watches, tablets, laptops and the like, in which bezels of the display products include straight edge areas and comer areas. In a design for panels, the gate driver on array is a progressive scanning circuit, generally. The gate driver on array is generally in a rectangular arrangement. In the corner area, a plurality of cascaded shift registers in the gate driver on array are generally arranged in a fan shape according to an arc shape of the display area in order to narrow the bezels. In this case, a quantity of shift registers closely arranged in units is definitely greater than a quantity’ of pixel rows to be connected with the shift registers. Generally, a shift register closest to a pixel is selected to connect to the pixel. Redundant shift registers are not removed, but replaced with a dummy shift register that does not need to be connected with the display area. The buildup dummy shift register can ensure etching uniformity of the display product, avoiding uneven display resulted in process differences due to different pattern densities.

[0159] In the design process, a layout of the dummy shift register is substantially the same as a layout of the shift register. Part of a structure of a same transistor in the dummy shift register may be connected with a high-level signal and a low-level signal at the same time, resulting in a problem of short circuit, thus reducing the reliability of the product, for example.

[0160] FIG. 1 is a schematic diagram of a structure of a display substrate, FIG. 2 illustrates a part of a bezel area of the display substrate, FIG. 3 illustrates schematically a part of a structure of a first side of a display area of a display substrate provided in an embodiment of the present disclosure, FIG. 4 illustrates schematically a part of a structure of a second side of the display area of the display substrate provided in the embodiment of the present disclosure, FIG. 5 illustrates schematically a part of a film in FIG. 3, and FIG. 6 illustrates schematically a part of a film in FIG. 4. As shown in FIGs. 1 to 6, a display substrate is provided in an embodiment of the present disclosure. The display substrate is provided with a display area 100 and a non-display area 200, and includes a base substrate, a pixel drive circuit P which is disposed on the base substrate and located in the display area 100, a drive circuit group and a dummy drive circuit group which are located in the non-display area. The pixel drive circuit is electrically connected with the drive circuit group, the drive circuit group includes at least one shift register, the dummy drive circuit group includes at least one dummy shift register, the dummy shift register includes a plurality of dummy active patterns DA and a plurality of dummy control electrodes DG, and the shift register includes a plurality of transistors, wherein a transistor includes an active pattern and a control electrode. As shown in FIGs. 5 and 6, a shape of at least part of the at least one dummy active pattern is the same as a shape of at least part of an active pattern of at least one transistor, a shape of at least part of at least one dummy control electrode is the same as a shape of at least part of a control electrode of at least one transistor, and orthographic projections of the dummy active patterns DA on the base substrate are not overlapped with orthographic projections of the dummy control electrodes DG on the base substrate.

[0161] In an exemplary implementation, as shown in FIGs. 5 and 6, a control electrode of at least one transistor located in the shift register at least partially overlapped with an orthographic projection of an active pattern of the control electrode on the base substrate.

[0162] In an exemplary implementation, a shape of at least part of tire at least one dummy active pattern is the same as a shape of at least part of an active pattern of the at least one transistor, and a shape of at least part of the at least one dummy control electrode is the same as a shape of at least part of the control electrode of the at least one transistor, which can ensure etching uniformity of the display substrate and improve the display effect of the display substrate.

[0163] In the present disclosure, a short circuit phenomenon caused by conduction between devices connected with different signal terminals in the dummy shift register units due to the existence of the dummy active patterns can be avoided by the absence of an overlapping area between the orthographic projections of the dummy active patterns DA on the base substrate and the orthographic projections of the dummy control electrodes DG on the base substrate, improving the reliability of the display substrate.

[0164] In an exemplary implementation, the display substrate may be an LTPO display substrate.

[0165] In an exemplary implementation, the pixel drive circuit may be of a 3TIC, 4TIC, 5T1C, 5T2C, 7T1C, or 8T1C structure.

[0166] In an exemplary implementation, FIG. 7A is an equivalent circuit schematic of a pixel drive circuit. As shown in FIG. 7A, the pixel drive circuit may include seven transistors (a first transistor Ml to a seventh transistor M7), one capacitor C, and eight signal terminals (a data signal terminal Data, a control signal terminal Scan, a scan signal terminal Gate, a reset signal terminal Reset, a light emitting signal terminal EM, an initial signal terminal VINIT, a first power supply terminal VDD, and a second power supply terminal VSS). FIG. 7A is illustrated with a 7T1C structure as an example.

[0167] In an exemplary implementation, a first plate of the capacitor C is connected with the first power supply terminal VDD, and a second plate of the capacitor C is connected with a first node NI. A control electrode of the first transistor MI is connected with the reset signal terminal Reset, a first electrode of the first transistor Ml is connected with the initial signal terminal VINIT, and a second electrode of the first transistor is connected with a first node Nl. A control electrode of a second transistor M2 is connected with the scan signal terminal Gate, a first electrode of the second transistor M2 is connected with the first node Nl, and a second electrode of the second transistor M2 is connected with a second node N2. A control electrode of the third transistor M3 is connected with the first node Nl, a first electrode of the third transistor M3 is connected with the second node N2, and a second electrode of the third transistor M3 is connected with a third node N3. A control electrode of the fourth transistor M4 is connected with the control signal terminal Scan, a first electrode of the fourth transistor M4 is connected with the data signal terminal Data, and a second electrode of the fourth transistor M4 is connected with the third node N3. A control electrode of the fifth transistor M5 is connected with the light emitting signal terminal EM, a first electrode of the fifth transistor M5 is connected with the first power supply terminal VDD, and a second electrode of the fifth transistor M5 is connected with the third node N3. A control electrode of the sixth transistor M6 is connected with the light emitting signal terminal EM, a first electrode of the sixth transistor M6 is connected with the second node N2, and a second electrode of the sixth transistor M6 is connected with a first electrode of a light emitting device. A control electrode of the seventh transistor M7 is connected with the control signal terminal Scan, a first electrode of the seventh transistor M7 is connected with the initial signal terminal VINIT, a second electrode of the seventh transistor M7 is connected with the first electrode of the light emitting device, and a second electrode of the light emitting device is connected with the second power supply terminal VSS.

[0168] In an exemplary implementation, the first transistor Ml may be referred to as a reset transistor, and when an active level signal is input to the reset signal terminal Reset, the first transistor Ml transmits an initialization voltage to the first node Nl to initialize a charge amount at the first node N1.

[0169] In an exemplary implementation, the second transistor M2 may be referred to as a compensation transistor, which is turned on to compensate a signal of the first node N1 when an active level signal is input to the control signal terminal Scan.

[0170] In an exemplary implementation, the third transistor M3 may be referred to as a drive transistor. The third transistor M3 determines a drive current flowing between the first power supply terminal VDD and the second power supply terminal VSS according to a potential difference between the control electrode and the first electrode of the third transistor T3.

[0171] In an exemplary implementation, the fourth transistor M4 may be referred to as a write transistor. When an active level signal is input to the scan signal terminal GATE , the fourth transistor M4 enables a data voltage at the data signal terminal Data to be input to the pixel drive circuit.

[0172] In an exemplary implementation, the fifth transistor M5 and the sixth transistor M6 may be referred to as light emitting control transistors. When an active level signal is input to the light emitting signal terminal EM, the fifth transistor M5 and the sixth transistor M6 enable the light emitting element to emit light by forming a path of drive current between the first power supply terminal VDD and the second power supply terminal VSS.

[0173] In an exemplary implementation, a signal of the first power supply terminal VDD is a high-level signal provided continuously, and a signal of the second power supply terminal VSS is a low-level signal.

[0174] In an exemplary implementation, both the first transistor Ml and the second transistor M2 are metal oxide transistors which are N-type transistors, and all of the third transistor M3 to the seventh transistor M7 are low-temperature poly-silicon transistors which are P-type transistors.

[0175] In an exemplary implementation, both the first transistor Ml and the second transistor M2 are oxide transistor and may reduce a leakage current and improve performance of the pixel drive circuit, which may reduce power consumption of the pixel drive circuit.

[0176] In an exemplary implementation, the first power supply terminal VDD is configured to continuously provide a high-level signal, and the second power supply terminal VSS is configured to continuously provide a low-level signal.

[0177] FIG. 7B is a timing diagram illustrating operations of the pixel drive circuit provided in FIG. 7A. An exemplary embodiment of the present disclosure will be described below by an operating process of the pixel drive circuit shown in FIG. 7B. The pixel drive circuit in FIG. 7A includes seven transistors (the first transistor Ml to the seventh transistor M7), one capacitor C, and eight signal terminals (the data signal terminal Data, the control signal terminal Scan, the scan signal terminal Gate, the reset signal terminal Reset, the light emitting signal terminal EM, the initial signal terminal VINIT, the first power supply terminal VDD, and the second power supply terminal VSS).

[0178] In an exemplary implementation, the operating process of the pixel drive circuit may include following stages Al to A3.

[0179] The first stage Al is referred to as a reset stage, in which all the signals of the reset signal tenninal Reset, the control signal terminal Scan and the light emitting signal terminal EM are high-level signals, and the signal of the scanning signal terminal Gate is a low-level signal. The signal of the reset signal terminal Reset, which is the low-level signal, turns on the first transistor Ml that provides a signal of the initial signal terminal VINIT to the second node N1 to initialize the capacitor C and clear an original data voltage in the capacitor. All the signals of the control signal terminal Scan and the light emitting signal terminal EM are high-level signals, the signal of the scanning signal terminal Gate is a low-level signal, therefore all the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are turned off, and the OLED does not emit light in this stage.

[0180] The second stage A2 is referred to as a data write stage or a threshold compensation stage, in which both the signals of the control signal terminal Scan and the reset signal terminal Reset are low-level signals, both die signals of the light emitting signal terminal EM and the scanning signal terminal Gate are high-level signals, such that the Data signal terminal Data outputs Data voltage. In this stage, since the first node N1 is a low-level signal, the third transistor M3 is turned on. The signal of the control signal terminal Scan is the low-level signal, both the fourth transistor M4 and the seventh transistor M7 are turned on, the signal of the scan signal terminal Gate is the high-level signal, and the second transistor M2 is turned on. The second transistor M2 and the fourth transistor M4 are turned on so that the data voltage output from the data signal terminal Data is provided to the first node N1 through the third node N3, the tumed-on third transistor M3, the second node N2, and the tumed-on second transistor M2, and a difference between the data voltage output from the data signal terminal Data and a threshold voltage of the third transistor M3 is charged to the capacitor C until a voltage at the first node N1 is Vd-|Vth|, wherein Vd is the data voltage output from the data signal terminal Data, and Vth is the threshold voltage of the third transistor M3. The seventh transistor M7 is turned on, so that an initialization voltage at the initial signal terminal VINIT is provided to a first electrode of the OLED to initialize (reset) the first electrode of the OLED and clear a pre-stored voltage therein, thereby completing initialization and ensuring that the OLED does not emit light. A signal of the reset signal terminal Reset is a low-level signal, and the first transistor Ml is turned off. The signal of the light emitting signal terminal EM is the high-level signal, and the fifth transistor M5 and the sixth transistor M6 are turned off.

[0181] The third stage A3 is referred to as alight emitting stage, in which all the signals of the control signal terminal Scan, the scanning signal terminal Gate, the light emitting signal terminal EM and the Reset signal terminal Reset are low-level signals. The signal of the light emitting signal terminal EM is the low-level signal, and both the fifth transistor M5 and the sixth transistor M6 are turned on. A supply voltage output from the first power supply terminal VDD provides a drive voltage to the first electrode of the OLED through the tumed-on fifth transistor M5, the third transistor M3, and the sixth transistor M6, to drive the OLED to emit light.

[0182] In a drive process of the pixel drive circuit, a drive current flowing through the third transistor M3 (drive transistor) is determined by a voltage difference between the control electrode and the first electrode of the third transistor M3. Since the voltage at the first node N1 is Vd-|Vth|, the drive current of the third transistor M3 is as follows: I=K*(Vgs-Vth)2=K*|(Vdd-Vd-Vth )-Vth]2=K*(Vdd-Vd)2

[0183] where I is the drive current flowing through the third transistor M3, that is, the drive current for driving an OLED, K is a constant, Vgs is the voltage difference between the control electrode and a first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output from the data signal terminal Data, and Vdd is the power supply voltage output from the first power supply terminal VDD.

[0184] In an exemplary implementation, as shown in FIGs. 5 and 6, a distance L between an orthographic projection of at least one dummy active pattern on the base substrate and a target dummy control electrode ranges from 0.8 microns to 2 microns, and the orthographic projection of the dummy active pattern on the base substrate is adjacent to an orthographic projection of the target dummy control electrode on the base substrate.

[0185] In an exemplaiy implementation, as shown in FIG. 2, the non-display area 200 includes at least one comer area CR and at least one linear bezel area LR, and the drive circuit group includes a plurality of drive circuits sequentially arranged in a direction close to the display area, and the drive circuits include a plurality of cascaded shift registers. The dummy drive circuit group includes a plurality of dummy drive circuits sequentially arranged in the direction close to the display area, and the dummy drive circuits include a plurality’ of cascaded dummy shift registers. The dummy drive circuit group is at least partially located in the comer area CR, the drive circuit group is located in the comer area CR and the linear bezel area LR, the drive circuit group and the dummy drive circuit group are located on first and second sides of the display area, wherein the first side and the second side of the display area are opposite to each other.

[0186] In an exemplary implementation, boundaries of the comer area may be arc-shaped, which is not limited thereto in the present disclosure.

[0187] In an exemplary implementation, as shown in FIG. 1, the display area 100 is further provided with a reset signal line RL, a light emitting signal line EL, a control signal line SL, and a scanning signal line GL. The reset signal line RL is electrically connected with the control electrode of the reset transistor, the light emitting signal line EL is electrically connected with the control electrode of the light emitting transistor, the control signal line SL is electrically connected with the control electrode of the compensation transistor, and the scan signal line GL is electrically connected with the control electrode of the write transistor. The plurality of drive circuits include a reset drive circuit, a scan drive circuit, a control drive circuit and a light emitting drive circuit. The plurality of dummy drive circuits include a dummy reset drive circuit, a dummy scan drive circuit, a dummy control drive circuit and a dummy light emitting drive circuit.

[0188] In an exemplary implementation, both the dummy reset drive circuit and the reset drive circuit are located on the first side of the display area, all of the dummy scan drive circuit, the dummy control drive circuit, the scan drive circuit and the control drive circuit are located on the first side and the second side of the display area, and both the dummy light emitting drive circuit and the light emitting drive circuit are located on the second side of the display area. The control drive circuit located on the first side and the second side of the display area is disposed symmetrically with respect to a center line extending in a second direction D2 of the display area. The scan drive circuit located on the first side and the second side of the display area is disposed symmetrically with respect to the center line extending in the second direction D2 of the display area. The reset drive circuit located on the first side of the display area and the light emitting drive circuit located on the second side of the display area are disposed symmetrically with respect to the center line extending in the second direction D2 of the display area.

[0189] In an exemplary implementation, the reset drive circuit, the control drive circuit and the scan drive circuit located on the first side of the display area are sequentially disposed in a direction close to the display area.

[0190] In an exemplary implementation, the dummy reset drive circuit, the dummy control drive circuit and the dummy scan drive circuit located on the first side of the display area are sequentially disposed in the direction close to the display area.

[0191] In an exemplary implementation, the light emitting drive circuit, the control drive circuit and the scan drive circuit located on the second side of the display area are sequentially disposed in a direction close to the display area.

[0192] In an exemplary implementation, the dummy light emitting drive circuit, the dummy control drive circuit and the dummy scan drive circuit located on the second side of the display area are sequentially disposed in the direction close to the display area.

[0193] In an exemplary implementation, the display substrate may further include a timing controller and a source drive circuit. The timing controller and the source drive circuit may be located in the non-display area.

[0194] In an exemplary implementation, the timing controller may provide the source drive circuit with a gray-scale value and a control signal suitable for specifications of the source drive circuit, provide the scan drive circuit with a clock signal, a scan start signal and the like suitable for specifications of the scan drive circuit, provide the control drive circuit with a clock signal, a control start signal and the like suitable for specifications of the control drive circuit, and provide the light emitting drive circuit with a clock signal, a light emitting stop signal and the like suitable for specifications of the light emitting drive circuit.

[0195] In an exemplary implementation, the source drive circuit may generate a data voltage to be provided to data signal lines DL1, DL2, D3... and DLN using the gray-scale value and the control signal received from the timing controller. For example, the source drive circuit may sample the gray-scale value using the clock signal, and apply a data voltage corresponding to the gray-scale value to the data signal lines DL1 to DLN in sub-pixel rows.

[0196] In an exemplary implementation, the scan drive circuit may generate scan signals to be provided to the scan signal lines by receiving the clock signal, the scan start signal and the like from the timing controller. For example, the scan drive circuit may sequentially provide a scan signal with an on-level pulse to scan signal lines. For example, the scan drive circuit may be constructed in a form of a shift register and may generate a scan signal in a manner of sequentially transmitting a scan start signal provided in a form of an on-level pulse to a next stage circuit under control of a clock signal.

[0197] In an exemplary implementation, the control drive circuit may generate a control signal to be provided to a control signal line by receiving a clock signal, a control start signal and the like from the timing controller. For example, the control drive circuit may sequentially provide a control signal with an on-level pulse to control signal lines. For example, the control drive circuit may be constructed in a form of a shift register, and may generate a control signal in a manner of sequentially transmitting a control start signal provided in a form of an on-level pulse to a next stage circuit under control of a clock signal.

[0198] In an exemplary' implementation, the light emitting drive circuit may generate an emission signal to be provided to a light emitting signal line by receiving the clock signal, the light emitting stop signal and the like from the timing controller. For example, the light emitting drive circuit may sequentially provide an emission signal with an off-level pulse to light emitting signal lines. For example, the light emitting drive circuit may be constructed in a form of a shift register and generate a light emitting signal in a manner of sequentially transmitting a light emitting stop signal provided in a form of an off-level pulse to a next stage circuit under control of a clock signal.

[0199] In an exemplary implementation, the reset drive circuit may generate an emission signal to be provided to the reset signal line by receiving the clock signal, the light emitting stop signal and the like from the timing controller. For example, the reset drive circuit may sequentially provide an emission signal with an off-level pulse to the reset signal line. For example, the reset drive circuit may be constructed in a form of a shift register and generate a reset signal in a manner of sequentially transmitting a reset stop signal provided in a form of an off-level pulse to a next stage circuit under control of a clock signal.

[0200] In an exemplary implementation, as shown in FIGs. 3 and 4, the reset drive circuit includes a plurality of cascaded reset shift registers R-GOA, the scan drive circuit includes a plurality of cascaded scan shift registers P-GOA, the control drive circuit includes a plurality of cascaded control shift registers N-GOA, and the light emitting drive circuit includes a plurality of cascaded light emitting shift registers E-GOA. At least one reset shift register is connected with at least one reset signal line, at least one scan shift register is connected with at least one scan signal line, at least one control shift register is connected with at least one control signal line, and at least one light emitting shift register is connected with at least one light emitting signal line. At least one shift register located on the first side of the display area includes at least one reset shift register, at least one control shift register and at least one scan shift register. FIG. 3 illustrates an example in which at least one shift register located on the first side of the display area includes one reset shift register, one control shift register and two scan shift registers. At least one shift register located on the second side of the display area includes at least one light emitting shift register, at least one control shift register and at least one scan shift register. FIG. 4 illustrates an example in which at least one shift register located on the second side of the display area includes one light emitting shift register, one control shift register and two scan shift registers.

[0201] In an exemplary implementation, as shown in FIGs. 3 and 4, the dummy reset drive circuit includes a plurality of cascaded reset shift registers DR-GO A, the dummy scan drive circuit includes a plurality of cascaded dummy scan shift registers DP-GOA, the dummy control drive circuit includes a plurality of cascaded dummy control shift registers DN-GOA, and the dummy light emitting drive circuit includes a plurality of cascaded dummy light emitting shift registers DE-GOA. At least one dummy reset shift register is connected with at least one dummy reset signal line, at least one dummy scan shift register is connected with at least one dummy scan signal line, at least one dummy control shift register is connected with at least one dummy control signal line, and at least one dummy light emitting shift register is connected with at least one dummy light emitting signal line. At least one dummy shift register located on the first side of the display area includes at least one dummy reset shift register, at least one dummy control shift register and at least one dummy scan shift register. FIG. 3 illustrates an example in which at least one dummy shift register located on the first side of the display area includes one dummy reset shift register, one dummy control shift register and two dummy scan shift registers. At least one dummy shift register located on the second side of the display area includes at least one dummy light emitting shift register, at least one dummy control shift register and at least one dummy scan shift register. FIG. 4 illustrates an example in which at least one dummy shift register located on the second side of the display area includes one dummy light emitting shift register, one dummy control shift register and two dummy scan shift registers.

[0202] In an exemplary implementation, the reset shift register R-GOA, the scan shift register P-GOA, the control shift register N-GOA and the light emitting shift register E-GOA may be of an 8T2C, 10T3C, 12T3C, 13T3C, 16T3C, or 16T4C circuit configuration, which is not limited thereto in the present disclosure.

[0203] FIG. 8A is an equivalent circuit diagram of a scan shift register according to an exemplary embodiment. As shown in FIG. 8A, the scan shift register includes a first scan transistor PT1 to an eighth scan transistor PT8, a first scan capacitor PCI and a second scan capacitor PC2. FIG. 8A illustrates an example in which the scan shift register is of an 8T2C circuit configuration.

[0204] In an exemplary implementation, a control electrode of a first scan transistor PT1 is electrically connected with a first clock signal terminal CKI, a first electrode of the first scan transistor PT1 is electrically connected with an input terminal PIN, and a second electrode of the first scan transistor PT1 is electrically connected with a first node Nl. A control electrode of a second scan transistor PT2 is electrically connected with the first node Nl, a first electrode of the second scan transistor PT2 is electrically connected with a first clock signal terminal CK, and a second electrode of the second scan transistor PT2 is electrically connected w ith a second node N2. A control electrode of a third scan transistor PT3 is electrically connected w ith the first clock signal terminal CKI, a first electrode of the third scan transistor PT3 is electrically connected with a second pow-er supply terminal VGL, and a second electrode of the third scan transistor PT3 is electrically connected with the second node N2. A control electrode of a fourth scan transistor PT4 is electrically connected with the second node N2, a first electrode of the fourth scan transistor PT4 is electrically connected with a first power supply terminal VGH, and a second electrode of the fourth scan transistor PT4 is electrically connected w ith an output terminal POUT. A control electrode of a fifth scan transistor PT5 is electrically connected with a third node N3, a first electrode of the fifth scan transistor PT5 is electrically connected with a second clock signal terminal CK2, and a second electrode of the fifth scan transistor PT5 is electrically connected with the output terminal GOUT. A control electrode of a sixth scan transistor PT6 is electrically connected with the second node N2, a first electrode of the sixth scan transistor PT6 is electrically connected with the first power supply terminal VGH, and a second electrode of the sixth scan transistor PT6 is electrically connected with a first electrode of a seventh scan transistor PT7. A control electrode of the seventh scan transistor PT7 is electrically connected with a second clock signal terminal PCK2, and a second electrode of the seventh scan transistor PT7 is electrically connected with the first node N1. A control electrode of an eighth scan transistor PT8 is electrically connected with the second power supply terminal VGL, a first electrode of the eighth scan transistor PT8 is electrically connected with the first node Nl, and a second electrode of the eighth scan transistor PT8 is electrically connected with the third node G3. A first plate PCI 1 of the first scan capacitor PCI is electrically connected with the first power supply terminal VGH, and a second plate PCI 2 of the first scan capacitor PCI is electrically connected with the second node N2. A first plate PC21 of a second scan capacitor PC2 is electrically connected with the output terminal POUT, and a second plate PC22 of the second scan capacitor PC2 is electrically connected with the third node N3.

[0205] In an exemplary implementation, the first scan transistor PT1 to the eighth scan transistor PT8 may be P-type transistors or may be N-type transistors.

[0206] In an exemplary implementation, the first power supply terminal VGH continuously provides a high-level signal, and the second power supply terminal VGL continuously provides a low-level signal.

[0207] FIG. 8B is a timing diagram of the scan shift register in FIG. 8 A. Taking the first scan transistor PT1 to the eighth scan transistor PT8 being P-type transistors as an example, as shown in FIG. 8B, an operating process of a scan shift register according to an exemplary embodiment includes following stages Bl to B4.

[0208] During the input stage Bl, signals of the first clock signal terminal CK1 and the input terminal PIN are low-level signals, and a signal of the second clock signal terminal CK2 is a high-level signal. Since a signal of the first clock signal terminal CK1 is a low-level signal, the first scan transistor PT1 is turned on, and a signal of the input terminal PIN is transmitted to the first node N1 through the first scan transistor PT I. Since a signal of the eighth scan transistor PT8 receives a low-level signal of the second power supply terminal VGL, the eighth scan transistor PT8 is turned on. A level of the third node N3 may turn on the fifth scan transistor PT5, and the signal of the second clock signal terminal CK2 is transmitted to the output terminal POUT through the fifth scan transistor PT5, that is, in the input stage DI, the output terminal POUT has the signal of the second clock signal terminal CK2 which is the high-level signal. In addition, since the signal of the first clock signal tenninal CK1 is the low-level signal, the third scan transistor PT3 is turned on, and the low-level signal of the second power supply terminal VGL is transmitted to the second node N2 via the third scan transistor PT3. In this case, both the fourth scan transistor PT4 and the sixth scan transistor PT6 are turned on. Since a signal of the second clock signal terminal PCK2 is a high-level signal, die seventh scan transistor PT7 is cut off.

[0209] During the output stage B2, a signal of the first clock signal terminal CK1 is a high-level signal, a signal of the second clock signal terminal CK2 is a low-level signal, and a signal of the input terminal PIN is a high-level signal. The fifth scan transistor PT5 is turned on, and the signal of the second clock signal terminal CK2 is used as a signal of the output terminal POUT via the fifth scan transistor PT5. During the output phase D2, a level at one end of the second scan capacitor PC2 connected with output terminal OUT, becomes a signal of the second power supply terminal VGL. Due to a bootstrap effect of the second scanning capacitor PC2, the eighth scan transistor PT8 is cut off, the fifth scan transistor PT5 can be turned on better, and the signal of the output terminal POUT is a low-level signal. In addition, the signal of the first clock signal terminal CK1 is the high-level signal, so that both the first scan transistor PT 1 and the third scan transistor PT3 are cut off. The second scan transistor PT2 is turned on, and the high-level signal of the first clock signal terminal CK1 is transmitted to the second node N2 via the second scan transistor PT2, so that both the fourth scan transistor PT4 and the sixth scan transistor PT6 are cut off. Since the signal of the second clock signal terminal CK2 is the low-level signal, the seventh scan transistor PT7 is turned on.

[0210] During the buffering stage B3, both signals of the first clock signal terminal CK1 and die second clock signal terminal CK2 are high-level signals, a signal of the input terminal PIN is die high-level signal, the fifth scan transistor PT5 is turned on, and the second clock signal terminal CK2 is used as an output signal POUT via the fifth control transistor PT5. Due to the bootstrap action of the second scan capacitor C2, a voltage value of the signal at the first node N1 increases. In addition, the signal of the first clock signal terminal CK1 is the high-level signal, so that both the first scan transistor PT1 and the third scan transistor PT3 are cut off, the eighth scan transistor PT8 is turned on, the second scan transistor PT2 is turned on, and the high-level signal of the first scan clock signal terminal CK1 is transmitted to the second node N2 via the second scan transistor PT2, and thus both the fourth scan transistor PT4 and the sixth scan transistor PT6 are cut off. Since the signal of the second clock signal terminal CK2 is the high-level signal, the seventh scan transistor PT7 is cut off.

[0211] In a first sub-stage B41 of the stabilization stage B4, a signal of the first clock signal terminal CK1 is the low-level signal, and both signals of the second clock signal terminal CK2 and the input terminal PIN are high-level signals. Since the signal of the first clock signal terminal CK1 is die low-level signal, the first scan transistor PT1 is turned on, a signal of the input terminal PIN is transmitted to the first node N1 via the first scan transistor PT1, and the second scan transistor PT2 is cut off. Since the eighth scan transistor PT8 is turned on, the fifth scan transistor PT5 is cut off. Since the signal of the first clock signal terminal CK1 is the low-level signal, the third scan transistor PT3 is turned on, both the fourth scan transistor PT4 and the sixth scan transistor PT6 are turned on, and the high-level signal of the first power supply terminal VGH is transmitted to the output terminal POUT via the fourth scan transistor PT4. That is, the signal of the output terminal POUT is the high-level signal.

[0212] In a second sub-stage t42 of the stabilization stage t4, a signal of the first clock signal terminal CK1 is the high-level signal, a signal of the second clock signal terminal CK2 is the low-level signal, and a signal of the input terminal PIN is the high-level signal. Both the fifth scan transistor PT5 and the second scan transistor PT2 are cut off. The signal of the first clock signal tenninal PCK1 is the high-level signal, so that both the first scan transistor PT1 and the third scan transistor PT3 are cut off. Both the fourth scan transistor PT4 and the sixth scan transistor PT6, which are held by the first scan capacitor PCI, are turned on, and a high-level signal is transmitted to the output terminal POUT via the fourth scan transistor PT4. That is, a signal of the output terminal POUT is the high-level signal.

[0213] During the second sub-stage t42, since the signal of the second clock signal terminal CK2 is the low-level signal, the seventh scan transistor PT7 is turned on, thus a high-level signal is transmitted to the third node N3 and the first node N1 via the sixth scan transistor PT6 and the seventh scan transistor PT7, so that signals at the third node N3 and the first node N1 remain as high-level signals.

[0214] In a third sub-stage t43, both signals of the first clock signal terminal CK1 and the second clock signal terminal CK2 are high-level signals, and a signal of the input terminal PIN is a high-level signal. Both the fifth scan transistor PT5 and the second scan transistor PT2 are cut off. A signal of the first clock signal terminal CK1 is a high-level signal, so that both the first scan transistor PT1 and the third scan transistor PT3 are cut off, and both the fourth scan transistor PT4 and the sixth scan transistor PT6 are tinned on. A high-level signal is transmitted to the output terminal POUT via the fourth scan transistor PT4. That is, a signal of the output terminal POUT is a high-level signal.

[0215] In an exemplar}' implementation, as shown in FIGs. 3 and 4, the display substrate may further include a scan initial signal line PSTV, a first scan clock signal line PCKI, a second scan clock signal line PCK2, a first scan power supply line PVGH, a second scan power supply line PVGL, and a scan cascade signal line PCL, which extend along the second direction D2. An input terminal of a first cascaded scan shift register is electrically connected with the scan initial signal line PSTV, and the scan cascade signal line PCL is electrically connected with an output terminal of an i-th cascaded scan shift register and an input terminal of an (i+l)-th cascaded scan shift register. A first clock signal terminal of the i-th cascaded scan shift register is electrically with the first scan clock signal line PCKI, and a second clock signal terminal is electrically connected with the second scan clock signal line PCK2. A first clock signal terminal of the (i+l)-th cascaded scan shift register is electrically connected with the second scan clock signal line PCK2, and a second clock signal terminal is electrically connected with the first scan clock signal line PCKI. A first power supply terminal of the i-th cascaded scan shift register is electrically connected with the first scan power supply line PVGH, and the second power supply terminal of the i-th cascaded scan shift register is electrically connected with the second scan power supply line PVGL.

[0216] FIG. 9A is an equivalent circuit diagram of a control shift register provided in an exemplary implementation. As shown in FIG. 9A, in an exemplary implementation, the control shift register may include a first control transistor NT1 to a sixteenth control transistor NT 16 and a first control capacitor NCI to a fourth control capacitor NC4, wherein any one of the first control capacitor NC1 to the fourth control capacitor NC4 includes a first plate and a second plate. FIG. 9A illustrates an example in which the control shift register is of a 16T3C circuit configuration.

[0217] As shown in FIG. 9A, a control electrode of the first control transistor NT1 is electrically connected with a first clock signal terminal CKI, and the first electrode of the first control transistor NT I is electrically connected with a signal input terminal NIN, and a second electrode of the first control transistor NT1 is electrically connected with a fourth node N4. A control electrode of the second control transistor NT2 is electrically connected with the fourth node N4, a first electrode of the second control transistor NT2 is electrically connected with the first clock signal terminal CKI, and a second electrode of the second control transistor NT2 is electrically connected with a fifth node N5. A control electrode of the third control transistor NT3 is electrically connected with the first clock signal terminal CKI, a first electrode of the third control transistor NT3 is electrically connected with a second power supply terminal VGL, and a second electrode of the third control transistor NT3 is electrically connected with the fifth node N5. A control electrode of the fourth control transistor NT4 is electrically connected with a sixth node N6, a first electrode of the fourth control transistor NT4 is electrically connected with a second clock signal terminal CK2, and a second electrode of the fourth control transistor NT4 is electrically connected with a seventh node N7. A control electrode of the fifth control transistor NT5 is electrically connected with the fifth node N5, a first electrode of the fifth control transistor NT5 is electrically connected with a first power supply terminal VGH, and a second electrode of the fifth control transistor NT5 is electrically connected with a seventh node N7. A control electrode of the sixth control transistor NT6 is electrically connected with a ninth node N9, a first electrode of the sixth control transistor NT6 is electrically connected with a second clock signal terminal CK2, and a second electrode of the sixth control transistor NT6 is electrically connected with an eighth node N8. A control electrode of the seventh control transistor NT7 is electrically connected with the second clock signal terminal CK2, a first electrode of the seventh control transistor NT7 is electrically connected with the eighth node N8, and a second electrode of the seventh control transistor NT7 is electrically connected with a first node N1. A control electrode of the eighth control transistor NT8 is electrically connected with the fourth node N4, a first electrode of the eighth control transistor NT8 is electrically connected with the first power supply terminal VGH, and a second electrode of the eighth control transistor NT8 is electrically connected with the first node Nl. A control electrode of the ninth control transistor NT9 is electrically connected with the first node Nl, a first electrode of the ninth control transistor NT9 is electrically connected with the first power supply terminal VGH, and a second electrode of the ninth control transistor NT9 is electrically connected with an output terminal NOUT. A control electrode of the tenth control transistor NT 10 is electrically connected with a second node N2, a first electrode of the tenth control transistor NT 10 is electrically connected with the second power supply terminal VGL, and a second electrode of the tenth control transistor NT 10 is electrically connected with the output terminal NOUT. A control electrode of the eleventh control transistor NTH is electrically connected with the second power supply terminal VGL, a first electrode of the eleventh control transistor NT11 is electrically connected with the fifth node N5, and a second electrode of the eleventh control transistor NTH is electrically connected with the ninth node N9. A control electrode of the twelfth control transistor NT 12 is electrically connected with the second pow er supply terminal VGL, a first electrode of the twelfth control transistor NT 12 is electrically connected with the fourth node N4, and a second electrode of the twelfth control transistor NT 12 is electrically connected with the second node N2. A control electrode of the thirteenth control transistor NT 13 is electrically connected with a third power supply terminal VCX, a first electrode of the thirteenth control transistor NT 13 is electrically connected with the first power supply terminal VGH, and a second electrode of the thirteenth control transistor NT 13 is electrically connected w ith the fourth node N4. A control electrode of the fourteenth control transistor NTH is electrically connected with the first clock signal terminal CK1, a first electrode of the fourteenth control transistor NT 14 is electrically connected with the signal input terminal NIN, and a second electrode of the fourteenth control transistor NTH is electrically connected w ith a tenth node N10. A control electrode of the fifteenth control transistor NT 15 is electrically connected with the second power supply terminal VGL, a first electrode of the fifteenth control transistor NT 15 is electrically connected with the tenth node N 10, and a second electrode of the fifteenth control transistor NT 15 is electrically connected with the sixth node N6. A control electrode of the sixteenth control transistor NT16 is electrically connected with the sixth node N 6, a first electrode of the sixteenth control transistor NT 16 is electrically connected with the sixth node N 6, and a second electrode of the sixteenth control transistor NT 16 is electrically connected with the second node N2. A first plate NC11 of the first control capacitor NCI is electrically connected with the ninth node N9, and a second plate NCI 2 of the first control capacitor NCI is electrically connected with the eighth node N8. A first plate NC21 of the second control capacitor NC2 is electrically connected with the first node Nl, and a second plate NC22 of the second control capacitor NC2 is electrically connected with the first power supply terminal VGH. A first plate C31 of the third control capacitor NC3 is electrically connected with the sixth node N6, and a second plate NC32 of the third control capacitor NC3 is electrically connected with the seventh node N7.

[0218] In an exemplary implementation, the second clock signal terminal CK2 is a low-level signal during a startup initialization stage, which prevents a ninth control transistor NT9 and a tenth control transistor NT10 of a last reset shift register from simultaneously being turned on because of delay of an output signal, or the second clock signal terminal CK2 is a low-level signal during an abnormal shutdown stage, which prevents the ninth control transistor NT9 and the tenth control transistor NT 10 from simultaneously being turned on. The second clock signal terminal CK2 continuously provides a high-level signal during a normal display stage. That is, the thirteenth control transistor NT13 is continuously cut off during the normal display stage.

[0219] FIG. 9B is a timing diagram of the control shift register provided in FIG. 9A. FIG. 9B illustrates an example in which the first control transistor NT1 to the sixteenth control transistor NT16 are P-type control transistors. As shown in FIG. 9B, an operation process of the control shift register may include the following stages Cl to C5.

[0220] During the first stage Cl, signals at the signal input terminal NIN and the second clock signal terminal CK2 are high-level signals and a signal at the first clock signal terminal CK1 is a low-level signal. As the signal at the first clock signal terminal CKI is the low-lc\ cl signal, the first control transistor NT 1, the third control transistor NT3 and the twelfth control transistor NT 12 are turned on. The tumed-on first control transistor NT1 transmits the high-level signal at the signal input terminal NIN to the fourth node N4, and the signal at the fourth node N4 becomes the high-level signal. The tumed-on twelfth control transistor NT 12 transmits the high-level signal at the fourth node N4 to the second node N2. The tumed-on fourteenth control transistor NT14 transmits the high-level signal at the signal input terminal NIN to the tenth node NIO, and the signal at the tenth node N10 becomes the high-level signal. The tumed-on fifteenth control transistor NT 15 transmits the high-level signal at the tenth node N10 to the sixth node N6, the second control transistor NT2, the fourth control transistor NT4, the eighth control transistor NT8, the tenth control transistor NT10 and the sixteenth control transistor NT 16 are turned off. In addition, as the tumed-on third control transistor NT3 transmits the low -level signal of the third pow er supply terminal VGL to the fifth node N5, the signal at the second node N5 becomes the low-level signal. As the tumed-on eleventh control transistor NTH transmits the low-level signal at the second node N5 to the ninth node N9, the signal at the sixth node N9 becomes the low-level signal, and the fifth control transistor NT5 and the sixth control transistor NT6 are turned on. Although the signal of the second clock signal temrinal CK2 is the high-level signal, since the seventh control transistor NT7 is turned off, the signal at the first node N1 is not pulled high and remains the low-level signal, the ninth control transistor NT9 is turned off, and the signal at the output terminal NOUT remains at a previous low level. During the first stage Cl, the signal at the first node N1 is the low-level signal, the signal at the second node N2 is the high-level signal, and the signal at the output terminal NOUT remains the previous low-level signal.

[0221] During a second stage C2, the signal of the second clock signal terminal CK2 is a low-level signal, and the signals at the signal input terminal NIN and the first clock signal terminal CKI are high-level signals. As the signal of the second clock signal terminal CK2 is the low-level signal, and the seventh control transistor NT7 is turned on. As the signal of the first clock signal terminal CKI is the high-level signal, both the first control transistor NT I and the third control transistor NT3 are turned off. All of the fourth node N4, the second node N2, the sixth node N6 and the tenth node N10, which are affected by the third control capacitor NC3, may continue to remain the high-level signal during the previous stage. Both the fifth node N5 and the ninth node N9, which are affected by the first control capacitor NCI, may continue to remain the low-level signal during the previous stage, so that both the fifth control transistor NT5 and the sixth control transistor NT6 are turned on. All of the second control transistor NT2, the fourth control transistor NT4, the eighth control transistor NT8 and the tenth control transistor NT 10 are turned off. In addition, as the low-level signal of the second clock signal terminal CK2 is transmitted to the first node N1 through the tumed-on sixth control transistor NT6 and the tumed-on seventh control transistor NT7, the ninth transistor NT9 is turned on, and the high-level signal at the first power supply terminal VGH is transmitted to the output terminal NOUT through the turned-on ninth control transistor NT9. Therefore, during this stage, the signal at the first node N1 is the low-level signal, the signal at the second node N2 is the high-level signal, and the signal at the output terminal NOUT is the high-level signal.

[0222] During a third stage C3, the signal of the first clock signal terminal CK is the low-level signal, and the signals at the signal input terminal NIN and the second clock signal terminal CK2 are high-level signals. As the signal of the second clock signal terminal CK2 is the high-level signal, the seventh control transistor NT7 is turned off. The first node Nl, which is affected by the second control capacitor NC2, remains the low-level signal during the previous stage. As the ninth control transistor NT is continuously turned on, the high-level signal of the first power supply terminal VGH is transmitted to the output terminal NOUT through the tumed-on ninth control transistor NT9. As the signal at the first clock signal terminal CK1 is the low-level signal, the first control transistor NT1, the third control transistor NT3 and the twelfth control transistor NT 12 are turned on. The tumed-on first control transistor NT1 transmits the high-level signal at the signal input terminal NIN to the fourth node N4, and the signal at the fourth node N4 becomes the high-level signal. The tumed-on twelfth control transistor NT12 transmits the high-level signal at the fourth node N4 to the second node N2. The tumed-on fourteenth control transistor NT 14 transmits the high-level signal at the signal input terminal NIN to the tenth node N10, and the signal at the tenth node Nl 0 becomes the high-level signal. The tumed-on fifteenth control transistor NT 15 transmits the high-level signal at the tenth node N10 to the sixth node N6, the second control transistor NT2, the fourth control transistor NT4, the eighth control transistor NT8, the tenth control transistor NT 10 and the sixteenth control transistor NT 16 are turned off. In addition, as the tumed-on third control transistor NT3 transmits the low-level signal of the third power supply terminal VGL to the fifth node N5, the signal at the second node N5 becomes the low-level signal. As the tumed-on eleventh control transistor NTH transmits the low-level signal at the second node N5 to the ninth node N9, the signal at the sixth node N9 becomes the low-level signal, and the fifth control transistor NT5 and the sixth control transistor NT6 are turned on. During this stage, the signal at the first node N1 is the low-level signal, the signal at the second node N2 is the high-level signal, and the signal at the output NOUT is the high-level signal.

[0223] During the fourth stage C4, the signals at the signal input terminal NIN and the second clock signal terminal CK2 are low-level signals, and the signal at the first clock signal terminal CK1 is the high-level signal. As the signal of the first clock signal terminal CK1 is the high-level signal, both the first control transistor NT1 and the third control transistor NT3 are turned off. As the signal of the second clock signal terminal CK2 is the low-level signal, and the seventh control transistor NT7 is turned on. Due to a storage function of the third control capacitor NC3, the signals at the fourth node N4, the second node N2, the sixth node N6 and the tenth node N10 remains the high-level signal during the previous stage, and the second control transistor NT2, the fourth control transistor NT4, the eighth control transistor NT8 and the tenth control transistor NT 10 are turned off. Due to a storage function of the first control capacitor NCI, the sixth node N9 is continuously remains the low-level signal during the previous stage, and both the fifth control transistor NT5 and the sixth control transistor NT6 are turned on. In addition, the low-level signal at the second clock signal terminal CK2 is transmitted to the first node N1 via the tumed-on sixth control transistor NT6 and the tumed-on seventh control transistor NT7, and the high-level signal at the first power supply terminal VGH is transmitted to the output terminal NOUT via the tumed-on ninth control transistor NT9, and the signal at the output terminal NOUT is still the high-level signal. During this stage, the signal at the first node N1 is the high-level signal, the signal at the second node N2 is the low-level signal, and the signal at the output NOUT is the high-level signal.

[0224] During the fifth stage C5, the signal of the second clock signal terminal CK2 is the high-level signal, and the signals of the signal input terminal NIN and the second clock signal terminal CK1 are low-level signals. The signal of the first clock signal tenninal CK1 is the low-level signal, and the first control transistor NT1, the third control transistor NT3, and the fourteenth control transistor NT 14 are turned on. As the signal at the second clock signal terminal CK2 is the high-level signal, the seventh control transistor NT7 is turned off. As the turned-on first control transistor NT1 transmits the low-level signal at the signal input NIN to the fourth node N4, the signal at the fourth node N4 is the low-level signal. As the tumed-on twelfth control transistor NT 12 transmits the low-level signal at the fourth node N4 to the first node N1. the signal at the first node N1 becomes the low-level signal. As the tumed-on fourteenth control transistor NT 14 transmits the low-level signal at the signal input NIN to the tenth node N10, the signal at the tenth node N10 is the low-level signal. As the tumed-on fifteenth control transistor NT 15 transmits the low-level signal at the tenth node N10 to the sixth node N6, the signal at the sixth node N6 is the low-level signal, and the second control transistor NT2, the fourth control transistor NT4, the eighth control transistor NT8 and the tenth control transistor NT 10 are turned on. As the tumed-on second control transistor NT2 transmits the low-level signal at the first clock signal terminal CK1 to the fifth node N5, the fifth node N5 is the low-level signal, the fifth node N5 and the ninth node N9 are continuously remains the low-level signal during the previous stage, and the fifth control transistor NT5 and the sixth control transistor NT6 are turned on. As the signal at the second clock signal terminal CK2 is the high-level signal, the seventh control transistor NT7 is turned off. In addition, as the high-level signal at the first power supply terminal VGH is transmitted to the first node N1 through the tumed-on eighth control transistor NT8, the ninth control transistor NT9 is turned off. As the low-level signal at the second power supply tenninal VGL is transmitted to the output terminal NOUT via the tumed-on tenth control transistor NT 10, the signal at the output terminal NOUT becomes the low-level signal. During this stage, the signal at the first node N1 is the high-level signal, the signal at the second node N2 is the low-level signal, and the signal at the output tenninal NOUT is the low-level signal.

[0225] In an exemplary implementation, as shown in FIGs. 3 and 4, the display substrate may further include two control initial signal lines NSTV, a first control clock signal line NCK1, a second control clock signal line NCK2, three first control power supply lines NVGH, two second control power supply lines NVGL, a third control power supply line NVCX, and a control cascade signal line NCL, which extend along the second direction D2. An input terminal of a first cascaded control shift register is electrically connected with a control initial signal line NSTV, and the control cascade signal line NCL is electrically connected with an output terminal of an i-th cascaded control shift register and an input terminal of an i-th cascaded control shift register. A first clock signal terminal of the i-th cascaded control shift register is electrically connected with the first control clock signal line NCK1, and a second clock signal terminal is electrically connected with the second control clock signal line NCK2. A first clock signal terminal of an (i+I)-th cascaded control shift register is electrically connected with the second control clock signal line NCK2, and a second clock signal terminal is connected with the first control clock signal line NCK1. A first power supply terminal of the i-th cascaded control shift register is electrically connected with a first control power supply line NVGH, a second power supply terminal of the i-th cascaded control shift register is electrically connected with a second control power supply line NVGL, and a third power supply terminal of the i-th cascaded control shift register is connected with the third control power supply line NVCX.

[0226] FIG. 10A is an equivalent circuit diagram of a reset shift register provided in an exemplary embodiment. As shown in FIG. 10A, in an exemplary implementation, the reset shift register includes a first reset transistor RT1 to a thirteenth reset transistor RT13 and a first reset capacitor RC1 to a third reset capacitor RC3. FIG. 10A illustrates an example in which the reset shift registers is of a 13T3C circuit configuration.

[0227] In an exemplary implementation, a control electrode of the first reset transistor RT1 is electrically connected with a second clock signal terminal CK2, a first electrode of the first reset transistor RT1 is electrically connected with an input terminal RIN, and a second electrode of the first reset transistor RT1 is electrically connected with a first node Nl. A control electrode of the second reset transistor RT2 is electrically connected with the first node N1, a first electrode of the second reset transistor RT2 is electrically connected with a second clock signal line CK2, and a second electrode of the second reset transistor RT2 is electrically connected with a second node N2. A control electrode of the third reset transistor RT3 is connected with the first clock signal terminal CK2, a first electrode of the third reset transistor RT3 is connected with a second power supply terminal VGL, and a second electrode of the third reset transistor RT3 is electrically connected with the second node N2. A control electrode of the fourth reset transistor RT4 is electrically connected with a third node N3, a first electrode of the fourth reset transistor RT4 is electrically connected with the first clock signal terminal CK1, and a second electrode of the fourth reset transistor RT4 is electrically connected with a fifth node N5. A control electrode of the fifth reset transistor RT5 is connected with a first node N4, a first electrode of the fifth reset transistor RT5 is connected with the fifth node N5, and a second electrode of the fifth reset transistor RT5 is connected with a first power supply terminal VGH. A control electrode of the sixth reset transistor RT6 is electrically connected with the fourth node N4, a first electrode of the sixth reset transistor RT6 is electrically connected with the first clock signal terminal CK1, and a second electrode of the sixth reset transistor RT6 is electrically connected with a sixth node N6. A control electrode of the seventh reset transistor RT7 is connected with the first clock signal terminal CK1, a first electrode of the seventh reset transistor RT7 is connected with the sixth node N6, and a second electrode of the seventh reset transistor RT7 is connected with a seventh node N7. A control electrode of the eighth reset transistor RT8 is electrically connected with the first node Nl, a first electrode of the eighth reset transistor RT8 is electrically connected with the first power supply terminal VGH, and a second electrode of the eighth reset transistor RT8 is electrically connected with the seventh node N7. A control electrode of the ninth reset transistor RT9 is connected with the seventh node N7, a first electrode of the ninth reset transistor RT9 is electrically connected with the first power supply terminal VGH, and a second electrode of the ninth reset transistor RT9 is electrically connected with an output terminal ROUT. A control electrode of the tenth reset transistor RT10 is electrically connected with the third node N3, a first electrode of the tenth reset transistor RT10 is electrically connected with the second power supply terminal VGL, and a second electrode of the tenth reset transistor RT10 is electrically connected with the output terminal ROUT. A control electrode of the eleventh reset transistor RT11 is electrically connected with the second power supply terminal VGL, a first electrode of the eleventh reset transistor RT 11 is electrically connected with the second node N2, and a second electrode of the eleventh reset transistor RT11 is electrically connected with the fourth node N4. A control electrode of the twelfth reset transistor RT12 is electrically connected with the second power supply terminal VGL, a first electrode of the twelfth reset transistor RT12 is electrically connected with the first node Nl, and a second electrode of the twelfth reset transistor RT12 is electrically connected with the third node N3. A control electrode of the thirteenth reset transistor RT13 is electrically connected with the second clock signal terminal CK2, a first electrode of the thirteenth reset transistor RT13 is electrically connected with the first node Nl, and a second electrode of the thirteenth reset transistor RT13 is electrically connected with the first power supply terminal VGH. A first plate RC11 of the first reset capacitor RC1 is connected with the fourth node N4, and a second plate RC12 of the first reset capacitor RC1 is connected with the sixth node N6. A first plate RC21 of the second reset capacitor RC2 is connected with the fourth node N7, and a second plate RC22 of the second reset capacitor RC2 is connected with the first power supply tenninal VGH. A first plate RC31 of the third reset capacitor RC3 is connected with the third node N3, and a second plate RC32 of the third reset capacitor RC3 is connected with the fifth node N5.

[0228] In an exemplary implementation, the first reset transistor RT1 to the thirteenth reset transistor RT13 may be P-type transistors or may be N-typc transistors.

[0229] In an exemplary implementation, the first power supply terminal VGH continuously provides the high-level signal, and the second power supply terminal VGL continuously provides the low-level signal. Since the second power supply terminal VGL continuously provides the low-level signal, the eleventh reset transistor RT11 and the twelfth reset transistor RT12 are continuously turned on.

[0230] In an exemplary' implementation, the signal at the second clock signal terminal CK2 is the low-level signal during the startup initialization stage, which prevents a ninth reset transistor RT9 and a tenth reset transistor RT10 of a last reset shift register from simultaneously being turned on because of delay of an output signal, or the signal at the second clock signal terminal CK2 is the low-level signal dining an abnormal shutdown stage, which prevents the ninth reset transistor RT9 and the tenth reset transistor RT10 from simultaneously being turned on. The second clock signal terminal CK2 continuously provides the high-level signal in a normal display stage, i.e. the thirteenth reset transistor RT13 is continuously cut off in the normal display stage.

[0231] FIG. 10B is a timing diagram of the reset shift register provided in FIG. 10A. FIG. I0B illustrates an example in which the first reset transistor RT1 to the thirteenth reset transistor RT13 are P-type transistors, and an operating process of the reset shift register provided in an exemplary embodiment may include following stages DI to D5.

[0232] During the first stage DI, the signal of the first clock signal tenninal CK1 is a high-level signal, and the signal of the third clock signal terminal CK2 is a low-level signal. As the signal at the second clock signal terminal CK2 is the low-level signal, the first reset transistor RT1, the third reset transistor RT3 and the twelfth reset transistor RT12 are tinned on. The tumed-on first reset transistor RT1 transmits the high-level signal of the input terminal RIN to the first node Nl, so that a level of the first node N1 becomes the high-level signal. The turned-on twelfth reset transistor RT12 transmits the high-level signal of the first node N1 to the third node N2, so that the second reset transistor RT2, the fourth reset transistor RT4, the eighth reset transistor RT8, and the tenth reset transistor RT10 are cut off. In addition, the tumed-on third reset transistor RT3 transmits the low-level signal of the third power supply terminal VGL to the second node N2, so that a level at the second node N2 becomes a low level. The tumed-on eleventh reset transistor RT11 transmits the low-level signal at the second node N2 to the fourth node N4, so that a level at the fourth node N4 becomes a low level, and both the fifth reset transistor RT5 and the sixth reset transistor RT6 are turned on. As the signal at the first clock signal terminal CK1 is the high-level signal, the seventh reset transistor RT7 is cut off. In addition, the ninth reset transistor RT9, which is affected by the third reset capacitor RC3, is cut off. During the first stage Pl, since both the ninth reset transistor RT9 and the tenth reset transistor RT10 are cut off, a signal at the output terminal ROUT remains the low level as before.

[0233] During the second stage D2, the signal at the first clock signal terminal CK1 is the low-Ici cl signal, and the signal of the second clock signal terminal CK2 is the high-level signal. As the signal at the first clock signal terminal CK1 is the low-level signal, the seventh reset transistor RT7 is turned on. As the signal of the second clock signal terminal CK2 is the high-level signal, both the first reset transistor RT1 and the third reset transistor RT3 are cut off. The first node Nl and the third node N3, which are affected by the third reset capacitor RC3, may continue to remain the high-level signal as that during the previous stage. The fourth node N4, which is affected by the first reset capacitor RC1, may continue to remain the low level as that during the previous stage. Therefore, both the fifth reset transistor RT5 and the sixth reset transistor RT6 are turned on. All of the second reset transistor RT2, the fourth reset transistor RT4, the eighth reset transistor RT8 and the tenth reset transistor RT10 are cut off. In addition, as the low-level signal at the first clock signal terminal CK1 is transmitted to the seventh node N7 via the tumed-on sixth reset transistor RT6 and the seventh reset transistor RT7, the ninth light emitting transistor RT9 is turned on. As the tumed-on ninth reset transistor RT9 outputs the high-level signal at the first power supply terminal VGH, the signal at the output terminal ROUT is the high-level signal. In addition,

[0234] during the third stage D3, the signal at the second clock signal terminal CK2 is the low-level signal, and the signal at the first clock signal terminal CK1 is the high-level signal. As the signal at the first clock signal terminal CK1 is the high-level signal, the seventh reset transistor RT7 is cut off. All of the second reset transistor RT2, the fourth reset transistor RT4, the eighth reset transistor RT8 and the tenth reset transistor RT10 are cut off. As the signal at the second clock signal terminal CK2 is the low-level signal, both the first reset transistor RT1 and the third reset transistor RT3 are turned on. The ninth reset transistor RT9, which is affected by the second reset capacitor RC3, remains the tumed-on state. As the tumed-on ninth reset transistor RT9 outputs the high-level signal at the first power supply terminal VGH, the signal at the output terminal ROUT is still the high-level signal.

[0235] During the fourth stage D4, the signal of the first clock signal terminal CK1 is the low-level signal and the signal of the second clock signal terminal CK2 is the high-level signal. As the signal at the second clock signal terminal CK2 is the high-level signal, both the first reset transistor RT1 and the third reset transistor RT3 are cut off. As the signal at the first clock signal terminal CK1 is at a low level, the seventh reset transistor RT7 is turned on. Due to a storage effect of the third reset capacitor RC3, both levels at the first node Nl and the third node N3 maintain the high-level signal as that during a previous stage, so that all of the second reset transistor RT2, the fourth reset transistor RT4, the eighth reset transistor RT8 and the tenth reset transistor RT10 are cut off. Due to a storage effect of the first reset capacitor RC1, the signal at the fourth node N4 continues to maintain at the low level as that dining the previous stage, so that both the fifth reset transistor RT5 and the sixth reset transistor RT6 are turned on. In addition, the low-level signal at the first clock signal terminal CK1 is transmitted to the seventh node N7 via the tumed-on sixth reset transistor RT6 and the seventh reset transistor RT7, and the tumed-on ninth reset transistor RT9 outputs the high-level signal at the first power supply terminal VGH, so that the signal at the output terminal ROUT is still the high-level signal.

[0236] During the fifth stage D5, the signal at the first clock signal terminal OKI is the high-level signal, and the signal at the third clock signal terminal CK2 is the low-level signal. As the signal at the second clock signal terminal CK2 is the low-level signal, both the first reset transistor RT1 and the third reset transistor RT3 are turned on. The signal at the first clock signal terminal CKI is the high-level signal, and the seventh reset transistor RT7 is cut off. The tumed-on first reset transistor RT1 transmits the low-level signal at the input terminal RIN to the first node Nl, so that the level at the first node Nl becomes the low level. The tumed-on twelfth reset transistor RT12 transmits the low-level signal at the first node Nl to the third node N3, so that the level at the third node N3 becomes the low level, and all of the second reset transistor RT2, the fourth reset transistor RT4, the eighth reset transistor RT8 and the tenth reset transistor RT10 are turned on. As the tumed-on second reset transistor RT2 transmits the low-level signal at the second clock signal terminal CK2 to the second node N2, the level at the second node N2 may be further lowered, so that levels at the second node N2 and the fourth node N4 continue to maintain at the low level as that during the previous stage, so that both the fifth reset transistor RT5 and the sixth reset transistor RT6 are turned on. As the signal at the first clock signal terminal CK1 is the high-level signal, the seventh reset transistor RT7 is cut off. In addition, the tumed-on eighth reset transistor RT8 transmits the high-level signal at the first power supply terminal VGH to the seventh node N7, and the ninth reset transistor RT9 is cut off. As the tumed-on tenth reset transistor RT10 outputs the low-level signal at the second power supply terminal VGL, the signal at the output terminal ROUT becomes the low level.

[0237] In an exemplary implementation, as shown in FIGs. 3 and 4, the display substrate may further include a reset initial signal line RSTV, a first reset clock signal line RCK1, a second reset clock signal line RCK2, a first reset power supply line RVGH, two second reset power supply lines RVGL, a third reset power supply line RVCX and a reset cascade signal line RCL, which extend along the second direction D2. An input terminal of the first cascaded reset shift register is electrically connected with the reset initial signal line RSTV, and the reset cascade signal line RCL is electrically connected with an output terminal of the i-th cascaded reset shift register and an input terminal of the (i +1 )-th cascaded reset shift register. A first clock signal terminal of the i-th cascaded reset shift register is electrically connected with the first reset clock signal line RCK1, and a second clock signal terminal is electrically connected with the second reset clock signal line RCK2. A first clock signal terminal of the (i+1 )-th cascaded reset shift register is electrically connected with the second reset clock signal line RCK2, and a second clock signal terminal is electrically connected with the first reset clock signal line RCK1. A first power supply terminal of the i-th cascaded reset shift register is electrically connected with the first reset power supply line RVGH, a second power supply terminal of the i-th cascaded reset shift register is electrically connected with a second reset power supply line RVGL, and a third power supply terminal of the i-th cascaded reset shift register is electrically connected with the third reset power supply line RVCX.

[0238] FIG. 11A is an equivalent circuit diagram of a light emitting shift register provided in an exemplary embodiment. As shown in FIG. 11A, in an exemplary implementation, the light emitting shift register includes first light to thirteenth emitting transistors ET1 to ETI3 and first to third light emitting capacitors ECI to EC3. FIG. 11A illustrates an example in which the light emitting shift register is of a 13T3C a circuit configuration. The circuit structure of the light emitting shift register is the same as the circuit structure of the reset register, which will not be repeated in the present disclosure.

[0239] FIG. 1 IB is a timing diagram of the light emitting shift register provided in FIG. 11A. First to fifth stages El to E5 in an operation process of the light emitting shift register are the same as those stages in the operation process of the reset shift register, which will not be repeated in the present disclosure.

[0240] In an exemplary implementation, as shown in FIGs. 3 and 4, a length of the reset drive circuit along the first direction D1 is greater than a length of the dummy reset drive circuit along the first direction DI, wherein the first direction is an arrangement direction of the plurality of drive circuits.

[0241] In an exemplary implementation, at least one dummy reset shift register is located between adjacent reset shift registers.

[0242] FIG. 12A is a schematic diagram of a part of a film of a reset shift register and a dummy reset shift register, and FIG. 12B is a schematic diagram of a part of a film of a reset shift register and a dummy reset shift register. As shown in FIGs. 12A and 12B, the reset shift register includes at least one reset transistor and at least one reset capacitor. At least one dummy drive unit further includes a plurality of dummy source-drain electrodes. At least part of at least one dummy active pattern in at least one dummy reset shift register has a same shape as a shape of at least part of an active pattern of the at least one reset transistor. At least part of at least one dummy control electrode in the at least one dummy reset shift register has a same shape as a shape of at least part of a control electrode of the at least one reset transistor or the at least one reset capacitor. At least part of at least one dummy source-drain electrode in the at least one dummy reset shift register has a same shape as a shape of at least part of at least one electrode of first and second electrodes of the at least one reset transistor.

[0243] In an exemplary implementation, as shown in FIG. 12A, at least one dummy reset register includes first to twenty-first dummy active patterns DRA1 to DRA21 and first to eighth dummy control electrodes DRG11 to DRG18. The at least one reset register includes an active pattern RT1-1 and a control electrode RT1 -2 of a first reset transistor to an active pattern RT13-1 and a control electrode RT13-2 of a thirteenth reset transistor. A shape of the first dummy active pattern DRA1 is the same as a shape of a part of the active pattern RT6-1 of tire sixth reset transistor. A shape of the second dummy active pattern DRA2 is the same as a shape of a part of the active pattern RT2-1 of the second reset transistor. A shape of the third dummy active pattern DRA3 is the same as a shape of a part of the active pattern RT6-1 of the sixth reset transistor. A shape of the fourth dummy active pattern DRA4 is the same as a shape of a part of the active pattern RT7-1 of the seventh reset transistor. A shape of the fifth dummy active pattern DRA5 is the same as a shape of a part of the active pattern RT2-1 of the second reset transistor. A shape of the sixth dummy active pattern DRA6 is the same as a shape of a part of the active pattern RT8-1 of the eighth reset transistor. A shape of the seventh dummy active pattern DRA7 is the same as a shape of a part of the active pattern RT13-1 of the thirteenth reset transistor. A shape of the eighth dummy active pattern DRA8 is the same as a shape of a part of the active pattern RT5-1 of the fifth reset transistor. A shape of the ninth dummy active pattern DRA9 is the same as shapes of a part of an active pattern RT11-1 of the eleventh reset transistor and a part of the active pattern RT12-1 of the twelfth reset transistor. A shape of the tenth dummy active pattern DRAIO is the same as a shape of a part of the active pattern RT12-1 of the twelfth reset transistor. A shape of the eleventh dummy active pattern DRA11 is the same as a shape of a part of the active pattern RT11-1 of the eleventh reset transistor. A shape of the twelfth dummy active pattern DRAW is the same as a shape of a part of the active pattern RT4-1 of the fourth reset transistor. A shape of any one of the thirteenth to twenty-first dummy active patterns DRA 13 to DRA21 is the same as a shape of a part of an integrated structure of an active pattern of the ninth reset transistor and the tenth reset transistor. A shape of the first dummy control electrode DRG11 is the same as a shape of a part of an integrated structure of a control electrode RT1 -2 of the first reset transistor and a control electrode RT3-2 of the third reset transistor. A shape of a part of the second dummy control electrode DRG12 is the same as a shape of a part of an integrated structure of a control electrode RT6-2 of the sixth reset transistor and the first plate RC11 of the first reset capacitor. A shape of a part of the second dummy control electrode DRG12 is the same as a shape of a part of a control electrode RT2-2 of the second reset capacitor. A shape of the third dummy control electrode DRG13 is the same as a shape of a part of a control electrode RT7-2 of the seventh reset transistor. A shape of a part of the fourth dummy control electrode DRG14 is the same as a shape of a part of a control electrode RT2-2 of the second reset capacitor. A shape of the fifth dummy control electrode DRG52 is the same as a shape of a part of a control electrode RT8-2 of the eighth reset capacitor. A shape of the sixth dummy control electrode DRG62 is the same as a shape of a part of a control electrode RT13-2 of the thirteenth reset transistor. A shape of a part of the seventh dummy control electrode DRG17 is the same as a shape of a part of an integrated structure of a control electrode RT11-2 of the eleventh reset transistor and a control electrode RT12-2 of the twelfth reset transistor. A shape of a part of the seventh dummy control electrode DRG17 is the same as a shape of a part of a control electrode RT5-2 of the fifth reset capacitor. A shape of a part of the seventh dummy control electrode DRG17 is the same as a shape of a part of an integrated structure of a control electrode RT9-2 of the ninth reset transistor and a first plate RC21 of the second reset capacitor. A shape of a part of the seventh dummy control electrode DRG17 is the same as a shape of a part of an integrated structure of a control electrode RT4-2 of the fourth transistor, a control electrode RT10-2 of the tenth reset transistor and a first plate RC31 of the third reset capacitor.

[0244] In an exemplary implementation, as shown in FIG. 12B, at least one dummy reset register includes first to ninth dummy source-drain electrodes DRS1 to DRS9. A shape of a part of the first dummy source-drain electrode DRS1 is the same as a shape of a part of the first electrode RT1-3 of the first reset transistor. A shape of a part of the first dummy source-drain electrode DRS1 is die same as a shape of a part of an integrated structure of a second electrode RT6-4 of the sixth reset transistor and a first electrode RT7-3 of the seventh reset transistor. A shape of a part of the first dummy source-drain electrode DRS1 is the same as a shape of a part of an integrated structure of a first electrode RT5-3 of the fifth reset transistor, a first electrode RT8-3 of the eighth reset transistor, a first electrode RT9-3 of the ninth reset transistor and a first electrode RT13-3 of the thirteenth reset transistor. A shape of a part of the first dummy source-drain electrode DRS1 is the same as a shape of a part of an integrated structure of a first electrode RT7-7 of the seventh reset transistor and a first electrode RT8-4 of the eighth reset transistor. A shape of a part of the first dummy source-drain electrode DRS1 is the same as a shape of a part of a second electrode RT13-4 of the thirteenth reset transistor. A shape of a part of the second dummy source-drain electrode DRS2 is the same as a shape of a part of a second electrode RT11-4 of the eleventh reset transistor. A shape of a part of the second dummy source-drain electrode DRS2 is the same as a shape of a part of an integrated structure of a second electrode RT2-4 of the second reset transistor, a second electrode RT3-4 of the third reset transistor and a first electrode RT11-3 of the eleventh reset transistor. A shape of a part of the third dummy source-drain electrode DRS3 is the same as a shape of a part of an integrated structure of the first electrode RT4-3 of the fourth reset transistor and a first electrode RT6-3 of the sixth reset transistor. A shape of a part of the fourth dummy source-drain electrode DRS4 is the same as a shape of a part of an integrated structure of a second electrode RT4-4 of the fourth reset transistor and a second electrode RT5-4 of the fifth reset transistor. A shape of a part of any one of the fifth to ninth dummy source-drain electrodes DRS5 to DRS is the same as a shape of a part of the second electrode RT10-4 of the tenth reset transistor.

[0245] In an exemplary embodiment, as shown in FIGs. 3 and 12B, an orthographic projection of the reset cascade signal line RCL on the base substrate is located between an orthographic projection of a first one of second reset power supply lines RVGL on the base substrate and an orthographic projection of the third reset power supply line RVCX on the base substrate.

[0246] In an exemplary implementation, as shown in FIGs. 3 and 12B, the dummy reset shift register is located on a side of the reset cascade signal line RCL close to the display area, and at least one dummy source-drain electrode in the dummy reset shift register is electrically connected with the first reset power supply line RVGH.

[0247] In an exemplary implementation, as shown in FIGs. 3 and 12B, the display substrate further includes a drive structure layer. The drive structure layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer. The reset cascade signal line RCL, the reset initial signal line RSTV and the two second reset power supply lines RVGL are located in the fourth conductive layer. The first reset clock signal line RCK1, the second reset clock signal line RCK2, the first reset power supply line RVGH and the third reset power supply line RVCX are located in the fifth conductive layer.

[0248] In an exemplary implementation, as shown in FIG. 4, a length of the light emitting drive circuit along the first direction DI is greater than or equal to a length of the dummy light emitting drive circuit along the first direction DI, wherein the first direction is an arrangement direction of the plurality of drive circuits.

[0249] FIG. 13A is a schematic diagram of a part of a film of a light emitting shift register and a dummy light emitting shift register, and FIG. I3B is a schematic diagram of a part of a film of a light emitting shift register and a dummy light emitting shift register. As shown in FIGs. 13A and 13B, the light emitting drive circuit includes a plurality of cascaded light emitting shift registers, and the dummy light emitting drive circuit includes at least one dummy light emitting shift register located between adjacent light emitting shift registers. The light emitting shift register includes at least one light emitting transistor and at least one light emitting capacitor. The at least one dummy shift register further includes a plurality of dummy source-drain electrodes. A shape of at least part of the at least one dummy active pattern in the at least one dummy light emitting shift register is the same as a shape of at least part of the active pattern of the at least one light emitting transistor. A shape of at least part of at least one dummy control electrode in the at least one dummy light emitting shift register is the same as a shape of at least part of the control electrode of the at least one light emitting transistor or of at least part of the light emitting capacitor. A shape of at least part of at least one dummy source-drain electrode in at least one dummy light emitting shift register has the same shape as a shape of at least part of at least one of the first and second electrodes of the at least one light emitting transistor.

[0250] In an exemplary implementation, as shown in FIG. 13A, at least one dummy light emitting register includes first to twenty-first dummy active patterns DEA1 to DEA21 and first to eighth dummy control electrodes DEG11 to DEG18. The at least one light emitting register includes an active pattern ET1-1 and a control electrode ET1-2 of a first light emitting transistor to an active pattern ET13-1 and a control electrode ET13-2 of a thirteenth light emitting transistor. A shape of the first dummy active pattern DEA1 is the same as a shape of a part of the active pattern ET6-1 of the sixth light emitting transistor. A shape of the second dummy active pattern DEA2 is the same as a shape of a part of the active pattern ET2-1 of the second light emitting transistor. A shape of the third dummy active pattern DEA3 is the same as a shape of a part of the active pattern ET6-1 of the sixth light emitting transistor. A shape of the fourth dummy active pattern DEA4 is the same as a shape of a part of the active pattern ET7-1 of the seventh light emitting transistor. A shape of the fifth dummy active pattern DEA5 is the same as a shape of a part of the active pattern ET2-1 of the second light emitting transistor. A shape of the sixth dummy active pattern DEA6 is the same as a shape of a part of the active pattern ET8-1 of the eighth light emitting transistor. A shape of the seventh dummy active pattern DEA7 is the same as a shape of a part of the active pattern ET13-I of the thirteenth light emitting transistor. A shape of the eighth dummy active pattern DEA 8 is the same as a shape of a part of the active pattern ET5-1 of the fifth light emitting transistor. A shape of the ninth dummy active pattern DEA9 is the same as shapes of a part of an active pattern ET11-1 of the eleventh light emitting transistor and a part of the active pattern ET12-1 of the twelfth light emitting transistor. A shape of the tenth dummy active pattern DEA 10 is the same as a shape of a part of the active pattern ET12-1 of the twelfth light emitting transistor. A shape of the eleventh dummy active pattern DEA11 is the same as a shape of a part of the active pattern ET11-1 of the eleventh light emitting transistor. A shape of the twelfth dummy active pattern DEA 10 is the same as a shape of a part of the active pattern ET4-1 of the fourth light emitting transistor. A shape of any one of the thirteenth to twenty-first dummy active patterns DEA 13 to DEA21 is the same as a shape of a part of an integrated structure of an active pattern of the ninth light emitting transistor and the tenth light emitting transistor. A shape of the first dummy control electrode DEG11 is the same as a shape of a part of an integrated structure of a control electrode ET1-2 of the first light emitting transistor and a control electrode ET3-2 of the third light emitting transistor. A shape of a part of the second dummy control electrode DEG12 is the same as a shape of a part of an integrated structure of a control electrode ET6-2 of the sixth light emitting transistor and the first plate EC 11 of the first light emitting capacitor. A shape of a part of the second dummy control electrode DEG12 is the same as a shape of a part of a control electrode ET2-2 of the second light emitting capacitor. A shape of the third dummy control electrode DEG13 is the same as a shape of a part of a control electrode ET7-2 of the seventh light emitting transistor. A shape of a part of the fourth dummy control electrode DEG14 is the same as a shape of a part of a control electrode ET2-2 of the second light emitting capacitor. A shape of the fifth dummy control electrode DEG52 is the same as a shape of a part of a control electrode ET8-2 of the eighth light emitting capacitor. A shape of the sixth dummy control electrode DEG62 is the same as a shape of a part of a control electrode ET13-2 of the thirteenth light emitting transistor. A shape of a part of the seventh dummy control electrode DEG17 is the same as a shape of a part of an integrated structure of a control electrode ET11-2 of the eleventh light emitting transistor and a control electrode ET12-2 of the twelfth light emitting transistor. A shape of a part of the seventh dummy control electrode DEG17 is the same as a shape of a part of a control electrode ET5-2 of the fifth light emitting capacitor. A shape of a part of the seventh dummy control electrode DEG17 is the same as a shape of a part of an integrated structure of a control electrode ET9-2 of the ninth light emitting transistor and the first plate EC21 of the second light emitting capacitor. A shape of a part of the seventh dummy control electrode DEG17 is the same as a shape of a part of an integrated structure of a control electrode ET4-2 of the fourth transistor, a control electrode ET10-2 of the tenth light emitting transistor and a first plate EC31 of the third light emitting capacitor.

[0251] In an exemplary implementation, as shown in FIG. 13B, at least one dummy light emitting register includes first to ninth dummy source-drain electrodes DESI to DES9. A shape of a part of the first dummy source-drain electrode DESI is the same as a shape of a part of the first electrode ET1-3 of the first light emitting transistor. A shape of a part of the first dummy source-drain electrode DESI is the same as a shape of a part of an integrated structure of a second electrode ET6-4 of the sixth light emitting transistor and a first electrode ET7-3 of the seventh light emitting transistor. A shape of a part of the first dummy source-drain electrode DESI is the same as a shape of a part of an integrated structure of a first electrode ET5-3 of the fifth light emitting transistor, a first electrode ET8-3 of the eighth light emitting transistor, a first electrode ET9-3 of the ninth light emitting transistor and a first electrode ET13-3 of the thirteenth light emitting transistor. A shape of a part of the first dummy source-drain electrode DES 1 is the same as a shape of a part of an integrated structure of a first electrode ET7-7 of the seventh light emitting transistor and a first electrode ET8-4 of the eighth light emitting transistor. A shape of a part of the first dummy source-drain electrode DESI is the same as a shape of a part of a second electrode ET13-4 of the thirteenth light emitting transistor. A shape of a part of the second dummy source-drain electrode DES2 is the same as a shape of a part of a second electrode ET11-4 of the eleventh light emitting transistor, a shape of a part of the second dummy source-drain electrode DES 2 is the same as a shape of a part of the integrated structure of the second electrode ET 2-4 of the second reset transistor, the second electrode ET 3-4 of the third reset transistor, and the first electrode ET 11-3 of the eleventh reset transistor. A shape of a part of the third dummy source-drain electrode DES3 is the same as a shape of apart of an integrated structure of the first electrode ET4-3 of the fourth light emitting transistor and a first electrode ET6-3 of the sixth light emitting transistor. A shape of a part of the fourth dummy source-drain electrode DES4 is the same as a shape of a part of an integrated structure of a second electrode ET4-4 of the fourth light emitting transistor and a second electrode ET5-4 of the fifth light emitting transistor. A shape of a part of any one of the fifth to ninth dummy source-drain electrodes DES5 to DES is the same as a shape of a part of the second electrode ET10-4 of the tenth light emitting transistor.

[0252] In an exemplary implementation, as shown in FIGs. 4 and 13B, orthographic projections of the light emitting initial signal line ESTV, a first one of second light emitting power supply lines EVGL, the third light emitting power supply line EVCX, the first light emitting clock signal line ECK1, the second light emitting clock signal line ECK2, the first light emitting power supply line EVGH and the second first light emitting power supply line EVGH on the base substrate are arranged sequentially along a direction close to the display area.

[0253] In an exemplary implementation, as shown in FIGs. 4 and 13B, the light emitting cascade signal line ECL is electrically connected with an output terminal of at least one cascaded light emitting shift register and an input terminal of at least one cascaded light emitting shift register, respectively. An orthographic projection of the light emitting cascade signal line ECL on the base substrate is located between an orthographic projection of the first one of second light emitting power supply lines EVGL on the base substrate and an orthographic projection of the third light emitting power supply line EVCX on the base substrate. The dummy light emitting shift register is located on a side of the light emitting cascade signal line ECL close to the display area, and at least one dummy source-drain electrode in the dummy light emitting shift register is electrically connected with the first light emitting power supply line EVGH.

[0254] In an exemplary implementation, the display substrate further includes a drive structure layer. The drive structure layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer. The light emitting cascade signal line ECL, the light emitting initial signal line ESTV and the two second light emitting power supply lines EVGL are located in the fourth conductive layer. The first light emitting clock signal line ECK1, the second light emitting clock signal line ECK2, the first light emitting power supply line EVGH and the third light emitting power supply line EVCX are located in the fifth conductive layer.

[0255] In an exemplary implementation, as shown in FIGs. 3 and 4, a length of the control drive circuit along the first direction DI is greater than or equal to a length of the dummy control drive circuit along the first direction DI, wherein the first direction DI is an arrangement direction of the plurality of drive circuits.

[0256] FIG. 14A is a schematic diagram of a part of a film of a control shift register and a dummy control shift register, and FIG. 14B is a schematic diagram of a part of a film of a control shift register and a dummy control shift register. As shown in FIGs. 14A and 14B, the control drive circuit includes a plurality of cascaded control shift registers, and the dummy control drive circuit includes at least one dummy control shift register located between adj acent control shift registers. The control shift register includes at least one control transistor and at least one control capacitor. The at least one dummy shift register further includes a plurality of dummy source-drain electrodes. A shape of at least part of the at least one dummy active pattern in the at least one dummy control shift register is the same as a shape of at least part of the active pattern of the at least one control transistor. A shape of at least part of at least one dummy control electrode in the at least one dummy control shift register is the same as a shape of at least part of the control electrode of the at least one control transistor or of at least part of the control capacitor. A shape of at least part of at least one dummy source-drain electrode in at least one dummy control shift register has the same shape as a shape of at least part of at least one of the first and second electrodes of the at least one control transistor.

[0257] In an exemplary implementation, as shown in FIG. 14A, at least one dummy control register includes first to thirtieth dummy active patterns DNA1 to DNA30 and first to ninth dummy control electrodes DNG11 to DNGI9. The at least one control register includes an active pattern NT1-1 and a control electrode NT 1-2 of a first control transistor to an active pattern NT 16-1 and a control electrode NT16-2 of a sixteenth control transistor. A shape of the first dummy active pattern DNA1 is the same as a shape of a part of the active pattern NT14-1 of the fourteenth control transistor. A shape of the second dummy active pattern DNA2 is the same as a shape of a part of the active pattern NT1-I of the first control transistor. A shape of the third dummy active pattern DNA3 is the same as a shape of a part of the active pattern NT 14-1 of the fourteenth control transistor. A shape of the fourth dummy active pattern DNA4 is the same as a shape of a part of the active pattern NT 1-1 of the first control transistor. A shape of the fifth dummy active pattern DNA5 is the same as a shape of a part of the active pattern NT3-1 of the third control transistor. A shape of the sixth dummy active pattern DNA6 is the same as a shape of a part of the active pattern NT3-1 of the third control transistor. A shape of the seventh dummy active pattern DNA7 is the same as a shape of a part of the active pattern NT14-1 of the fifteenth control transistor. A shape of the eighth dummy active pattern DNA8 is the same as a shape of a part of the active pattern NT15-1 of the fifteenth control transistor. A shape of the ninth dummy active pattern DNA9 is the same as a shape of a part of the active pattern NT4-1 of the fourth control transistor. A shape of the tenth dummy active pattern DNA10 is the same as a shape of a part of the active pattern NT4-1 of the fourth control transistor. Shapes of the eleventh dummy active pattern DNA11 and the fourteenth dummy active pattern DNA14 are the same as a shape of a part of the active pattern NT7-1 of the seventh control transistor. A shape of the twelfth dummy active pattern DNA12 is the same as a shape of a part of the thirteenth dummy active pattern DNA13 and of the active pattern NT6-1 of the sixth control transistor. A shape of the fifteenth dummy active pattern DNA15 is the same as a shape of a part of the seventeenth dummy active pattern DNA17 and of the active pattern NT8-1 of the seventh control transistor. A shape of the sixteenth dummy active pattern DNA16 is the same as a shape of a part of the eighteenth dummy active pattern DNA18 and of the active pattern NT5-1 of the fifth control transistor. A shape of the twelfth dummy active pattern DNA12 is the same as a shape of the thirteenth dummy active pattern DNA13 or a shape of a part of the active pattern NT6-1 of the sixth control transistor. A shape of the nineteenth dummy active pattern DNA19 is the same as a shape of a part of the active pattern NT 13-1 of the thirteenth control transistor. A shape of the twentieth dummy active pattern DNA20 is the same as a shape of a part of the active pattern NT16-1 of the sixteenth control transistor. A shape of the twenty-first dummy active pattern DNA21 is the same as a shape of a part of the active pattern NT12-1 of the twelfth control transistor. A shape of any one of the twenty-second to thirtieth dummy active patterns DNA22 to DNA30 is the same as a shape of a part of an integrated structure of an active pattern of the ninth control transistor and the tenth control transistor. A shape of the first dummy control electrode DNG11 is the same as a shape of a part of an integrated structure of the control electrode NT 1-2 of the first control transistor, the control electrode NT3-2 of the third control transistor and the control electrode NT 14-2 of the fourteenth control transistor. A shape of a part of the second dummy control electrode DNG12 is the same as a shape of a part of an integrated structure of a control electrode NT6-2 of the sixth control transistor and the first plate ECI 1 of the first control capacitor. A shape of the third dummy control electrode DNG13 is the same as a shape of a part of a control electrode NT7-2 of the seventh control transistor. A shape of the third dummy control electrode DNG13 is the same as a shape of a part of an integrated structure of a control electrode NT8-2 of the ninth control transistor and the first plate NCI 1 of the second control capacitor. A shape of the fourth dummy control electrode DNG14 is the same as a shape of a part of the control electrode NT 11-2 of the eleventh control transistor and of the control electrode NT 15-2 of the fifteenth control transistor. A shape of a part of the fifth dummy control electrode DNG15 is the same as a shape of a part of a control electrode NT5-2 of the fifth control transistor. A shape of the fifth dummy control electrode DNG15 is the same as a shape of a part of a control electrode NT2-2 of the second control transistor. A shape of a part of the sixth dummy control electrode DNG62 is the same as a shape of a part of a control electrode NT13-2 of the thirteenth control transistor. A shape of a part of the seventh dummy control electrode DNG17 is the same as a shape of a part of an integrated structure of a control electrode NT4-2 of the fourth control transistor, a control electrode NT 16-2 of the sixteenth control transistor and a first plate NC31 of the third control capacitor. A shape of the eighth dummy control electrode DNG18 is the same as a shape of a part of a control electrode NT 12-2 of the twelfth control transistor. A shape of a part of the ninth dummy control electrode DNG19 is the same as a shape of a part of a control electrode NT5102 of the tenth control transistor. A shape of a part of the ninth dummy control electrode DNG19 is the same as a shape of a part of an integrated structure of a control electrode NT4-2 of the fourth control transistor, a control electrode NT 16-2 of the sixteenth control transistor and a first plate NC31 of the third control capacitor.

[0258] In an exemplary implementation, as shown in FIG. 14B, at least one dummy control register includes first to fifth dummy source-drain electrodes DNS1 to DNS5. A shape of a part of the first dummy source-drain electrode DNS1 is the same as a shape of a part of an integrated structure of the first electrode NT 1-3 of the first control transistor and a first electrode NT 14-3 of the fourteenth control transistor. A shape of a part of the second dummy source-drain electrode DNS2 is the same as a shape of a part of the second electrode NT 1-4 of the first control transistor. A shape of a part of the second dummy source-drain electrode DNS2 is the same as a shape of a part of the first electrode NT3-3 of the third control transistor. A shape of a part of the second dummy source-drain electrode DNS2 is the same as a shape of a part of the first electrode NT4-3 of the fourth control transistor. A shape of a part of the second dummy source-drain electrode DNS2 is the same as a shape of a part of the second electrode NT 15-4 of the fifteenth control transistor. A shape of a part of the second dummy source-drain electrode DNS2 is the same as a shape of a part of an integrated structure of the second electrode NT14-2 of the fourteenth control electrode and the first electrode NT15-3 of the fifteenth control transistor. A shape of a part of the third dummy source-drain electrode DNS3 is the same as a shape of a part of the first electrode NT6-3 of the sixth control electrode. A shape of a part of the fourth dummy source-drain electrode DNS4 is the same as a shape of a part of an integrated structure of the second electrode NT7-4 of the seventh control transistor and the second electrode NT8-4 of the eighth control transistor. A shape of apart of the fourth dummy source-drain electrode DNS4 is the same as a shape of a part of an integrated structure of the second electrode NT9-4 of the ninth control transistor and the second electrode NT10-4 of the tenth control transistor. A shape of a part of the fourth dummy source-drain electrode DNS4 is the same as a shape of a part of the first electrode NT 10-3 of the tenth control electrode. A shape of a part of the fourth dummy source-drain electrode DNS4 is the same as a shape of a part of an integrated structure of the first electrode NT8-3 of the eighth control transistor, the first electrode NT9-9 of the ninth control transistor and the first electrode NT13-3 of the thirteenth control transistor. A shape of a part of the fourth dummy sourcedrain electrode DNS4 is the same as a shape of a part of an integrated structure of tire first electrode NT12-3 of the twelfth control transistor and the second electrode NT13-4 of the thirteenth control transistor. A shape of a part of the fifth dummy source-drain electrode DNS5 is the same as a shape of a part of the second electrode NT5-4 of the fifth control transistor. A shape of a part of the fifth dummy source-drain electrode DNS5 is the same as a shape of a part of the first electrode NT3-3 of the third control transistor. A shape of a part of the fifth dummy source-drain electrode DNS5 is the same as a shape of a part of the first electrode NT 16-3 of the sixteenth control transistor.

[0259] In an exemplaiy7 implementation, as shown in FIGs. 3,4 and 14B, at least one of the control initial signal lines NSTV, the first control clock signal line NCK1, the second control clock signal line NCK2, the first control power supply lines NVGH, the second control power supply lines NVGL, the third control power supply line NVCX and the control cascade signal line NCL extends along the second direction, and the first direction intersects with the second direction. A first control initial signal line NSTV, a first one of second control power supply lines NVGL, a second control initial signal line NSTV, the first control clock signal line NCK1, the second control clock signal line NCK2, a first one of first control power supply lines NVGH, a third control power supply line NVCX, a second first control power supply line NVGH, a third first control power supply line NVGH and a second one of second control power supply lines NVGL are sequentially arranged in a direction close to the display area.

[0260] In an exemplary implementation, as shown in FIGs. 3,4 and 14B, the control cascade signal line NCL is electrically connected with an output terminal of at least one cascaded control shift register and an input terminal of at least one cascaded control shift register, respectively. An orthographic projection of the control cascade signal line NCL on the base substrate is located between an orthographic projection of the second control initial signal line NSTV on the base substrate and an orthographic projection of the first control clock signal line NCK1 on the base substrate.

[0261] In an exemplaiy implementation, as shown in FIG. 14B, the control cascade signal line NCL divides a region in which the dummy control shift register is located into a first region NR1 and a second region NR2. At least one dummy source-drain electrode located in the first region NR1 is connected with the first one of second control power supply lines NVGL, and at least one dummy source-drain electrode located in the second region NR2 is connected with at least one first control power supply line NVGH.

[0262] In an exemplary implementation, the display substrate further includes a drive structure layer. The drive structure layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer. The control cascade signal line NCL is located in the fourth conductive layer, and the control initial signal line NSTV, the first control clock signal line NCK1, the second control clock signal line NCK2, the first control power supply line NVGH, the two second control power supply lines NVGL and the third control power supply line NVCX are located in the fifth conductive layer.

[0263] In an exemplary implementation, as shown in FIGs. 3 and 4, a length of the scan drive circuit along the first direction is greater than or equal to a length of the dummy scan drive circuit along the first direction DI, wherein the first direction DI is an arrangement direction of the plurality of drive circuits.

[0264] FIG. 15A is a schematic diagram of a part of a film of a scan shift register and a dummy scan shift register, and FIG. 15B is a schematic diagram of a part of a film of a scan shift register and a dummy scan shift register. As shown in FIGs. 15A and I5B, in an exemplary implementation, the scan drive circuit includes a plurality of cascaded scan shift registers, and the dummy scan drive circuit includes: at least one dummy scan shift register located between adjacent scan shift registers. The scan shift register includes at least one scan transistor and at least one scan capacitor. The at least one dummy shift register further includes a plurality of dummy source-drain electrodes. At least part of at least one dummy active pattern in at least one dummy scan shift register has a same shape as a shape of at least part of an active pattern of the at least one scan transistor. At least part of at least one dummy control electrode in the at least one dummy scan shift register has a same shape as a shape of at least part of a control electrode of the at least one scan transistor or the at least one scan capacitor. At least part of at least one dummy source-drain electrode in the at least one dummy scan shift register has a same shape as a shape of at least part of at least one electrode of first and second electrodes of the at least one scan transistor.

[0265] In an exemplary implementation, as shown in FIG. 15A, at least one dummy scan register includes first to thirteenth dummy active patterns DPA1 to DPA13 and first to fifth dummy control electrodes DPG11 to DPG15. At least one scan register includes an active pattern PT1-1 and a control electrode PT1-2 of the first scan transistor to an active pattern PT8-1 and a control electrode PT8-2 of the eighth scan transistor. Shapes of the first dummy active pattern DPA1 and the second dummy active pattern DPA2 are the same as a shape of a part of the active pattern PT 1-1 of the first scan transistor. Shapes of the third dummy active pattern DPA3 and the fourth dummy active pattern DPA4 are the same as a shape of a part of the active pattern PT2-1 of the second scan transistor. Shapes of the fifth dummy active pattern DPA5 and the sixth dummy active pattern DPA6 are the same as a shape of a part of the active pattern PT3-1 of the third scan transistor. Shapes of the seventh to tenth dummy active patterns DPA7 to DPA 10 are the same as shapes of a part of the active pattern PT4-1 of the fourth scan transistor and the active pattern PT5-1 of the fifth scan transistor. A shape of a part of the eleventh dummy active pattern DPA11 is the same as a shape of a part of the active pattern PT1-1 of the first scan transistor, and a shape of a part of the eleventh dummy active pattern DPA11 is the same as a shape of a part of the active pattern PT6-1 of the sixth scan transistor. A shape of the twelfth dummy active pattern DPA 12 is the same as a shape of a part of the active pattern PT7-1 of the seventh scan transistor. A shape of the thirteenth dummy active pattern DPA 13 is the same as a shape of a part of the active pattern PT8-1 of the eighth scan transistor. A shape of the first dummy control electrode DPG11 is the same as a shape of a part of an integrated structure of a control electrode PT 1-2 of the first scan transistor and a control electrode PT3-2 of the third scan transistor. A shape of a part of the second dummy control electrode DPG12 is the same as a shape of a part of the integrated structure of the control electrode PT2-2 of the second scan transistor. A shape of the third dummy control electrode DPG13 is the same as a shape of a part of a control electrode PT8-2 of the eighth scan transistor. A shape of the fourth dummy control electrode DPG14 is the same as a shape of a part of a control electrode PT7-2 of the seventh scan transistor. A shape of a part of the fifth dummy control electrode DPG15 is the same as a shape of a part of a control electrode PT5-2 of the fifth scan transistor. A shape of the fifth dummy control electrode DPG15 is the same as a shape of a part of an integrated structure of the control electrode PT2-2 of the fourth scan transistor, the control electrode PT6-2 of the sixth scan transistor and the first plate PCI 1 of the first scan capacitor. A shape of the fifth dummy control electrode DPG15 is the same as a shape of a part of an integrated structure of the control electrode PT5- of the fifth scan transistor and the first plate PC21 of the second scan capacitor.

[0266] In an exemplary implementation, as shown in FIG. 15B, at least one dummy scan register includes first to fourth dummy source-drain electrodes DPS1 to DPS4. A shape of a part of the first dummy source-drain electrode DPS1 is the same as a shape of a part of an integrated structure of the first electrode PT 1-3 of the first scan transistor and a first electrode PT 14-3 of the fourteenth scan transistor. A shape of a part of the second dummy source-drain electrode DPS2 is the same as a shape of a part of the second electrode PT 1-4 of the first scan transistor. A shape of a part of the second dummy source-drain electrode DPS2 is the same as a shape of a part of the first electrode PT3-3 of the third scan transistor. A shape of a part of the second dummy source-drain electrode DPS2 is the same as a shape of a part of the first electrode PT4-3 of the fourth scan transistor. A shape of a part of the second dummy source-drain electrode DPS2 is the same as a shape of a part of the second electrode PT15-4 of the fifteenth scan transistor. A shape of a part of the second dummy source-drain electrode DPS2 is the same as a shape of a part of an integrated structure of the second electrode PT 14-2 of the fourteenth scan electrode and the first electrode PT 15-3 of the fifteenth scan transistor. A shape of a part of the third dummy source-drain electrode DPS3 is the same as a shape of a part of the first electrode PT6-3 of the sixth scan electrode. A shape of a part of the fourth dummy sourcedrain electrode DPS4 is the same as a shape of a part of an integrated structure of the second electrode PT7-4 of the seventh scan transistor and the second electrode PT8-4 of the eighth scan transistor. A shape of a part of the fourth dummy source-drain electrode DPS4 is the same as a shape of a part of an integrated structure of the second electrode PT9-4 of the ninth scan transistor and the second electrode PT10-4 of the tenth scan transistor. A shape of a part of the fourth dummy sourcedrain electrode DPS4 is the same as a shape of a part of the first electrode PT 10-3 of the tenth scan electrode. A shape of a part of the fourth dummy source-drain electrode DPS4 is the same as a shape of a part of an integrated structure of the first electrode PT8-3 of the eighth scan transistor, the first electrode PT9-9 of the ninth scan transistor and the first electrode PT 13-3 of the thirteenth scan transistor. A shape of a part of the fourth dummy source-drain electrode DPS4 is the same as a shape of a part of an integrated structure of the first electrode PT12-3 of the twelfth scan transistor and the second electrode PT 13-4 of the thirteenth scan transistor.

[0267] In an exemplary implementation, as shown in FIGs. 3,4 and 15B, the second scan power supply line PVGL, the first scan clock signal line PCK1, the second scan clock signal line PCK2, the scan initial signal line PSTV and the first scan power supply line PVGH are sequentially arranged in a direction close to the display area.

[0268] In an exemplary implementation, as shown in FIGs. 3,4 and I5B, the scan cascade signal line PCL is electrically connected with an output terminal of the at least one scan shift register and an input terminal of the at least one scan shift register, respectively. An orthographic projection of the scan cascade signal line PCL on the base substrate is located between an orthographic projection of the second scan clock signal line PCK2 on die base substrate and an orthographic projection of the scan initial signal line PSTV on the base substrate.

[0269] In an exemplary implementation, as shown in FIG. I5B, the scan cascade signal line PCL divides a region in which the dummy scan shift register is located into a first region PR1 and a second region PR2. At least one dummy source-drain electrode located in the first region PR1 is connected with the second scan power supply line PVGL, and at least one dummy source-drain electrode located in the second region PR2 is connected with the first scan power supply line PVGH.

[0270] In an exemplary implementation, the display substrate may further include a drive structure layer. The drive structure layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer. The scan cascade signal line PCL is located in the fourth conductive layer. The scan initial signal line PSTV, the first scan clock signal line PCK1, die second scan clock signal line PCK2, the first scan power supply line PVGH and the second scan power supply line PVGL are located in the fifth conductive layer.

[0271] In an exemplary implementation, an orthographic projection of the dummy active pattern DA on the base substrate is not overlapped with an orthographic projection of the dummy control electrode DG on die base substrate, so that an area of the dummy active pattern in the dummy drive circuit group is less than an area of the active pattern in the drive circuit group, thereby reducing an overlapping area between at least one signal line (e.g., a clock signal line) in the display substrate and the dummy active pattern, reducing a coupling capacitance between the signal lines and the active patterns, avoiding potential leakage in the display substrate, and reducing the power consumption of the display substrate.

[0272] In an exemplary implementation, an orthographic projection of the dummy active pattern DA on the base substrate is not overlapped with an orthographic projection of the dummy control electrode DG on the base substrate, and there is no intact transistor structure in the dummy drive circuit group. Therefore, the display substrate does not need to be connected with a test circuit for verifying the dummy drive circuit group, and a test efficiency of the display substrate can be improved.

[0273] In an exemplary implementation, the drive circuit group includes at least one transistor and at least one capacitor. The dummy drive circuit group includes a plurality of dummy active patterns, a plurality of dummy control electrodes and a dummy source-drain electrode. The display substrate further includes a signal output line, at least one cascade signal line and a plurality of signal lines, which are located in the non-display area. The plurality of signal lines are connected with the drive circuit group and the dummy circuit group, respectively. The signal output lines are connected with the drive circuit group. The drive structure layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer.

[0274] The semiconductor layer includes, at least, an active pattern of at least one transistor and at least one dummy active pattern of a plurality of dummy active patterns.

[0275] The first conductive layer includes, at least, a control electrode of at least one transistor, one plate of at least one capacitor, and at least one dummy active pattern of a plurality of dummy control electrodes.

[0276] The second conductive layer includes, at least, the other plate of at least one capacitor.

[0277] The third conductive layer includes, at least, a signal output line.

[0278] The fourth conductive layer includes, at least, at least one signal line and cascade signal lines.

[0279] The fifth conductive layer includes, at least, at least one signal line.

[0280] In an exemplary implementation, the drive structure layer may further include a first insulation layer located between the semiconductor layer and the first conductive layer, a second insulation layer located between the first conductive layer and the second conductive layer, a third insulation layer located between the second conductive layer and the third conductive layer, a fourth insulation layer located between the third conductive layer and the fourth conductive layer, and a fifth insulation layer located between the fourth conductive layer and the fifth conductive layer, and a planarization layer.

[0281] In an exemplary implementation, as shown in FIGs. 3 and 4, the display substrate further includes at least one initial signal line located in the non-display area. The at least one initial signal line is located on a side of at least one of the plurality of signal lines close to the display area, and is located in the fifth conductive layer. An orthographic projection of the at least one initial signal line on the base substrate is at least partially overlapped with orthographic projections of the drive circuit group and the dummy drive circuit group on the base substrate. FIGs. 3 and 4 illustrate two initial signal lines INIL1 and 1ML2 as an example.

[0282] In an exemplary implementation, two adjacent dummy scan shift registers are arranged along an arc-shaped boundary of an edge comer area, and at least one cascaded scan shift register may be provided between the two adjacent dummy scan shift registers or the two dummy scan shift registers are directly adjacent. One of the two adjacent dummy scan shift registers may be referred to as a first adjacent dummy scan shift register, and the other may be referred to as a second adjacent dummy scan shift register. At least one dummy source-drain electrode in the first adjacent dummy scan shift register may be electrically connected with one of the first scan clock signal line and the second scan clock signal line, and at least one dummy source-drain electrode in the second adjacent dummy scan shift register may be electrically connected with the other of the first scan clock signal line and the second scan clock signal line.

[0283] In an exemplary implementation, two adjacent dummy control shift registers are arranged along an arc-shaped boundary of an edge comer area, and at least one cascaded control shift register may be provided between the two adjacent dummy control shift registers or the two dummy control shift registers are directly adjacent. One of the two adjacent dummy control shift registers may be referred to as a first adjacent dummy control shift register, and the other may be referred to as a second adjacent dummy control shift register. At least one dummy source-drain electrode in the first adjacent dummy control shift register may be electrically connected with one of the first control clock signal line and the second control clock signal line, and at least one dummy source-drain electrode in the second adjacent dummy control shift register may be electrically connected with the other of the first control clock signal line and the second control clock signal line.

[0284] In an exemplary implementation, two adjacent dummy reset shift registers are arranged along an arc-shaped boundary of an edge comer area, and at least one cascaded reset shift register may be provided between the two adjacent dummy reset shift registers or the two dummy reset shift registers are directly adjacent. One of the two adjacent dummy reset shift registers may be referred to as a first adjacent dummy reset shift register, and the other may be referred to as a second adjacent dummy reset shift register. At least one dummy source-drain electrode in the first adjacent dummy reset shift register may be electrically connected with one of the first reset clock signal line and the second reset clock signal line, and at least one dummy source-drain electrode in the second adjacent dummy reset shift register may be electrically connected with the other of the first reset clock signal line and the second reset clock signal line.

[0285] In an exemplary implementation, two adjacent dummy light emitting shift registers are arranged along an arc-shaped boundary of an edge comer area, and at least one cascaded light emitting shift register may be provided between the two adjacent dummy light emitting shift registers or the two dummy light emitting shift registers are directly adjacent. One of the two adjacent dummy light emitting shift registers may be referred to as a first adjacent dummy light emitting shift register, and the other may be referred to as a second adjacent dummy light emitting shift register. At least one dummy source-drain electrode in the first adjacent dummy light emitting shift register may be electrically connected with one of the first light emitting clock signal line and the second light emitting clock signal line, and at least one dummy source-drain electrode in the second adjacent dummy light emitting shift register may be electrically connected with the other of the first light emitting clock signal line and the second light emitting clock signal line.

[0286] Exemplary description is made below through a manufacturing process of a display substrate. A “patterning process” mentioned in the present disclosure includes photoresist coating, mask exposure, development, etching, photoresist stripping, and the like for a metal material, an inorganic material, or a transparent conductive material, and includes organic material coating, mask exposure, development, and the like for an organic material. Deposition may be any one or more of sputtering, evaporation, and chemical vapor deposition, coating may be any one or more of spray coating, spin coating, and inkjet printing, and etching may be any one or more of dry etching and wet etching, the present disclosure is not limited thereto. A “thin film” refers to a layer of thin film made of a certain material on a base substrate using deposition, coating, or other processes. If the “thin film” does not need to be processed through a patterning process in the entire manufacturing process, the “thin film” may also be called a “layer”. If the “thin film” needs to be processed through the patterning process in the entire manufacturing process, the “thin film” is called a “thin film” before the patterning process is performed and is called a “layer” after the patterning process is performed. At least one “pattern” is contained in the “layer” which has been processed through the patterning process. “A and B are provided in a same layer” in the present disclosure means that A and B are formed simultaneously through a same patterning process, and a “thickness” of a film is a dimension of the film in a direction perpendicular to a display substrate. In an exemplary implementation of the present disclosure, “an orthographic projection of B is within a range of an orthographic projection of A” or “an orthographic projection of A contains an orthographic projection of B” refers to that a boundary of the orthographic projection of B falls within a range of a boundary of the orthographic projection of A, or the boundary of the orthographic projection of A coincides with the boundary of the orthographic projection of B. In an exemplary implementation, a structure of the light emitting shift register is the same as a structure of the reset shift register, and a structure of the dummy light emitting shift register is the same as a structure of the dummy reset shift register. Only manufacturing methods of the scan shift register and the dummy scan shift register, the control shift register and the dummy control shift register, and the reset shift register and the dummy reset shift register are described hereinafter. Manufacturing methods of the light emitting shift register and the dummy light emitting shift register are the same as manufacturing methods of the reset shift register and the dummy reset shift register, which will not be repeated below.

[0287] (I) A pattern of a semiconductor layer is formed on a base substrate. In an exemplary implementation, forming the pattern of the semiconductor layer on a base substrate may include depositing a semiconductor thin fdm on the base substrate, patterning the semiconductor thin film through a patterning process to form the pattern of the semiconductor layer. As shown in FIGs. 16 to 18, FIG. 16 is a schematic diagram of a scan shift register and a dummy scan shift register after forming a pattern of a semiconductor layer, FIG. 17 is a schematic diagram of a control shift register and a dummy control shift register after forming a pattern of a semiconductor layer, and FIG. 18 is a schematic diagram of a reset shift register and a dummy reset shift register after forming a pattern of a semiconductor layer.

[0288] In an exemplary implementation, as shown in FIGs. 16 to 18, the pattern of the semiconductor layer may include, at least, an active pattern PT1-1 of the first scan transistor to an active pattern PT8-I of the eighth scan transistor in the scan shift register, active patterns of first to thirteenth dummy active patterns DPA1 to DPA 13 in the dummy scan shift register, a first control transistor NT1-1 to an active pattern NT 16-1 of the sixteenth control transistor located in the control shift register, first to thirtieth dummy active patterns DNA1 to DNA30 in the dummy control shift register, an active pattern RT1-1 of the first register transistor to an active pattern RT13-1 of the thirteenth reset transistor in the reset shift register, and first to twenty-first dummy active patterns DRAI to DRA2I in the dummy reset shift register.

[0289] In an exemplary implementation, the active pattern PT4-1 of the fourth scan transistor and the active pattern PT5-1 of the fifth scan transistor are integrated, the active pattern PT6-1 of the sixth scan transistor, the active pattern PT7-1 of the seventh scan transistor and the active pattern PT8-1 of the eighth scan transistor are integrated, and the active pattern PT1-1 of the first scan transistor, the active pattern PT2-1 of the second scan transistor and the active pattern PT3-1 of the third scan transistor are separately disposed.

[0290] In an exemplary implementation, any one of the first dummy active patterns DPA1 to the thirteenth dummy active patterns DPA 13 located in the dummy scan shift register is separately disposed.

[0291] In an exemplary implementation, the active pattern NT2-1 of the second control transistor and the active pattern NT11-1 of the eleventh control transistor are integrated, the active pattern NT9-I of the ninth control transistor and the active pattern NT 10-1 of the tenth control transistor are integrated, and the active pattern NT8-1 of the eighth control transistor, the active pattern NT12-1 of the twelfth control transistor, the active pattern NT13-1 of the thirteenth control transistor and tire active pattern NT 16-1 of the sixteenth control transistor are integrated. The active pattern NT 1-1 of the first control transistor, the active pattern NT3-I of the third control transistor, the active pattern NT4-I of the fourth control transistor, the active pattern NT5-I of the fifth control transistor, the active pattern NT6-1 of the sixth control transistor, the active pattern NT7-1 of the seventh control transistor, and the active pattern NT15-1 of the fifteenth control transistor are separately disposed.

[0292] In an exemplary implementation, any one of the first dummy active patterns DNA1 to the thirtieth dummy active patterns DNA30 located in the dummy control shift register is separately disposed.

[0293] In an exemplary implementation, the active pattern RT4-1 of the fourth reset transistor, the active pattern RT5-1 of the fifth reset transistor, the active pattern RT7-1 of the seventh reset transistor, the active pattern RT8-1 of the eighth reset transistor, and the active pattern RT13-1 of the thirteenth reset transistor are integrated. The active pattern RT9-1 of the ninth reset transistor and the active pattern RT10-1 of the tenth reset transistor are active patterns. The active pattern RT1-1 of the first reset transistor, the active pattern RT2-1 of the second reset transistor, the active pattern RT3-1 of the third reset transistor, the active pattern RT6-I of the sixth reset transistor, the active pattern RT11-1 of the eleventh reset transistor and the active pattern RT12-1 of the twelfth reset transistor are disposed separately.

[0294] In an exemplary implementation, any one of the first dummy active patterns DRA1 to the thirtieth dummy active patterns DRA21 located in the dummy reset shift register is separately disposed.

[0295] (2) A pattern of a first conductive layer is formed. In an exemplary implementation, forming the pattern of the first conductive layer may include depositing a first insulation thin film and a first conductive thin film on the base substrate on which the aforementioned patterns are formed, patterning the first conductive film by a patterning process to form a first insulation layer covering the pattern of the semiconductor layer, and a pattern of a first conductive layer disposed on the pattern of the first insulation layer. As shown in FIGs. 19 to 24, FIG. 19 is a schematic diagram of the pattern of the first conductive layer in the scan shift register and the dummy scan shift register. FIG. 20 is a schematic diagram of the pattern of the first conductive layer after formed by the scan shift register and the virtual scan shift register. FIG. 21 is a schematic diagram of a pattern of a first conductive layer in the control shift register and the dummy control shift register. FIG. 22 is a schematic diagram of a sequential pattern of the first conductive layer in the control shift register and the dummy control shift register. FIG. 23 is a schematic diagram of the pattern of the first conductive layer formed by the reset shift register and the dummy reset shift register. FIG. 24 is a schematic diagram of the reset shift register and the dummy reset shift register after the pattern of the first conductive layer is formed. In an exemplary implementation, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0296] In an exemplary implementation, the pattern of the first conductive layer may at least include control electrodes PT 1-2 to PT8-2 of the first to eighth scan transistors of the scan shift register and a first plate PCI 1 of the first scan capacitor and a first plate PC21 of the second scan capacitor in the scan shift register, first to fifth dummy control electrodes DP Al 1 to DPG15 in the dummy scan shift register, a first control transistor NT 1-2 to a control electrode NT 16-2 of the sixteenth control transistor and a first plate NCI 1 of the first control capacitor to a first plate NC31 of the third control capacitor in the control shift register, first to ninth dummy control electrodes DNG11 to DNG19 in the dummy control shift register, a control electrode RT1-2 of the first reset transistor to a control electrode RT13-2 of the thirteenth reset transistor and a first plate RC11 of the first reset capacitor to a first plate RC31 of the third reset capacitor in the reset shift register, and first to eighth dummy control electrode DRG11 to DRG18 in the dummy reset shift register.

[0297] In an exemplar}' implementation, the control electrode PT1-2 of the first scan transistor and the control electrode PT3-2 of the third scan transistor form an integrated structure. The control electrode PT4-2 of the fourth scan transistor, the control electrode PT6-2 of the sixth scan transistor, and the first plate PCI 1 of the first scan capacitor form an integrated structure. The control electrode PT5-2 of the fifth scan transistor and the first plate PC21 of the second scan capacitor form an integrated structure. The control electrode PT2-2 of the second scan transistor, the control electrode PT7-2 of the seventh scan transistor, and the control electrode PT8-2 of the eighth scan transistor are separately disposed.

[0298] In an exemplary implementation, any one of the first to fifth dummy control electrodes DPA11 to DPG15 of the dummy scan shift register is disposed separately.

[0299] In an exemplary implementation, the control electrode NT 1-2 of the first control transistor, the control electrode NT3-2 of the third control transistor and the control electrode NT14-2 of the fourteenth control transistor form an integrated structure. The control electrode NT2-2 of the second control transistor and the control electrode NT8-2 of the eighth control transistor form an integrated structure. The control electrode NT6-2 of the sixth control transistor and the first plate NCI 1 of the first control capacitor form an integrated structure. The control electrode NT5-2 of the fifth control transistor and the control electrode NT 11-2 of the eleventh control transistor form an integrated structure. The control electrode NT4-2 of the fourth control transistor, the control electrode NT16-2 of the sixteenth control transistor and the first plate NC 31 of the third control capacitor form an integrated structure, and the control electrode NT9-2 of the ninth control transistor and the first plate NC21 of the second control capacitor form an integrated structure. The control electrode NT5-2 of the fifth control transistor, the control electrode NT7-2 of the seventh control transistor, the control electrode NT10-2 of the tenth control transistor, the control electrode NT12-2 of the twelfth control transistor, and the control electrode NT 13-2 of the thirteenth control transistor are separately disposed.

[0300] In an exemplary implementation, any one of the first to ninth dummy control electrodes DNG11 to DNG19 of the dummy control shift register is disposed separately.

[0301] In an exemplary implementation, the control electrode RT1-2 of the first reset transistor and the control electrode RT3-2 of the third reset transistor form an integrated structure. The control electrode RT6-2 of the sixth reset transistor and the first plate RC11 of the first reset capacitor form an integrated structure. The control electrode RT11-2 of the eleventh reset transistor and the control electrode RT12-2 of the twelfth reset transistor form an integrated structure. The control electrode RT4-2 of the fourth reset transistor, the control electrode RT10-2 of the tenth reset transistor and the first plate RC31 of the third reset capacitor form an integrated structure, and the control electrode RT9-2 of the ninth reset transistor and the first plate RC21 of the second reset capacitor form an integrated structure. The control electrode RT2-2 of the second reset transistor, the control electrode RT5-2 of the fifth reset transistor, the control electrode RT7-2 of the seventh reset transistor, the control electrode RT8-2 of the eighth reset transistor and the control electrode RT13-2 of the thirteenth reset transistor are separately disposed.

[0302] In an exemplary implementation, any one of the first to eighth dummy control electrodes DRG11 to DRG18 of the dummy reset shift register is disposed separately.

[0303] In an exemplary implementation, an extending direction of a control electrode of at least one transistor and an extending direction of an active pattern are mutually perpendicular to each other. An orthographic projection of any one of the dummy control electrodes on the base substrate is not overlapped with orthographic projections of the dummy active patterns on the base substrate.

[0304] (3) A pattern of a second conductive layer is formed. In an exemplary implementation, forming the pattern of the second conductive layer may include depositing a second insulation thin film and a second conductive thin film on the base substrate on which the aforementioned patterns are formed, patterning the second conductive film by a patterning process to form a pattern of a second insulation layer covering the pattern of the first conductive layer, and a pattern of a second conductive layer disposed on the second insulation layer. As shown in FIGs. 25 to 30, FIG. 25 is a schematic diagram of the pattern of the second conductive layer in the scan shift register and the dummy scan shift register. FIG. 26 is a schematic diagram of the pattern of the second conductive layer after formed by the scan shift register and the virtual scan shift register. FIG. 27 is a schematic diagram of a pattern of a second conductive layer in the control shift register and the dummy control shift register. FIG. 28 is a schematic diagram after forming a pattern of the second conductive layer in the control shift register and the dummy control shift register. FIG. 29 is a schematic diagram of the pattern of the second conductive layer formed by the reset shift register and the dummy reset shift register. FIG. 30 is a schematic diagram of the reset shift register and the dummy reset shift register after the pattern of the second conductive layer is formed. In an exemplary implementation, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0305] In an exemplary implementation, the pattern of the second conductive layer may include, at least, a second plate PC12 of the first scan capacitor, a second plate PC22 of the second scan capacitor and the first scan connection line PL1 which are located in the scan shift register, a first dummy electrode DPG21, a second dummy electrode DPG22 and a third dummy electrode DPG23 located in the dummy scan shift register, a second plate NCI 2 of the first control capacitor to a second plate NC32 of the third control capacitor and the first scan connect line NL1 which are located in the control shift register, the first dummy electrode DNG11 to the fourth dummy control electrode DNG14 which are located in the dummy control shift register, a second plate RC12 of the first reset capacitor to a first plate RC32 of the third reset capacitor w hich are located in the reset shift register, and the first to third dummy electrodes DRG21 to DRG23 which are located in the dummy reset shift register.

[0306] In an exemplary implementation, a shape of the first dummy electrode DPG21 located in the dummy scan shift register is the same as a shape of a part of the first scan signal line PL1. A shape of the second dummy electrode DPG22 located in the dummy scan shift register is the same as a shape of a part of the second plate PC 12 of the first scan capacitor. A shape of the third dummy electrode DPG23 located in the dummy scan shift register is the same as a shape of a part of the second plate PC22 of the second scan capacitor.

[0307] In an exemplary implementation, a shape of the first dummy electrode DNG21 located in the dummy control shift register is the same as a shape of a part of the second plate NCI2 of the first control capacitor. A shape of the second dummy electrode DNG22 located in the dummy control shift register is the same as a shape of a part of the second plate NC22 of the second control capacitor. Shapes of the third dummy electrode DNG23 and the fourth dummy electrode DNG24 located in the dummy control shift register are the same as a shape of a part of the first plate NC32 of the third control capacitor.

[0308] In an exemplary implementation, a shape of the first dummy electrode DRG21 located in the dummy reset shift register is the same as a shape of a part of the second plate RC12 of the first reset capacitor. A shape of the second dummy electrode DRG22 located in the dummy reset shift register is the same as a shape of a part of the second plate RC22 of the second reset capacitor. A shape of the third dummy electrode DRG23 located in the dummy reset shift register is the same as a shape of a part of the first plate RC32 of the third reset capacitor.

[0309] (4) A pattern of a third conductive layer is formed. In an exemplary implementation, forming the pattern of the third conductive layer may include depositing a third insulation thin film and a third conductive film on the base substrate on which the aforementioned patterns are formed, and patterning the third conductive film by a patterning process to form the pattern of the third insulation layer covering the pattern of the second conductive layer and the pattern of the third conductive layer located on the pattern of the third insulation layer. As shown in FIGs. 31 to 34, FIG. 31 is a schematic diagram of the pattern of the third conductive layer located in the control shift register and the dummy control shift register, FIG. 32 is a schematic diagram of die control shift register and the dummy control shift register after the pattern of the third conductive layer is formed, FIG. 33 is a schematic diagram of the pattern of Hie third conductive layer in the reset shift register and the dummy reset shift register, and FIG. 34 is a schematic diagram of the reset shift register and the dummy reset shift register after the pattern of the third conductive layer is patterned. In an exemplary implementation, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0310] In an exemplary implementation, the pattern of the third conductive layer may include, at least, a dummy electrode DNG31 located in the dummy control shift register, a second reset connection line RL2 located in the reset shift register, and a dummy electrode DRG31 located in the dummy reset shift register.

[0311] In an exemplary implementation, a shape of the dummy electrode DRG31 located in the dummy reset shift register is the same as a shape of a part of the second reset connection line RL2.

[0312] (5) A pattern of a fourth insulation layer is formed. In an exemplary implementation, forming the pattern of the fourth insulation layer may include depositing a fourth insulation thin film on the base substrate on which the aforementioned patterns are formed, patterning the fourth insulation thin film by a patterning process to form a pattern of a fourth insulation layer covering the aforementioned structure, wherein the fourth insulation layer is provided with a plurality of via patterns. As shown in FIGs. 35 to 37, FIG. 35 is a schematic diagram of the scan shift register and the dummy scan sift register after the fourth insulation layer is formed, FIG. 36 is a schematic diagram of the control shift register and the dummy control shift register after the fourth insulation layer is formed, and FIG. 37 is a schematic diagram of the reset shift register and the dummy reset shift register after the fourth insulation layer is formed.

[0313] In an exemplary implementation, the pattern of the fourth insulation layer may include, at least, first to fourteenth vias VI to V14 located in the scan shift register, first to nineteenth vias DVI to V19 located in the dummy scan shift register, first to tw enty-fourth vias Hl to H24 located in the control shift register, first to forty-second vias DH1 to DH42 located in the dummy control shift register, first to twenty-second vias KI to K22 located in the reset shift register, and first to thirty-first vias DK1 to DK31 located in the reset scan shift register.

[0314] (6) A pattern of a fourth conductive layer is formed. In an exemplary implementation, forming the pattern of the fourth conductive layer may include depositing a fourth conductive thin film on the base substrate on which the aforementioned patterns are formed, and patterning the fourth conductive film by a patterning process to form a pattern of a fourth conductive layer disposed on a pattern of the fourth insulation layer. As shown in FIGs. 38 to 43, FIG. 38 is a schematic diagram of the pattern of the fourth conductive layer in the scan shift register and the dummy scan shift register. FIG. 39 is a schematic diagram of the pattern of the fourth conductive layer after formed by the scan shift register and the virtual scan shift register. FIG. 40 is a schematic diagram of a pattern of a fourth conductive layer in the control shift register and the dummy control shift register. FIG. 41 is a schematic diagram after forming a pattern of the fourth conductive layer in the control shift register and the dummy control shift register. FIG. 42 is a schematic diagram of the pattern of the fourth conductive layer in the reset shift register and the dummy reset shift register. FIG. 43 is a schematic diagram of the reset shift register and the dummy reset shift register after the pattern of the fourth conductive layer is formed. In an exem plan implementation, the fourth conductive layer may be referred to as a first source drain metal (SD1) layer.

[0315] In an exemplary implementation, the pattern of the fourth conductive layer may include, at least, first and second electrodes PT1-3 and PT1-4 in the first scan transistor of the scan shift register to the first and second electrodes PT8-3 and PT8-4 in the eighth scan transistor, first to fourth dummy source-drain electrodes DPS1 to DPS4 in the dummy scan shift register, first and second electrodes NT1-3 and NT1-4 of the first control transistor to first and second electrodes NT8-3 and NT8-4 of the eighth control transistor in the control shift register, first to fifth dummy source-drain electrodes DNS1 to DNS5 in the dummy control shift register, first and second electrodes RT1-3 and RT1-4 of the first reset transistor to first and second electrodes 8-3 and 8-4 of the eighth reset transistor in the reset shift register, first to ninth dummy source-drain electrodes DRS1 to DRS9 in the dummy reset shift register, the scan cascade signal line PCL, the control cascade signal line NCL, the reset cascade signal line RCL, the reset initial signal line RSTV and the two second reset power supply lines RVGL.

[0316] In an exemplary implementation, the first to third dummy source-drain electrodes DPS1 to DPS3 in the dummy scan shift register are located on a side of the scan cascade signal line PCL away from the display area, and the fourth dummy source-drain electrode DPS4 in the dummy scan shift register is located on a side of the scan cascade signal line PCL close to the display area.

[0317] In an exemplary implementation, the first and second electrodes RT1 -3 and RT1 -4 of the first reset transistor to the first and second electrodes RT8-3 and RT8-4 of the eighth reset transistor in the reset shift register and the first to ninth dummy source-drain electrodes DRS 1 to DRS9 in the dummy reset shift register are disposed between the two second reset power supply lines RVGL.

[0318] In an exemplary implementation, the first dummy source-drain electrode DNS1 and the second dummy source-drain electrode DNS2 located in the dummy control shift register are located on a side of the control cascade signal line NCL away from the display area, and the third to fifth dummy source-drain electrodes DNS3 to DNS5 in the dummy control shift register are located on a side of the control cascade signal line NCL close to the display area.

[0319] In an exemplary implementation, the first to ninth dummy source-drain electrodes DRS1 to DRS9 in the dummy reset shift register are located on a side of the reset cascade signal line RCL close to the display area.

[0320] (7) A pattern of a planarization layer is formed. In an exemplar} implementation, forming the pattern of the planarization layer may include depositing a fifth insulation thin film on the base substrate on which the aforementioned patterns are fonned, coating a planarization thin film, patterning the fifth insulation thin film and the planarization thin film by a patterning process to form a pattern of a fifth insulation layer and a pattern of a planarization layer which cover the aforementioned structures, wherein the planarization layer is provided with patterns of a plurality of vias. As shown in FIGs. 44 to 46, FIG. 44 is a schematic diagram of die scan shift register and the dummy scan sift register after the planarization layer is formed, FIG. 45 is a schematic diagram of the control shift register and the dummy control shift register after the planarization layer is fonned, and FIG. 46 is a schematic diagram of the reset shift register and the dummy reset shift register after the planarization layer is formed.

[0321] In an exemplary implementation , the plurality of vias in the planarization layer may include, at least, fifteenth and sixteenth vias VI5 and VI6 in the scan shift register, twentieth and twenty -first dummy vias DV20 and VD21 in the dummy scan shift register, twenty-fifth to thirty-first vias H25 to H31 in the control shift register, forty-third to forty-fifth vias DH43 to DH45 in the dummy control shift register, twenty-third and twenty-fourth vias K23 and K24 in the reset shift register, and thirty-second via DK32 in the reset scan shift register.

[0322] (8) A pattern of a fifth conductive layer is formed. In an exemplaiy implementation, forming the pattern of the fifth conductive layer may include depositing a fifth conductive thin film on the base substrate on which the aforementioned patterns are formed, and patterning the fifth conductive film by a patterning process to form a fifth conductive layer disposed on the fifth insulation layer. As shown in FIGs. 47 to 52, FIG. 47 is a schematic diagram of the pattern of the fifth conductive layer in the scan shift register and the dummy scan shift register. FIG. 48 is a schematic diagram of the pattern of the fifth conductive layer after formed by the scan shift register and the virtual scan shift register. FIG. 49 is a schematic diagram of a pattern of a fifth conductive layer in the control shift register and the dummy control shift register. FIG. 50 is a schematic diagram after fonning a pattern of the fifth conductive layer in the control shift register and the dummy control shift register. FIG. 51 is a schematic diagram of the pattern of the fifth conductive layer in the reset shift register and the dummy reset shift register. FIG. 52 is a schematic diagram of the reset shift register and the dummy reset shift register after the pattern of the fifth conductive layer is formed. In an exemplary implementation, the fifth conductive layer may be referred to as a second source drain metal (SD2) layer.

[0323] In an exemplary implementation, the pattern of the fifth conductive layer may include, at least, a scan initial signal line PSTV, a first scan clock signal line PCK1, a second scan clock signal line PCK2, a first scan power supply line PVGH, a second scan power supply line PVGL, a first initial signal line INIL1, a second initial signal line INIL2, a control initial signal line NSTV, a first control clock signal line NCKI, a second control clock signal line NCK2, a first control power supply line NVGH, a second control power supply line NVGL, a third control power supply line NVCX, a reset initial signal line RSTV, a first reset clock signal line RCK1, a second reset clock signal line RCK2, a first reset power supply line RVGH, a second reset power supply line RVGL and a third reset power supply line RVCX.

[0324] So far, a drive circuit layer has been manufactured on the base substrate. In a plane parallel to the display substrate, the drive circuit layer may include a plurality of shift registers and a plurality of dummy shift registers. In a plane perpendicular to the display panel, the drive circuit layer may be disposed on the base substrate. The drive circuit layer may include a semiconductor layer, a first insulation layer, a first conductive layer, a second insulation layer, a third conductive layer, a fourth insulation layer, a fourth conductive layer, a fifth insulation layer, a planarization layer and a fifth conductive layer that are sequentially disposed on the base substrate.

[0325] In an exemplary implementation, the base substrate may be a rigid base substrate or a flexible base substrate, wherein the rigid base substrate may be, but is not limited to, one or more of glass and metal foil; the flexible base substrate may be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyan late, polyarylester, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0326] In an exemplar}' implementation, the flexible base substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer and a second inorganic material layer which are stacked. Materials of the first flexible material layer and the second flexible material layer may be Polyimide (PI), Polyethylene Terephthalate (PET), or a surface-treated polymer soft film, etc., and materials of the first inorganic material layer and the second inorganic material layer may be Silicon Nitride (SiNx), Silicon Oxide (SiOx), or the like, for improving water and oxygen resistance of the base substrate. The first inorganic material layer and the second inorganic material layer may also be referred to as barrier layers, and a material of the semiconductor layer may be amorphous silicon (a-si). In an exemplary7 implementation, taking a stacked structure of PIl / Barrierl / a-si / PI2 / Barrier2 as an example, its manufacturing process may include: first coating a layer of polyimide on a glass carrier board, after the layer of polyimide is cured to form a film, a first flexible (PI 1) layer is formed; then depositing a layer of barrier thin film on the first flexible layer to fonn a first barrier (Barrier 1) layer overlaying the first flexible layer; then depositing a layer of amorphous silicon thin film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating another layer of polyimide on the amorphous silicon layer, after this layer of polyimide is cured to form a film, a second flexible (PI2) layer is formed; and then depositing a layer of barrier thin film on the second flexible layer to form a second barrier (Barrier 2) layer covering the second flexible layer, so as to complete manufacturing of the base substrate.

[0327] In an exemplary implementation, the semiconductor layer may be an amorphous silicon layer, a polysilicon layer, or may be a metal oxide layer. The metal oxide layer may be an oxide including indium and tin, an oxide including tungsten and indium, an oxide including tungsten, indium, and zinc, an oxide including titanium and indium, an oxide including titanium, indium, and tin, an oxide including indium and zinc, an oxide including silicon, indium, and tin, or an oxide including indium or gallium and zinc. The metal oxide layer may be of a mono-layer structure, a double-layer structure, or a multi-layer structure.

[0328] In an exemplary implementation, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer may be made of a metal material, such as any one or more of Argentum (Ag), Copper (Cu), Aluminum (Al), and Molybdenum (Mo), or an alloy material of the aforementioned metals, such as an Aluminum Neodymium alloy (AINd) or a Molybdenum Niobium alloy (MoNb), and may be of a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo.

[0329] In an exemplary implementation, the first insulation layer, the second insulation layer, the third insulation layer, the fourth insulation layer and the fifth insulation layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be in a single layer, multiple layers, or in a composite layer. The first insulation layer and the second insulation layer may be referred to as Gate Insulation (GI) layers, the third insulation layer may be referred to as Interlayer Dielectric (ILD) layers, and the fourth insulation layer may be referred to as a Passivation (PVX) layer.

[0330] In an exemplary implementation, the planarization layer may be made of an organic material, such as resin.

[0331] In an exemplary implementation, after manufacturing the drive circuit layer is completed, a light emitting structure layer is manufactured on the drive circuit layer, and a manufacturing process of the light emitting structure layer may include following operations.

[0332] Depositing an anode conductive thin film on the base substrate on which the above-mentioned patterns are formed, patterning the anode conductive thin film through a patterning process to form a pattern of an anode conductive layer disposed on the second planarization layer, depositing a pixel definition thin film on the base substrate on which the above-mentioned patterns are formed, patterning the pixel definition thin film through a patterning process to fonn a pattern of a pixel definition layer exposing the pattern of the anode conductive layer, coating an organic light emitting material on the base substrate on which the pattern of the pixel definition layer is formed, patterning the organic light emitting material through a patterning process to form a pattern of an organic structure layer, depositing a cathode conductive thin film on the base substrate on which the pattern of the organic structure layer is formed, and patterning the cathode conductive thin film through a patterning process to fonn a cathode conductive layer.

[0333] So far, the light emitting structure layer has been manufactured on the base substrate.

[0334] In an exemplary implementation, the anode conductive layer includes, at least, patterns of a plurality of anodes. The patterns of the plurality of anodes may include an anode of a first light emitting device, an anode of a second light emitting device, an anode of a third light emitting device, and an anode of a fourth light emitting device, wherein the anode of the first light emitting device is located at a red sub-pixel emitting red light, the anode of the second light emitting device may be located at a blue sub-pixel emitting blue light, the anode of the third light emitting device may be located at a first green sub-pixel emitting green light, and the anode of the fourth light emitting device may be located at a second green sub-pixel emitting green light.

[0335] In an exemplary implementation, the anode of the first light emitting device and the anode of the second light emitting device may be alternately disposed in the first direction, and the anode of the third light emitting device and the anode of the fourth light emitting device may be alternately disposed in the first direction. Alternatively, the anode of the first light emitting device and the anode of the second light emitting device may be alternately disposed in the second direction, and the anode of the third light emitting device and the anode of the fourth light emitting device may be alternately disposed in the second direction.

[0336] In an exemplary implementation, four sub-pixels in one pixel unit may have a same anode shape and a same area, or may have different anode shapes and different areas.

[0337] In an exemplary implementation, the anode conductive layer may be of a single-layer structure, such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO), or may be of a multi-layer composite structure, such as ITO / Ag / ITO.

[0338] In an exemplary implementation, the organic structure layer may at least include: an organic emitting layer of a light emitting device.

[0339] In an exemplary implementation, the cathode conductive layer may include, at least, cathodes of a plurality of light emitting devices.

[0340] In an exemplary implementation, the cathode layer may be made of a metal material, such as any one or more of Argentum (Ag), Copper (Cu), Aluminum (Al), and Molybdenum (Mo), or the above conductive alloy materials, such as an Aluminum Neodymium alloy (AINd) or a Molybdenum Niobium alloy (MoNb), and may have a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the fourth conductive layer may be of a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0341] The display substrate according to the embodiment of the present disclosure may be applied to a display product with any resolution.

[0342] In an exemplary implementation, a subsequent manufacturing process may include forming an encapsulation structure layer on the cathode conductive layer, and the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer which are stacked. The first encapsulation layer and the third encapsulation layer may be made of an inorganic material, the second encapsulation layer may be made of an organic material, and the second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer, which may ensure that external water vapor cannot enter the light emitting structure layer.

[0343] A display apparatus is also provided in an embodiment of the present disclosure, which may include a display substrate.

[0344] The display substrate is the display substrate according to any of the aforementioned embodiments, and has similar implementation principles and implementation effects, which will not be repeated here.

[0345] In an exemplary implementation, the display apparatus may be any product or component with a display function, such as a wearable device, a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, and a navigator.

[0346] The drawings in the embodiments of the present disclosure only involve structures involved in the embodiments of the present disclosure, and other structures may refer to a general design.

[0347] For the sake of clarity, a thickness and size of a layer or a micro structure are enlarged in the accompanying drawings used for describing the embodiments of the present disclosure. It may be understood that when an element such as a layer, film, region, or substrate is described as being “on” or “under” another element, the element may be “directly” located “on” or “under” the another element, or there may be an intermediate element.

[0348] Although implementations of the present disclosure are disclosed above, contents described are only implementations used for ease of understanding of the present disclosure, but not intended to limit the present disclosure. Any of those skilled in the art of the present disclosure can make any modifications and variations in the implementation and details without departing from the spirit and scope of the present disclosure. However, the protection scope of the present disclosure should be subject to the scope defined by the appended claims.

Claims

1. A display substrate having a display area and a non-display area, comprising a base substrate, a pixel drive circuit located in the display area, a drive circuit group and a dummy drive circuit group, which are located in the non-display area, disposed on the base substrate; wherein the pixel drive circuit is electrically connected with the drive circuit group, the drive circuit group comprises at least one shift register, the dummy drive circuit group comprises at least one dummy shift register, the dummy shift register comprises a plurality of dummy active patterns and a plurality of dummy control electrodes, and the shift register comprises a plurality of transistors, wherein a transistor comprises an active pattern and a control electrode;a shape of at least part of the at least one dummy active pattern is the same as a shape of at least part of an active pattern of at least one transistor, a shape of at least part of at least one dummy control electrode is the same as a shape of at least part of a control electrode of at least one transistor, and an orthographic projection of at least one of the dummy active patterns on the base substrate is not overlapped with an orthographic projection of at least one of the dummy control electrodes on the base substrate.

2. The display substrate of claim 1, wherein a distance between the orthographic projection of the at least one dummy active pattern on the base substrate and a target dummy control electrode ranges from 0.8 microns to 2 microns;the orthographic projection of the dummy active pattern on the base substrate is adjacent to an orthographic projection of the target dummy control electrode on the base substrate.

3. The display substrate of claim 1, wherein the non-display area comprises at least one comer area and at least one linear bezel area, the drive circuit group comprises a plurality of drive circuits sequentially arranged in a direction close to the display area, the drive circuit comprises a plurality of cascaded shift registers, the dummy drive circuit group comprises a plurality of dummy drive circuits arranged sequentially in a direction close to the display area, and the dummy drive circuit comprises a plurality of cascaded dummy shift registers;the dummy drive circuit group is at least partially located in the comer area, the drive circuit group is located in the comer area and the linear bezel area, the drive circuit group and the dummy drive circuit group are located on first and second sides of the display area, wherein the first side and the second side of the display area are opposite to each other.

4. The display substrate of claim 3, wherein the display area is provided with a pixel drive circuit and at least one reset signal line, the pixel drive circuit comprises a drive transistor and a reset transistor, the reset transistor is electrically coimected with a control electrode of the drive transistor, and the reset signal line is electrically connected with a control electrode of the reset transistor; the plurality of drive circuits comprise a reset drive circuit located on one of the first side and the second side of the display area, and the plurality of dummy drive circuits comprise a dummy reset drive circuit;a length of the reset drive circuit along a first direction is greater than a length of the dummy reset drive circuit along the first direction, and the first direction is an arrangement direction of a plurality of drive circuits.

5. The display substrate of claim 4, wherein the reset drive circuit comprises a plurality’ of cascaded reset shift registers, the dummy reset drive circuit comprises at least one dummy reset shift register located between adjacent reset shift registers;the reset shift registers comprise at least one reset transistor and at least one reset capacitor; at least one dummy shift register further comprises a plurality of dummy source-drain electrodes;a shape of at least part of at least one dummy active pattern in at least one dummy reset shift register is the same as a shape of at least part of an active pattern of the at least one reset transistor, a shape of at least part of at least one dummy control electrode in the at least one dummy reset shift register is the same as a shape of at least part of a control electrode of the at least one reset transistor or the at least one reset capacitor, and a shape of at least part of at least one dummy source-drain electrode in the at least one dummy reset shift register is the same as a shape of at least part of at least one electrode of first and second electrodes of the at least one reset transistor.

6. The display substrate of claim 4, wherein the non-display area is further provided with a reset cascade signal line, a reset initial signal line, a first reset clock signal line, a second reset clock signal line, a first reset power supply line, two second reset power supply lines and a third reset power supply line;at least one of the reset initial signal line, the first reset clock signal line, the second reset clock signal line, the first reset power supply line, the second reset power supply lines, the third reset power supply line and the reset cascade signal line extends along a second direction, the first direction intersects with the second direction;orthographic projections of the reset initial signal line, a first one of second reset power supply lines, the third reset power supply line, the first reset clock signal line, the second reset clock signal line, the first reset 70power supply line and a second one of second reset power supply lines on the substrate are sequentially arranged along a direction close to the display area.

7. The display substrate of claim 5, wherein the non-display area is provided with the reset cascade signal line, the two second reset power supply lines and the third reset power supply line, and the reset shift register comprises an input terminal and an output terminal;the reset cascade signal line is electrically connected with an output terminal of at least one reset shift register and an input terminal of at least one reset shift register, respectively; an orthographic projection of the reset cascade signal line on the base substrate is located between an orthographic projection of the first one of second reset power supply lines on the base substrate and an orthographic projection of the third reset power supply line on the base substrate.

8. The display substrate of claim 5, wherein the non-display area is provided with the reset cascade signal line and a first reset power supply line;the dummy reset shift register is located on a side of the reset cascade signal line close to the display area, and at least one dummy source-drain electrode in the dummy reset shift register is electrically connected with the first reset power supply line.

9. The display substrate of claim 6, further comprising drive structure layers; the drive structure layers comprise a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer;the reset cascade signal line, the reset initial signal line and the two second reset power supply lines are located in the fourth conductive layer, and the first reset clock signal line, the second reset clock signal line, the first reset power supply line and the third reset power supply line are located in the fifth conductive layer.

10. The display substrate of claim 3, wherein the display area is provided with a pixel drive circuit and at least one light emitting signal line, the pixel drive circuit comprises a drive transistor and a light emitting transistor that is electrically connected with at least one of a first electrode and a second electrode of the drive transistor, and the light emitting signal line is electrically connected with a control electrode of the light emitting transistor; the plurality of drive circuits comprise a light emitting drive circuit located on the other side of the first side and the second side of the display area, and the plurality of dummy drive circuits comprise a dummy light emitting drive circuit;a length of the light emitting drive circuit along a first direction is greater than or equal to a length of the dummy light emitting drive circuit along the first direction, and the first direction is an arrangement direction of a plurality of drive circuits.

11. The display substrate of claim 10, wherein the light emitting drive circuit comprises a plurality of cascaded light emitting shift registers, the dummy light emitting drive circuit comprises at least one dummy light emitting shift register located between adjacent light emitting shift registers;the light emitting shift registers comprise at least one light emitting transistor and at least one light emitting capacitor; at least one dummy shift register further comprises a plurality of dummy source-drain electrodes;a shape of at least part of at least one dummy active pattern in at least one dummy light emitting shift register is the same as a shape of at least part of an active pattern of the at least one light emitting transistor, a shape of at least part of at least one dummy control electrode in the at least one dummy light emitting shift register is the same as a shape of at least part of a control electrode of the at least one light emitting transistor or the at least one light emitting capacitor, and a shape of at least part of at least one dummy source-drain electrode in the at least one dummy light emitting shift register is the same as a shape of at least part of at least one electrode of first and second electrodes of the at least one light emitting transistor.

12. The display substrate of claim 10, wherein die non-display area is further provided with a light emitting cascade signal line, a light emitting initial signal line, a first light emitting clock signal line, a second light emitting clock signal line, a first light emitting power supply line, two second light emitting power supply lines and a third light emitting power supply line;at least one of the light emitting initial signal line, the first light emitting clock signal line, the second light emitting clock signal line, the first hght emitting power supply line, the second light emitting power supply line, the third light emitting power supply line and the light emitting cascade signal line extends along a second direction, wherein the first direction intersects with the second direction;orthographic projections of the light emitting initial signal line, a first one of second light emitting power supply lines, the third light emitting power supply line, the first light emitting clock signal line, the second light emitting clock signal line, the first light emitting power supply line and a second one of first light emitting power supply lines on the base substrate are sequentially arranged along a direction close to the display area.

13. The display substrate of claim 11, wherein the non-display area is provided with a light emitting cascade signal line, two second light emitting power supply lines and a third light emitting power supply line, and the reset shift register comprises an input terminal and an output terminal;the light emitting cascade signal line is electrically connected with an output terminal of at least one light emitting shift register and an input terminal of at least one light emitting shift register, respectively; an orthographic projection of the light emitting cascade signal line on the base substrate is located between an orthographic projection of the first one of second light emitting power supply lines on the base substrate and an orthographic projection of the third light emitting power supply line on the base substrate.

14. The display substrate of claim 11, wherein the non-display area is provided with the light emitting cascade signal line and a first light emitting power supply line;the dummy light emitting shift register is located on a side of the light emitting cascade signal line close to the display area, and at least one dummy source-drain electrode in the dummy light emitting shift register is electrically connected with the first light emitting power supply line.

15. The display substrate of claim 12, further comprising drive structure layers; the drive structure layers comprise a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer;the light emitting cascade signal line, the light emitting initial signal line and the two second light emitting pow er supply lines are located in the fourth conductive layer; the first light emitting clock signal line, the second light emitting clock signal line, the first light emitting pow er supply line and the third light emitting power supply line are located in the fifth conductive layer.

16. The display substrate of claim 3, w herein the display area is provided w ith a pixel drive circuit and at least one control signal line, the pixel drive circuit comprises a drive transistor and a compensation transistor, the compensation transistor is electrically connected with a control electrode and a second electrode of the drive transistor, and the control signal line is electrically coimected with a control electrode of the compensation transistor; the plurality of drive circuits comprise a control drive circuit located on the first side and the second side of the display area, and the plurality of dummy drive circuits comprise a dummy control drive circuit;a length of the control drive circuit along a first direction is greater than or equal to a length of the dummy control drive circuit along the first direction, and the first direction is an arrangement direction of a plurality of drive circuits.

17. The display substrate of claim 16, wherein the control drive circuit comprises a plurality of cascaded control shift registers, the dummy control drive circuit comprises at least one dummy control shift register located between adjacent control shift registers;the control shift registers comprise at least one control transistor and at least one control capacitor; at least one dummy shift register further comprises a plurality of dummy source-drain electrodes;a shape of at least part of at least one dummy active pattern in at least one dummy control shift register is the same as a shape of at least part of an active pattern of the at least one control transistor, a shape of at least part of at least one dummy control electrode in the at least one dummy control shift register is the same as a shape of at least part of a control electrode of the at least one control transistor or the at least one control capacitor, and a shape of at least part of at least one dummy source-drain electrode in the at least one dummy control shift register is the same as a shape of at least part of at least one electrode of first and second electrodes of the at least one control transistor.

18. The display substrate of claim 16, wherein the non-display area is further provided with a control cascade signal line, two control initial signal lines, a first control clock signal line, a second control clock signal line, three first control power supply lines, two second control power supply lines and a third control power supply line;at least one of the control initial signal lines, the first control clock signal line, a second control clock signal line, the first control power supply line, the second control power supply lines, the third control power supply lines and the control cascade signal line extends along a second direction, and the first direction intersects with the second direction;a first control initial signal line, a first one of second control power supply lines, a second control initial signal line, the first control clock signal line, the second control clock signal line, a first one of first control power supply lines, the third control power supply line, a second one of first control power supply lines, a third one of first control power supply lines and a second one of second control power supply lines are sequentially arranged along a direction close to the display area.

19. The display substrate of claim 17, wherein the non-display area is further provided with a control cascade signal line, two control initial signal lines and a first control clock signal line, and the control shift register comprises an input terminal and an output terminal;the control cascade signal line is electrically connected with an output terminal of at least one cascaded control shift register and an input terminal of at least one cascaded control shift register, respectively; an74orthographic projection of tire control cascade signal line on the base substrate is located between an orthographic projection of a second one of control initial signal lines on the base substrate and an orthographic projection of the first control clock signal line on the base substrate.

20. The display substrate of claim 17, wherein the non-display area is further provided with a control cascade signal line, three first control power supply lines and two second control power supply lines;the control cascade signal line divides a region in which the dummy control shift register is located into a first region and a second region; at least one dummy source-drain electrode located in the first region is connected with a first one of second control power supply lines, and at least one dummy source-drain electrode located in the second region is connected with at least one of first control power supply lines.

21. The display substrate of claim 18, further comprising drive structure layers; the drive structure layers comprise a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer;the control cascade signal line is located in the fourth conductive layer, and the control initial signal line, the first control clock signal line, the second control clock signal line, the first control power supply line, the two second control power supply lines and the third control power supply line are located in the fifth conductive layer.

22. The display substrate of claim 3, wherein the display area is provided with a pixel drive circuit and at least one scan signal line, the pixel drive circuit comprises a drive transistor and a write transistor, the write transistor is electrically connected with a control electrode and a first electrode of the drive transistor, and the scan signal line is electrically connected with a control electrode of the write transistor; the plurality of drive circuits comprise a scan drive circuit located on the first side and the second side of the display area, and the plurality of dummy drive circuits comprise a dummy scan drive circuit;a length of the scan drive circuit along a first direction is greater than or equal to a length of the dummy scan drive circuit along the first direction, and the first direction is an arrangement direction of a plurality of drive circuits.

23. The display substrate of claim 22, wherein die scan drive circuit comprises a plurality of cascaded scan shift registers, the dummy scan drive circuit comprises at least one dummy scan shift register located between adjacent scan shift registers;the scan shift registers comprise at least one scan transistor and at least one scan capacitor; at least one dummy shift register further comprises a plurality of dummy source-drain electrodes;a shape of at least part of at least one dummy active pattern in at least one dummy scan shift register is the same as a shape of at least part of an active pattern of the at least one scan transistor, a shape of at least part of at least one dummy control electrode in the at least one dummy scan shift register is the same as a shape of at least part of a control electrode of the at least one scan transistor or the at least one scan capacitor, and a shape of at least part of at least one dummy source-drain electrode in the at least one dummy scan shift register is the same as a shape of at least part of at least one electrode of first and second electrodes of the at least one scan transistor.

24. The display substrate of claim 22, wherein the non-display area is further provided with a scan cascade signal line, a scan initial signal line, a first scan clock signal line, a second scan clock signal line, a first scan power supply line and a second scan power supply line;at least one of the scan initial signal line, the first scan clock signal line, the second scan clock signal line, the first scan power supply line, the second scan power supply line and the scan cascade signal line extends along a second direction, the first direction intersects with the second direction;the second scan power supply line, the first scan clock signal line, the second scan clock signal line, the scan initial signal line and the first scan power supply line are sequentially arranged along a direction close to the display area.

25. The display substrate of claim 23, wherein the non-display area is further provided with a scan cascade signal line, a scan initial signal line and a second scan clock signal line, the scan shift register comprises an input terminal and an output terminal;the scan cascade signal line is electrically coimected with an output terminal of the at least one scan shift register and an input terminal of the at least one scan shift register, respectively; an orthographic projection of the scan cascade signal line on the base substrate is located between an orthographic projection of the second scan clock signal line on the base substrate and an orthographic projection of the scan initial signal line on the base substrate.

26. The display substrate of claim 23, wherein the non-display area is further provided with a scan cascade signal line, a first scan power supply line and a second scan power supply line;the scan cascade signal line divides a region in which the dummy scan shift register is located into a first region and a second region; at least one dummy source-drain electrode located in the first region is connected with the second scan power supply line, and at least one dummy source-drain electrode located in the second region is connected with the first scan power supply line.

27. The display substrate of claim 24, further comprising drive structure layers; the drive structure layers comprise a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer;the scan cascade signal line is located in the fourth conductive layer, the scan initial signal line, the first scan clock signal line, the second scan clock signal line, the first scan power supply line and the second scan power supply line are located in the fifth conductive layer.

28. The display substrate of claim 3, wherein the drive circuit group comprises a scan drive circuit, a control drive circuit, a light emitting drive circuit and a reset drive circuit;the reset drive circuit, the control drive circuit and the scan drive circuit located on the first side of the display area are sequentially arranged in a direction close to the display area, and the light emitting drive circuit, the control drive circuit and the scan drive circuit located on the second side of the display area are sequentially arranged in a direction close to the display area;the scan drive circuit located on the first side of the display area and the scan drive circuit located on the second side of the display area are symmetrically arranged with respect to a center line extending along the second direction of the display area, the control drive circuit located on the first side of the display area and the control drive circuit located on the second side of the display area are symmetrically arranged with respect to the center line extending along the second direction of the display area, and the reset drive circuit located on the first side of the display area and the light emitting drive circuit located on the second side of the display area are symmetrically arranged with respect to the center line extending along the second direction of the display area.

29. The display substrate of claim 3, wherein the drive circuit group comprises at least one transistor and at least one capacitor, the dummy drive circuit group includes a plurality of dummy active patterns, a plurality of dummy control electrodes and a dummy source-drain electrode, the display substrate further comprises a signal output line, at least one cascade signal line and a plurality of signal lines, which are located in the non-display area, the plurality of signal lines are connected with the drive circuit group and the dummy circuit group, respectively, the signal output lines are connected with the drive circuit group;the drive structure layer comprises a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer;the semiconductor layer comprises, at least, an active pattern of at least one transistor and at least one dummy active pattern of a plurality of dummy active patterns;the first conductive layer comprises, at least, a control electrode of at least one transistor, one plate of at least one capacitor, and at least one dummy active pattern of a plurality of dummy control electrodes;the second conductive layer comprises, at least, the other plate of at least one capacitor;the third conductive layer comprises, at least, a signal output line;the fourth conductive layer comprises at least one signal line and cascade signal lines; andthe fifth conductive layer comprises at least one signal line.

30. The display substrate of claim 29, further comprising at least one initial signal line located in the non-display area; whereinat least one initial signal line is located on a side of at least one of a plurality of signal lines close to the display area and is located in the fifth conductive layer; andan orthographic projection of the at least one initial signal line on the base substrate is at least partially overlapped with orthographic projections of the drive circuit group and the dummy drive circuit group on the base substrate.

31. A display apparatus, comprising: the display substrate of any one of claims 1 to 30.

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