Electronic devices and methods of manufacture

Abstract

A method for manufacturing an electronic device, the method comprising: (i) providing a substrate 200 comprising a non-metallic growth surface 200a; (ii) forming a graphene layer structure 205 on and

Description

The present invention relates to electronic devices and methods for the manufacture of such electronic devices. More particularly, the present invention relates to electronic devices containing a van der Waals heterostructure of the two-dimensional materials graphene and a transition metal dichalcogenide (TMD). Preferred electronic devices are a field-effect transistor (FET) and a hall-effect sensor (HES). Graphene is a well-known two-dimensional material which has been shown to provide unique characteristics and performance suitable for electronic devices. Despite the many advantages associated with graphene, the material’s lack of a bandgap is a limitation for various electronic devices, as is its sensitivity to impurities which can result from its method of manufacture which results is a shift in the Dirac point. “2D Electronics Based on Graphene Field Effect Transistors: Tutorial for Modelling and Simulation” Micromachines 2021, 12, 979 provides an overview of different graphene transistor topologies in which it is acknowledged that reports in the art of top-gated graphene transistors mostly have back-gates. This is to tune all of the transistors to the same point (by tuning them all to the same Dirac point) and as such are essential features of known devices and their operation. US 2021 / 193801 A1 relates to semiconductor devices by using a 2D material layer and a barrier layer as a channel of a transistor. Two-dimensional material heterostructures (which may be referred to as van der Waals heterostructures by virtue of only van der Waals interactions between adjacent layers) have been used in electronic devices and can utilise the different electronic properties of two different materials (such as their bandgap) in the manufacture of electronic devices exhibiting more unique and exceptional electrical and optical properties. “2D Heterostructures for Ubiquitous Electronics and Optoelectronics: Principles, Opportunities, and Challenges” Chern. Rev. 2022, 122, 6, 6514 provides a comprehensive review of recent advances of two-dimensional material heterostructures in electronic devices. Despite the advances in the art, there remains a need for techniques which can deliver the extraordinary properties that two-dimensional materials have to offer, in particular at large-scale for the mass manufacture of electronic devices. There is also a need for processes suitable for integration with standard technology ubiquitous in the field of silicon based fabrication processes (i.e. CMOS compatibility). There is a yet further a need for devices which utilise graphene without requiring a gate to revert the graphene to charge neutrality. “Van der Waals Heterostructure Based Field Effect Transistor Application” Crystals 2018, 8, 8 discusses the process of assembling van der Waals heterostructures and their application in transistors. “Influence of the density of states of graphene on the transport properties of graphene / MoS2 / metal vertical field-effect transistors” Appl. Phys. Lett. 2015, 106, 223103; “Two-dimensional Cold Electron Transport for Steep-slope Transistors” ACS Nano 2021, 15, 3, 5762; and “Low-Power Complementary Inverter Based on Graphene / Carbon-Nanotube and Graphene / MoS2 Barristors” Nanomaterials 2022, 12, 3820, are all examples of prior art which disclose FETs containing graphene and a TMD which comprise a silicon substrate which is used as a back-gate in operation. “High carrier mobility in graphene doped using a monolayer of tungsten oxyselenide” Nature Electronics 2021,4, 731 reports high-density p-type doping of graphene by oxidising monolayer WSe2 into monolayer tungsten oxyselenide by exposure to ozone under UV illumination. “MOVPE of Large-Scale M0S2 / WS2, WS2 / M0S2, WS2 / Graphene and MoS2 / Graphene 2D-2D Heterostructures for Optoelectronic Applications” MRS Advances 2020, 5, 1625 relates to the large-scale deposition of TMDs on graphene by CVD processes. The present invention aims to overcome, or at least reduce, the problems in the prior art so as to provide devices with improved performance, or to at least provide a commercially viable alternative thereto. A first aspect of the present invention relates to a method for the manufacture of an electronic device, the method comprising: (i) providing a substrate comprising a non-metallic growth surface; (ii) forming a graphene layer structure on and across the growth surface by CVD; (Hi) patterning the graphene layer structure, thereby retaining a patterned graphene layer structure, and thereby exposing a first portion of the growth surface; (iv) forming a TMD layer structure on the patterned graphene layer structure and the exposed portion of the growth surface by CVD; (v) patterning the TMD layer structure thereby retaining a patterned TMD layer structure that is on a first portion of the patterned graphene layer structure defining a region of overlap, and extends onto the adjacent first portion of the growth surface; and (vi) forming: (a) a first electrical contact in contact with the patterned graphene layer structure; (b) a second electrical contact in contact with the patterned TMD layer structure. A second aspect of the present invention similarly relates to an electronic device, in particular a fieldeffect transistor (FET) comprising: a substrate comprising a non-metallic surface; a CVD-grown graphene layer structure on the non-metallic surface of the substrate; a CVD-grown TMD layer structure on a portion of the graphene layer structure, together defining a region of overlap, and the TMD layer structure extending onto an adjacent portion of the non-metallic surface of the substrate; a layer of dielectric material on the TMD layer structure and above said region of overlap; a first electrical contact in contact with the graphene layer structure; a second electrical contact in contact with the TMD layer structure; and a third electrical contact on the layer of dielectric material and above said region of overlap. A third aspect of the present invention relates to a method for the manufacture of a sensor the method comprising: (i) providing a substrate comprising a non-metallic growth surface; (ii) forming a hexagonal boron nitride layer structure (h-BN) on and across the growth surface; (Hi) forming a graphene layer structure on and across the h-BN layer structure by CVD; (iv) forming a TMD layer structure on and across the graphene layer structure by CVD; (v) patterning the graphene layer structure and the TMD layer structure; and (vi) forming two or more electrical contacts in contact with the graphene layer structure. A fourth aspect of the present invention similarly relates to a sensor comprising: a substrate comprising a non-metallic surface; a hexagonal boron nitride layer structure (h-BN) on the non-metallic surface; a CVD-grown and patterned graphene layer structure on the h-BN layer structure; a CVD-grown TMD layer structure on and across the graphene layer structure; and two or more electrical contacts in contact with the graphene layer structure; wherein the sensor does not comprise a gate contact. The present disclosure will now be described further. In the following passages, different aspects / embodiments of the disclosure are defined in more detail. Each aspect / embodiment so defined may be combined with any other aspect / embodiment or aspects / embodiments unless clearly indicated to the contrary. In particular, any feature indicated as being preferred or advantageous may be combined with any other feature or features indicated as being preferred or advantageous. In particular, it will be appreciated that the FET or sensor of the second and fourth aspects may be, and preferably are, obtained by the respective method of manufacture of the first and third aspects. Equivalently, the methods described herein are preferably for the manufacture the respective device. Accordingly, features described in respect of the electronic device can apply equally to the method, and vice versa. The various aspects of the present invention are unified by the combination of graphene and TMD each having been grown directly by CVD. As such, there is described herein a further aspect of a diode that is essentially equivalent to the FET, with the exception that there is no third (gate) electrical contact; i.e. a diode comprising: a substrate comprising a non-metallic surface; a graphene layer structure CVD-grown on the non-metallic surface of the substrate; a TMD layer structure CVD-grown on a portion of the graphene layer structure, together defining a region of overlap, and the TMD layer structure extending onto an adjacent portion of the non-metallic surface of the substrate; a first electrical contact in contact with the graphene layer structure; and a second electrical contact in contact with the TMD layer structure; wherein the diode does not comprise a gate contact, and preferably further comprising a layer of dielectric material on and across the graphene layer structure and the TMD layer structure. The present invention relates generally to electronic devices and methods for the manufacture of such electronic devices. Given the materials used, such electronic devices may be referred to as two-dimensional material, graphene and / or TMD containing electronic devices. In the devices of the present invention, at least the graphene layer structure provides an active channel for the device in that electrical contacts are provided in contact with at least the graphene layer structure for the introduction of charge carriers (e.g. an electrical current). The method of manufacture comprises a first step of providing a substrate comprising a non-metallic growth surface. Within the art of semiconductor electronics manufacturing, a substrate is a well-known term which may be used synonymously with, for example, a wafer. A wafer is typically predominantly formed of silicon and may then have layers of thin films deposited thereon and etched so as to fabricate electronic devices and integrated circuits. Suitable materials for providing the non-metallic growth surface include silicon (Si), silicon carbide (SiC), silicon nitride (Si3N4), silicon dioxide (SiOz), sapphire (AI2O3), aluminium gallium oxide (AGO), hafnium dioxide (HfOz), zirconium dioxide (ZrOz), yttria-stabilised hafnia (YSH), yttria-stabilised zirconia (YSZ), magnesium aluminate (MgAlzO4), yttrium orthoaluminate (YAIO3), strontium titanate (SrTiOs), cerium oxide (CezOs), scandium oxide (SC2O3), erbium oxide (ErzOs), magnesium difluoride (MgFz), calcium difluoride (CaFz), strontium difluoride (SrFz), barium difluoride (BaFz), scandium trifluoride (ScFs), germanium (Ge), hexagonal boron nitride (h-BN), cubic boron nitride (c-BN) and / or a 11l / V semiconductor such as aluminium nitride (AIN) and gallium nitride (GaN). Preferably, the non-metallic surface is silicon nitride, silicon dioxide, sapphire, aluminium nitride, YSZ, scandium oxide, germanium, h-BN and / or calcium difluoride. Preferably, the non-metallic surface is sapphire, yttria-stabilised zirconia, scandium oxide or calcium difluoride. In some embodiments, the non-metallic surface may have a specific crystallographic orientation, for example <111 >YSZ, SC2O3 or CaF2 or <1-102> (r-plane) sapphire. In some preferred embodiments, the substrate comprises, or consists of, a first layer which provides the non-metallic surface and a support layer. In some embodiments, the substrate may consist of one such material. In some preferred embodiments, the substrate comprises, or consists of, a first (or upper) layer which provides the non-metallic surface and a support layer. Preferably, the support layer comprises silicon. A silicon support layer, includes a “pure” silicon wafer (essentially consisting of silicon, doped or undoped) or what may be referred to as a CMOS wafer which includes additional associated circuitry embedded therein. The upper layer may preferably be formed of inorganic oxide or nitride such as those described herein and provides the non-metallic surface. The thickness of a silicon support layer is generally much thicker that the thickness of the layer thereon. When and where present, the support layer typically has a thickness of 250 pm to 1.5 mm, for example from 400 pm to 1 mm. On the other hand, the thickness of a layer thereon is substantially thinner. Preferably, the thickness of such layer is at least 2 nm, preferably at least 5 nm and / or less than 500 nm, preferably less than 100 nm. Suitable ranges for the thickness of the layer are preferably 5 nm to 100 nm, preferably 10 to 50 nm. In some embodiments, very thin layers are preferred and the thickness of the layer may preferably be from 2 nm to 10 nm. In some embodiments, the first and / or second layer does not comprise the native silicon oxide which may be removed from the surface of the silicon support before forming the layer. The method comprises forming a graphene layer structure on and across the growth surface by CVD. Graphene is a very well-known two-dimensional material referring to an allotrope of carbon comprising a single layer of carbon atoms in a hexagonal lattice. A graphene layer structure, as used herein, refers to one or more layers of graphene. Accordingly, the present invention relates to the formation of a monolayer of graphene as well as multilayer graphene. A graphene layer structure preferably has from 1 to 10 monolayers of graphene. In many subsequent device applications (e.g. a field-effect transistor, and in particular sensors such as a hall-effect sensor), one monolayer of graphene is particularly preferred. Accordingly, the graphene layer structure is preferably a graphene monolayer. Nevertheless, multilayer graphene may be preferable for certain applications and 2 or 3 layers of graphene may be preferred. The preparation of sufficiently large area graphene with high uniformity has been major problem in the art which has hindered the uptake of graphene in commercial processes and ultimately electronic devices. The standard in the art is to manufacture graphene by CVD on copper foils or other catalytic metal substrates. A significant proportion of research and development has since focussed on the need to optimise the process by which graphene is transferred from such substrates to those of interest for electronic devices (i.e. non-metallic substrates, for example semiconductors such as silicon and insulators such as sapphire). However, the inventors found that graphene grown on copper is inevitably contaminated, if not with copper, at least with the additional materials which are essential to effect the transfer. These include transfer polymers such as PMMA, metal etchants and solvents to remove the polymer. Polymer residues are however never fully removed and graphene provided by such methods cannot be devoid of transfer polymers and / or copper. Additionally, the physical manipulation of the graphene during transfer leads to defects in the atomically thin material. Forming the graphene layer structure (or the TMD layer structure as described herein) directly on the substrate avoids steps such as transferring which can otherwise introduce impurities. For example, direct formation avoids using transfer polymers, etching solutions and solvents. Forming may be considered synonymous with synthesising, manufacturing, producing and growing. CVD refers generally to a range of chemical vapour deposition techniques, each of which involve vacuum deposition to produce thin film materials such as two-dimensional crystalline materials like graphene. Volatile precursors, those in the gas phase or suspended in a gas, are decomposed to liberate the necessary species to form the desired material, carbon in the case of graphene. CVD as described herein is intended to refer to thermal CVD such that the formation of graphene from the decomposition of a carbon-containing precursor is the result of the thermal decomposition of said carbon-containing precursor. A layer structure CVD-grown directly on a surface can be distinguished from one transferred, due to the absence of metallic and other impurities. Preferably, the method involves forming the graphene layer structure by thermal CVD such that decomposition is a result of heating the carbon-containing precursor. Preferably, the temperature of the growth surface during CVD is from 700°C to 1350°C, preferably from 800°C to 1250°C, more preferably from 1000°C to 1250°C. The inventors have found that such temperatures are particularly effective for providing graphene growth directly on the materials described herein by CVD. Preferably, the CVD reaction chamber used in the method disclosed herein is a cold-walled reaction chamber wherein a heater coupled to the substrate is the only source of heat to the chamber. In a particularly preferred embodiment, the CVD reaction chamber comprises a close-coupled showerhead having a plurality, or an array, of precursor entry points. Such CVD apparatus comprising a close-coupled showerhead may be known for use in MOCVD processes. Accordingly, the method may alternatively be said to be performed using an MOCVD reactor comprising a close-coupled showerhead. In either case, the showerhead is preferably configured to provide a minimum separation of less than 100 mm, more preferably less than 25 mm, even more preferably less than 10 mm, between the surface of the substrate and the plurality of precursor entry points. As will be appreciated, by a constant separation it is meant that the minimum separation between the surface of the substrate and each precursor entry point is substantially the same. The minimum separation refers to the smallest separation between a precursor entry point and the substrate surface (i.e. the surface of the metal oxide layer). Accordingly, such an embodiment involves a “vertical” arrangement whereby the plane containing the precursor entry points is substantially parallel to the plane of the substrate surface (i.e. the growth surface). The precursor entry points into the reaction chamber are preferably cooled. The inlets, or when used, the showerhead, are preferably actively cooled by an external coolant, for example water, so as to maintain a relatively cool temperature of the precursor entry points such that the temperature of the precursor as it passes through the plurality of precursor entry points and into the reaction chamber is less than 100°C, preferably less than 50°C. For the avoidance of doubt, the addition of precursor at a temperature above ambient does not constitute heating the chamber, since it would be a drain on the temperature in the chamber and is responsible in part for establishing a temperature gradient in the chamber. Preferably, a combination of a sufficiently small separation between the substrate surface and the plurality of precursor entry points and the cooling of the precursor entry points, coupled with the heating of the substrate to with a decomposition range of the precursor, generates a sufficiently steep thermal gradient extending from the substrate surface to the precursor entry points to allow graphene formation on the substrate surface. As disclosed in WO 2017 / 029470, very steep thermal gradients may be used to facilitate the formation of high-quality and uniform two-dimensional material layers directly on non-metallic substrates, preferably across the entire surface of the substrate. The substrate may have a diameter of at least 5 cm (2 inches), at least 15 cm (6 inches) or at least 30 cm (12 inches). Particularly suitable apparatus for the method described herein include an Aixtron® Close-Coupled Showerhead® reactor and a Veeco® TurboDisk reactor. Consequently, in a particularly preferred embodiment wherein the method of the present invention involves using a method as disclosed in WO 2017 / 029470, forming the graphene layer structure by CVD comprises: providing the substrate on a heated susceptor in a close-coupled reaction chamber, the close-coupled reaction chamber having a plurality of cooled inlets arranged so that, in use, the inlets are distributed across the growth surface of the substrate and have constant separation from the substrate; cooling the inlets to less than 100°C; introducing a carbon-containing precursor in a gas phase and / or suspended in a gas through the inlets and into the close-coupled reaction chamber; and heating the susceptor to achieve a growth surface temperature of at least 50°C in excess of a decomposition temperature of the precursor, to provide a thermal gradient between the growth surface and inlets that is sufficiently steep to allow the formation of graphene from carbon released from the decomposed precursor; wherein the constant separation is less than 100 mm, preferably less than 25 mm, even more preferably less than 10 mm. In another particularly preferred embodiment wherein the method involves using a method as disclosed in WO 2019 / 138231 (the contents of which is incorporated herein in its entirety), forming the graphene layer structure by CVD comprises: providing the substrate on a heated susceptor in a reaction chamber, the reaction chamber having a plurality of inlets arranged so that, in use, the inlets are distributed across the growth surface and have constant separation from the substrate; rotating the heated susceptor at a rotation rate of at least 600 rpm, preferably up to 3000 rpm; introducing a carbon-containing precursor in a gas phase and / or suspended in a gas through the inlets and into the reaction chamber; and heating the susceptor to achieve a growth surface temperature of at least 50°C in excess of a decomposition temperature of the precursor; wherein the constant separation is at least 12 cm, preferably up to 20 cm. As will be appreciated, such CVD steps may be used in other aspects of the present invention and the substrate and growth surface shall be interpreted accordingly whereby the uppermost exposed layer upon which the two-dimensional material is formed provides the growth surface. The most common carbon-containing precursor in the art for graphene growth is methane (CPU). The inventors have found that it is preferable that the carbon-containing precursor used to form graphene is an organic compound, that is, a chemical compound, or molecule, that contains a carbon-hydrogen covalent bond, which comprises two or more carbon atoms. The carbon-containing precursor is preferably a C3-C10 organic compound consisting of carbon and hydrogen and, optionally, oxygen, nitrogen, fluorine, chlorine and / or bromine, even more preferably a C6-C9 organic compound. In a preferred embodiment, the precursor does not comprise a heteroatom, such that the precursor consists of carbon and hydrogen. In other words, preferably the carbon-containing precursor is a hydrocarbon, preferably an alkane. It is also preferable that the organic compound comprise at least two methyl groups (-CH3). Particularly preferred organic compounds for use as carbon-containing precursors, and methods of forming graphene therefrom by CVD, are described in GB 2604377 (the contents of which is incorporated herein in its entirety). The graphene layer structure formed by CVD extends across the growth surface of the underlying substrate. Therefore, the method further comprises a step of patterning the graphene layer structure. Patterning may be carried out using conventional techniques known to those skilled in the art thereby retaining a patterned graphene layer structure. By removing a portion of the graphene layer structure, a corresponding first portion of the growth surface is exposed. The present invention is particularly suitable for the mass manufacture of an array of electronic devices on a common substrate. As such, patterning preferably comprises forming a plurality, or an array, of patterned graphene layer structures (wherein generally each is identical). Conventional techniques for patterning include photolithography. However, one advantage of the present invention is that transfer techniques are avoided in the provision of the two-dimensional materials such that use of photolithographic materials (e.g. photosensitive organic polymers and solvents) could introduce impurities. Therefore, it is particularly preferred that patterning the graphene layer structure comprises forming a layer of dielectric material on and across the graphene layer structure and co-patterning the layer of dielectric material and graphene layer structure thereby exposing a first portion of the growth surface. Co-patterning may use photolithography, and the dielectric layer serves to protect the two-dimensional material from surface contamination during patterning. Co-patterning will be understood to refer to patterning both the graphene and dielectric to have the same shape whereby their edges align above one another. Such a step further comprises patterning the co-patterned layer of dielectric material so as to expose a first portion of the co-patterned graphene layer structure which is adjacent the exposed first portion of the growth surface of the substrate (i.e. to expose the surface of the graphene). As described further herein, the first portion of graphene is used to define a region of overlap such that the portion is directly adjacent the exposed growth surface such that there is no dielectric material remaining between the exposed first portion of graphene and the exposed first portion of substrate. Furthermore, the dielectric material which is retained serves to protect the reminder of the graphene layer structure throughout the further manufacturing steps and ultimately in the final device. The dielectric layer may be formed by any conventional means, for example physical vapour deposition techniques such as molecular beam epitaxy (MBE), sputtering, thermal evaporation, e-beam evaporation, or ALD. Any typical dielectric material may be used, including those described herein for the non-metallic surface of the substrate, in particular inorganic dielectrics, preferably metal oxides. For example, suitable dielectric metal oxides include AI2O3, HfO2, MgO, MgAl2O4, ZnO, Ga2O3, TiO2, SrTiO3, LaAIO3, Ta2O5, LiNbO3, Y2O3, Y-stabilised ZrO2 (YSZ), ZrO2, Y3AI50i2 (YAG), and MoO3. Preferably, the dielectric layer is formed by ALD. ALD is technique known in the art that comprises the reaction of at least two precursors in a sequential, self-limiting manner. Repeated cycles to the separate precursors allow the growth of a layer in a conformal manner (i.e. uniform thickness across the entire surface) due to the layer-by-layer growth mechanism. For example, alumina is a particularly preferred dielectric and can be formed by sequential exposure to trimethylaluminium (TMA) and an oxygen source, preferably one or more of water (H2O), O2, and ozone (O3). The dielectric layer may consist of a single material, or may be formed of two or more sub-layers of dielectric materials. Preferably, the layer of dielectric material has a thickness of at least 5 nm, preferably at least 10 nm, and / or at most 100 nm, preferably at most 50 nm. Layers of dielectric material as described herein typically have a substantially uniform thickness. The inventors have found that a dielectric layer may be formed on the graphene layer structure so as to dope the graphene. The dielectric layer preferably comprises a dielectric metal oxide, preferably molybdenum oxide which the inventors have found is particularly suited for counter doping CVD-grown graphene (which is typically n-type whereas the intrinsic doping of transferred graphene is typically p-type due to exposure to catalytic metal substrates and / or transfer polymers and / or wet processing chemicals). Other suitable dielectric transition metal oxides have a high work function in order to counter dope the graphene, and may be formed from transition metal oxides may be selected from the group consisting of: molybdenum oxide (e.g. MoOs, MOO2), chromium oxide (e.g. CrOs, Cr20s), vanadium oxide (V2O5), tungsten oxide (WO3), nickel oxide (NiO), cobalt oxide (CO3O4), copper oxide (CuO), silver oxide (AgO), titanium oxide (TiO2), tantalum oxide (Ta2Os), and mixtures thereof; preferably molybdenum oxide (e.g. MoOs), chromium oxide (e.g. CrOs), vanadium oxide, tungsten oxide, nickel oxide, and mixtures thereof; and molybdenum oxide being particularly preferred. Accordingly, it is preferred that the dielectric layer comprises a first sub-layer formed of molybdenum oxide, wherein the first sub-layer is provided on the graphene layer structure. A second sub-layer may be formed therein and of a conventional inorganic oxide, nitride, carbide, fluoride or sulphide, typically another metal oxide such as aluminium oxide. The thickness of such a first sub-layer is preferably less than 5 nm, more preferably less than 3 nm, for example from 0.1 nm to 5 nm. The inventors have found that this thickness may be used to control the extent of doping of the graphene layer structure to arrive the desired charge carrier concentration whereby a greater thickness leads to more p-doping. The desired nominal thickness can be achieved through use of a Quartz Crystal Microbalance (QCM) during formation, particularly of molybdenum oxide, which provides the skilled person with an in-situ measurement of the amount of material deposited when carrying out the method. The thickness of the layer is therefore a mean average thickness of the layer. The thickness may then equally be readily determined by those skilled in the art using conventional techniques, for example AFM. The first sub-layer may be deposited using conventional means in the art, for example PVD techniques such as sputtering or evaporation (e.g. thermal evaporation). The first sub-layer is generally not formed by deposition of a metal and oxidation since complete oxidation of the metal to provide the metal oxide with a sufficiently high work function is unreliable without resulting in undesirable oxidation and therefore damage to the underlying graphene layer structure. Furthermore, such a method may introduce impurities which may otherwise acts as dopants which ultimately affect stability at elevated temperatures. Equally, the first sub-layer is generally not formed by a method which utilises a metal oxide precursor (such as a metal organic compound in particular). That is, through techniques such as PVD or the like, the first sub-layer may be directly formed as a metal oxide on the surface of the graphene layer structure. In some embodiments the graphene layer structure has a charge carrier concentration of less than 5x1012 cm-2, preferably less than 2x1012 cm-2, more preferably less than 1012 cm-2, as a result of the combination of materials and method of manufacture described herein. The charge carrier concentration is that measured at ambient conditions (e.g. 0 V and 25°C) after manufacture is complete. The method further comprises a step of forming a TMD layer structure on the patterned graphene layer structure and the exposed portion of the growth surface by CVD. Transition metal dichalcogenides (TMDs or TMDCs), like graphene, are well-known two-dimensional materials. TMDs have the chemical formula MX2 wherein M is a transition metal and X is a chalcogen atom. A TMD layer structure, as used herein, refers to one or more layers of TMD (which may consist of the same TMD, i.e. a homostructure, or may include different TMD layers, i.e. a heterostructure). Accordingly, the present invention relates to the formation of a monolayer of TMD as well as multilayer TMD. A TMD layer structure preferably has from 1 to 10 monolayers of TMD. In many subsequent device applications (e.g. the field-effect transistor described herein) one monolayer of TMD is particularly preferred. Accordingly, the TMD layer structure is preferably a TMD monolayer. Nevertheless, multilayer TMD may be preferable for certain applications and 2 or 3 layers of TMD may be preferred. Examples of suitable semiconducting TMDs include M0S2, WS2, MoSe2, WSe2 and MoTe2. As will be appreciated, a monolayer of TMD refers to one layer of M atoms sandwiched between two layers of X atoms. The TMD layer structure is formed by CVD and the discussion of CVD above in respect of graphene applies equally here. As will be appreciated, such a process may be referred to as MOCVD growth given the need for a transition metal such that the TMD is also preferably grown using an MOCVD reactor. Additionally, the growth surface of the substrate upon which the TMD layer structure is formed will be recognised as being provided in part by the patterned graphene layer structure (at least in the region which will define the first portion), and optionally the dielectric layer, together with the exposed portion of the substrate growth surface. Critically, the inventors have found that the TMD layer structure is more temperature sensitive than the graphene layer structure, particularly when exposed to the precursor for the following two dimensional material. Where the decomposition temperatures of carbon-containing precursors, and therefore the temperature to which the substrate need be heated, is greater for the CVD growth of graphene than a TMD, the inventors have found that it is therefore essential to form the graphene layer structure on the substrate prior to the formation of the TMD layer structure. That is, the TMD layer structure is more sensitive to degradation from highly reactive carbon-containing intermediates which form during the formation of graphene than the graphene layer structure is to the TMD intermediates. Suitable transition metal-containing and chalcogen-containing precursors for use in the formation of a TMD layer structure are well known. Examples of transition metal precursors (which may be organometallic precursors) include zero valent metal precursors such as metal hexacarbonyls (e.g. Mo(CO)e and W(CO)e) and metallocene complexes. Examples of chalcogen precursors include dialkyls, such as dimethyl, diethyl, di-isopropyl and di-tertbutyl - sulfide, selenide and telluride. Such precursors are sufficiently volatile to be provided in a gas phase or suspended in a gas phase for use in an MOCVD reactor. TMDs may also be formed by CVD using transition metal oxides and pure chalcogen, though these methods are less preferred due to the higher temperatures required which risk damaging the graphene during growth. Preferably, the temperature of the graphene layer structure and the exposed non-metallic growth surface of the substrate during CVD formation of the TMD layer structure is less than 500°C, preferably from 100°C to 400°C. Furthermore, without wishing to be bound by theory, it is believed that a substantially flat graphene layer structure, which results from direct CVD-growth on a substantially flat substrate surface, is beneficial for electronic devices since physical deformities in the two-dimensional material (e.g. wrinkles and steps) are detrimental for its unique electronic characteristics. The method further comprises patterning the TMD layer structure. Patterning may be carried out as described above for the graphene layer structure, e.g. by photolithography. As such, in some preferred embodiments, the method further comprises forming a layer of dielectric material on, and preferably across, the patterned TMD layer structure. In such embodiments, the patterning of the TMD layer structure may comprise co-patterning with the layer of dielectric material. Where a (first) layer of dielectric material has already been formed on the graphene layer structure, the additional layer of dielectric material may therefore be referred to as a further or second layer of dielectric material. The TMD layer structure is patterned (or co-patterned as the case may be) so as to retain a patterned TMD layer structure that is on a first portion of the patterned graphene layer structure (as described hereinabove). This first portion defines the entire region of overlap between the patterned TMD layer structure and the patterned graphene layer structure. Moreover, it is preferred that the (further or second) dielectric layer is formed on the TMD layer structure above the region overlap. Such a dielectric layer is particularly suitable as a gate dielectric for the manufacture of a transistor as described herein. Preferably, the dielectric layer extends across the entire region of overlap. This would necessarily be the result of co-patterning. The thickness of such a dielectric layer may be equivalent to that described herein for the first dielectric layer, though may preferably be thinner as a gate dielectric, for example at most 25 nm. The thickness is generally uniform across the entire layer though, for the avoidance of doubt, the thickness is that measured above the region of overlap. The patterned TMD layer structure also extends onto the adjacent first portion of the growth surface (and therefore over the “step” at the edge of the patterned graphene layer structure). Without wishing to be bound by theory, a monolayer of graphene reduces the step height thereby facilitating formation of the TMD layer structure across this boundary. The thickness of a monolayer of graphene is known to be about 0.34 nm whereas the thickness of a monolayer of TMD, M0S2 for example, is larger at about 0.65 nm, such that the step height is reduced by having graphene directly on the substrate, particularly monolayer graphene, offering an advantage over prior devices in which graphene is provided on and extending off the edge of a TMD. The vast majority of the prior art utilises transferred graphene whereby such sub-nanometer differences are considerably less significant given the wrinkles and defects which result from the process. Accordingly, the ordering of the graphene and TMD solves a specific problem which the inventors have found is unique to graphene CVD-grown directly onto the substrate / wafer which forms part of the final electronic device. The method also comprises a step of forming electrical contacts. Typically, the electrical contacts are formed of metal, such as chromium, titanium, aluminium, nickel and / or gold and may be formed by conventional techniques in the art. The method comprises forming a first electrical contact in contact with the patterned graphene layer structure and a second electrical contact in contact with the patterned TMD layer structure. As such, the region of overlap, which is a portion which may be described as a van der Waals heterostructure, provides a vertical junction between the graphene and TMD, and a barrier to current flow between the first and second (i.e. source and drain) contacts. This junction may be utilised in a diode (including electrooptic applications such as photodetectors), or preferably to modulate the flow of current in a transistor. Therefore, a preferred embodiment comprises forming a third electrical contact on the layer of dielectric material and above said region of overlap. Preferably, the third electrical contact is provided above an edge of said portion of the graphene layer structure (i.e. an edge under the TMD layer structure). In some embodiments, the third electrical contact extends across the entire width of overlap (i.e. along a lateral direction between the first and second contacts) and may preferably extend beyond the region of overlap over the TMD layer structure and / or over the graphene layer structure. The third contact may extend across the entire region (i.e. the whole area of overlap) which can depend on the arrangement of the first and second contacts so as to provide a third contact across an area which extends over any path between the first and second contacts. Contacts are provided in contact with at least a surface and / or an edge of the two-dimensional materials. Preferably, one or both of the first and second electrical contacts are in contact with at least an edge, and may contact only an edge, of the graphene layer structure or the TMD layer structure, respectively. That is, in contact with an edge only is intended to mean not in contact with a surface since the contact will form on and contact the surface of the substrate adjacent the edge. Edge only contacts may be achieved by forming contacts after co-patterning since the dielectric layer(s) protect the surface of the two-dimensional material(s). In other embodiments, the dielectric layer may be further patterned to expose a portion of the two-dimensional material surface adjacent the edge and contacts may then be provided in contact with the edge and the correspondingly adjacent surface. It is also preferred that the method further comprises forming a passivation layer on and across the electrical contacts, and any exposed portions of: (a) the patterned graphene layer structure; (b) the patterned TMD layer structure; and (c) where present, any layers of dielectric material. The passivation layer is typically a layer of dielectric material (such as that described hereinabove) and may therefore be referred to as a further or third layer of dielectric material. The passivation layer serves to encompass the layers of the electronic device thereby providing a protective air and moisture barrier coating. The passivation layer may in particular serve to encapsulate and protect the edges of the two-dimensional materials which may otherwise remain exposed after the aforementioned manufacturing steps. The thickness of such a layer may be greater than that of the other dielectric layers described, for example, at least 100 nm or at least 250 nm. Therefore, one particularly preferred embodiment of the present invention comprises: (i) providing a substrate comprising a non-metallic growth surface; (ii) forming a graphene layer structure on and across the growth surface by CVD; (iii-a) forming a first layer of dielectric material on and across the graphene layer structure; (iii-b) co-patterning the first layer of dielectric material and graphene layer structure thereby exposing a first portion of the growth surface, thereby retaining a co-patterned graphene layer structure and layer of dielectric material; and (iii-c) patterning the co-patterned layer of dielectric material thereby exposing a first portion of the co-patterned graphene layer structure adjacent the exposed first portion of the growth surface of the substrate; (iv) forming a TMD layer structure on an exposed portion of the patterned graphene layer structure (preferably across thereby forming on the entire first portion) and an exposed portion of the growth surface by CVD (the TMD layer structure may also be formed and extend onto the adjacent patterned dielectric material); (v-a) forming a second layer of dielectric material on and across the TMD layer structure above said region of overlap; and (v-b) co-patterning the second layer of dielectric material and TMD layer structure thereby retaining a patterned TMD layer structure that is on (and, as above, preferably across) the first portion of the patterned graphene layer structure defining a region of overlap, and which extends onto the adjacent first portion of the growth surface; and (vi) forming: (a) a first electrical contact in contact with an edge of the patterned graphene layer structure; (b) a second electrical contact in contact with an edge of the patterned TMD layer structure; (c) a third electrical contact on the layer of dielectric material and above said region of overlap. The present invention also relates to a field-effect transistor (FET). As described in respect of the method of manufacture, the device comprises a substrate comprising a non-metallic surface, a graphene layer structure CVD-grown on the non-metallic surface of the substrate, and a TMD layer structure CVD-grown on a portion of the graphene layer structure, together defining a region of overlap, and the TMD layer structure extending onto an adjacent portion of the non-metallic surface of the substrate. In accordance with the method described herein, “CVD-grown” is intended to refer to graphene and TMD grown (or formed) by CVD directly on the growth surface of the relevant substrate / wafer / intermediate. This excludes graphene and TMD grown by CVD elsewhere, in particular grown on catalytic metal substrates such as copper, and then transferred. Therefore, in particularly preferred embodiments of this and other aspects described herein, the graphene layer structure and the TMD layer structure are substantially devoid of transfer polymers (e.g. organic polymers) and / or copper (and preferably other catalytic metals well-known in the art such as nickel). This is achieved by virtue of the complete absence of these materials in the manufacturing process. The physical transfer of two-dimensional materials can introduce numerous defects which negatively impacts the physical and electronic properties. As such, a person skilled in the art can readily ascertain whether a graphene or TMD layer structure, and by extension a device, is one comprising a CVD-grown graphene or TMD layer structure that has been grown directly using conventional techniques in the art such as AFM and energy dispersive X-ray (EDX) spectroscopy. Furthermore, such transfer based processes are not suitable for large scale manufacture (such as on CMOS substrates in fabrication plants). Unintentional doping, particularly from the catalytic metal substrates together with the etching solutions, also results in the production of material which is are sufficiently consistent from sample to sample as is required for commercial production of electronic devices. The FET requires a layer of dielectric material on the TMD layer structure and above said region of overlap. The layer of dielectric material may, and preferably does, extend beyond the region of overlap. Preferably, the layer of dielectric material extends across the entire region of overlap. As will be appreciated, the layer of dielectric material may comprise or consist of the first and / or second layers of dielectric material, and optionally the passivation layer, as described in respect of the method. The first and second layers are generally distinct having been co-patterned with the respective two-dimensional material and a passivation layer which encapsulates the further layers of the device may provide one continuous dielectric layer formed of the first and second dielectrics and passivation layer. Preferably, the layer of dielectric material extends on and across the graphene layer structure and the TMD layer structure, and preferably the edges of the two-dimensional materials thereby encapsulating them. The dielectric may be referred to as a gate dielectric and serve to electrically isolate the third contact from the two-dimensional material at least in an area above the region of overlap. The FET comprises a first electrical contact in contact with the graphene layer structure and a second electrical contact in contact with the TMD layer structure, which are each preferably in contact with only an edge of the two-dimensional materials. This can be achieved through co-patterning the graphene and TMD with a layer of dielectric material thereon so as to only expose an edge of the two-material for contact with the electrical contact. These electrical contacts may be referred to as source and drain electrodes. The FET further comprises the third electrical contact (i.e. a gate contact) on the layer of dielectric material and above said region of overlap. The present invention also relates to a method for the manufacture of a sensor, such as a magnetoresistance sensor or preferably a hall-effect sensor (HES). The method comprises providing a substrate comprising a non-metallic growth surface as already described herein. The method comprises forming a hexagonal boron nitride layer structure (h-BN) on and across the growth surface, forming a graphene layer structure on and across the h-BN layer structure by CVD, and forming a TMD layer structure on and across the graphene layer structure by CVD. Preferably, the steps of forming the graphene layer structure and TMD layer structure by CVD are carried out consecutively in situ. It is also preferred to form the h-BN layer structure by CVD and more preferably, all CVD steps are carried out consecutively in situ within the same reaction chamber. h-BN is a well-known two-dimensional material that is analogous to graphene. Accordingly, an h-BN layer structure shall be interpreted accordingly as preferably having from 1 to 10 monolayers, though the h-BN used herein may have many more layers. In the manufacture of a sensor, the present inventors have found that a layer of hexagonal boron nitride (h-BN) provides an ideal substrate surface upon which to provide a graphene layer structure so as to form a van der Waals heterostructure, which together with the TMD layer structure, sandwiches the graphene layer structure. Even more preferably, the method comprises forming a further h-BN layer structure on the TMD layer structure. The method comprises patterning the graphene layer structure and the TMD layer structure. Preferably, the method comprises co-patterning so as to form the same shape graphene and TMD sharing a continuous outer edge. Suitable patterns and geometries are known to those skilled in the art suitable. Common shapes for a HES include crosses with four contacts provided at the end of each arm of the cross, though other geometries include rectangles (including squares), circles, clover leaves, and hall-bars. In some preferred embodiments, the method further comprises a step of forming a dielectric layer on and across the TMD layer structure before co-patterning the dielectric layer with the graphene and TMD layer structures. In some preferred embodiments, the dielectric layer is a further h-BN layer structure. The method further comprises forming two or more electrical contacts in contact with the graphene layer structure, though generally four or more contacts are preferred. Preferably, the method of manufacturing a hall-effect sensor comprises a step of forming a passivation layer after patterning thereby encapsulating the graphene layer structure and the TMD layer structure (and when present the dielectric layer). Formation of a passivation layer may take place either before or after the step of forming the two or more electrical contacts. As will be appreciated, if performed after formation of the electrical contacts, the passivation layer may be etched to access the contacts, or may simply be wirebonded directly through the passivation layer. As such, the present invention also relates to a sensor, preferably a HES, that is preferably obtainable by the method described above, the HES comprising: a substrate comprising a non-metallic surface, an h-BN layer structure on the non-metallic surface, a patterned graphene layer structure CVD-grown on the h-BN layer structure, a TMD layer structure CVD-grown on and across the graphene layer structure; and two or more electrical contacts in contact with the graphene layer structure. The method does not comprise forming a third, or gate, electrical contact. As such, the sensor does not comprise a gate contact. Preferably, the non-metallic surface of the substrate is provided by inorganic oxide or nitride, and more preferably the substrate consists of an inorganic oxide or nitride such as silicon oxide, silicon nitride and / or sapphire. The substrate as described above generally has a thickness that is significantly too large to allow for a gate contact provided on the underside to provide gate modulation of the graphene layer structure. It is typical in the prior art for two-dimensional materials to be transferred to substrates such as SiOa / Si in which the underlying semiconductive silicon support (which may be doped) can serve as a gate contact. As such, preferably the substrate of the sensor has a thickness of 250 pm or more, preferably 500 pm or more. Similarly, the presence of a passivation layer would restrict top gating. Nevertheless, it will also be appreciated that without the requirement for a gate contact, the present invention permits the electronic device to be manufactured especially thin through removal of the support. This may be carried out after formation of the encapsulating passivation layer. As discussed above, typical substrate thicknesses are hundreds of microns and may be up to about 1 mm and even up to about 2 mm thick. In embodiments of the present invention, the underlying support of the substrate is thinned to reduce its thickness and / or remove it altogether after device fabrication on the upper surface (through what is known as “back-grinding" or “wafer-thinning”). Silicon is a particularly suitable support for wafer-thinning (for example, as described in WO 2022 / 175273). Thinning may be carried out by etching with an etchant and / or grinding (preferably where etching follows a preliminary grinding). The support thickness after thinning may be 200 microns or less, preferably 100 microns or less, and may be removed completely to leave only the “first layer” of the substrate as described herein which generally has a sub-micron thickness. Advantageously, the electronic device without a gate contact may be packaged within standard electronic device packages and / or may be used in applications where space and / or weight is constrained. It is advantageous for the HES described herein to be combined with additional components or electronic devices within the same package. For example, in one embodiment, the thinned HES without a gate contact is packaged together with an ASIC chip. It is necessary and ubiquitous in the prior art for a gate contact to be used so as to return the graphene layer structure to charge neutrality in order to facilitate its function as a sensor which relies on the unique properties demonstrated by graphene at or near the Dirac point. This is a particular concern for sensors. The method and sensor described herein provide a graphene layer structure encapsulated in a van der Waals sandwich which does not require a gate voltage (Vg) during operation thereby reducing the complexity of the device. In other words, the HES of the present invention may be used with Vg = 0 V. Therefore, in a further aspect, the present invention relates to the use of the HES described herein in a method of sensing and measuring a magnetic field without application of a gate voltage. The TMD layer structure having been formed directly on the graphene layer structure may be used to counter dope the n-type CVD-grown graphene to a suitable charge carrier concentration. Through use of the method described herein, it is preferred that the graphene layer structure has a charge carrier concentration of 1012 citt2 or less, preferably 5x1011 cnr2 or less (as measured at 0 V and 25°C). Preferably, the HES is used as a current sensor.. Figures The present invention will now be described further with reference to the following non-limiting Figures, in which: Figure 1 illustrates, in cross-section, an embodiment in accordance with the method of the first aspect of the present invention for the manufacture of an embodiment of an FET in accordance with the second aspect of the present invention. Figure 2 illustrates, in cross-section, an embodiment in accordance with the method of the third aspect of the present invention for the manufacture of an embodiment of an HES in accordance with the fourth aspect of the present invention. Figure 1 illustrates, in cross-section, an exemplary method of the first aspect of the present invention for the manufacture of an exemplary FET 250. In a first step 100, a graphene layer structure 205 (preferably a monolayer) is grown on the non-metallic surface 200a of a substrate 200. In some embodiments, the substrate 200 may comprise a silicon support and an upper layer formed of inorganic oxide or nitride which provides the exposed non-metallic surface 200a. The graphene layer structure 205 is formed by CVD, preferably in an MOCVD reactor as described herein, and is formed across the surface 200a. In a second step 105, a first dielectric layer 210 formed of an inorganic oxide is formed on and across the graphene layer structure 205. Such a layer may preferably be formed of a first sub-layer of molybdenum oxide followed by a second sub-layer of aluminium oxide. Such a layer dopes the graphene layer structure 205 to a desirable charge carrier concentration and also protects the graphene layer structure 205 during patterning step 110 which may be carried out using conventional photolithography techniques. Patterning step 110 co-patterns the graphene layer structure 205 and first dielectric layer 210 to have the same co-patterned shape 205’ and 210’. The removal of a portion of these layers re-exposes a portion of the substrate surface 200a’ adjacent the patterned stack 2057210’. A further patterning step 115, which may also be carried out by conventional photolithography, etches a portion of the patterned dielectric layer 210’ thereby exposing a surface portion of the patterned graphene layer structure surface 205a’ that is directly adjacent the exposed substrate surface 200a’. This leaves a further patterned dielectric layer 210”. The method then involves a step 120 of forming a TMD layer structure 215 on the exposed portion of the patterned graphene layer structure 205a’ and the exposed portion of the growth surface 200a’ by CVD. As shown in Figure 1, the TMD layer structure 215 may also be formed and extend onto the adjacent patterned dielectric material 210” that remains on the patterned graphene layer structure 205’ and a continuous layer. In other embodiments, the layer may be discontinuous across the step at the edge of the dielectric layer, particularly where the dielectric layer 210 / 2107210” is sufficiently thick. On the other hand, the thickness of the graphene layer structure 205 is much less (e.g. a monolayer has a thickness of about 0.34 nm) facilitating continuous layer formation. In the following step 125, a second dielectric layer 220 (which may be formed of multiple sub-layers equivalent or even identical to the first dielectric layer 210, or may simply consist of aluminium oxide for example) is formed on and across the TMD layer structure 215. The second dielectric layer 220 may be formed by PVD deposition of a first sub-layer followed ALD deposition of the second sub-layer so as to have a generally conformal and uniform thickness. In step 130, the second dielectric layer 220 and TMD layer structure 215 are patterned to leave a patterned second dielectric layer 220’ on and across a patterned TMD layer structure 215’. The patterned TMD layer structure 215’ is arranged on the previously exposed surface portion of the patterned graphene layer structure surface 205a’ defining a region of overlap 225 with the patterned graphene layer structure 205’ (which will be appreciated to be an area), and further extends onto the previously exposed substrate surface 200a’. Any TMD layer structure which forms on the patterned dielectric material 210” is removed during the patterning. At least in the region of overlap, the patterned second dielectric layer 220’ preferably has a thickness of less than 25 nm to function as a gate dielectric in FET 250. Patterning steps 110 and 130 result in patterned graphene layer structure 205’ and patterned TMD layer structure 215’, respectively, in which only the edges of the two-dimensional materials are exposed. The method illustrated in Figure 1 comprises a step 135 of depositing metallic electrical contacts to contact at least an edge of each two-dimensional material. A first electrical contact 230 is formed to contact an edge of the patterned graphene layer structure 205’ and a second electrical contact 235 is deposited to contact an edge of the patterned TMD layer structure 215’. In the same step 135, a third electrical contact is formed on the patterned second dielectric layer 220’ and above the entire width of the region of overlap 225 (including above an edge of the patterned graphene layer structure 205’). The width of overlap is seen in the cross-section of Figure 1 (which is a cross-section of the FET 250 that includes a path between (i.e. bisects) the first and second electrical contacts 230, 235). A passivation layer 245 is deposited on and across all of the layers in a further step 140 to encapsulate said layers. In particular, the passivation layer 245 encapsulates any remaining exposed edges of the two-dimensional materials (not visible in the cross-sections illustrated in Figure 1). As will be appreciated, the method of Figure 1 may be used to manufacture an array of FETs 250 which share a common substrate 200. The array may then be diced from the common substrate into a smaller array and / or individual FETs 250 for subsequent packaging. Figure 2 illustrates, in cross-section, an exemplary method of the third aspect of the present invention for the manufacture of an exemplary HES 440. In a first step 300, an h-BN layer structure is grown on the non-metallic surface 400a of a substrate 400. In some preferred embodiments, the substrate 200 consists of an inorganic oxide such as r-plane sapphire and may have a thickness of 250 pm or more. The h-BN layer structure is formed by CVD in an MOCVD reactor as described herein, and is formed across the surface 400a. In-situ, in the same reaction chamber, a graphene layer structure 410 (preferably a monolayer) is formed in a second step 305 across the surface 405a of the h-BN layer structure 405. In-situ, in the same reaction chamber, a TMD layer structure 415 is formed in a third step 310 across the surface 410a of the graphene layer structure 410, thereby sandwiching the graphene layer structure 410 between the h-BN layer structure 405 and the TMD layer structure 415 in a van der Waals heterostructure. In a further step 315, a dielectric layer 420, which may be formed of multiple sub-layers, is formed on and across the TMD layer structure 415, for example by ALD, and then the stack of layers are patterned in step 320. In particular, the dielectric layer 420, the TMD layer structure 415 and the graphene layer structure at least are co-patterned to produce a patterned stack in which each of said layers share a continuous outer edge. The shape is not particularly limited, though one preferred shape is a cross having four arms and / or a shape having a fourfold rotational symmetry. The crosssection illustrated in Figure 2 may be one which bisects such a cross along a plane of mirror symmetry. In some embodiments, the h-BN layer structure 405 may also be co-patterned. In step 320, metallic electric contacts 425 and 430 are deposited to contact at least an edge of the graphene layer structure at distal edges (e.g. the distal ends of two opposing arms of a cross). A passivation layer 435 is deposited on and across all of the layers in a further step 325 to encapsulate said layers. In particular, the passivation layer 435 encapsulates any remaining exposed edges of the two-dimensional materials in HES 440 and may have a thickness of 100 nm or more. The method does not comprise forming a gate contact to modulate the charge carrier concentration of the graphene layer structure 410, nor would it be practical to modulate the charge carrier density through the thick substrate 400 or passivation layer 435. As used herein, the singular form of “a”, “an” and “the” include plural references unless the context clearly dictates otherwise. The use of the term “comprising” is intended to be interpreted as including such features but not excluding other features and is also intended to include the option of the features necessarily being limited to those described. In other words, the term also includes the limitations of “consisting essentially of” (intended to mean that specific further components can be present provided they do not materially affect the essential characteristic of the described feature) and “consisting of” (intended to mean that no other feature may be included such that if the components were expressed as percentages by their proportions, these would add up to 100%, whilst accounting for any unavoidable impurities), unless the context clearly dictates otherwise. It will be understood that, although the terms "first", "second", etc. may be used herein to describe various elements, layers and / or portions, the elements, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, layer or portion from another, or a further, element, layer or portion and may therefore be replaced or exchanged with one another for clarity (e.g. for appropriate antecedence) without affecting the scope. It will be understood that the term “on” is intended to mean “directly on” such that there are no intervening layers between one material being said to be “on” another material. Spatially relative terms, such as “under”, "below", "beneath", "lower", “over”, "above", "upper" and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s). It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device as described herein is turned over, elements described as "under” or “below" other elements or features would then be oriented “over” or "above" the other elements or features. Thus, the example term "under" can encompass both an orientation of over and under. The device may be otherwise oriented and the spatially relative descriptors used herein interpreted accordingly. Similarly, these terms will be understood to mean “directly” above (or over and the like), so as to be vertically oriented with respect to the plane of the substrate growth surface as opposed to being merely further from or closer to the substrate. The foregoing detailed description has been provided by way of explanation and illustration, and is not intended to limit the scope of the appended claims. Many variations of the presently preferred embodiments illustrated herein will be apparent to one of ordinary skill in the art, and remain within the scope of the appended claims and their equivalents. For the avoidance of doubt, the entire contents of all documents acknowledged herein are incorporated herein by reference. The present disclosure will now be described further with reference to the following numbered clauses. 1. A method for the manufacture of an electronic device, the method comprising: (i) providing a substrate comprising a non-metallic growth surface; (ii) forming a graphene layer structure on and across the growth surface by CVD; (Hi) patterning the graphene layer structure, thereby retaining a patterned graphene layer structure, and thereby exposing a first portion of the growth surface; (iv) forming a TMD layer structure on the patterned graphene layer structure and the exposed portion of the growth surface by CVD; (v) patterning the TMD layer structure thereby retaining a patterned TMD layer structure that is on a first portion of the patterned graphene layer structure defining a region of overlap, and extends onto the adjacent first portion of the growth surface; and (vi) forming: (a) a first electrical contact in contact with the patterned graphene layer structure; (b) a second electrical contact in contact with the patterned TMD layer structure. 2. The method according to clause 1, wherein step (iii) of patterning the graphene layer structure comprises forming a layer of dielectric material on and across the graphene layer structure and copatterning the layer of dielectric material and graphene layer structure thereby exposing a first portion of the growth surface; and wherein step (iii) further comprises patterning the co-patterned layer of dielectric material thereby exposing the first portion of the co-patterned graphene layer structure adjacent the exposed first portion of the growth surface of the substrate. 3. The method according to clause 1 or clause 2, wherein step (v) of patterning the TMD layer structure comprises forming a layer of dielectric material on the TMD layer structure above said region of overlap, preferably wherein the layer of dielectric material is formed on and across the TMD layer structure, and co-patterning the layer of dielectric material and TMD layer structure. 4. The method according to clause 3, wherein step (vi) further comprises forming a third electrical contact on the layer of dielectric material and above said region of overlap. 5. The method according to any of clauses 1 to 4, further comprising forming a passivation layer on and across the electrical contacts, and any exposed portions of: (a) the patterned graphene layer structure; (b) the patterned TMD layer structure; and (c) where present, any layers of dielectric material. 6. The method according to any of clauses 1 to 5, wherein one or both of the first and second electrical contacts are in contact with only an edge of the graphene layer structure or the TMD layer structure, respectively. 7. The method according to any of clauses 1 to 6, wherein the temperature of the non-metallic growth surface of the substrate during CVD formation of the graphene layer structure is from 700°C to 1350°C, preferably from 800°C to 1250°C, more preferably from 1000°C to 1250°C. 8. The method according to any of clauses 1 to 7, wherein the temperature of the graphene layer structure and the exposed non-metallic growth surface of the substrate during CVD formation of the TMD layer structure is less than 500°C, preferably from 100°C to 400°C. 9. A field-effect transistor (FET) comprising: a substrate comprising a non-metallic surface; a graphene layer structure CVD-grown on the non-metallic surface of the substrate; a TMD layer structure CVD-grown on a portion of the graphene layer structure, together defining a region of overlap, and the TMD layer structure extending onto an adjacent portion of the non-metallic surface of the substrate; a layer of dielectric material on the TMD layer structure and above said region of overlap; a first electrical contact in contact with the graphene layer structure; a second electrical contact in contact with the TMD layer structure; and a third electrical contact on the layer of dielectric material and above said region of overlap. 10. The FET according to clause 9, wherein the layer of dielectric material extends across the entire region of overlap, preferably on and across the graphene layer structure and the TMD layer structure. 11. The FET according to clause 9 or clause 10, wherein the third electrical contact is provided above an edge of said portion of the graphene layer structure, preferably wherein the third electrical contact extends across the entire region of overlap. 12. The FET according to any of clauses 9 to 11, wherein the TMD layer structure is a TMD monolayer. 13. The FET according to any of clauses 9 to 12, wherein the substrate is a silicon-containing wafer comprising a silicon support and an upper layer of inorganic oxide or nitride providing the non-metallic surface. 14. A method for the manufacture of a sensor, the method comprising: (i) providing a substrate comprising a non-metallic growth surface; (ii) forming a hexagonal boron nitride layer structure (h-BN) on and across the growth surface; (Hi) forming a graphene layer structure on and across the h-BN layer structure by CVD; (iv) forming a TMD layer structure on and across the graphene layer structure by CVD; (v) patterning the graphene layer structure and the TMD layer structure; and (vi) forming two or more electrical contacts in contact with the graphene layer structure. 15. The method according to clause 14, further comprising forming a passivation layer thereby encapsulating the graphene layer structure and the TMD layer structure either before or after the step of forming the two or more electrical contacts. 16. The method according to clause 14 or clause 15, wherein steps (iii) and (iv) are carried out consecutively in-situ, preferably wherein steps (ii), (iii) and (iv) are carried out consecutively in-situ. 17. A sensor comprising: a substrate comprising a non-metallic surface; a hexagonal boron nitride layer structure (h-BN) on the non-metallic surface; a patterned graphene layer structure CVD-grown on the h-BN layer structure; a TMD layer structure CVD-grown on and across the graphene layer structure; and two or more electrical contacts in contact with the graphene layer structure; wherein the sensor does not comprise a gate contact. 18. The sensor according to clause 17, wherein the graphene layer structure has a charge carrier concentration of 1012 cm-2 or less, preferably 5x1011 cm-2 or less. 19. The sensor according to clause 17 or clause 18, further comprising a second h-BN layer structure on the TMD layer structure. 20. The sensor according to any of clauses 17 to 19, further comprising a passivation layer encapsulating the patterned graphene layer structure and the TMD layer structure, and when present, the second h-BN layer structure. 21. The sensor according to any of clauses 17 to 20, wherein the non-metallic surface is provided by inorganic oxide or nitride, preferably wherein the substrate consists of an inorganic oxide or nitride, preferably silicon oxide, silicon nitride and / or sapphire. 22. The sensor according to any of clauses 17 to 21, wherein the substrate has a thickness of 250 pm or more, preferably 500 pm or more. 23. The method according to any of clauses 1 to 8 or clauses 14 to 16, wherein forming the graphene layer structure by CVD comprises: providing the substrate on a heated susceptor in a close-coupled reaction chamber, the close-coupled reaction chamber having a plurality of cooled inlets arranged so that, in use, the inlets are distributed across the growth surface of the substrate and have constant separation from the substrate; cooling the inlets to less than 100°C; introducing a carbon-containing precursor in a gas phase and / or suspended in a gas through the inlets and into the close-coupled reaction chamber; and heating the susceptor to achieve a growth surface temperature of at least 50°C in excess of a decomposition temperature of the precursor, to provide a thermal gradient between the growth surface and inlets that is sufficiently steep to allow the formation of graphene from carbon released from the decomposed precursor; wherein the constant separation is less than 100 mm, preferably less than 25 mm, even more preferably less than 10 mm. 24. The method according to any of clauses 1 to 8 or clauses 14 to 16, wherein forming the graphene layer structure by CVD comprises: providing the substrate on a heated susceptor in a reaction chamber, the reaction chamber having a plurality of inlets arranged so that, in use, the inlets are distributed across the growth surface and have constant separation from the substrate; rotating the heated susceptor at a rotation rate of at least 600 rpm, preferably up to 3000 rpm; introducing a carbon-containing precursor in a gas phase and / or suspended in a gas through the inlets and into the reaction chamber; and heating the susceptor to achieve a growth surface temperature of at least 50°C in excess of a decomposition temperature of the precursor; wherein the constant separation is at least 12 cm, preferably up to 20 cm. 25. Use of the sensor obtained by the method of any of clauses 14 to 16, 24 or 25, or according to any of clauses 17 to 22, in a method of sensing and measuring a magnetic field without application of a gate voltage.

Claims

1. A method for the manufacture of an electronic device, the method comprising:(i) providing a substrate comprising a non-metallic growth surface;(ii) forming a graphene layer structure on and across the growth surface by CVD;(Hi) patterning the graphene layer structure, thereby retaining a patterned graphene layer structure, and thereby exposing a first portion of the growth surface;(iv) forming a TMD layer structure on the patterned graphene layer structure and the exposed portion of the growth surface by CVD;(v) patterning the TMD layer structure thereby retaining a patterned TMD layer structure that is on a first portion of the patterned graphene layer structure defining a region of overlap, and extends onto the adjacent first portion of the growth surface; and(vi) forming:(a) a first electrical contact in contact with the patterned graphene layer structure;(b) a second electrical contact in contact with the patterned TMD layer structure;wherein step (v) of patterning the TMD layer structure comprises forming a layer of dielectric material on the TMD layer structure above said region of overlap and co-patterning the layer of dielectric material and TMD layer structure; andwherein step (vi) further comprises forming a third electrical contact on the layer of dielectric material and above said region of overlap.

2. The method according to claim 1, wherein step (iii) of patterning the graphene layer structure comprises forming a layer of dielectric material on and across the graphene layer structure and copatterning the layer of dielectric material and graphene layer structure thereby exposing a first portion of the growth surface; and wherein step (iii) further comprises patterning the co-patterned layer of dielectric material thereby exposing the first portion of the co-patterned graphene layer structure adjacent the exposed first portion of the growth surface of the substrate.

3. The method according to claim 1 or claim 2, wherein the layer of dielectric material is formed on and across the TMD layer structure.

4. The method according to any of claims 1 to 3, further comprising forming a passivation layer on and across the electrical contacts, and any exposed portions of:(a) the patterned graphene layer structure;(b) the patterned TMD layer structure; and(c) where present, any layers of dielectric material.

5. The method according to any of claims 1 to 4, wherein one or both of the first and second electrical contacts are in contact with only an edge of the graphene layer structure or the TMD layer structure, respectively.

6. The method according to any of claims 1 to 5, wherein the temperature of the non-metallic growth surface of the substrate during CVD formation of the graphene layer structure is from 700°C to 1350°C, preferably from 800°C to 1250°C, more preferably from 1000°C to 1250°C.

7. The method according to any of claims 1 to 6, wherein the temperature of the graphene layer structure and the exposed non-metallic growth surface of the substrate during CVD formation of the TMD layer structure is less than 500°C, preferably from 100°C to 400°C.

8. A field-effect transistor (FET) comprising:a substrate comprising a non-metallic surface;a graphene layer structure CVD-grown on the non-metallic surface of the substrate;a TMD layer structure CVD-grown on a portion of the graphene layer structure, together defining a region of overlap, and the TMD layer structure extending onto an adjacent portion of the non-metallic surface of the substrate;a layer of dielectric material on the TMD layer structure and above said region of overlap;a first electrical contact in contact with the graphene layer structure;a second electrical contact in contact with the TMD layer structure; anda third electrical contact on the layer of dielectric material and above said region of overlap.

9. The FET according to claim 8, wherein the layer of dielectric material extends across the entire region of overlap, preferably on and across the graphene layer structure and the TMD layer structure.

10. The FET according to claim 8 or claim 9, wherein the third electrical contact is provided above an edge of said portion of the graphene layer structure, preferably wherein the third electrical contact extends across the entire region of overlap.

11. The FET according to any of claims 8 to 10, wherein the TMD layer structure is a TMD monolayer.

12. The FET according to any of claims 8 to 11, wherein the substrate is a silicon-containing wafer comprising a silicon support and an upper layer of inorganic oxide or nitride providing the non-metallic surface.

13. The method according to any of claims 1 to 7, wherein forming the graphene layer structure by CVD comprises:providing the substrate on a heated susceptor in a close-coupled reaction chamber, the close-coupled reaction chamber having a plurality of cooled inlets arranged so that, in use, the inlets are distributed across the growth surface of the substrate and have constant separation from the substrate;cooling the inlets to less than 100°C;introducing a carbon-containing precursor in a gas phase and / or suspended in a gas through the inlets and into the close-coupled reaction chamber; andheating the susceptor to achieve a growth surface temperature of at least 50°C in excess of a decomposition temperature of the precursor, to provide a thermal gradient between the growth surface and inlets that is sufficiently steep to allow the formation of graphene from carbon released from the decomposed precursor;wherein the constant separation is less than 100 mm, preferably less than 25 mm, even more preferably less than 10 mm.

14. The method according to any of claims 1 to 7, wherein forming the graphene layer structure by CVD comprises:providing the substrate on a heated susceptor in a reaction chamber, the reaction chamber having a plurality of inlets arranged so that, in use, the inlets are distributed across the growth surface and have constant separation from the substrate;rotating the heated susceptor at a rotation rate of at least 600 rpm, preferably up to 3000 rpm;introducing a carbon-containing precursor in a gas phase and / or suspended in a gas through the inlets and into the reaction chamber; andheating the susceptor to achieve a growth surface temperature of at least 50°C in excess of a decomposition temperature of the precursor;wherein the constant separation is at least 12 cm, preferably up to 20 cm.A

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