Conditional branch future instruction processing

Abstract

An apparatus includes conditional branch future instruction processing circuitry configured to process a conditional branch future instruction BFCSEL specifying a branch point, a branch condition, and

Description

The present technique relates to the field of data processing, and more particularly to branch instructions and processing thereof. Program flow may include instructions for a data processing apparatus to process. Program flow may include one or more branch instructions, such as a conditional branch instruction. A branch instruction in program flow causes a branch to a point in program flow corresponding to a branch target, and a conditional branch instruction causes a branch to a point in program flow dependent on evaluation of a branch condition. At least some examples of the present technique provide an apparatus comprising: conditional branch future instruction processing circuitry configured to process a conditional branch future instruction, the conditional branch future instruction specifying a branch point, a branch condition, and a branch target, wherein the branch point is indicative of a point in program flow subsequent to the conditional branch future instruction where program flow is to conditionally branch to a point in program flow corresponding to the branch target dependent on satisfaction of the branch condition; and branch condition evaluating circuitry configured to determine whether the branch condition is satisfied at a point in program flow subsequent to processing of the conditional branch future instruction, to determine whether the program flow is to branch from the branch point to the point in program flow corresponding to the branch target. At least some examples of the present technique provide a computer-readable medium storing computer-readable code for fabrication of an apparatus as described herein. At least some examples of the present technique provide a method comprising: processing a conditional branch future instruction, the conditional branch future instruction specifying a branch point, a branch condition, and a branch target, wherein the branch point is indicative of a point in program flow subsequent to the conditional branch future instruction where program flow is to conditionally branch to a point in program flow corresponding to the branch target dependent on satisfaction of the branch condition; and determining whether the branch condition is satisfied at a point in program flow subsequent to processing of the conditional branch future instruction, to determine whether the program flow is to branch from the branch point to the point in program flow corresponding to the branch target. At least some examples provide a computer program for controlling a host data processing apparatus to provide an instruction execution environment for execution of target program code, the computer program comprising: conditional branch future instruction processing program logic configured to process a conditional branch future instruction, the conditional branch future instruction specifying a branch point, a branch condition, and a branch target, wherein the branch point is indicative of a point in program flow subsequent to the conditional branch future instruction where program flow is to conditionally branch to a point in program flow corresponding to the branch target dependent on satisfaction of the branch condition; and branch condition evaluating program logic configured to determine whether the branch condition is satisfied at a point in program flow subsequent to processing of the conditional branch future instruction, to determine whether the program flow is to branch from the branch point to the point in program flow corresponding to the branch target. At least some examples of the present technique provide a method of compiling a sequence of program instructions to generate a compiled program, the method comprising: determining branch information indicative of a frequency at which a conditional branch in program flow to a different point in program flow is taken; determining, based on the branch information, whether the frequency satisfies a predetermined branching threshold; and inserting, in response to determining that the frequency satisfies a predetermined branching threshold, a conditional branch future instruction into the program instructions, the conditional branch future instruction specifying a branch point, a branch condition, and a branch target, wherein the branch point is indicative of a point in program flow subsequent to the conditional branch future instruction where program flow is to conditionally branch to a point in program flow corresponding to the branch target dependent on satisfaction of the branch condition. Further aspects, features and advantages of the present technique will be apparent from the following description of examples, which is to be read in conjunction with the accompanying drawings, in which: Figure 1 illustrates an example data processing apparatus; Figure 2 illustrates an example apparatus according to the present techniques; Figure 3A illustrates an example conditional branch future instruction; Figure 3B illustrates an example program flow including a conditional branch instruction and a conditional branch; Figure 4A illustrates an example conditional branch future instruction; Figure 4B illustrates an example program flow including a conditional branch instruction and a conditional branch; Figure 5A illustrates an example program flow when the branch condition is evaluated at the time of conditional branch future instruction execution; Figure 5B illustrates an example fetch-decode-execute pipeline for the program flow of figure 5A; Figure 6A illustrates an example program flow when the branch condition is evaluated subsequent to the time of conditional branch future instruction execution; Figure 6B illustrates an example fetch-decode-execute pipeline for the program flow of figure 6A when the branch condition is satisfied; Figure 6C illustrates an example fetch-decode-execute pipeline for the program flow of figure 6A when the branch condition is not satisfied; Figure 7A illustrates an example program flow when the branch condition is evaluated subsequent to the time of conditional branch future instruction execution and at a specified branch condition evaluation point; Figure 7B illustrates an example fetch-decode-execute pipeline for the program flow of figure 7A when the branch condition is satisfied; Figure 7C illustrates an example fetch-decode-execute pipeline for the program flow of figure 7A when the branch condition is not satisfied; Figure 8 illustrates example steps for evaluating a conditional branch future instruction; Figure 9 illustrates example steps for evaluating a conditional branch future instruction; Figure 10 illustrates examples steps for inserting a conditional branch future instruction into program instructions; and Figure 11 illustrates a simulation example. A branch future instruction may be included in program flow in advance of a branch to provide the data processing apparatus with advance warning of the branch, so that the data processing apparatus can prepare to branch to the branch target in advance of the branch. In a similar way, a conditional branch future instruction provides advance warning of a conditional branch, where whether the branch is taken is dependent on evaluation of a branch condition. Such branch future and conditional branch future instructions can reduce a delay to processing when the branch is then reached. An apparatus (e.g. data processing apparatus) comprises conditional branch future instruction processing circuitry configured to process a conditional branch future instruction. The conditional branch future instruction specifies a branch point, a branch condition, and a branch target. The branch point is indicative of a point in program flow, subsequent to the conditional branch future instruction, where program flow is to conditionally branch to a point in program flow corresponding to the branch target, dependent on satisfaction of the branch condition. One way of evaluating the branch condition, to determine whether the program flow is to branch from the branch point to the point in program flow corresponding to the branch target, is to determine whether the branch condition is satisfied when the conditional branch future instruction is processed (e.g. executed, such as when the instruction reaches an execution stage of a processing pipeline). However, this places a limitation on how far ahead in program flow from the branch point the conditional branch future instruction can be placed, because the outcome of the branch condition evaluation cannot change between when the conditional branch future instruction is processed and thus when the branch condition is also evaluated, and when the branch point occurs, as otherwise the evaluation of the branch condition will no longer be valid for the branch point. That is to say, for the evaluation of the branch condition to still be valid when program flow reaches the branch point, the outcome of the branch condition evaluation (which may include evaluating one or more flags, which may change in value) cannot have changed between when the conditional branch future instruction is processed and the branch condition is evaluated, and when the branch point occurs. Thus, there is a limit to how far in advance a conditional branch future instruction can be placed in program flow from its associated branch point. For example, a compiler would not be able to pull the conditional branch future instruction ahead of an intervening instruction that causes a change of condition flags. This means that there is a limit to how far in advance of the branch point the branch target and / or branch fail target can be determined (as these are specified by the conditional branch future instruction), and thus there is a limit to how far in advance of the branch point instructions associated with the branch target and / or branch fail target can be fetched. This can cause a processing bubble, whereby a processor is not fetching / decoding / executing instructions during one or more processing cycles, because program flow may reach the branch point before instructions associated with the branch target / branch fail target have been fetched and thus a delay is then caused while these instructions are fetched. This processing bubble can cause a delay in processing and thus reduces processing performance. Further, this processing bubble may increase with increasing processing pipeline size. The present inventors have identified that it would be advantageous to increase the separation in program flow between a conditional branch future instruction and its associated branch point, to reduce the likelihood and size of processing bubbles occurring in the processing pipeline. Hence, in the examples discussed below, the apparatus also comprises branch condition evaluating circuitry to determine whether the branch condition is satisfied at a point in program flow subsequent to processing of the conditional branch future instruction, to determine whether the program flow is to branch from the branch point to the point in program flow corresponding to the branch target. As such, rather than evaluating the branch condition at the time of processing the conditional branch future instruction, the determination as to whether the branch condition is satisfied is performed at a subsequent point in program flow. Accordingly, a separation in program flow between the conditional branch future instruction and the associated branch point can be increased, and so the branch target can be known earlier and thus instructions associated with the branch target can be fetched earlier. Hence, in the event that the branch condition is satisfied when it is subsequently evaluated, the likelihood that the instructions associated with the branch target have already been fetched is increased, thereby reducing the likelihood of a processing bubble occurring while the processor is waiting for instructions associated with the branch target to be fetched. In the event that the branch condition is not satisfied, the speculatively fetched instructions (that were fetched on the prediction that the branch to the branch target would be taken) can be flushed, while a performance penalty is still less than the performance improvement realised when the branch condition is correctly predicted as being satisfied. As a result, by moving the branch condition evaluation to a later point in program flow than the conditional branch future instruction processing, processing performance can be increased. Indeed, in a lightweight implementation absent of dynamic branch prediction circuitry, the present approach provides improved performance. In some examples, the branch condition evaluating circuitry is configured to determine that the program flow is to branch from the branch point to the point in program flow corresponding to the branch target in response to determining that the branch condition is satisfied. Hence, the branch to the branch target is taken when the branch condition is satisfied. In some examples, the conditional branch future instruction processing circuitry is configured to fetch one or more instructions associated with the branch target, based on predicting that the branch condition will be satisfied, subsequent to processing the conditional branch future instruction and before determining whether the branch condition is satisfied. By predicting that the branch condition will be satisfied, the processing circuitry can fetch instructions associated with the branch target earlier in program flow, before the branch point is reached, and before the determination of whether the branch condition is actually satisfied. As a result, the likelihood of a processing bubble occurring in the event that the branch condition is satisfied when later determined can be reduced. In some implementations, such an approach may be supported by action of a compiler, which inserts conditional branch future instructions based on having determined that the likelihood of the branch being taken is greater than a threshold (such as greater than 50% of the time). Hence, in such an implementation, the conditional branch future instruction processing circuitry can reliably statically predict that the branch condition will be satisfied (i.e. that the branch will be taken), and thus delays in processing can be reduced. In some examples, predicting that the branch condition will be satisfied is based on the conditional branch future instruction being processed by the conditional branch future processing circuitry. Hence, the processing of the conditional branch future instruction may itself act as the action causing the prediction that the branch condition will be satisfied. The prediction can therefore be performed in an efficient manner. In some examples, the conditional branch future instruction processing circuitry is configured to fetch the one or more instructions associated with the branch target independent of a dynamic branch prediction state learned from previous instruction execution. Thus, a dynamic branch prediction state is not used to inform the fetching of the instructions. The present inventors have realised that the present approach may be suited to low-power implementations, where circuitry for maintaining a dynamic branch prediction state is not included. In some examples, predicting that the branch condition will be satisfied is based on processing the conditional branch future instruction and is independent of history information learnt from previous attempts at instruction execution. Hence, the branch condition prediction can be efficiently performed without reference to history information. In some examples, predicting that the branch condition will be satisfied is based on an instruction type of the conditional branch future instruction and is independent of history information learnt from previous attempts at instruction execution. Hence, the trigger for the prediction that the branch condition will be satisfied is the type of instruction, and thus in examples, that the instruction is a conditional branch future instruction is the trigger for predicting that the branch condition will be satisfied without having to refer to history information. As a result, the conditional branch future instruction processing circuitry can efficiently determine whether to predict that the branch condition will be satisfied. In some examples, the branch condition evaluating circuitry is configured to determine whether the branch condition is satisfied at the branch point. In such an example, the separation between the conditional branch future instruction and the point that the branch condition is evaluated is maximised, and this can increase the likelihood that processing delays will be avoided when the branch point is reached. In some examples, the branch condition evaluating circuitry is configured to determine whether the branch condition is satisfied at a point in program flow between the conditional branch future instruction and the branch point. Hence, there can be flexibility associated with when the branch condition is evaluated, depending on implementation. In some examples, the conditional branch future instruction specifies a branch condition evaluation point corresponding to the point in program flow subsequent to processing of the conditional branch future instruction where the branch condition evaluating circuitry is to determine whether the branch condition is satisfied. Hence, the conditional branch future instruction can itself inform when the branch condition is to be evaluated. For example, this may correspond to a point in program flow after one or more flags that are to be evaluated as part of the branch condition evaluation have changed for the last time before the branch point, and so the branch condition evaluation can be reliably performed without the branch condition evaluation outcome changing again before the branch point. In the event of mispredicting that the branch condition will be satisfied when it actually is not satisfied, this can further reduce wasted cycles when instructions are flushed following the misprediction. In some examples, the branch condition evaluating circuitry is configured to process a conditional branch evaluation instruction, the conditional branch evaluation instruction specifying a branch condition evaluation point corresponding to the point in program flow subsequent to processing of the conditional branch future instruction where the branch condition evaluating circuitry is to determine whether the branch condition is satisfied. Hence, an instruction other than the conditional branch future instruction may specify the branch condition evaluation point. In some examples, the address of the conditional branch evaluation instruction is indicative of the branch condition evaluation point. Thus, the branch condition evaluation point can be efficiently determined. In some examples, the branch condition evaluation point corresponds to an offset relative to the branch point. Thus, the branch condition evaluation point can be efficiently specified and a size of the conditional branch future instruction can be reduced. In some examples, to determine whether the branch condition is satisfied, the branch condition evaluating circuitry is configured to evaluate at least one flag. This provides an efficient determination of the branch condition. In some examples, a plurality of flags are evaluated. In some examples, the branch condition corresponds to a type of comparison condition. For example, a plurality of flags may be evaluated to determine whether the branch condition is satisfied. In some examples, the branch point and branch target are indicative of respective program counter offsets relative to a program counter value associated with the conditional branch future instruction. Hence, the branch point and branch target may be efficiently specified in the conditional branch future instruction. In some examples, the branch point is indicative of a first instruction in program flow that will not be executed when the program flow branches to the point in program flow corresponding to the branch target. Hence, the branch point in program flow can be efficiently specified. In some examples, the conditional branch future instruction processing circuitry is configured to, in response to the branch condition evaluating circuitry determining that the branch condition is satisfied, process instructions in program flow from the point in program flow corresponding to the branch target. Hence, when the branch condition is satisfied, program flow may branch to the branch target and continue from there. In some examples, the conditional branch future instruction specifies a branch fail target indicative of a point in program flow where the program flow is to branch dependent on the branch condition not being satisfied. In some examples, the branch condition evaluating circuitry is configured to determine that the program flow is to branch from the branch point to the branch fail target in response to determining that the branch condition is not satisfied. Hence, when the branch condition is not satisfied, program flow may branch to the branch fail target and continue from there. Hence, in some examples, the conditional branch future instruction may specify both a branch target for when the branch condition is satisfied and a branch fail target for when the branch condition is not satisfied. In other examples, only a branch target may be specified, and program flow may continue in sequence in the event that the branch condition is not satisfied rather than branching to a later point in program flow. In some examples, the conditional branch future instruction processing circuitry is configured to, in response to the branch condition evaluating circuitry determining that the branch condition is not satisfied, process instructions in program flow from the point in program flow corresponding to the branch fail target. In some examples, the conditional branch future instruction processing circuitry is configured to, in response to the branch condition evaluating circuitry determining that the branch condition is not satisfied, flush previously fetched instructions that were fetched based on a prediction that the branch condition will be satisfied. Hence, speculatively fetched instructions which were fetched based on a misprediction of the branch condition can be flushed, and instruction processing may then continue from the branch fail target (or in sequence where a branch fail target is not specified). An apparatus and method for processing conditional branch future instructions present in program flow have been described above. Insertion of the conditional branch future instructions into program flow to generate a compiled program will now be described. At least examples may provide a method of compiling a sequence of program instructions to generate a compiled program, the method comprising: determining branch information indicative of a frequency at which a conditional branch in program flow to a different point in program flow is taken; determining, based on the branch information, whether the frequency satisfies a predetermined branching threshold; and inserting, in response to determining that the frequency satisfies a predetermined branching threshold, a conditional branch future instruction into the program instructions, the conditional branch future instruction specifying a branch point, a branch condition, and a branch target, wherein the branch point is indicative of a point in program flow subsequent to the conditional branch future instruction where program flow is to conditionally branch to a point in program flow corresponding to the branch target dependent on satisfaction of the branch condition. In some examples, the branch information is determined based on determining compiler heuristics. In some examples, the branch information is determined based on data generated from a simulation. In this way, conditional branch future instructions may be inserted into program instructions when the frequency that a branch is taken is greater than a predetermined branching threshold. Thus, when an apparatus having circuitry such as that described above processes a conditional branch future instruction, the prediction that the branch condition will be satisfied is more likely to be correct (because the conditional branch future instruction was inserted on the basis of the branch being taken and thus the branch condition being satisfied at a frequency above a branching threshold, such as 50%). This increases the likelihood that the apparatus processing the instruction correctly speculatively fetches instructions associated with the branch target and thus reduces the likelihood of a processing delay when the branch point is reached. Particular examples will now be described with reference to the figures. Figure 1 schematically illustrates an example of a data processing apparatus 2. The data processing apparatus has a processing pipeline 4 which includes a number of pipeline stages. In this example, the pipeline stages include a fetch stage 6 for fetching instructions from an instruction cache 8; a decode stage 10 for decoding the fetch program instructions to generate micro-operations to be processed by remaining stages of the pipeline; an issue stage 12 for checking whether operands required for the micro-operations are available in a register file 14 and issuing micro-operations for execution once the required operands for a given microoperation are available; an execute stage 16 for executing data processing operations corresponding to the micro-operations, by processing operands read from the register file 14 to generate result values; and a writeback stage 18 for writing the results of the processing back to the register file 14. It will be appreciated that this is merely one example of possible pipeline architecture, and other systems may have additional stages or a different configuration of stages. For example in an out-of-order processor an additional register renaming stage could be included for mapping architectural registers specified by program instructions or micro-operations to physical register specifiers identifying physical registers in the register file 14. The execute stage 16 includes a number of processing units, for executing different classes of processing operation. For example the execution units may include an arithmetic / logic unit (ALU) 20 for performing arithmetic or logical operations; a floating-point unit 22 for performing operations on floating-point values, a branch unit 24 for evaluating the outcome of branch operations and adjusting the program counter which represents the current point of execution accordingly; and a load / store unit 28 for performing load / store operations to access data in a memory system 8, 30, 32, 34. The execute stage 16 may include a plurality of execution stages. In this example the memory system include a level one data cache 30, the level one instruction cache 8, a shared level two cache 32 and main system memory 34. It will be appreciated that this is just one example of a possible memory hierarchy and other arrangements of caches can be provided. The specific types of processing unit 20 to 28 shown in the execute stage 16 are just one example, and other implementations may have a different set of processing units or could include multiple instances of the same type of processing unit so that multiple micro-operations of the same type can be handled in parallel. It will be appreciated that Figure 1 is merely a simplified representation of some components of a possible processor pipeline architecture, and the processor may include many other elements not illustrated for conciseness, such as address translation or memory management mechanisms. Figure 2 schematically illustrates an example apparatus 36 having conditional branch future instruction processing circuitry 38 and branch condition evaluation circuitry 40. Apparatus 36 may be included as part of data processing apparatus 2 of figure 1. Conditional branch future instruction processing circuitry 38 is configured to process a conditional branch future instruction, the conditional branch future instruction specifying a branch point, a branch condition, and a branch target, wherein the branch point is indicative of a point in program flow subsequent to the conditional branch future instruction where program flow is to conditionally branch to a point in program flow corresponding to the branch target dependent on satisfaction of the branch condition. Branch condition evaluating circuitry 40 is configured to determine whether the branch condition is satisfied at a point in program flow subsequent to processing of the conditional branch future instruction, to determine whether the program flow is to branch from the branch point to the point in program flow corresponding to the branch target. Hence, as discussed herein, determining whether the branch condition is satisfied is performed at a time later than when the conditional branch future instruction is processed (i.e. executed). This reduces or avoids processing delay when the branch point is reached, as explained further with reference to figures 5A to 7C. Figure 3A shows an example conditional branch future instruction. As shown, the conditional branch future instruction specifies a branch point, a branch condition, and a branch target. This instruction is considered conditional because whether program flow branches to the branch target is dependent on whether the branch condition is satisfied when it is evaluated. Also, this instruction is a branch future instruction because it indicates that a branch point is present in subsequent program flow, i.e. that there is a future branch point. Such conditional branch future instructions can be inserted into program flow, for example by a compiler when compiling a sequence of instructions, to assist the apparatus processing the instructions with handling branches in program flow. The branch point is indicative of a point in program flow subsequent to the conditional branch future instruction where program flow is to conditionally branch. In some examples, the branch point is indicative of a program counter offset relative to a program counter associated with the conditional branch future instruction. In some cases, a subset of the offset may be used, for example when a least significant bit of the offset is 0 it may not be encoded. The branch point may be indicative of a first instruction in program flow that is not executed when the branch is taken, and hence the actual branch may be considered as immediately preceding the branch point. The branch target corresponds to the point in program flow to which program flow is to conditionally branch dependent on satisfaction of the branch condition. The branch target may be indicative of an address or program counter associated with an instruction in program flow. In examples, the branch target is indicative of a program counter offset relative to a program counter value associated with the conditional branch future instruction. The branch condition is evaluated (i.e. it is determined whether the branch condition is satisfied) at a point in program flow subsequent to the conditional branch future instruction. The outcome of the branch condition evaluation informs whether the branch to the branch target is to be taken. For example, when the branch condition is satisfied, the branch to the branch target is taken and program flow branches to the point in program flow corresponding to the branch target, and when the branch condition is not satisfied, the branch is not taken. In this case, the program flow may continue sequentially to the next instruction in program flow (i.e. without branching to the point in program flow corresponding to the branch target). To determine whether the branch condition is satisfied, at least one flag may be evaluated. A flag may indicate state information, and may be set as a result of instruction execution. Different flags may be set dependent on the instruction result. Examples of flags include a negative flag, a zero flag, a carry flag and an overflow flag. One or more flags may be stored in one or more system registers. For example, it may be determined whether a flag is set to zero, and when it is set to zero, the branch condition may be determined as being satisfied. In some examples, to determine whether the branch condition is satisfied, a plurality of flags may be evaluated (for example a plurality of flags may be compared). In some examples, the branch condition may correspond to a type of comparison condition (or a subtraction). Examples of comparison conditions include EQ (equal), NE (not equal), CS (carry set), CC (carry clear), Ml (negative), PL (positive or zero), VS (signed overflow), VC (no signed overflow), HI (unsigned higher), LS (unsigned lower or same), GE (signed greater than or equal), LT (signed less than), GT (signed greater than), and LE (signed less than or equal). Hence, the branch condition may correspond to a type of various different comparison conditions, and the disclosure is not particularly limited in this respect. In an example where the branch condition corresponds to a comparison condition, the comparison condition may be evaluated to determine whether the branch condition is satisfied. Figure 3B illustrates an example program flow including a conditional branch instruction and a conditional branch. As shown, the program flow includes a number of instructions, denoted by lx- In this example, the third instruction in program flow is a BFCSEL (i.e. conditional branch future instruction), specifying a branch point, branch condition, and branch target. As shown in figure 3B, the branch point corresponds to branch instruction Ib, and so when program flow reaches Ib (and before executing Ib), the branch condition is evaluated. When it is determined that the branch condition is satisfied, program flow branches to the instruction in program flow corresponding to the branch target, It, as shown by the arrow. When it is determined that the branch condition is not satisfied, program flow continues to the next instruction in program flow without branching, and so program flow continues to Ib. It will be appreciated that the way the branch point is specified is not particularly limited and may be varied depending on implementation. For example, rather than the branch point being indicative of a first instruction in program flow that will not be executed when the program flow branches to the point in program flow corresponding to the branch target, the branch point may instead be indicative of a last instruction in program flow that will be executed before the program flow branches to the point in program flow corresponding to the branch target. Figure 4A shows another example conditional branch future instruction, similar to the instruction of figure 3A. In this example, the conditional branch future instruction also specifies a branch fail target, as shown in figure 4A. The branch fail target is indicative of a point in program flow where the program flow is to branch dependent on the branch condition not being satisfied. The discussion of figure 3A applies to figure 4A, except that, when the branch condition is not satisfied, rather than continuing in sequence, the program flow branches to the point in program flow corresponding to the branch fail target. This is further explained with reference to Figure 4B. Figure 4B shows the same example program flow as Figure 3B, except, when it is determined that the branch condition is not satisfied, program flow branches to the point in program flow corresponding to the branch fail target. In this way, program flow branches at the branch point irrespective of whether the branch condition is satisfied, but program flow branches to different points in program flow depending on whether the branch condition is satisfied or not. The timing of the branch condition evaluation will now be discussed in more detail with reference to figures 5A to 7C. As discussed above, one way to evaluate the branch condition is to evaluate the branch condition at the time that the conditional branch future instruction is processed (e.g. reaches a final stage of an execution pipeline). This is shown in figures 5A and 5B. Figure 5A shows an example program flow for when the branch condition is evaluated at the time of conditional branch future instruction execution. As shown, the BFCSEL instruction is located in program flow after l5 where the values of one or more flags are updated. This is because the BFCSEL instruction in this example cannot be located earlier than when the one or more flags are updated because then the flags evaluated at the time of the BFCSEL instruction would not correspond to the flag values present at the time of the branch point at I?. Hence, as discussed, there is a limit to how far in advance of the branch point at I7 the BFCSEL instruction can be placed in this example because the values of the one or more flags are updated at l5. The program flow of figure 5A also shows a branch target corresponding to instruction l2o and a branch fail target corresponding to I40. Figure 5B shows an example fetch-decode-execute pipeline, shown by F, D, E1, and E2, for the program flow of figure 5A. In this example, the pipeline has two execute stages, E1 and E2, and flags are evaluated at E2, although it will be appreciated that this may vary depending on implementation. As shown in figure 5B, the instructions of the program flow of figure 5A are processed sequentially by the pipeline. At cycle 9, when the BFCSEL instruction reaches the final execution stage at E2, it is determined whether the branch condition is satisfied, i.e. the one or more flags are evaluated. Once the outcome of the branch condition evaluation is known, instructions associated with either the branch target or the branch fail target (depending on whether the branch condition was satisfied or not) start then being fetched from cycle 10. For example, if the branch condition is satisfied, the instructions l2o, I21 associated with the branch target are then fetched in cycles 10 and 11. If the branch condition is not satisfied, the instructions I40, I41 associated with the branch fail target are fetched in cycles 10 and 11. As discussed in relation to figures 3A and 3B, in some examples a branch fail target is not specified and so processing may just continue in program flow order without branching to a branch fail target (i.e. continue to Is). However, because the outcome of the branch condition evaluation was not known until the BFCSEL instruction was executed at cycle 9 and because the branch target / branch fail target specified by the BFCSEL instruction are not known before the BFCSEL executes at cycle 9, instructions associated with the branch target / branch fail target cannot be fetched any earlier than cycle 9. Hence, a bubble of two processing cycles is formed (i.e. empty slots in the processing pipeline when an instruction is not being fetched, decoded, or executed), as shown by ‘x’ in the fetch, decode, and execute columns. This processing bubble causes a delay in processing and thus reduces processing performance, and is caused by not having knowledge of the branch target / branch fail target earlier in program flow, which itself is caused by having to insert the BFCSEL instruction after one or more flags are updated due to evaluating the branch condition when the BFCSEL instruction is executed (and thus requiring that the flags do not change between when they are evaluated and the branch point). Further, this processing bubble may increase with increasing processing pipeline size. Figures 6A and 6B illustrate how this processing bubble can be reduced or avoided by evaluating the branch condition at a point subsequent to the execution of the BFCSEL instruction, according to the present techniques. Figure 6A shows an example program flow corresponding to the program flow of figure 5A, except the BFCSEL instruction is located before the one or more flags are updated at instruction I5. Figure 6B shows an example fetch-decode-execute pipeline, shown by F, D, E1, and E2, for the program flow of figure 6A, in a similar manner to figure 5B, for when the branch condition is satisfied. In this example, because the BFCSEL instruction is placed earlier in program flow due to not requiring the evaluation of the branch condition at BFCSEL execution, the BFCSEL instruction is executed at cycle 3 and therefore the branch target and branch fail target specified by the BFCSEL instruction are known at cycle 3, and thus earlier than cycle 9 as per the example of figure 5B. Hence, instructions associated with the branch target can be fetched earlier than the example of Figure 5B, based on predicting that the branch condition will be satisfied. Indeed, in examples, the branch condition is predicted as being satisfied by default, for example in response to the BFCSEL instruction being processed. In examples, this prediction is performed independent of any dynamic branch prediction state learned from previous instruction execution. In some examples, a compiler may insert BFCSEL instructions when the likelihood that the branch being taken is greater than a predetermined threshold, such as 50%, and so conditional branch future instruction processing circuitry may be configured to determine that the branch condition will be satisfied based on the presence of the BFCSEL instruction. Thus, because it is predicted that the branch condition will be satisfied, the instruction associated with the branch target (i.e. instructions l2o and I21) can be speculatively fetched at cycles 8 and 9. This means that the instructions associated with the branch target are ready for when the branch point is reached. In the example of Figure 6A-6C, the branch condition is evaluated at the branch point (i.e. before instruction I?). Hence, when instruction Ie reaches the final execute stage E2, the branch condition is evaluated. In the example of figure 6B, the branch condition is satisfied and so the prediction that the branch condition will be satisfied is correct, and the speculative fetching of the instructions associated with the branch target in advance of the branch point has resulted in the processing bubble shown in figure 5B being eliminated. Accordingly, a processing delay is avoided when the branch point is reached and processing performance is increased. Figure 6C shows the alternative case to Figure 6B, and thus shows an example processing pipeline when the branch condition is not satisfied. Because it was predicted that the branch condition will be satisfied, the instructions associated with the branch target (l2o and l21) were speculatively fetched at cycles 8 and 9 as discussed above. The branch condition is then evaluated at cycle 10 in a similar way to figure 6B. However, the branch condition is not satisfied in this case, and thus program flow is to branch to the instructions associated with the branch fail target (instructions l40 and l41) rather than the branch target. As a result, instructions l20 and l2i have been incorrectly fetched and are flushed (shown by strikethrough), and instructions l40 and l41 are now fetched in cycles 11 and 12. This misprediction that the branch condition will be satisfied when it is later determined that it is not satisfied thus introduces a processing bubble and requires the flushing of the instructions fetched based on the misprediction. Compared to figure 5B, in the event of incorrectly predicting that the branch condition will be satisfied, l4i reaches the final execute stage one processing cycle later. However, in the event of correctly predicting that the branch condition will be satisfied, l2i reaches the final execute stage two processing cycles earlier than the example of figure 5B. As a result, overall processing performance is increased. Further, when the BFCSEL instructions are inserted based on the branch condition being satisfied more often than not (for example as a result of a compiler inserting BFCSEL instructions when the frequency of the branch being taken is greater than a threshold such as 50%), processing performance is further increased. In some examples described herein, the conditional branch future instruction may also specify a branch condition evaluation point. The branch condition evaluation point corresponds to the point in program flow subsequent to processing of the conditional branch future instruction where the branch condition evaluating circuitry is to determine whether the branch condition is satisfied. The branch condition evaluation point may be specified by a compiler, for example, to correspond to a point where it is known that the value of the one or more flags which may be evaluated to evaluate the branch condition are not going to change before the branch point. The use of a branch condition evaluation point can be useful because it can reduce the processing performance penalty in the event that the prediction that the branch condition will be satisfied is incorrect (i.e. it can reduce the processing delay incurred in the example of figure 6C). This will now be described with reference to figures 7A-C. Figure 7A shows an example program flow for when the branch condition is evaluated at the branch condition evaluation point. In this example, the branch condition evaluation point corresponds to instruction Is, which is when the one or more flags are updated (which is also the last update before the branch point). Figure 7B shows an example fetch-decode-execute pipeline, shown by F, D, E1, and E2, for the program flow of figure 7A, in a similar manner to figure 6B, for when the branch condition is satisfied. In this example, rather than evaluating the branch condition (i.e. the flags) at cycle 10 when instruction Ie reaches the last execute stage as per figure 6B, the branch condition is evaluated at the branch condition evaluation point and thus at cycle 9 when instruction l5 reaches the last execute stage as shown in figure 7B. As for the example of figure 6B, because the branch target is known earlier, and so the instructions associated with the branch target can be fetched in advance of the branch point, a processing bubble is avoided and instruction I21 reaches the final execute stage at cycle 12. That is to say, like for figure 6B, the example of figure 7B avoids the two cycle delay of figure 5B. Figure 7C shows the case where the branch condition is not satisfied, in a similar manner to figure 6C. In this example, like for figure 7B, the branch condition is evaluated at the branch condition evaluation point and thus at cycle 9 when instruction l5 reaches the last execute stage as shown in figure 7C. However, the branch condition is not satisfied in this case, and thus program flow is to branch to the instructions associated with the branch fail target (instructions I40 and I41) rather than the branch target. As a result, instructions l2o and I21 have been incorrectly fetched and are flushed (shown by strikethrough), and instructions l40 and I41 are now fetched. However, in contrast to figure 6C where instructions l40 and l4i are fetched in cycles 11 and 12, because the branch condition evaluation point is earlier than the branch point, instructions l40 and l4i are instead fetched in cycles 10 and 11. Hence, compared to figure 6C where the branch condition is evaluated at the branch point, by evaluating the branch condition at the branch condition evaluation point (which is earlier than the branch point), one cycle of processing delay can be avoided. As a result, instruction I41 reaches the final execute stage in figure 7C in cycle 14, which is the same as the example of figure 5B. Thus, the processing performance penalty in the event that the prediction that the branch condition will be satisfied is incorrect (when evaluating the branch condition at a point later than BFCSEL execution) can be avoided. This improves processing performance. Figure 8 illustrates steps for evaluating a conditional branch future instruction. Step S80 comprises processing a conditional branch future instruction, the conditional branch future instruction specifying a branch point, a branch condition, and a branch target, wherein the branch point is indicative of a point in program flow subsequent to the conditional branch future instruction where program flow is to conditionally branch to a point in program flow corresponding to the branch target dependent on satisfaction of the branch condition. Step S80 may be performed by the conditional branch future instruction processing circuitry 38 of figure 2. Step S82 comprises determining whether the branch condition is satisfied at a point in program flow subsequent to processing of the conditional branch future instruction, to determine whether the program flow is to branch from the branch point to the point in program flow corresponding to the branch target. Step S82 may be performed by the branch condition evaluation circuity 40 of figure 2. Figure 9 illustrates example steps for evaluating a conditional branch future instruction. Step S90 comprises processing a conditional branch future instruction, such as a BFCSEL instruction like that shown in figures 3A or 4A. In some examples, processing the conditional branch future instruction refers to executing the conditional branch future instruction, such as when the conditional branch future instruction reaches a final execution stage of a processing pipeline. However, it will be appreciated that other execution stages of the processing pipeline may instead be used. As discussed herein, the conditional branch future instruction may specify a branch point, branch condition, and branch target (and in some examples a branch fail target). Step S92 comprises predicting that the branch condition will be satisfied. In examples, this prediction is based on processing the conditional branch future instruction in step S90. In examples, this prediction is independent of history information learnt from previous attempts at instruction execution. In examples, this prediction is based on an instruction type of the conditional branch future instruction, i.e. that the instruction is a conditional branch future instruction is the trigger to cause the prediction that the branch condition will be satisfied. Step S94 comprises fetching one or more instructions associated with the branch target. This step may be performed based on predicting that the branch condition will be satisfied in step S92, subsequent to processing the conditional branch future instruction in step S90, and before step S96. Step S94 may be performed independent of a dynamic branch prediction state learned from previous instruction execution. Step S96 comprises determining whether the branch condition is satisfied. This step is performed subsequent to step S90, as discussed herein, and may be performed at a point in program flow corresponding to the branch point or at a point in program flow before the branch point and after the processing of the conditional branch future instruction. As discussed herein, determining whether the branch condition is satisfied may comprise evaluating at least one flag. The at least one flag may indicate a result of instruction execution and may be stored in one or more system registers to indicate state information. The branch condition may correspond to a type of comparison condition, and thus to determine whether the branch condition is satisfied, the at least one flag may be evaluated using the comparison condition. When the branch condition is satisfied (e.g. the comparison condition is satisfied), the process continues to step S98. Step S98 comprises processing instruction in program flow from the point in program flow corresponding to the branch target. Hence, the branch to the branch target at the branch point is taken (because the branch condition is satisfied), and program flow branches to the point in program flow corresponding to the branch target. Program flow then continues from the branch target. However, when the branch condition is not satisfied (e.g. the comparison condition is not satisfied), the instructions that were fetched based on the prediction that the branch condition will be satisfied are flushed. Hence, step S100 comprises flushing previously fetched instructions that were fetched based on the prediction that the branch condition will be satisfied. The process then continues to step S102. Step S102 comprises processing instructions in program flow from the point in program flow corresponding to the branch fail target. For example, step S102 may comprise fetching instructions from the point in program flow corresponding to the branch fail target. Hence, the branch to the branch fail target is taken (because the branch condition is not satisfied), and program flow branches to the point in program flow corresponding to the branch fail target. Program flow then continues from the branch fail target. In some cases, the conditional branch future instruction may not specify a branch fail target and instead, on determining that the branch condition is not satisfied, program flow may instead continue in sequence (i.e. a branch to the branch fail target is not taken). In this way, as discussed above in relation to figures 6A to 7C, the present approach is able to reduce or avoid a processing delay when the branch point is reached, thereby improving processing performance. Figure 10 illustrates examples steps for inserting a conditional branch future instruction into program instructions. Figure 10 may be performed by a compiler. Step S102 comprises determining branch information indicative of a frequency at which a conditional branch in program flow to a different point in program flow is taken. In some examples, the different point in program flow corresponds to a branch target associated with the conditional branch. The branch information may be determined based on determining compiler heuristics. In some examples, the branch information is determined based on data generated from a simulation of the program flow. Step S106 comprises determining, based on the branch information, whether the frequency satisfies a predetermined branching threshold. For example, the predetermined branching threshold may be 50% or more. Step S108 comprises inserting, in response to determining that the frequency satisfies a predetermined branching threshold (such as 50%), a conditional branch future instruction into the program instructions, the conditional branch future instruction specifying a branch point, a branch condition, and a branch target, wherein the branch point is indicative of a point in program flow subsequent to the conditional branch future instruction where program flow is to conditionally branch to a point in program flow corresponding to the branch target dependent on satisfaction of the branch condition. In this way, conditional branch future instructions may be inserted into program instructions when the frequency that a branch is taken is greater than a predetermined branching threshold. Thus, when an apparatus having circuitry such as that described in figure 2 processes a conditional branch future instruction, the prediction that the branch condition will be satisfied is more likely to be correct (because the conditional branch future instruction was inserted on the basis of the branch being taken and thus the branch condition being satisfied at a frequency above a branching threshold, such as 50%). This increases the likelihood that the apparatus processing the instruction correctly speculatively fetches instructions associated with the branch target and thus reduces the likelihood of a processing delay when the branch point is reached. Concepts described herein may be embodied in computer-readable code for fabrication of an apparatus that embodies the described concepts. For example, the computer-readable code can be used at one or more stages of a semiconductor design and fabrication process, including an electronic design automation (EDA) stage, to fabricate an integrated circuit comprising the apparatus embodying the concepts. The above computer-readable code may additionally or alternatively enable the definition, modelling, simulation, verification and / or testing of an apparatus embodying the concepts described herein. For example, the computer-readable code for fabrication of an apparatus embodying the concepts described herein can be embodied in code defining a hardware description language (HDL) representation of the concepts. For example, the code may define a register-transfer-level (RTL) abstraction of one or more logic circuits for defining an apparatus embodying the concepts. The code may define a HDL representation of the one or more logic circuits embodying the apparatus in Verilog, System Verilog, Chisel, or VHDL (Very High-Speed Integrated Circuit Hardware Description Language) as well as intermediate representations such as FIRRTL. Computer-readable code may provide definitions embodying the concept using system-level modelling languages such as SystemC and SystemVerilog or other behavioural representations of the concepts that can be interpreted by a computer to enable simulation, functional and / or formal verification, and testing of the concepts. Additionally or alternatively, the computer-readable code may define a low-level description of integrated circuit components that embody concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. The one or more netlists or other computer-readable representation of integrated circuit components may be generated by applying one or more logic synthesis processes to an RTL representation to generate definitions for use in fabrication of an apparatus embodying the invention. Alternatively or additionally, the one or more logic synthesis processes can generate from the computer-readable code a bitstream to be loaded into a field programmable gate array (FPGA) to configure the FPGA to embody the described concepts. The FPGA may be deployed for the purposes of verification and test of the concepts prior to fabrication in an integrated circuit or the FPGA may be deployed in a product directly. The computer-readable code may comprise a mix of code representations for fabrication of an apparatus, for example including a mix of one or more of an RTL representation, a netlist representation, or another computer-readable definition to be used in a semiconductor design and fabrication process to fabricate an apparatus embodying the invention. Alternatively or additionally, the concept may be defined in a combination of a computer-readable definition to be used in a semiconductor design and fabrication process to fabricate an apparatus and computer-readable code defining instructions which are to be executed by the defined apparatus once fabricated. Such computer-readable code can be disposed in any known transitory computer-readable medium (such as wired or wireless transmission of code over a network) or non-transitory computer-readable medium such as semiconductor, magnetic disk, or optical disc. An integrated circuit fabricated using the computer-readable code may comprise components such as one or more of a central processing unit, graphics processing unit, neural processing unit, digital signal processor or other components that individually or collectively embody the concept. Figure 11 illustrates a simulator implementation that may be used. Whilst the earlier described embodiments implement the present invention in terms of apparatus and methods for operating specific processing hardware supporting the techniques concerned, it is also possible to provide an instruction execution environment in accordance with the embodiments described herein which is implemented through the use of a computer program. Such computer programs are often referred to as simulators, insofar as they provide a software based implementation of a hardware architecture. Varieties of simulator computer programs include emulators, virtual machines, models, and binary translators, including dynamic binary translators. Typically, a simulator implementation may run on a host processor 1140, optionally running a host operating system 1130, supporting the simulator program 1120. In some arrangements, there may be multiple layers of simulation between the hardware and the provided instruction execution environment, and / or multiple distinct instruction execution environments provided on the same host processor. Historically, powerful processors have been required to provide simulator implementations which execute at a reasonable speed, but such an approach may be justified in certain circumstances, such as when there is a desire to run code native to another processor for compatibility or re-use reasons. For example, the simulator implementation may provide an instruction execution environment with additional functionality which is not supported by the host processor hardware, or provide an instruction execution environment typically associated with a different hardware architecture. An overview of simulation is given in “Some Efficient Architecture Simulation Techniques”, Robert Bedichek, Winter 1990 IISENIX Conference, Pages 53 - 63. To the extent that embodiments have previously been described with reference to particular hardware constructs or features, in a simulated embodiment, equivalent functionality may be provided by suitable software constructs or features. For example, particular circuitry may be implemented in a simulated embodiment as computer program logic. Similarly, memory hardware, such as a register or cache, may be implemented in a simulated embodiment as a software data structure. In arrangements where one or more of the hardware elements referenced in the previously described embodiments are present on the host hardware (for example, host processor 730), some simulated embodiments may make use of the host hardware, where suitable. The simulator program 1120 may be stored on a computer-readable storage medium (which may be a non-transitory medium), and provides a program interface (instruction execution environment) to the target code 1110 (which may include applications, operating systems and a hypervisor) which is the same as the interface of the hardware architecture being modelled by the simulator program 1120. Thus, the program instructions of the target code 1110 described above, may be executed from within the instruction execution environment using the simulator program 1120, so that a host computer 1140 which does not actually have the hardware features of the apparatus 2 discussed above can emulate these features. In the present application, the words “configured to...” are used to mean that an element of an apparatus has a configuration able to carry out the defined operation. In this context, a “configuration” means an arrangement or manner of interconnection of hardware or software. For example, the apparatus may have dedicated hardware which provides the defined operation, or a processor or other processing device may be programmed to perform the function. “Configured to” does not imply that the apparatus element needs to be changed in any way in order to provide the defined operation. In the present application, lists of features preceded with the phrase “at least one of” mean that any one or more of those features can be provided either individually or in combination. For example, “at least one of: [A], [B] and [C]” encompasses any of the following options: A alone (without B or C), B alone (without A or C), C alone (without A or B), A and B in combination (without C), A and C in combination (without B), B and C in combination (without A), or A, B and C in combination. Although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not 5 limited to those precise embodiments, and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope of the invention as defined by the appended claims.

Claims

1. An apparatus comprising:conditional branch future instruction processing circuitry configured to process a conditional branch future instruction, the conditional branch future instruction specifying a branch point, a branch condition, and a branch target, wherein the branch point is indicative of a point in program flow subsequent to the conditional branch future instruction where program flow is to conditionally branch to a point in program flow corresponding to the branch target dependent on satisfaction of the branch condition; andbranch condition evaluating circuitry configured to determine whether the branch condition is satisfied at a point in program flow subsequent to processing of the conditional branch future instruction, to determine whether the program flow is to branch from the branch point to the point in program flow corresponding to the branch target.

2. The apparatus of claim 1, in which the branch condition evaluating circuitry is configured to determine that the program flow is to branch from the branch point to the point in program flow corresponding to the branch target in response to determining that the branch condition is satisfied.

3. The apparatus of any preceding claim, in which the conditional branch future instruction processing circuitry is configured to fetch one or more instructions associated with the branch target, based on predicting that the branch condition will be satisfied, subsequent to processing the conditional branch future instruction and before determining whether the branch condition is satisfied.

4. The apparatus of claim 3, in which predicting that the branch condition will be satisfied is based on the conditional branch future instruction being processed by the conditional branch future processing circuitry.

5. The apparatus of claims 3 or 4, in which the conditional branch future instruction processing circuitry is configured to fetch the one or more instructions associated with the branch target independent of a dynamic branch prediction state learned from previous instruction execution.

6. The apparatus of any of claims 3 to 5, in which predicting that the branch condition will be satisfied is based on processing the conditional branch future instruction and is independent of history information learnt from previous attempts at instruction execution.

7. The apparatus of any preceding claim, in which the branch condition evaluating circuitry is configured to determine whether the branch condition is satisfied at the branch point.

8. The apparatus of any of claims 1 to 6, in which the branch condition evaluating circuitry is configured to determine whether the branch condition is satisfied at a point in program flow between the conditional branch future instruction and the branch point.

9. The apparatus of claim 8, in which the conditional branch future instruction specifies a branch condition evaluation point corresponding to the point in program flow subsequent to processing of the conditional branch future instruction where the branch condition evaluating circuitry is to determine whether the branch condition is satisfied.

10. The apparatus of claim 9, in which the branch condition evaluation point corresponds to an offset relative to the branch point.

11. The apparatus of claim 8, in which the branch condition evaluating circuitry is configured to process a conditional branch evaluation instruction, the conditional branch evaluation instruction specifying a branch condition evaluation point corresponding to the point in program flow subsequent to processing of the conditional branch future instruction where the branch condition evaluating circuitry is to determine whether the branch condition is satisfied.12 The apparatus of claim 11, in which the address of the conditional branch evaluation instruction is indicative of the branch condition evaluation point.

13. The apparatus of any preceding claim, in which to determine whether the branch condition is satisfied, the branch condition evaluating circuitry is configured to evaluate at least one flag.

14. The apparatus of any preceding claim, in which the branch condition corresponds to a type of comparison condition.

15. The apparatus of any preceding claim, in which the branch point and branch target are indicative of respective program counter offsets relative to a program counter value associated with the conditional branch future instruction.

16. The apparatus of any preceding claim, in which the branch point is indicative of a first instruction in program flow that will not be executed when the program flow branches to the point in program flow corresponding to the branch target.

17. The apparatus of any preceding claim, in which the conditional branch future instruction processing circuitry is configured to, in response to the branch condition evaluating circuitry determining that the branch condition is satisfied, process instructions in program flow from the point in program flow corresponding to the branch target.

18. The apparatus of any preceding claim, in which the conditional branch future instruction specifies a branch fail target indicative of a point in program flow where the program flow is to branch dependent on the branch condition not being satisfied.

19. The apparatus of claim 18, in which the branch condition evaluating circuitry is configured to determine that the program flow is to branch from the branch point to the branch fail target in response to determining that the branch condition is not satisfied.

20. The apparatus of claim 19, in which the conditional branch future instruction processing circuitry is configured to, in response to the branch condition evaluating circuitry determining that the branch condition is not satisfied, process instructions in program flow from the point in program flow corresponding to the branch fail target.

21. The apparatus of claim 19 or 20, in which the conditional branch future instruction processing circuitry is configured to, in response to the branch condition evaluating circuitry determining that the branch condition is not satisfied, flush previously fetched instructions that were fetched based on a prediction that the branch condition will be satisfied.

22. A computer-readable medium to store computer-readable code for fabrication of the apparatus of any preceding claim.

23. A method comprising:processing a conditional branch future instruction, the conditional branch future instruction specifying a branch point, a branch condition, and a branch target, wherein the branch point is indicative of a point in program flow subsequent to the conditional branch future instruction where program flow is to conditionally branch to a point in program flow corresponding to the branch target dependent on satisfaction of the branch condition; anddetermining whether the branch condition is satisfied at a point in program flow subsequent to processing of the conditional branch future instruction, to determine whether the program flow is to branch from the branch point to the point in program flow corresponding to the branch target.

24. A computer program comprising instructions which, when executed by a host data processing apparatus, control the host data processing apparatus to provide an instruction execution environment for execution of target program code, the computer program comprising: conditional branch future instruction processing program logic configured to process a conditional branch future instruction, the conditional branch future instruction specifying a branch point, a branch condition, and a branch target, wherein the branch point is indicative of a point in program flow subsequent to the conditional branch future instruction where program flow is to conditionally branch to a point in program flow corresponding to the branch target dependent on satisfaction of the branch condition; andbranch condition evaluating program logic configured to determine whether the branch condition is satisfied at a point in program flow subsequent to processing of the conditional branch future instruction, to determine whether the program flow is to branch from the branch point to the point in program flow corresponding to the branch target.

25. A method of compiling a sequence of program instructions to generate a compiled program, the method comprising:determining branch information indicative of a frequency at which a conditional branch in program flow to a different point in program flow is taken;determining, based on the branch information, whether the frequency satisfies a predetermined branching threshold; andinserting, in response to determining that the frequency satisfies a predetermined branching threshold, a conditional branch future instruction into the program instructions, the conditional branch future instruction specifying a branch point, a branch condition, and a branch target, wherein the branch point is indicative of a point in program flow subsequent to the conditional branch future instruction where program flow is to conditionally branch to a point in program flow corresponding to the branch target dependent on satisfaction of the branch condition.26

Images