SRT Digit Selection Component

Abstract

A component for digit selection in an SRT algorithm using a redundant digit set 𝑄. The component includes an input (302) to receive a remainder signal representing a remainder 𝑅 and a second input (

Description

FIELD

[0001] The present disclosure relates to architectures for implementing SRT division. BACKGROUND

[0002] Hardware logic can be configured to implement division and square root operations in computer devices. Hardware implementations typically use slow division algorithms, which are based on a recurrence equation. Like handwritten long division methods, division algorithms are iterative and work to determine one or more digits of the quotient at each iteration. At each iteration, a running quotient estimate is updated in a register, and a partial remainder is produced for use in calculating a next quotient digit at the next iteration.

[0003] Some division algorithms are more efficient than others when implemented in hardware. For example, some algorithms can calculate (or estimate) more than one bit of the quotient at each iteration. These algorithms therefore arrive at a final output in fewer iterations than a different algorithm that calculates the quotient one digit at a time.

[0004] SRT (Sweeney, Robson, Tocher) division is an example of such an algorithm. SRT division involves selecting, at each iteration, a quotient digit from a redundant quotient digit set. The digit set is redundant in that the number of elements in the digit set is greater than the radix (base) of the digit set. For example, if the digit set is radix-4, there are greater than four possible quotient digits to select from at each iteration.

[0005] Using a redundant digit set, a given number may be represented in more than one different way. For example, one possible digit set in radix-4 is {-2, -1, 0, 1, 2}. The number 6 (in decimal) can equally be represented in base 4 by 12 (4+2), or by 22 (8-2), where the bar represents the negative digit in the set. This redundancy allows quotients to be calculated in fewer iterations, as each quotient digit need only be suitably estimated, rather than precisely calculated. Moreover, later quotient digit selections can account for error in previous iteration estimates, to arrive at the correct quotient. For example, if 6 were a quotient being calculated, either 1 or 2 could have been selected in the highest bit value position.

[0006] Implementing SRT division requires a way to select a quotient digit at each iteration of the algorithm. Known implementations of SRT division use lookup tables (LUTs), which are consulted at each iteration to determine which digit in the digit set should be selected. LUTs are pre-coded arrays, which map input signals to an SRT digit to be selected. SRT division takes normalized inputs of dividend and divisor, meaning that a LUT applies to all operations using the same radix.

[0007] In known implementations, SRT digit selection is performed using a short width Carry Propagate Adder (CPA) on remainder signals (remainder sum and carry discussed later herein). Based on the output of the CPA and the divisor, the LUT is consulted to determine an SRT digit to be selected. Latency in SRT division systems is heavily dependent on the digit selection logic. SUMMARY

[0008] This Summary is provided merely to illustrate some of the concepts disclosed herein and possible implementations thereof. Not everything recited in the Summary section is necessarily intended to be limiting on the scope of the disclosure. Rather, the scope of the present disclosure is limited only by the claims.

[0009] One example problem with SRT division implementations is that different operations (e.g., square root, signed division, unsigned division, floating point division, floating point square root) require different implementations of digit selection logic. Therefore, increased flexibility for performing different operations comes at a cost of higher storage demands. Examples of the present disclosure provide SRT digit selection logic which generalizes to any radix and to any operation, thus providing additional functionality and storage advantages over known implementations.

[0010] Another example problem is one of improving performance of an SRT division system. Higher performance, in terms of quotient digits estimated per iteration, can be achieved by operating at higher radix. However, known architectures do not generalize to any radix and increasing performance this way typically requires a corresponding increase in architectural complexity. Consequently, latency along the critical path increases as higher radix digit sets are used.

[0011] Examples herein provide a digit selection component which reduces latency at higher radix, by removing reliance on LUTs and removing Carry Propagate Adders (CPAs) from the critical path. Instead, pre-calculated bounds are encoded for the digit set and Carry Save Adders (CSAs) with shorter latency are implemented. If latency on the critical path is not reduced, CPU clock frequency may need to be reduced accordingly and the performance gains from using higher radix are reduced, along with performance loss across the entire CPU.

[0012] According to a first aspect of the present disclosure there is provided a digit selection component for a processing system, wherein the digit selection component is configured to implement digit selection in an SRT algorithm, wherein the SRT algorithm operates in radix x using a redundant digit set Q, the digit selection component comprising: a first input configured to receive a remainder signal representing a remainder R and a second input configured to receive an operand signal representing an operand D, for each non-zero candidate digit qt in digit set Q, a respective instance of bound logic, wherein each instance of bound logic comprises: bound calculation logic configured to calculate a bound Bt as a function of the digit qt and the operand D\ and comparison logic configured to generate a comparison bit based on the bound Bt and the remainder signal, wherein the comparison bit indicates a relative size of the remainder R and the bound B^ zero-digit bound logic configured to output a preset comparison bit, the zero-digit logic corresponding to a candidate digit q0 = 0 in the redundant digit set Q\ digit selection logic configured to receive comparison bits from the respective bound logic instances and the preset comparison bit from the zero-digit bound logic, and to generate, based on the comparison bits, a digit selection signal indicating selection of a digit q* e Q\ and a selection component output configured to output the digit selection signal.

[0013] In some examples, the bound calculation logic is configured to calculate an upper bound B^ The comparison logic may be configured to generate a comparison bit which indicates whether the remainder R is less than the upper bound Bt.

[0014] In some examples, the bound calculation logic is configured to calculate a lower bound B^ The comparison logic may be configured to generate a comparison bit which indicates whether the remainder R is greater than the lower bound Bi.

[0015] In some examples, each instance of bound logic comprises: a first comparison channel configured to generate a first candidate comparison bit, wherein the first comparison channel comprises first CSA and comparator logic, inverter logic, and first XOR logic, and is configured to: using the first CSA and comparator logic, subtract the lower bound Bt from the remainder signal and extract a MSB of the subtraction; invert the MSB of the subtraction using the inverter logic, resulting in a first inverted MSB; receive a sign bit of the operand signal and, using the first XOR logic, calculate the first candidate comparison bit by performing an XOR operation between the first inverted MSB and the sign bit of the operand signal; a second comparison channel configured to generate a second candidate comparison bit, wherein the second comparison channel comprises second CSA and comparator logic, and second XOR logic, and is configured to: using the second CSA and comparator logic, add the lower bound Bt to the remainder signal and extract a second MSB of the summation; receive a sign bit of the operand signal and, using the second XOR logic, calculate the second candidate comparison bit by performing an XOR operation between the MSB of the summation and the sign bit of the operand signal; Boolean OR logic configured to generate the comparison bit by performing a Boolean OR operation between the first candidate comparison bit and the second candidate comparison bit.

[0016] In some examples, the lower bound is calculated as a function f(qL,D) of the digit qt and the operand D, wherein: / (^,0) = (1 + 2(^-1))0.

[0017] In some examples, the SRT algorithm operates in Radix-8 (x = 8), wherein the digit selection component comprises eight bound logic instances respectively representing digits -4, -3, -2, -1, 1, 2, 3 and 4 in digit set Q = {-4, -3, -2, -1,0,1,2,3,4}.

[0018] In some examples, the SRT algorithm operates in Radix-16 (x = 16), wherein the digit selection component comprises sixteen bound logic instances respectively representing digits -8, -7, -6, -5, -4, -3, -2, -1, 1, 2, 3, 4, 5, 6, 7 and 8 in digit set Q = {-8, -7, —6, -5, —4, -3, —2, -1,0,1,2, 3,4, 5, 6, 7, 8}.

[0019] According to a second aspect of the present disclosure, there is provided a computer implemented method of performing digit selection in an SRT algorithm, the method implemented by the digit selection component the first aspect and comprising: receiving a remainder signal representing a remainder R, and an operand signal representing an operand O; for each non-zero candidate digit qL in a redundant SRT digit set Q, generating a comparison bit based on the remainder signal and the operand signal; setting a preset comparison bit corresponding to a candidate digit q0 = 0 in the redundant digit set Q\ generating, based on the comparison bit for each candidate digit qit and the preset zero-digit comparison bit, a digit selection signal indicating selection of a digit q* e Q\ and outputting the digit selection signal.

[0020] According to a third aspect of the present disclosure, there is provided a processing system configured to perform the method of the second aspect.

[0021] According to a fourth aspect of the present disclosure there is provided a method of manufacturing, using an integrated circuit manufacturing system, a processing system according to the third aspect.

[0022] According to a fifth aspect of the present disclosure there is provided a system configured to implement an iterative SRT algorithm, comprising: initialisation logic, iteration logic, an iteration register, results logic, a results register, and counter logic, wherein the iteration logic comprises: a digit selection component according to any embodiment of the first aspect, the digit selection component configured to receive a remainder signal and an operand signal from the iteration register, and to output the digit selection signal; on-the-fly conversion logic configured to generate an updated estimate signal at each iteration based on an estimate signal from the iteration register and based on the digit selection signal; addition circuitry configured to generate an updated remainder by subtracting a multiple of the operand from the remainder signal, the multiple determined by the digit selection signal; wherein the counter logic controls the iteration register to store the updated estimate signal and updated remainder signal.

[0023] The digit selection component may be embodied in hardware on an integrated circuit. There may be provided a method of manufacturing, at an integrated circuit manufacturing system, a digit selection component. There may be provided an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the system to manufacture a digit selection component. There may be provided a non-transitory computer readable storage medium having stored thereon a computer readable description of a digit selection component that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying a digit selection component.

[0024] There may be provided an integrated circuit manufacturing system comprising: a non-transitory computer readable storage medium having stored thereon a computer readable description of the digit selection component; a layout processing system configured to process the computer readable description so as to generate a circuit layout description of an integrated circuit embodying the digit selection component; and an integrated circuit generation system configured to manufacture the digit selection component according to the circuit layout description. The layout processing system may be configured to determine positional information for logical components of a circuit derived from the integrated circuit description so as to generate the circuit layout description of the integrated circuit embodying the graphics processing system.

[0025] There may be provided computer program code for performing any of the methods described herein. There may be provided non-transitory computer readable storage medium having stored thereon computer readable instructions that, when executed at a computer system, cause the computer system to perform any of the methods described herein.

[0026] The above features may be combined as appropriate, as would be apparent to a skilled person, and may be combined with any of the aspects of the examples described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Examples will now be described in detail with reference to the accompanying drawings in which:

[0028] Figure 1 is a highly schematic diagram of an example computer system configured to implement an SRT algorithm;

[0029] Figure 2 shows a highly schematic diagram of iteration logic configured to implement an SRT algorithm;

[0030] Figure 3 illustrates an example digit selection component according to some examples of the present disclosure;

[0031] Figure 4 illustrates example comparison logic configured to generate a comparison bit in a digit selection component;

[0032] Figure 5 shows a computer system in which a graphics processing system is implemented; and

[0033] Figure 6 shows an integrated circuit manufacturing system for generating an integrated circuit embodying a graphics processing system.

[0034] The accompanying drawings illustrate various examples. The skilled person will appreciate that the illustrated element boundaries (e.g., boxes, groups of boxes, or other shapes) in the drawings represent one example of the boundaries. It may be that in some examples, one element may be designed as multiple elements or that multiple elements may be designed as one element. Common reference numerals are used throughout the figures, where appropriate, to indicate similar features. DETAILED DESCRIPTION

[0035] The following description is presented by way of example to enable a person skilled in the art to make and use the invention. The present invention is not limited to the embodiments described herein and various modifications to the disclosed embodiments will be apparent to those skilled in the art.

[0036] Embodiments will now be described by way of example only.

[0037] SRT division and square root algorithms can be implemented in hardware logic on computing devices such as CPUs. All SRT implementations require logic configured to select, at each iteration, a suitable digit from a redundant digit set. Digit selection logic is an important aspect of systems configured to implement SRT algorithms. Latency in such systems is strongly dependent on the way the digit selection logic is implemented. In known implementations, digit selection logic also changes depending on the types of operations that need to be supported. For this reason, support for multiple SRT operation types may require additional digit selection logic at a cost of CPU area.

[0038] The present disclosure relates to a digit selection component for use in SRT algorithm implementations. The digit selection component provides advantages in latency over known digit selection techniques, and enables the SRT operations to be generalised over numerical formats and operation types; this provides improvements in functionality and CPU area demand, relative to known implementations.

[0039] In examples where numbers such as remainders, estimates, operands, quotients etc. are referred to as ‘signals’, the signals will be understood as binary numbers encoded in signal form (e.g., as electrical signals) in such a way as to be processed by hardware logic. Similarly, references to a ‘number’ in the context of a hardware implementation will be understood to mean a corresponding encoded signal representing that number.

[0040] Systems for Implementing SRT Division

[0041] Reference is made to Figure 1, which shows a high-level block diagram of an example processing block 100, configured with logic for implementing an SRT algorithm. The logic of the processing block 100 may be implemented on a computing device such as a CPU. Figure 1 shows an example of a system in which the digit selection component described herein may be implemented.

[0042] The example processing block 100 comprises initialisation logic 110, iteration logic 130, and results logic 150. An SRT digit selection component 132 forms part of the iteration logic 130. The example processing block 100 further comprises an iteration register 120, a results register 140, and a finite state machine (FSM) and counter 160.

[0043] The initialisation logic 110 is configured to receive one or more input 102 and to perform initialisation operations on the input(s). The input 102 may comprise first and second data, respectively representing operands of a division operation.

[0044] The initialisation operations may include normalization, exception detection, and initialisation of the registers 120, 140 in preparation for the iteration stage. The initialisation logic 110 outputs initial iteration data, including for example an initial estimate of the quotient (e.g., zero), a normalised initial remainder (equal to the dividend prior to iteration), a normalised operand (e.g., divisor or early root estimate in the case of square root operations), and data indicating exponents and shift values of the normalised numbers. In the case that an error is detected, an error signal is output from the initialisation logic 110.

[0045] The iteration register 120 holds iteration data on which the iteration logic 130 operates. After initialisation by the initialisation logic 110, the iteration register 120 may be updated with the output data of the initialisation stage — i.e., initial iteration data. In subsequent iterations, the iteration register 120 is updated based on outputs of the iteration logic 130. The outputs of the iteration logic 130 may include an updated estimate (of the quotient or root), partial remainder signals (e.g., separate remainder sum and remainder carry signals).

[0046] Note the operand (e.g., divisor) may in some cases be constant throughout iterations, and may not be updated at each iteration. However, for square root operations, this depends on the architecture design. For example, some architectures may update the operand at each iteration until the operand value stabilises. E.g., by updating for a predetermined number of iterations, or until the operand has a predetermined invariance over successive iterations. However, in some examples, a square root divisor may be constructed based only on current estimate signals stored in the iteration register.

[0047] A first multiplexor (MUX) 172 may be provided to control whether the iteration register 120 is updated based on outputs of the initialisation logic 110 or the iteration logic 130. That is, the first MUX 172 may comprise first and second inputs from the initialisation 110 and iteration logic 130 respectively. A control signal issued by the FSM and counter 160 controls which of the inputs to the first MUX 172 is selected. The iteration register 120 is updated with data at the selected input to the first MUX 172.

[0048] The counter 160 may comprise a register which decrements at each iteration until all iterations are complete. For example, the counter may be initialised with a number of required iterations, and then may count down by 1 each iteration. The number of required iterations may be calculated as the floating-point mantissa bit width divided by log2(radix). In other examples, the counter may be initialised with the number of quotient bits required, and count down each iteration by log2(radix).

[0049] The iteration logic 130 operates on iteration data of the iteration register 120 and implements an SRT algorithm to calculate a quotient and remainder of a division operation, or a square root of an input operand. At each iteration, the digit selection component 132 determines which digit in an SRT digit set should be selected as the quotient digit (partial quotient) for the iteration, based on remainder signals, a current estimate, and an operand signal in the iteration register 120.

[0050] Some data in the iteration register 120 may not be subject to operations of the iteration logic 130. For example, exponents previously associated with the normalised operand and remainder are not considered at the iteration stage, and may remain unchanged.

[0051] The results register 140 holds final iteration data ready for the results stage. A second MUX 174 may be provided to control whether the results register 140 is updated based on outputs of the initialisation logic 110 or the iteration logic 130. That is, the second M UX 174 may comprise first and second inputs from the initialisation 110 and iteration logic 130 respectively. A control signal issued by the FSM and counter 160 controls which of the inputs to the first MUX 172 is selected. The results register 140 is updated with data at the selected input to the second MUX 174. In the case that the MUX input connected to the iteration logic 130 is selected, the results register 140 may be updated with final iteration data, ready for processing by the results logic. In the case that the MUX input connected to the initialisation logic 110 is selected, the results register 140 may be updated with data result data produced at the initialisation stage. For example, error detection processes at the initialisation stage may provide a result to the results register 130, bypassing the iteration stage.

[0052] The results logic 150 operates on data in the results register 140, such as final iteration data from the iteration stage. The results logic 150 is configured to perform operations such as denormalisation, corrections, and rounding etc. For example, former exponents of the normalised remainder and operand signals may be considered and applied to the final estimate to generate an output at the correct order of magnitude. In integer division operations, an output of the results logic 150 may comprise a quotient and a remainder. Outputs at the results stage account also for sign information in signed operations. In floating-point division and square root operations, a single output value may be output, representing an estimate quotient or root to a predefined degree of uncertainty.

[0053] Iteration Stage

[0054] For further context as to how the present digit selection component may be implemented to perform SRT division and root operations, reference is made to Figure 2. Figure 2 illustrates exemplary iteration logic 130 configured in radix 2, with redundant digit set {-1, 0,1}. It will be understood that the structure of iteration logic 130 may differ at higher radix. Figure 2 provides an example of how iteration data in the iteration register is updated at each iteration to move closer to a final estimate. Updated estimates and remainders are stored in the iteration register after each iteration, and these updated values for the basis of the next iteration. Figure 2 further illustrates how outputs of the present digit selection component 132 may be used in the process of calculating the updated estimates and remainders.

[0055] Logic in the digit selection component 132 is discussed in more detail later with reference to Figures 3 and 4. However, for the purpose of illustrating the SRT iteration stage, it will be understood that the SRT digit selection component of Figure 2 outputs a digit selection signal 134, indicating which of the plurality of digits in the SRT digit set is to be selected at the current iteration. The digit selection signal 134 may comprise a onehot signal, wherein the active (1) bit in the onehot signal indicates a selected SRT digit in the set.

[0056] Inputs to the iteration logic 130 of Figure 2 comprise a current estimate (est) 21a, a decremented estimate (est_dec) 23a, a remainder signal (rem) 25a, and an operand signal 27. The est_dec signal 23a is equal to the est signal minus 1 (est_dec = est - 1). The est_dec signal is used in some implementations of square root operations, as discussed below.

[0057] The example iteration logic 130 of Figure 2 comprises on-the-fly conversion (OTF) logic 210. The OTF logic 210 is configured to output a new estimate (new_est) 21b and a new decremented estimate (new_est_dec) 23b at each iteration. The new estimates are calculated by combining a selected SRT digit (indicated by signal 134) with the est signal 21a and / or est_dec signal 23a. Note that new_est_dec = new_est - 1.

[0058] Though not shown in Figure 2, the OTF logic may comprise logic for performing alignment operations, masking operations, MLIXing, and one-hot to binary conversion. For example, square root estimates are left-aligned. In division operations, left-or right-aligned estimates may be used. In division operations, right-aligned estimates may be easier to operate on, as the current estimates est and est_dec can be concatenated with the new quotient digit indicated by digit selection signal 134.

[0059] At each iteration, the digit selection component 132 operates on the current remainder signal 25a held in the iteration register, and on the operand 27. In practice, the remainder 25a may be stored in redundant form as two separate signals, rem_sum and rem_carry. The aim of SRT division is to subtract a multiple of the operand from the remainder at each iteration, where the multiple is determined by the selected SRT digit. However, when calculating rem - q^D (for SRT digit qL and operand D), there is no need to propagate carries in the new remainder and add latency as a consequence. Instead, the calculated sum and carry signals may be stored separately in redundant form to allow for lower latency and higher achievable radix. In hardware terms, keeping the remainder 25a in redundant rem_sum and rem_carry form allows carry propagate adders (CPAs) to be replaced with lower latency CSA circuitry.

[0060] In division operations, operand 27 is the divisor. However, square root operations have no specified divisor. In square root operations, a different operand referred to as the square root divisor (sqrt_divisor) is formed. Processes for forming a sqrt_divisor are described in more detail below.

[0061] The digit selection component 132 may not require all bits of the rem_sum, rem_carry, and operand (or sqrt_divisor) signals. Instead, only a given number of most significant bits (MSBs) may be required to achieve suitable digit selection accuracy. As explained below, an SRT digit is selected based on a relative size of the remainder 25a and the operand 27 (both of which are normalised). In place of a LUT, the present digit selection component 132 calculates bounds for each digit in the set. Enough MSBs of the remainder and operand are required to accurately categorise the relative size of the remainder and divisor, in view of the bounds calculated by the selection component 132.

[0062] The number of MSBs required to accurately categorise this relative size depends on the radix of the system, and on the redundancy of the digit set. By way of example, systems operating in radices 2, 4, 8, and 16 may respectively require 4, 8, 12, and 16 MSBs of precision to correctly reduce the remainder at each iteration.

[0063] Reference numeral 206 denotes logic configured to multiply the operand D by each SRT digit qt in the set. In Figure 2, the radix-2 digit set {-1, 0, +1} is used, and a separate channel calculates each of -D, 0, and D for respective values of qt in the set. Of course, the channels calculating D and 0 require no logical calculation, since D is the input and 0 is represented by a bit string of all zeros. -D can be represented by the two’s complement of D, by bit flipping D and adding 1. This can be done logically with low latency using a bit inverter (NOT gate) and incrementor circuitry, for example.

[0064] In higher radix implementations, there may be more than one choice of digit set available. For example, radix-4 may use maximally redundant set {-3, -2, -1,0, 1,2, 3}, or minimally redundant set {-2, -1,0, 1,2}. Since binary multiplications by factors other than powers of 2 require complex multiplication circuitry and bring higher latency, SRT implementations may opt to use digit sets comprising only powers of 2. Therefore, in radix-4 the minimally redundant set may be used. By contrast, however, radix-8 and above requires digits that are not integer powers of two, which require calculation of a hard multiple in binary calculations. At radix-8 and above this trade-off can be made to give better overall performance with more area. Other known techniques may be employed to avoid or minimise the increased latency of multiplying by 3.

[0065] Figure 2 shows the three respective values of qtD, qt e {-1,0,1} input to a multiplexor 204. The multiplexor 204 is controlled by the digit selection output 134 of the selection component 132 such that the correct input signal is output from the multiplexor as signal 208. That is, digit selection output 134 indicates a selected value of qh and the multiplexor 204 uses the selection output 134 to control which input signal to allow through as the output 208.

[0066] Note that since later operations require q^D to be subtracted from the remainder, the ‘correct’ signal output from the MUX 204 for selected digit qt may be configured as the input corresponding to -qtD. This is so that two’s complement calculations are not duplicated in logic 206, and again at the CSA 230.

[0067] Carry Save Adder (CSA) circuitry 230 calculates the new remainder 25b by subtracting q^D from the remainder 25a. Subtracting q^D may amount to adding signal 208, if the MUX 204 is configured output -q^D for selected digit qL. As above, separate rem_sum and rem_carry signals may be used. The new remainder 25b is therefore stored in redundant form, removing the need for high latency CPA circuitry.

[0068] As noted above, the iteration logic 130 can perform division and square root operations. The implementation differences between division and square root operations lies in the handling of the operand. For example, in division operations the operand is constant, and represents the divisor of the division operation. At each iteration of a division operation, the operand is multiplied by the selected SRT quotient digit, and then subtracted from the remainder to produce the new remainder signal 25b (comprising new rem_sum and rem_carry signals still in redundant form).

[0069] In square root calculations, there is no specified divisor and a different operand referred to as the sqrt_divisor is formed. Formation of the square root divisor is discussed above. In some examples, an instance of root logic 220 may be implemented per digit (e.g., per channel in logic 206 of Figure 2). Technically, there are multiple ways to implement root logic 220 based on area / latency trade-offs. In some examples, the operand 27 may be the estimate 21a or decremented estimate 23a, taken directly from the iteration register. In this example, the number being extracted from the iteration register may be different in each iteration.

[0070] Alternatively, such as in Figure 2, the operand 27 may be an early root estimate stored in the iteration register after the initialisation stage. In this example, the input operand is constant over each iteration. However, a new sqrt_divisor is calculated at each iteration by root logic 220. In this case, as shown in Figure 2, a multiplexor 202 is configured to output either the operand 27 or sqrt_divisor signal, depending on whether a division or square root operation is being performed. As described above, the output of multiplexor 202 is provided as an input to the digit selection component 132. Therefore, in square root operations, an SRT digit is selected based on the sqrt_divisor.

[0071] The example of Figure 2 is separable into two primary channels: one for updating the estimates, and a second for updating the remainder. Both channels use the selected SRT digit. Estimates are updated by concatenating the selected SRT digit qt directly, e.g., using onehot-to-binary logic to decode the onehot SRT digit indication signal 134 and concatenate the estimates with the binary SRT digit. The new remainder is calculated by subtracting qjD from the current remainder.

[0072] Digit selection Component

[0073] Figure 3 illustrates an example digit selection component 300. The digit selection component 300 is configured to perform digit selection in an SRT algorithm using a given radix (x) and a given digit set Q. The selection component 300 includes logic configured to calculate bounds for each digit in the set, assess an input remainder against the calculated bounds, to select an SRT digit in the set based on the assessment of the remainder against the bounds, and to output a signal that indicates which digit is selected.

[0074] At the logic level, the digit selection component 300 comprises a first input 302 configured to receive a remainder signal 32, and a second input 304 configured to receive an operand signal 34.

[0075] The remainder signal may be kept in a redundant form, comprising separate remainder sum 32a and remainder carry 32a signals. The first input 302 may therefore comprise two input channels for respectively receiving the remainder sum 32a and remainder carry 32b signals.

[0076] The remainder sum 32a, remainder carry 32b, and operand signals 34 may represent most significant bits (MSBs) of respective remainder sum, remainder carry, and operand values held in an iteration register. That is, shortening the bit width of input signals causes a reduction in latency in the digit selection component 300. However, sufficient MSBs are required to achieve a suitable precision. Error analysis or trial and error may be used to find an optimal bit width for each input signal. In square root operations, the bit width may be increased by 1 relative to division operations. This provides the necessary increase in precision to perform square root operations.

[0077] The selection component 300 comprises instances of bound logic 310 for each non-zero candidate digit qt in redundant digit set Q. The example of Figure 3 shows a digit selection component for use in radix-4 calculations, using a digit set Q = {—2, -1,0,1,2}. As such, the selection component 300 of Figure 3 comprises four instances of bound logic 310, each corresponding to one of the non-zero digits in Q.

[0078] Each instance of bound logic 310 comprises bound calculation logic 320 and comparison logic 330. In some examples, a register 390 may also be implemented between the bound calculation logic 320 and the comparison logic. Based on input remainder and operand signals, each instance of bound logic 310 generates and outputs a comparison bit 38a, which indicates whether or not the remainder is greater than the respective bound calculated by bound logic 320.

[0079] A preset comparison bit 38b is also provided in respect of the zero-digit in set Q. This digit may be set to 1 by convention. The zero digit in the SRT digit set is only selected in comparison bits for all other SRT digits are zero. In this case, when no other SRT digit comparison digit reads T, the zero SRT digit is selected based on the present comparison bit 38b..

[0080] As discussed in more detail below, the bounds define a lower limit for relative size of the remainder and the operand for a particular digit qt e Q to be selected. This removes the need for consulting a LUT, and further removes the need for high-latency CPA logic in the digit selection component 300. Lower bounds Bt for selecting a digit qt can be suitably approximated using the following generalised formula: / 1 + 2(qt - 1)\ = ---—--- D, \ 2 / where D is the operand.

[0081] This generalised formula is applicable at any radix, but becomes stricter, i.e., closer to the true bound, at higher radix. However, the above approximation always returns a higher bound than the ‘true’ theoretical bound, so that if the condition R >Bt is true based on the approximated bound, the same is true in respect of the true bound.

[0082] Each instance of bound logic 310 comprises bound calculation logic 320. The bound calculation logic 320 calculates a lower bound Bt, which corresponds to the digit qL represented by the bound logic instance 310. The bound calculation logic may implement the equation: Bt = (1 + 2((^ -1)) * D, based on operand signal D. Note that the generalised equation gives a bound that is twice as large as the generalised formula identified above. Rather than implementing a shift or align operation to divide by 2, the comparison logic 330 may instead align the remainder signals such that they are multiplied by 2. This approach is equivalent to dividing by 2 when calculating the bounds, and simplifies the constant multiply logic to further reduce latency. The bound calculation logic 320 outputs a signal labelled oper_bnd 40 in Figure 3.

[0083] The bound calculation above requires a multiplication of the operand. However, to reduce latency this constant multiply may be transformed as a set of CSA and / or CPA adders, rather than an entire multiply logic unit. Further, in division operations the operand is constant. A register 390 may be provided to store precalculated bounds and remove the latency of the constant multiplier. Such a register 390, if placed between the bound calculation logic and comparison logic 330, may also help to reduce latency in higher radix operations. Implementing this register removes the critical path from operand MSBs to oper_bnd.

[0084] Each instance of bound logic 310 comprises comparison logic 330. The comparison logic 330 is configured to generate a comparison bit 38a based on the lower bound Bi and the remainder signal, e.g., the remainder sum signal 32a, and the remainder carry signal 32b. The comparison bit 38a is set so as to indicate whether the remainder greater than the respective bound Bi. E.g., by convention, a comparison bit of 1 may indicate the remainder is greater than the bound.

[0085] The comparison logic may comprise two channels 332, 334, respectively labelled dgt_sub and dgt_add. Logic within the respective channels is discussed in more detail later with reference to Figure 4. However, at a high level the two channels calculate respective candidate comparison bits by implementing different logic to compare the remainder to the bound. The two candidate comparison bits may then be transformed by OR logic 336 into a final comparison bit 38a. If either channel 332, 334 indicates the remainder is greater than the bound, then the final comparison bit (labelled dgt_cmp) is set.

[0086] Implementing two channels 332, 334 enables digit selection in signed SRT division operations. That is, depending on whether the remainder and / or operand are positive or negative, different logic is required to determine whether the remainder is greater than the bound. As explained further later herein, using the two channels 332, 334 ensures output comparison bits are accurate in both integer and signed division contexts.

[0087] In any case, the output of each instance of bound logic 310 includes a comparison bit 38a.

[0088] The digit selection component 300 further comprises digit select logic 340 configured to receive comparison bits 38a from the respective bound logic instances 310, and the preset comparison bit 38b from the zero-digit bound logic. Based on the comparison bits, the digit select logic generates a digit selection signal indicating selection of a digit q* e Q. The selected quotient digit is the digit associated with a highest lower bound Bi for which R> B^ That is, the remainder R may be found to be greater than more than one of the bounds. The digit associated with the largest bound Bt for which R >Bt is selected.

[0089] In some examples, upper bounds may be calculated rather than lower bounds, and the digit selection component generates the digit selection signal based on the upper bounds. In such examples, the selected quotient digit is the digit associated with a lowest upper bound Bt for which R <B^ That is, the remainder R may be found to be lower than more than one of the bounds. The digit associated with the lowest bound Bt for which R <Bi is selected.

[0090] Since larger SRT digits are always associated with larger bounds, the correct quotient digit may be identified by ordering the input comparison bits based on the SRT digits they correspond to, and subsequently calculating a onehot bit string based on logic: dgt_cmp[i] &&! dgt_cmp[i + 1]

[0091] '&&’ represents a Boolean AND logic gate. According to the equation above, the onehot bit string contains a 1 in a bit place with index i, if the comparison bit with index i + 1 is NOT set to 1. This technique is outlined by way of example. Other techniques for generating a digit selection signal may be used.

[0092] The selection component 300 further comprises a component output 306, configured to output the digit selection signal indicating which digit is selected (e.g., signal 134 of Figure 2). As above, this signal may be a onehot bit string with a bit width equal to the number of SRT digits in the set Q. Each place value in the onehot bit string may correspond to a particular digit The output signal may indicate selection of a particular digit by having a T at a particular place value.

[0093] Figure 3 also shows an operand negation pipeline 360, configured to optionally negate (i.e., invert) the operand before the operand digit selection mux. If the remainder and operand have the same sign then the operand is negated (resulting in a subtraction: R - qD). Otherwise, if the remainder and operand have different signs, then the operand is not negated (resulting in a addition: R + qD). In all cases, |R| - \qtD\ should hold, such that the remainder tends towards 0 over multiple iterations. However, given the redundant nature of the digit set, SRT algorithms may overshoot at some iterations and still arrive at a correct answer.

[0094] Figure 4 is a high-level block diagram illustrating an example instance of comparison logic 330. In the example of Figure 4, the comparison logic 330 comprises a dgt_sub channel 332 and a dgt_add channel 334. Each channel 332, 334 receives as input a remainder sum signal 32a, remainder carry signal 32b, and a bound signal 40. As noted with reference to Figure 3, the bound signal 40 (oper_bnd) is output by the bound calculation logic 320, and is either received at the comparison logic 330 directly from the bound calculation logic 320, or from a register 390 positioned between the bound calculation logic 320 and comparison logic 330. A sign bit of the operand is also be received as input to a Boolean XOR gate 460 in each channel 332, 334. Each channel 332, 334 calculates a respective candidate comparison bit, which are then compared via OR logic 336 to generate a comparison bit 38a for the instance of comparison logic 330.

[0095] The mathematical reasoning behind the logic in the dgt_sub 332 and dgt_add 334 channels is discussed later herein. The description of Figure 4 provides an example logical pipeline for calculating comparison bits in each instance of comparison logic 310.

[0096] The dgt_sub channel 332 is considered first. In the dgt_sub channel 332, the bound 40 is subtracted from the remainder as part of the calculation of the candidate comparison bit.

[0097] Received at the dgt_sub channel 332 is the rem_sum signal 32a, the rem_carry signal 32b, and the bound signal 40. The input rem_sum 32a and rem carry 32b signals are shifted left by one bit by align logic 410a, 410b. In binary operations, this amounts to a multiplication by 2. The use of alignment, rather than shifting circuitry, means no latency cost comes with the aligns. The multiplication by 2 in respect of the remainder signals offsets a division by 2 which is not performed in the bound calculation logic. As discussed above, the bound signal 40 may be calculated as (1 + 2- 1)) * D, whilst the general formula is1—y—-1 * D.

[0098] To subtract the bound from the remainder, the aligned remainder signals are added to the two’s complement of the bound signal 40. The two’s complement of the bound signal is calculated by applying bitwise NOT logic 420 to the bound signal 40, generating a bit-flipped version of the bound. An incrementation 422 of +1 is applied to complete the two’s complement transformation. The incrementation 422 is inserted in the least significant bit of the CSA, which has no area or latency cost.

[0099] The CSA is then configured to perform carry save addition on the aligned remainder signals and the two’s complement of the bound signal. The CSA 430 effectively calculates rem_sum + rem_carry — oper_bnd.

[0100] CSA logic 430 provides two binary string outputs. A first output (e.g., output A) comprises a sum of the input digits at each bit position, with no propagation of carries. A second string output (e.g., output B) provides a string of carries from the previous sums at each bit position.

[0101] Carry propagate logic 440 operates on the outputs (A and B) of the CSA 430. Typically, a final value for rem_sum + rem_carry — oper_bnd would be calculated by evaluating A+B using a carry propagate adder (CPA) with high latency. However, it is possible to determine whether the remainder is greater than the bound (i.e., whether rem_sum + rem_carry — oper_bnd is positive or negative) using only the most significant bit (i.e., the sign bit) of what would be the CPA output. Since only the most significant bit is required, the carry propagate logic 440 can be implemented with latency equivalent to a comparator, rather than a full carry propagate adder.

[0102] In the dgt_sub channel 332, an output bit of the CPL 440 is bit flipped via a Boolean NOT gate 450. A Boolean XOR 460 is then applied between the output of the NOT gate 450 and a sign bit of the operand. That is, the most significant bit of the operand may also be provided as an input to the dgt_sub channel 332. XOR with the operand sign applies a correction for when the divisor is negative, allowing for the remainder and divisor to be signed (enabling signed division). Output from the XOR 460 is a first candidate comparison bit (dgt_cmp_cand1). The mathematical context for these operations is outlined below.

[0103] The dgt_add channel 334 is now considered. In the dgt_add channel 334, the bound 40 is added to the remainder as part of the calculation of the respective candidate comparison bit (dgt_cmp_cand2).

[0104] Received at the dgt_add channel 334 is the rem_sum signal 32a, the rem_carry signal 32b, and the bound signal 40. As in the dgt_sub channel 332, the input rem_sum 32a and rem carry 32b signals are shifted left by one bit by align logic 410a, 410b.

[0105] To add the bound signal 40 to the remainder, the aligned remainder signals are input to the CSA, which performs carry save addition on the aligned remainder signals and the bound signal 40. A small bias 424 of +1 may also added to the least significant bit in the CSA. This bias term 242 stabilises the bound calculation when the remainder is negative and the operand is positive. The bias term 424 is added at the least significant bit and has no latency or area cost. The CSA 430 calculates rem_sum + rem_carry + oper_bnd, producing two binary string outputs. A first output (e.g., output C) comprises a sum of the input digits at each bit position, with no propagation of carries. A second string output (e.g., output D) provides a string of carries from the earlier sums.

[0106] Carry propagate logic 440 operates on the outputs (C and D) of the CSA 430. Using a CPA, the final value for rem_sum + rem_carry + oper_bnd would be calculated by evaluating C+D and propagating the carries. However, like in the dgt_sub channel 332, it is possible to determine whether the remainder is greater than the bound (i.e., whether rem_sum + rem_carry + oper_bnd is negative or positive) using only the most significant bit (i.e., the sign bit) of what would be the CPA output. Since only the most significant bit is required, the carry propagate logic 440 can be implemented with latency equivalent to a comparator, rather than a full carry propagate adder.

[0107] In the dgt_add channel 332, a Boolean XOR 460 is applied between the output of the CPL 440 and a sign bit of the operand. This applies a correction in the case that the operand is negative, allowing for the remainder and divisor to be signed (enabling signed division). Like the dgt_sub channel 332, the most significant bit of the operand may also be provided as an input to the dgt_add channel 334. Output from the XOR 460 is the second candidate comparison bit (dgt_cmp_cand2).

[0108] For cases where the remainder and operand have the same sign, the output (dgt_cmp_cand1) of the dgt_sub channel 332 determines the value of the comparison bit (dgt_cmp) 38a. That is, when remainder and operand signs are the same, dgt_add 334 will always give dgt_cmp_cand2 = 0, but dgt_sub 332 may give dgt_cmp_cand1 as either 1 or 0. In the case that the remainder and operand have different signs, the output of the dgt_add channel 334 determines the value of the comparison bit (dgt_cmp) 38a. That is, when remainder and operand signs are different, dgt_sub 332 will always give dgt_cmp_candl = 0, but dgt_sub 332 may give dgt_cmp_cand2 as either 1 or 0.

[0109]       Mathematical considerations

[0110] The following description outlines the mathematical considerations underpinning logic in the examples of Figures 3 and 4.

[0111] Lower bounds for selection of an SRT digit qt based on operand D can be calculated using the generalised formula:

[0112] The divisor_bound defines a lower bound for the size of the remainder. When the remainder is greater than the bound, a comparison bit dgt_cmp[i] may be set to 1 using comparison logic: dgt_cmp[j] = rem >oper_bnd[j], where rem is the remainder.

[0113] However, directly implementing the functions above in logic causes too much latency in the critical path. Several manipulations to the inputs and to the functions can be made to enable lower latency hardware implementation.

[0114] For instance, the width of the SRT logic may be controlled to improve latency in the digit selection component. That is, only a set number of MSBs of the remainder and operand signals may be considered. Further, in the wider system implementing the iterative SRT algorithm, the remainder signal may be kept in a redundant form as separate rem_sum and rem_carry signals. This removes the need for carry propagate adders to fully evaluate the remainder at each iteration.

[0115] In the digit selection component, MSBs of the respective remainder sum and remainder carry signals rem_sum and rem_carry may be used: rem_sum_top = rem_sum[BW — 1: BW — T0P_BW] rem_carry_top = rem_carry[BW — 1: BW — TOP_BW], where TOP_BW is a parameter controlling the bit width of the SRT logic — i.e., how many MSBs are used.

[0116] The notation above in square brackets indicates a bit slice. For instance, [BW - 1: BW - T0P_BW] means that bits are taken from rem_sum from bit position (index) BW - T0P_BW, up to and including index BW - 1.

[0117] Note that the overall remainder MSBs would be given by: rem_top = rem_sum_top + rem_carry_top

[0118] Comparison bits (dgt_cmp[i]) indicating whether the condition rem >oper_bnd[j] is satisfied for digit qt can therefore be calculated as: dgt_cmp[i] = (rem_sum_top + rem_carry_top) >oper_bnd[i]

[0119] The comparison bit may therefore be evaluated (in unsigned operations) by subtracting oper_bnd[i] from the combined remainder signals rem_sum_top + rem_carry_top.

[0120] Further changes may be made to extend the functionality of the digit select component to signed division operations. For instance, the calculation of dgt_cmp[j] can be separated into different calculation channels (e.g., dgt_sub 332 and dgt_add 334) to account for differences in sign between the remainder and operand.

[0121] In one channel (see dgt_sub 332), the bound is subtracted from the remainder. In a second channel (see dgt_add 334), the bound is added to the remainder: rem_sum_top + rem_carry_top — oper_bnd[j] rem,...,, + remrarr„ + operhnrir,i + 1 sumtop carrytop ona[ij

[0122] The above equations represent outputs of the CPL 440 blocks in the dgt_sub 332 and dgt_add 334 channels respectively.

[0123] As noted above, latency improvements may be realised in the digit selection component by simplifying the bound calculation logic. This may be done by removing the factor of | from the general equation, and offsetting this factor by multiplying the remainder signals by 2.

[0124] Figure 3 illustrates an example where oper_bnd[i] is calculated as oper_bnd[j] = (1 + 2(q; — 1)) * D_top, and where the CSAs 430 and CPL 440 in dgt_sub 332 and dgt_add 334 respectively extract a most significant bit of: sum_sub[TOP_BW] = (rem_sum_top « 1) + (rem_carry_top « 1) — oper_bnd[j] sumadd[TOpBw] = (remsumtop « 1) + (remcarrytop « 1) + operbndW + 1

[0125] The sum_sub[TOP_BW] and sum_add[TOP_BW] parameters represent outputs of the CPL 440 in the dgt_sub and dgt_add channels 332, 334 respectively.

[0126] As discussed above, to correctly generate a digit select for all combinations of positive / negative remainder / operand, a NOT gate 450 (!) is applied in the dgt_sub channel 332, and both channels 332, 334 apply an XOR (A) 460 with the operand sign bit (oper_sign). Each channel ultimately outputs a respective candidate comparison bit (dgt_cmp_cand1, dgt_scmp_cand2). The comparison logic 330 of Figure 3 then outputs a final comparison bit (dgt_cmp[i]) according to the following equation: dgt_cmp[i] = (dgt_cmp_candl)||(dgt_cmp_cand2) = (! sum_sub[T0P_BW] A oper_sign)||(sum_add[TOP_BW] A oper_sign), where ‘||’ represents a Boolean OR (336) between the candidate comparison bits of each channel.

[0127] As discussed previously, the present digit selection component provides advantages in latency over known digit selection techniques, as the need to consult a LUT at each iteration is removed. Furthermore, known implementations of digit selection components configured to support a particular radix. The present techniques advantageously extend to any radix, providing further functional benefits compared to known systems.

[0128] Figure 5 shows a computer system in which processing systems described herein may be implemented. The computer system comprises a CPU 502, a GPU 504, a memory 506, a neural network accelerator (NNA) 508 and other devices 514, such as a display 516, speakers 518 and a camera 522. A processing block 510 (corresponding to processing block 100) is implemented on the CPU 502. In other examples, one or more of the depicted components may be omitted from the system, and / or the processing block 510 may be implemented on the GPU 504 or within the NNA 508. The components of the computer system can communicate with each other via a communications bus 520. A store 512 is implemented as part of the memory 506.

[0129] The digit selection component of Figures 3 and 4 are shown as comprising a number of functional blocks. This is schematic only and is not intended to define a strict division between different logic elements of such entities. Each functional block may be provided in any suitable manner. It is to be understood that intermediate values described herein as being formed by a digits selection component need not be physically generated by the digit selection component at any point and may merely represent logical values which conveniently describe the processing performed by the digit selection component between its input and output.

[0130] The digit selection components described herein may be embodied in hardware on an integrated circuit. The digit selection component described herein may be configured to perform any of the methods described herein. Generally, any of the functions, methods, techniques or components described above can be implemented in software, firmware, hardware (e.g., fixed logic circuitry), or any combination thereof. The terms “module,” “functionality,” “component”, “element”, “unit”, “block” and “logic” may be used herein to generally represent software, firmware, hardware, or any combination thereof. In the case of a software implementation, the module, functionality, component, element, unit, block or logic represents program code that performs the specified tasks when executed on a processor. The algorithms and methods described herein could be performed by one or more processors executing code that causes the processor(s) to perform the algorithms / methods. Examples of a computer-readable storage medium include a randomaccess memory (RAM), read-only memory (ROM), an optical disc, flash memory, hard disk memory, and other memory devices that may use magnetic, optical, and other techniques to store instructions or other data and that can be accessed by a machine.

[0131] The terms computer program code and computer readable instructions as used herein refer to any kind of executable code for processors, including code expressed in a machine language, an interpreted language or a scripting language. Executable code includes binary code, machine code, bytecode, code defining an integrated circuit (such as a hardware description language or netlist), and code expressed in a programming language code such as C, Java or OpenCL. Executable code may be, for example, any kind of software, firmware, script, module or library which, when suitably executed, processed, interpreted, compiled, executed at a virtual machine or other software environment, cause a processor of the computer system at which the executable code is supported to perform the tasks specified by the code.

[0132] A processor, computer, or computer system may be any kind of device, machine or dedicated circuit, or collection or portion thereof, with processing capability such that it can execute instructions. A processor may be or comprise any kind of general purpose or dedicated processor, such as a CPU, GPU, NNA, System-on-chip, state machine, media processor, an application-specific integrated circuit (ASIC), a programmable logic array, a field-programmable gate array (FPGA), or the like. A computer or computer system may comprise one or more processors.

[0133] It is also intended to encompass software which defines a configuration of hardware as described herein, such as HDL (hardware description language) software, as is used for designing integrated circuits, or for configuring programmable chips, to carry out desired functions. That is, there may be provided a computer readable storage medium having encoded thereon computer readable program code in the form of an integrated circuit definition dataset that when processed (i.e. run) in an integrated circuit manufacturing system configures the system to manufacture a digit selection component configured to perform any of the methods described herein, or to manufacture a digit selection component comprising any apparatus described herein. An integrated circuit definition dataset may be, for example, an integrated circuit description.

[0134] Therefore, there may be provided a method of manufacturing, at an integrated circuit manufacturing system, a digit selection component as described herein. Furthermore, there may be provided an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, causes the method of manufacturing a digit selection component to be performed.

[0135] An integrated circuit definition dataset may be in the form of computer code, for example as a netlist, code for configuring a programmable chip, as a hardware description language defining hardware suitable for manufacture in an integrated circuit at any level, including as register transfer level (RTL) code, as high-level circuit representations such as Verilog or VHDL, and as low-level circuit representations such as OASIS (RTM) and GDSII. Higher level representations which logically define hardware suitable for manufacture in an integrated circuit (such as RTL) may be processed at a computer system configured for generating a manufacturing definition of an integrated circuit in the context of a software environment comprising definitions of circuit elements and rules for combining those elements in order to generate the manufacturing definition of an integrated circuit so defined by the representation. As is typically the case with software executing at a computer system so as to define a machine, one or more intermediate user steps (e.g. providing commands, variables etc.) may be required in order for a computer system configured for generating a manufacturing definition of an integrated circuit to execute code defining an integrated circuit so as to generate the manufacturing definition of that integrated circuit.

[0136] An example of processing an integrated circuit definition dataset at an integrated circuit manufacturing system so as to configure the system to manufacture a digit selection component will now be described with respect to Figure 6.

[0137] Figure 6 shows an example of an integrated circuit (IC) manufacturing system 602 which is configured to manufacture a digit selection component as described in any of the examples herein. In particular, the IC manufacturing system 602 comprises a layout processing system 604 and an integrated circuit generation system 606. The IC manufacturing system 602 is configured to receive an IC definition dataset (e.g. defining a digit selection component as described in any of the examples herein), process the IC definition dataset, and generate an IC according to the IC definition dataset (e.g. which embodies a digit selection component as described in any of the examples herein). The processing of the IC definition dataset configures the IC manufacturing system 602 to manufacture an integrated circuit embodying a digit selection component as described in any of the examples herein.

[0138] The layout processing system 604 is configured to receive and process the IC definition dataset to determine a circuit layout. Methods of determining a circuit layout from an IC definition dataset are known in the art, and for example may involve synthesising RTL code to determine a gate level representation of a circuit to be generated, e.g. in terms of logical components (e.g. NAND, NOR, AND, OR, MUX and FLIP-FLOP components). A circuit layout can be determined from the gate level representation of the circuit by determining positional information for the logical components. This may be done automatically or with user involvement in order to optimise the circuit layout. When the layout processing system 604 has determined the circuit layout it may output a circuit layout definition to the IC generation system 606. A circuit layout definition may be, for example, a circuit layout description.

[0139] The IC generation system 606 generates an IC according to the circuit layout definition, as is known in the art. For example, the IC generation system 606 may implement a semiconductor device fabrication process to generate the IC, which may involve a multiple-step sequence of photo lithographic and chemical processing steps during which electronic circuits are gradually created on a wafer made of semiconducting material. The circuit layout definition may be in the form of a mask which can be used in a lithographic process for generating an IC according to the circuit definition. Alternatively, the circuit layout definition provided to the IC generation system 606 may be in the form of computer-readable code which the IC generation system 606 can use to form a suitable mask for use in generating an IC.

[0140] The different processes performed by the IC manufacturing system 602 may be implemented all in one location, e.g. by one party. Alternatively, the IC manufacturing system 602 may be a distributed system such that some of the processes may be performed at different locations, and may be performed by different parties. For example, some of the stages of: (i) synthesising RTL code representing the IC definition dataset to form a gate level representation of a circuit to be generated, (ii) generating a circuit layout based on the gate level representation, (iii) forming a mask in accordance with the circuit layout, and (iv) fabricating an integrated circuit using the mask, may be performed in different locations and / or by different parties.

[0141] In other examples, processing of the integrated circuit definition dataset at an integrated circuit manufacturing system may configure the system to manufacture a digit selection component without the IC definition dataset being processed so as to determine a circuit layout. For instance, an integrated circuit definition dataset may define the configuration of a reconfigurable processor, such as an FPGA, and the processing of that dataset may configure an IC manufacturing system to generate a reconfigurable processor having that defined configuration (e.g. by loading configuration data to the FPGA).

[0142] In some embodiments, an integrated circuit manufacturing definition dataset, when processed in an integrated circuit manufacturing system, may cause an integrated circuit manufacturing system to generate a device as described herein. For example, the configuration of an integrated circuit manufacturing system in the manner described above with respect to Figure 6 by an integrated circuit manufacturing definition dataset may cause a device as described herein to be manufactured.

[0143] In some examples, an integrated circuit definition dataset could include software which runs on hardware defined at the dataset or in combination with hardware defined at the dataset. In the example shown in Figure 6, the IC generation system may further be configured by an integrated circuit definition dataset to, on manufacturing an integrated circuit, load firmware onto that integrated circuit in accordance with program code defined at the integrated circuit definition dataset or otherwise provide program code with the integrated circuit for use with the integrated circuit.

[0144] The implementation of concepts set forth in this application in devices, apparatus, modules, and / or systems (as well as in methods implemented herein) may give rise to performance improvements when compared with known implementations. The performance improvements may include one or more of increased computational performance, reduced latency, increased throughput, and / or reduced power consumption. During manufacture of such devices, apparatus, modules, and systems (e.g. in integrated circuits) performance improvements can be traded-off against the physical implementation, thereby improving the method of manufacture. For example, a performance improvement may be traded against layout area, thereby matching the performance of a known implementation but using less silicon. This may be done, for example, by reusing functional 5 blocks in a serialised fashion or sharing functional blocks between elements of the devices, apparatus, modules and / or systems. Conversely, concepts set forth in this application that give rise to improvements in the physical implementation of the devices, apparatus, modules, and systems (such as reduced silicon area) may be traded for improved performance. This may be done, for example, by manufacturing multiple instances of a 10 module within a predefined area budget.

[0145] The applicant hereby discloses in isolation each individual feature described herein and any combination of two or more such features, to the extent that such features or combinations are capable of being carried out based on the present specification as a whole in the light of the common general knowledge of a person skilled in the art, 15 irrespective of whether such features or combinations of features solve any problems disclosed herein. In view of the foregoing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the invention.

Claims

1. A digit selection component for a processing system, wherein the digit selection component is configured to implement digit selection in an SRT algorithm, wherein the SRT algorithm operates in radix x using a redundant digit set Q, the digit selection component comprising:a first input configured to receive a remainder signal representing a remainder R and a second input configured to receive an operand signal representing an operand D,for each non-zero candidate digit qt in digit set Q, a respective instance of bound logic, wherein each instance of bound logic comprises:bound calculation logic configured to calculate a bound as a function of the digit qt and the operand D\comparison logic configured to generate a comparison bit based on the bound Bt and the remainder signal, wherein the comparison bit indicates a relative size of the remainder R and the boundzero-digit bound logic configured to output a preset comparison bit, the zero-digit logic corresponding to a candidate digit q0 = 0 in the redundant digit set Q\digit selection logic configured to receive comparison bits from the respective bound logic instances and the preset comparison bit from the zero-digit bound logic, and to generate, based on the comparison bits, a digit selection signal indicating selection of a digit q* e Q\ anda selection component output configured to output the digit selection signal.

2. The digit selection component of claim 1, wherein the bound calculation logic is configured to calculate an upper bound B^ and wherein the comparison logic is configured to generate a comparison bit which indicates whether the remainder R is less than the upper bound B^3. The digit selection component of claim 1, wherein the bound calculation logic is configured to calculate a lower bound B^, and wherein the comparison logic is configured to generate a comparison bit which indicates whether the remainder R is greater than the lower bound B^.

4. The digit selection component of claim 3, wherein each instance of bound logic comprises:a first comparison channel configured to generate a first candidate comparison bit, wherein the first comparison channel comprises first CSA and comparator logic, inverter logic, and first XOR logic, and is configured to:using the first CSA and comparator logic, subtract the lower bound Bt from the remainder signal and extract a MSB of the subtraction; invert the MSB of the subtraction using the inverter logic, resulting in a first inverted MSB; receive a sign bit of the operand signal and, using the first XOR logic, calculate the first candidate comparison bit by performing an XOR operation between the first inverted MSB and the sign bit of the operand signal;a second comparison channel configured to generate a second candidate comparison bit, wherein the second comparison channel comprises second CSA and comparator logic, and second XOR logic, and is configured to:using the second CSA and comparator logic, add the lower bound to the remainder signal and extract a second MSB of the summation; receive a sign bit of the operand signal and, using the second XOR logic, calculate the second candidate comparison bit by performing an XOR operation between the MSB of the summation and the sign bit of the operand signal;Boolean OR logic configured to generate the comparison bit by performing a Boolean OR operation between the first candidate comparison bit and the second candidate comparison bit.

5. The digit selection component of claim 4, wherein the first CSA and comparator logic comprises a bitwise inverter and an incrementor, and is configured to subtract the lower bound Bt from the remainder signal by inverting the lower bound Bt using the bitwise inverter, resulting in an inverted bound, to sum the remainder signal with the inverted bound, and to increment the sum of the remainder and the inverted bound.

6. The digit selection component of any of claims 3-5, wherein the lower bound Bt is calculated as a function of the digit qt and the operand D, wherein:

7. The digit selection component of claim 6, wherein the comparison logic comprises align logic configured to perform a constant left shift of one bit on the remainder signal.

8. The digit selection component of any preceding claim, wherein the remainder signal is a redundant remainder signal comprising a remainder sum signal and a remainder carry signal, wherein the first input comprises a first remainder input for receiving a remainder sum signal, and a second remainder input for receiving a remainder carry signal.

9. The method of claim 8 when dependent on claim 4, wherein the CSA and comparator logic is configured to subtract the lower bound Bt from the remainder signal by performing carry save addition between the remainder sum signal and the remainder carry signal, and subtracting the bound B^.

10. The digit selection component of any preceding claim, wherein each instance of bound logic comprises a bound register positioned between the bound calculation logic and the comparison logic, the bound register configured to store the bound B^11. The digit selection component of any preceding claim, wherein the digit set Q is a minimally redundant digit set.

12. The digit selection component of claim 11, wherein the SRT algorithm operates in Radix-2 (x = 2), wherein the digit selection component comprises two bound logic instances respectively representing digits -1 and 1 in digit set Q = {-1,0,1,}.

13. The digit selection component of claim 11, wherein the SRT algorithm operates in Radix-4 (x = 4), wherein the digit selection component comprises four bound logic instances respectively representing digits -2, -1, 1 and 2 in digit set Q = {-2,-1,0,1,2}.

14. The digit selection component of claim 11, wherein the SRT algorithm operates in Radix-8 (x = 8), wherein the digit selection component comprises eight bound logic instances respectively representing digits -4, -3, -2, -1, 1, 2, 3 and 4 in digit set Q = {-4,-3,-2,-1,0,1,2,3,4}.

15. The digit selection component of claim 11, wherein the SRT algorithm operates in Radix-16 (x = 16), wherein the digit selection component comprises sixteen bound logic instances respectively representing digits -8, -7, -6, -5, -4, -3, -2, -1, 1, 2, 3, 4, 5, 6, 7 and 8 in digit set Q = {-8, -7, -6, -5, -4, -3, -2,-1,0,1,2, 3,4, 5, 6, 7,8}.

16. A computer implemented method of performing digit selection in an SRT algorithm, the method implemented by the digit selection component of any preceding claim and comprising:receiving a remainder signal representing a remainder R, and an operand signal representing an operand D,for each non-zero candidate digit qt in a redundant SRT digit set Q, generating a comparison bit based on the remainder signal and the operand signal;setting a preset comparison bit corresponding to a candidate digit q0 = 0 in the redundant digit set Q\generating, based on the comparison bit for each candidate digit qit and the preset zero-digit comparison bit, a digit selection signal indicating selection of a digit q* e Q\ andoutputting the digit selection signal.

17. A processing system configured to perform the method of claim 16.

18. The processing system of claim 17, wherein the processing system is embodied in hardware on an integrated circuit.

19. A method of manufacturing, using an integrated circuit manufacturing system, a processing system as claimed in any of claims 17 or 18.

20. A system configured to implement an iterative SRT algorithm, comprising:initialisation logic, iteration logic, an iteration register, results logic, a results register, and counter logic,wherein the iteration logic comprises:a digit selection component according to any of claims 1 to 15, the digit selection component configured to receive a remainder signal and an operand signal from the iteration register, and to output the digit selection signal;on-the-fly conversion logic configured to generate an updated estimate signal at each iteration based on an estimate signal from the iteration register and based on the digit selection signal;addition circuitry configured to generate an updated remainder by subtracting a multiple of the operand from the remainder signal, the multiple determined by the digit selection signal;wherein the counter logic controls the iteration register to store the updated estimate signal and updated remainder signal.

21. The system of claim 20, wherein the remainder signal is a redundant remainder signal comprising a remainder sum signal and a remainder carry signal,wherein the updated remainder signal is a redundant updated remainder signal comprising an updated remainder sum signal and an updated remainder carry signal, andwherein the counter logic controls the iteration register to store the updated remainder sum signal and updated remainder carry signal separately, in redundant form.

22. The system of claim 20 or 21, further comprising an operand negation pipeline configured to invert the operand signal before the operand signal is input to the addition circuitry when the operand signal and the remainder signal have a same bit value in respective sign bits.

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