Bitwise shift operation module

Abstract

The present disclosure relates to bitwise shift operations using left integer shift logic and right integer shift logic. An input bit string, a shift count signal and an operation selection signal ar

Description

FIELD

[0001] The present disclosure relates to the processing of vector bitwise rotations by a processing system. BACKGROUND

[0002] Bitwise shift operations are useful in a variety of computing contexts, such as in arithmetic algorithms and in cryptography. In many cases, hardware logic may be configured in a processing system to implement left and right shift operations. Left shift logic (e.g. a left bitwise shifter) and right shift logic (e.g. a right bitwise shifter) are computing components which are configured to translate bits of a string left or right by a given number of bit positions. 0s may fill the empty bit positions into which no bit in the original string moves. Left shifters effectively multiply the input bit string by a power 2 (10 in binary), where the power is given by a shift count. Similarly, right-shifters effectively multiply a bit string by a power of Vi.

[0003] Rotational shifts are a particularly useful operation in cryptography, such in applications like encryption, decryption, and key generation. In a rotational shift operation, bits in a bit sequence are shifted in a left or right direction by a number of bit places indicated by a shift count. However, unlike left and right integer shift operations, bits which are shifted beyond the end of the bit string are not lost, but are instead redirected to the opposite end of the bit string.

[0004] In some processing systems, dedicated hardware logic is configured to implement rotational shifts. Such processing systems may be designed with power consumption in mind, as the rotational shifter may comprise just one circuit and not require different parts of the output to be calculated in different logical circuits (e.g., in separate left and right shift circuitry). SUMMARY

[0005] In practice, processing systems that include a dedicated rotational shifter still need to include respective left and right integer shifting logic. This means that extending functionality of the processing system to integer and rotational shifts using dedicated rotational shift logic and separate left and right shifters comes at a cost of increased area in the processing system. Performing rotational shifts with a single dedicated circuit also requires the logic to be clock gated. Area cost in the processing system is further increased by the need for additional registers in clock gated circuitry.

[0006] Aspects of the present disclosure relate to systems and techniques that reduce the processor area required to implement integer and rotational shifts in either direction. Examples herein are configured to re-use existing left and right integer shift logic (i.e. logic already present in a processing system and used for other purposes) to implement rotational shifts. The additional logic required to extend the functionality to include rotational shifts is also optimised to minimise latency.

[0007] This summary is provided merely to illustrate some of the concepts disclosed herein and possible implementations thereof. Not everything recited in the summary section is necessarily intended to be limiting on the scope of the disclosure. Rather, the scope of the present disclosure is limited only by the claims.

[0008] According to a first aspect of the present disclosure there is provided a computer-implemented method of performing a bitwise shift operation in a processing system comprising left integer shift logic, and right integer shift logic, the method comprising: receiving an input bit string, a shift count signal indicating a number of bits by which to perform a shift operation, and an operation selection signal indicating one of a left integer shift, a right integer shift, a left rotational shift, and a right rotational shift; generating a left-shift count signal and a right-shift count signal based on the shift count signal and the operation indication signal; using the left integer shift logic, performing a left integer shift operation based on the input bit string and the left-shift count signal, resulting in a left-shifted bit string signal; using the right integer shift logic, performing a right integer shift operation based on the input bit string and the right-shift count signal, resulting in a right-shifted bit string signal; generating a left constant-shift signal by performing a constant left integer shift of 1 bit on the left-shifted bit string signal, and generating a right constant-shift signal by performing a constant right integer shift of 1 bit on the right-shifted bit string signal; generating respective candidate results for each of a left integer shift, a right integer shift, a left rotational shift, and a right rotational shift, using the generated signals; and outputting a final result signal based on the operation select signal, wherein the final result signal comprises one of the respective candidate result signals.

[0009] In some examples, generating respective candidate results comprises: generating a first candidate result comprising the left-shifted bit string signal, generating a second candidate result comprising the right-shifted bit string signal, generating a third candidate result by performing a bitwise OR between the left shift signal and the right constant-shift signal, and generating a fourth candidate result by performing a bitwise OR between the right shift signal and the left constant-shift signal.

[0010] In some examples, outputting a final result comprises receiving, at an output multiplexor of the processing system, the first, second, third, and fourth candidate result signals, and the operation indication signal

[0011] In some examples, the input bit string is a scalar bit string and the shift count signal is a scalar shift count signal. Performing the left integer shift operation may comprise shifting the input bit string by a number of bits indicated in the left-shift count signal, and performing the right integer shift operation comprises shifting the input bit string by a number of bits indicated in the right-shift count signal.

[0012] In some examples, the input bit string is a vector bit string comprising a plurality of elements, each with a common element bit width, and wherein the shift count signal is a vector signal comprising a plurality of slices, each slice indicating a number of bits by which to perform a shift operation on a corresponding element of the vector bit string; wherein generating the left-shift count signal comprises generating a respective element left-shift count signal corresponding to each element of the plurality of elements, based on the corresponding shift count slice for each element; wherein generating the right-shift count signal comprises generating a respective element right-shift count signal corresponding to each element of the plurality of elements, based on the corresponding shift count slice for each element; wherein performing the left integer shift operation comprises performing a left vector integer shift operation, wherein each element of the input bit string is shifted independently of the other elements, by a number of bits indicated by the corresponding element left-shift count; wherein performing the right integer shift operation comprises performing a right vector integer shift operation, wherein each element of the input bit string is shifted independently of the other elements, by a number of bits indicated by the corresponding element right-shift count; wherein generating the left-constant shift signal comprises applying AND logic to prevent propagation of bits between elements, and wherein generating the right-constant shift signal comprises applying AND logic to prevent propagation of bits between elements.

[0013] According to a second aspect of the present disclosure there is provided a processing system configured to perform the method according to any embodiment of the first aspect.

[0014] According to a third aspect of the present disclosure, there is provided a method of manufacturing, using an integrated circuit manufacturing system, a processing system according to the second aspect.

[0015] The shift operation module (e.g., the processing system of the second aspect) may be embodied in hardware on an integrated circuit. There may be provided a method of manufacturing, at an integrated circuit manufacturing system, a shift operation module. There may be provided an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the system to manufacture a shift operation module. There may be provided a non-transitory computer readable storage medium having stored thereon a computer readable description of a shift operation module that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying a shift operation module.

[0016] There may be provided an integrated circuit manufacturing system comprising: a non-transitory computer readable storage medium having stored thereon a computer readable description of the shift operation module; a layout processing system configured to process the computer readable description so as to generate a circuit layout description of an integrated circuit embodying the shift operation module; and an integrated circuit generation system configured to manufacture the shift operation module according to the circuit layout description. The layout processing system may be configured to determine positional information for logical components of a circuit derived from the integrated circuit description so as to generate the circuit layout description of the integrated circuit embodying the graphics processing system.

[0017] There may be provided computer program code for performing any of the methods described herein. There may be provided non-transitory computer readable storage medium having stored thereon computer readable instructions that, when executed at a computer system, cause the computer system to perform any of the methods described herein.

[0018] The above features may be combined as appropriate, as would be apparent to a skilled person, and may be combined with any of the aspects of the examples described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] To assist understanding of the present disclosure and to show how embodiments may be put into effect, reference is made by way of example to the accompanying drawings in which:

[0020] Figure 1 illustrates input and output bit strings of an example rotation operation;

[0021] Figure 2 is a flowchart representing an example method for performing integer and rotational shifts using common logic;

[0022] Figure 3a illustrates example logic for generating left_shift and right_shift signals;

[0023] Figure 3b illustrates example logic for generating a result signal based on the left_shift and right_shift signals in Figure 3a, and based on an operation selection signal;

[0024] Figure 4 illustrates an example computing device configured to implement integer and rotational shifts in accordance with examples herein;

[0025] Figure 5 shows a computer system in which a processing system is implemented; and

[0026] Figure 6 shows an integrated circuit manufacturing system for generating an integrated circuit embodying a processing system.

[0027] The accompanying drawings illustrate various examples. The skilled person will appreciate that the illustrated element boundaries (e.g., boxes, groups of boxes, or other shapes) in the drawings represent one example of the boundaries. It may be that in some examples, one element may be designed as multiple elements or that multiple elements may be designed as one element. Common reference numerals are used throughout the figures, where appropriate, to indicate similar features. DETAILED DESCRIPTION

[0028] The following description is presented by way of example to enable a person skilled in the art to make and use the invention. The present invention is not limited to the embodiments described herein and various modifications to the disclosed embodiments will be apparent to those skilled in the art.

[0029] Embodiments will now be described by way of example only.

[0030] The result of a rotational shift operation can be written as a logical combination of a left integer shift and a right integer shift. Consider a bit string a of bit width BW, being rotated by a number of bit positions given by a shift count (sft_cnt). A left rotation (rol) and right rotation (ror) by the shift count can respectively be represented as: rol(a) = a « sft_cnt | (a » (BW — sft_cnt)) ror(a) = a » sft_cnt | (a « (BW — sft_cnt)), where « and » represent left and right integer shifts respectively, and | represents a bitwise OR operation between the two terms either side.

[0031] Figure 1 illustrates how a rotational shift can be decomposed in terms of left and right shifts. Figure 1 illustrates a left rotation operation, which takes a shift count and a bit string as input.

[0032] Reference numeral 102 denotes a bit string a = 10110110. An 8-bit string is used by way of example. The techniques herein extend to bit strings of any length.

[0033] Reference numeral 110 denotes bit string a', which is equal to a after being subject to a left rotational shift of 5 bits. That is, for input bit string a and shift count sft_cnt = 5, the left rotation operation outputs bit string a’.

[0034] During the rotation operation, each bit in bit string a 102 is translated 5 places to the left. If, during this process, a bit is translated further than the left-most bit of a, that bit is sent to the right-most bit position before continuing to translate leftwards. Arrows 108 illustrate the translations of each bit from string a 102 to a' 110.

[0035] Due to the rotational nature of the operation, some bits of a 102 have a net translation to a' 110 in the left direction. This is the case for bits which are not shifted further than the left-most bit of a. These bits are subject to a left integer shift by sft_cnt bit positions.

[0036] By contrast, any bit in a which is shifted beyond the left-most bit is effectively right shifted, having a bit position in a' which is further to the right than their bit position in a. All of these bits are effectively subject to a right integer shift by the bit width BW minus the shift count.

[0037] Reference numeral 104 denotes a after being subject to an integer left shift (sll) by the shift count of 5. In the left integer shift, bits which are shifted beyond the left-most bit position are lost, and 0s fill the right-most bit each time the shift occurs. The bit string 104 therefore comprises the last 3 bits of a, and five 0s in the five right-most bit positions.

[0038] Reference numeral 106 denotes a after being subject to an integer right shift (srl) by the bitwidth of a (which is 8) minus the shift count (which is 5) (srl(BVF - sft_cnt) = srZ(3)). In the right integer shift, bits which are shifted beyond the right-most bit position are lost, and Os fill the left-most bit each time the shift occurs. The bit string 106 therefore comprises three Os, followed by the five left-most bits of a.

[0039] A bitwise OR operation between bit strings 104 and 106 gives an answer equivalent to bit string a' 110, as identified above, and as illustrated in Figure 1: [(a « sftcnt) | a » (BW — sft_cnt)] = ar = rol(a, sft_cnt)

[0040] This equation holds for any bit string a of bit width BW being left rotated by shift count sft_cnt. Similarly, for right rotations (ror): a » sft_cnt | (a « (BW — sft_cnt)) = ror(a, sft_cnt)

[0041] Whilst rotational shifts may be mathematically represented in terms of separate integer left and right shifts, implementing rotational shifts with acceptable computer performance using existing left and right integer shifting logic is a non-trivial task. For example, calculating BW - sft_cnt requires addition logic which adds considerable latency to the critical path.

[0042] The present disclosure provides techniques and methods which enable integer and rotational shifts in left or right directions to be computed using shared integer shifter logic. These systems and techniques provide a reduction in area on the processing unit by removing the need for a separate and clock gated rotational shift circuit. Further, the present examples enable this extended functionality with minimal added latency relative to systems which implement only left and right integer shifts.

[0043] As noted above, naive attempts to implement rotational shifts using existing left and right integer shift logic would incur high latency, as a calculation of bit-width minus shift count must be made. This requires high latency addition logic. However, the present disclosure outlines how the mathematics may be reformulated and generalised, extending the functionality of the processor system to integer and rotational shifts with minimal added latency.

[0044] First, it has been noted that the shifter requires only the bottom log2 BW bits of the shift count. This is because a bit string of a given bit width is invariant under rotational shifts by a shift count that is a multiple of the bit width. I.e., rotating an 8-bit string by a shift count of 8 (or any integer multiple of 8) leaves the bit string unchanged. Thus, for an 8-bit string, only log2 8 = 3 bits of the shift count are required by the shifter. Any value between 0 and 7 can be represented with 3 bits, and any shift by 8 bits or more is equivalent to a shift by 0-7 bits.

[0045] This means that a shift by BW - sft_cnt can be re-written as a shift by the two’s complement of the shift count. For instance, consider a left rotational shift of an 8-bit string, by a shift count of 5. In this example, a right shift of 3 bits is required, because BW -sft_cnt = (8 - 5) = 3. In binary, the shift count (sft_cnt) of 5 is written as 101. Recall that only 3 bits are needed because log2 8 = 3. Therefore, the two’s complement of the shift count is given by Oil (bit flip of 101, plus 1). 011 in binary is equal to 3 in decimal, giving the correct right-shift count.

[0046] Whilst no direct calculation of BW - sft_cnt need be performed based on the above, it is noted calculating the two’s complement of the shift count nevertheless requires some addition circuitry. Two’s complements are calculated by performing a bitwise NOT operation, followed by an incrementation by +1. The incrementation is an addition which incurs latency, as carries need to be propagated to calculate the final value.

[0047] However, a further insight has been made, which removes the need for incrementation. Latency in calculating BW - sft_cnt is therefore further reduced.

[0048] By the definition of two’s complement numbers, the invert of sft_cnt (i.e., NOT(sft_cnt)) is always one smaller than the two’s complement of sft_cnt (which would be given as NOT(sft_cnt) + 1). Therefore, to shift by BW - sft_cnt, it is always equivalent to perform an integer shift by the invert of sft_cnt, followed by another shift in the same direction of 1 bit.

[0049] A constant integer shift by 1 bit can be done with no latency, e.g., using align operations. The above observations therefore mean that BW - sft_cnt may be evaluated without the need for any addition circuitry.

[0050] Overall, given input bit string a and shift count sft_cnt, left (rol) and right (ror) rotation operations may be evaluated as: rol(a) = (a « sft_cnt) | ((a » ~sft_cnt ) » 1) ror(a) = (a » sft_cnt) | ((a « ~sft_cnt) « 1) , where ~ denotes the invert applied to the shift count.

[0051] In integer shift operations, the outputs are calculated as: s 11(a) = a « sft_cnt sr 1(a) = a» sft_cnt

[0052] All shift operations (left / right, integer / rotation) may therefore be calculated with low latency using integer shift logic. For the rotation operations, further steps are necessary to effectively evaluate BW - sft_cnt and determine how much to shift in the opposite direction than the rotation (e.g., the right shift count in a left rotation).

[0053] Herein, we introduce the notation left_sft_cnt and right_sft_cnt. In any operation — left or right, integer or rotation — left_sft_cnt denotes a number of bits by which the input bit string is subject to a left integer shift. Similarly, right_sft_cnt denotes a number of bits by which the input bit string is subject to a right integer shift. left_sft_cnt and right_sft_cnt are calculated based on the input shift count sft_cnt.

[0054] Note that left_sft_cnt and right_sft_cnt denote a number of bits by which the bit string is shifted by integer shifting circuitry. The constant integer shift by 1 bit is not accounted for in right_sft_cnt and left_sft_cnt.

[0055] By way of example, to evaluate a left rotation, a left integer shift of left_sft_cnt bits is performed, and a right integer shift of right_sft_cnt bits is performed. As above, the right shifted signal (denoted righ.t_sh.ift, as below) is later subject to an additional right shift of 1 bit, using align operations. In this example, according to the logic above,right_sft_cnt is equal to sft_cnt, and right_sft_cnt is equal to ~sft_cnt.

[0056] In a second example, to evaluate a right rotation, a right integer shift of right_sft_cnt bits is performed, and a left integer shift of left_sft_cnt bits is performed. As above, the left shifted signal (denoted left_shift, as below) is later subject to an additional left shift of 1 bit, using align operations. In this example, according to the logic above, right_sft_cnt is equal to sft_cnt, and right_sft_cnt is equal to ~sft_cnt.

[0057] In most situations, left_sft_cnt and right_sft_cnt are equal to sft_cnt. The exceptions are right_sft_cnt in a left rotation, and left_sft_cnt in a right rotation. Other than in these situations, left_sft_cnt and right_sft_cnt may always be set equal to sft_cnt. Of course, right_sft_count in left integer shifts is redundant, as is the left_sft_count in right integer shifts. However, values for left_sft_cnt and right_sft_cnt are consistent across all left / right integer / rotation shifts based on the permutations outlined above.

[0058] In examples below, the correct shifts are performed by calculating the value of a parameter left_sft_cnt and right_sft_cnt, based on the selected operation.

[0059] By calculating left_sft_cnt and right_sft_cnt and performing these shifts on bit string a, left-shifted and right-shifted versions of a are generated: left_shift = (a « left_sft_cnt) right_shift = (a » right_sft_cnt)

[0060] Having calculated left_shift and right_shift signals, the results for all operations simplify in form to: Operation Desired Result Left integer left_shift Right integer right_shift Left rotation left_shift | (right_shift » 1) Right rotation right_shift | (left_shift « 1)

[0061] In examples herein, candidate results for each operation (left / right, integer / rotation) are calculated based on the desired results in the table above.

[0062] Using the observations above, the underlying mathematical process for calculating the output of a rotational shift operation is reformulated such that: a. rotational shifts can be performed using existing left and right integer shift logic with no need for dedicated rotation logic; b. logic required to extend the functionality of the system to include rotational shifts adds minimal latency, relative to the latency in performing integer shifts; and c. logic required to extend the functionality of the system takes minimal processor area compared to dedicated hardware rotational shift logic.

[0063] Example systems and techniques herein operate in accordance with the observations above, and therefore provide advantages in processor area and latency.

[0064] A method of performing a shift operation according to some examples herein is now described with reference to the flowchart of Figure 2. The method represented in Figure 2 may be implemented in a processing system such as a CPU, which comprises an input, left integer shift logic, right integer shift logic, and an output multiplexor.

[0065] At a high level, the method represented by Figure 2 comprises calculating four candidate results for four candidate shift operations. I.e., a respective result for integer and rotational shifts in left and right directions. Each candidate result is provided to the output multiplexor, and the operation selection signal controls which candidate result is output as a final result.

[0066] To calculate the four candidate results, an input bit string is subject to left and right integer shift operations. Each candidate result is formed by logically combining different shifted versions of the bit string.

[0067] Figure 2 begins at a step S201, wherein inputs including a bit string a, an operation selection signal op_select, and a shift count signal sft_cnt are received. The shift count signal indicates a number of bits by which to perform the shift operation. The operation selection signal indicates a shift operation comprising one of: a left integer shift, a right integer shift, a left rotational shift, and a right rotational shift. The bit string a is the subject of the selected shift operation, and may be of any bit width, e.g., 64-bit, 32-bit, 16-bit, 8-bit etc.

[0068] At a next step 203a and 203b, left and right shift counts (left_sft_cnt, right_sft_cnt) are generated, based on the shift count signal and the operation selection signal. As noted above, left_sft_cnt = sft_cnt unless the operation is a right rotation, in which case left_sft_cnt = ~sft_cnt. Similarly, right_sft_cnt = sft_cnt unless the operation is a left rotation, in which case right_sft_cnt = ~sft_cnt. This selection may be implemented using multiplexors receiving inputs of left_sft_cnt and ~sft_cnt, and having the output controlled by the operation selection signal.

[0069] At a next step S205a, S05b, respective left- and right-shifted versions of a are calculated. Left and right integer shift logic are used to respectively calculate: left_shift = (a « left_sft_cnt) right_shift = (a » right_sft_cnt)

[0070] The input bit string is shifted by a number of bits indicated by the left-shift count signal and right-shift count signal respectively.

[0071] Step S207 represents a constant shift of the left_shift signal by 1 bit in the left direction, and a constant shift of the right_shift signal by 1 bit in the right direction: (left_shift « 1) (right_shift » 1)

[0072] This constant shift may be performed by align operations and add no latency to the critical path.

[0073] After step S207, the left_shift, right_shift, (left_shift « 1), and (right_shift » 1) signals have all been calculated, and are available for constructing different candidate results in accordance with the table above.

[0074] Candidate results are generated at a next step S209. A first candidate result is the left-shifted bit string signal. This first candidate result corresponds to the left integer shift operation: sll = (left_shift).

[0075] A second candidate result is the right-shifted bit string signal. The second candidate result corresponds to the right integer shift operation: srl = (right_shift)

[0076] A third candidate result is generated by performing a bitwise OR between the left_shift signal and the right constant-shift signal (right_shift » 1). The third candidate result corresponds to the left rotational shift operation: rol = left_shift | (right_shift » 1)

[0077] A fourth candidate result is generated by performing a bitwise OR between the right_shift signal and the left constant-shift signal (left_shift « 1). The fourth candidate result corresponds to the right rotational shift operation: ror = right_shift | (left_shift « 1)

[0078] At a final step S211, a final result signal is output based on the candidate result signals and the operation select signal. The final result signal comprises one of the first, second, third, and fourth candidate result signals. The candidate result selected as the final result is the correct result for the shift operation indicated by the operation select signal. The selection of a correct final result signal based on the operation select signal is implemented using an output multiplexor, taking the four candidate results and the operation select signal as inputs.

[0079] Reference is now made to Figures 3a and 3b, which are highly schematic logic diagrams. Figures 3a and 3b illustrate logic for calculating candidate results for left and right integer and rotation operations, and outputting a final result based on an operation selection signal. The logic of Figures 3a and 3b may be implemented in a shift operation module (e.g., shift operation module 420 of Figure 4), embodied on a processing device such as a CPU. Methods and processes described as being performed by logic illustrated in Figures 3a and 3b may therefore be considered as being performed by a shift operation module according to the examples herein.

[0080] Reference numeral 312 denotes a shift count signal (sft_cnt). The shift count signal 312 may comprise a binary signal which indicates a number of bits by which to perform an operation. As noted above, the shift count signal need only comprise the log2 BW lowest bits of the shift count. The shift count signal 312 may therefore comprise a truncated version of a larger shift count stored in a register, comprising only the necessary LSBs.

[0081] Figure 3a comprises an inverter 304 comprising NOT logic, which is configured to calculate a bitwise inversion on a bit string. The inverter 304 takes a binary input signal and flips 0s to 1s, and 1s to 0s. The shift count signal 312 is input to the inverter 304 to generate an inverted shift count signal 318 (~sft_cnt).

[0082] Figure 3a comprises a left shift MUX 320 and a right shift mux 330. The left shift MUX 320 receives the shift count 312 and inverted shift count 318 signals as input. The left and right shift MUXs are controlled by an operation selection signal 314, which indicates a selected shift operation being performed.

[0083] The left and right shift MUXs 320, 330 follow the formulae outlined above to determine left_sft_cnt 322 and right_sft_cnt 332 signals. Le.: , (ror: ~sftcnt left sft ent = ] . ... - - ( else: sf tcnt , c (rol: ~sft_cnt riant sft ent = 1 . _ (else: sft_cnt

[0084] Figure 3a shows left integer shift logic 306 and right integer shift logic 308. The left integer shift logic takes the left shift count 322 and an input bit string a (316) as input and performs a left integer shift operation of left_sft_cnt bits on the input bit string 316. Similarly, the right integer shift logic takes the right shift count 332 and input bit string a (316) as input and performs a right integer shift operation of right_sft_cnt bits on the input bit string 316.

[0085] The left integer shift logic 306 outputs a left_shift signal 342. The right integer shift logic 308 outputs a right_shift signal 344. As above, these signals are used in calculating candidate results for each type of shift operation.

[0086] With reference now to Figure 3b, the left_shift 342 and right_shift 344 signals are used to generate respective candidate results 382a-382d for each type of shift operation (sll, srl, rol, ror).

[0087] Figure 3b shows an output multiplexor 390 comprising four inputs, one for each respective candidate result 382a-d. The output multiplexor 390 further receives the operation selection signal 314 as a control input. The operation selection signal indicates which of the candidate results 382a-d is output as a result signal 392. The logic of Figure 3b calculates and combines left_shift 342, right_shift 344, (left_shift « 1) 352, and (right_shift » 1) 362 signals so as to generate candidate results 382a-d for each type of shift operation. The table presented previously is copied again below for convenience, and shows how the candidate outputs are calculated based on the above signals 342, 344, 352, 362 Operation Candidate Result Left integer left_shift Right integer right_shift Left rotation left_shift | (right_shift » 1) Right rotation right_shift | (left_shift « 1)

[0088] The left_shift signal 342 is provided as a first input 382a to the output multiplexor 390, labelled Res_1. The right_shift signal 344 is provided as a second input 382b to the output multiplexor 390, labelled Res_2.

[0089] Figure 3b shows constant left shift logic 350 and constant right shift logic 360. The constant left and right shift logic 350, 360 are configured to perform a respective left and right shifts by one bit position. In some examples, the constant shift logic 350, 360 may be implemented using align operations. That is, constant shifts may be implemented in hardware by altering the ordering of wires between successive logic components. This incurs no additional latency.

[0090] The left_shift signal 342 is input to the constant left shift logic 350 to generate a left-constant shift signal 352 (left_shift « 1). Similarly, the right_shift signal 344 is input to the constant right shift logic 360 to generate a right-constant shift signal 362 (right_shift « 1).

[0091] The (right_shift « 1) signal 362 is then combined by OR logic 370a ( | ) with the left_shift signal 342 to generate the third candidate result 382c (Res_3). Similarly, the (left_shift « 1) signal 352 is then combined by OR logic 370b ( | ) with the right_shift signal 344 to generate the fourth candidate result 382d (Res_4).

[0092] A result signal 392 equal to a selected one of the candidate results 382a-d is output by the output MUX 390. The op_select signal 314 controls which of the candidate results 382a-d is provided as the result signal 392.

[0093] The op_select signal 314 may be configured in one of four unique states, one for each type of shift operation. The output MUX 390 may be configured such that each input (candidate result) 382a-d is associated with a corresponding unique state of the op_select signal 314. When the op_select signal 314 indicates one of the unique states, the output MUX 390 lets through the input signal (candidate result) which corresponds to that unique state.

[0094] The op_select signal may be configured in different ways. For instance, the op_select signal 314 may comprise a onehot bit string, with each bit position in the signal 314 representing one of the operations, and wherein the bit position comprising a 1 indicates the selected operation. In other examples, the op_select signal may comprise a binary signal with each value 0-3 (i.e., 00, 01, 10, 11) representing a shift operation. The output MUX may interpret the binary signal to output the correct candidate result 382a-d.

[0095] Figure 3b includes a first table 32 and a second table 34. The first table 32 indicates which of the four candidate results corresponds to which combination of signals 342, 344, 352, 362. Table 34 shows which candidate result is selected, depending on the shift operation indicated by the op_select signal 314. Vector Shifts

[0096] Examples where the input bit string is operated on as a single entity may be referred to as scalar processing examples, However, the concepts outlined above may be extended to vector processing, wherein the input bit string a represents a vector comprising a plurality of elements and each element in the vector bit string is operated on (shifted) independently of the other elements in the bit string.

[0097] A vector bit string is separable into a plurality of elements, each element having a same element bit width. For example, an input bit string of 64 bits may represent a vector comprising 2 elements of 32 bits each, 4 elements of 16 bits each, 8 elements of 8 bits each, and so on.

[0098] In vector shift operations, each element Et of the bit string a may be shifted or rotated by a different number of bit positions. That is, the sft_cnt signal may be interpreted as a plurality of slices S^, each slice defining an element shift count for a corresponding element in the input bit string. The input bit string a may have a same total bit width as the input sft_cnt signal (e.g., 64 bits). However, it remains the case that only the bottom log2(e / m_W) bits of each slice in sft_cnt is required to accurately perform the shifts. Note that elm_bw defines a bit width of elements Et in the input bit string a, and and slices SL in the input sft_cnt signal.

[0099] By way of example, if the element bit width (elm_bw) is 16 bits, then the bottom 4 bits (log216 = 4) of each 16-bit slice in sft_cnt would be used to shift a corresponding 16-bit element of the input bit string.

[0100] In vector processing examples, the mechanism for selecting a shift operation may remain the same as in scalar examples, where the input bit string is processed as a single element. The same operation is performed over each element in the vector. However, in vector processing examples, shifts occur discretely within each element of the vector. That is, bits do not propagate to a next element in the direction of the shift, but are either lost as they shift beyond an element boundary (in integer shifts) or are rotated to the other end of the element when an element boundary is crossed (in rotational shifts).

[0101] To perform a vector shift, respective elm_left_sft_cnti and elm_right_sft_cnti signals are calculated for each element Et of the input bit string, based on corresponding slices St of the sft_cnt signal. Vector shift circuitry applies left and right vector integer shifts to each element Et, with no crossover of bit values between elements.

[0102] As in scalar examples, vector shift circuitry outputs a left_shift signal and a right_shift signal. In vector examples, left_shift is a concatenation of left-shifted elements (Ei « elm_left_sft_cnti), each element having been integer shifted left by respective elm_left_sft_cnt values specific to that element. Similarly, right_shift is a concatenation of right-shifted elements (Et » elm_left_sft_cnti), each element having been integer shifted right by respective elm_right_sft_cnt values specific to that element.

[0103] As described with reference to Figure 3b, left_shift and right_shift signals are manipulated by logic in various ways to construct candidate results for each operation. In vector processing examples, a minor modification is made to the constant left and constant right shift logic (e.g., 350, 360 in Figure 3b) to ensure the constant shifts to not propagate bit values between elements during the constant shift.

[0104] In vector processing examples, AND logic may be implemented at element boundaries in the constant left shift logic 350 and in the constant right shift logic 360. When an integer shift is performed on a bit string, a zero is placed in the rearmost bit position of that string (the bit position into which no bit is shifted). Because of this, bits can be prevented from moving between elements by implementing AND logic on the rearmost bits of each element (referred to as boundary bits). I.e., 0 AND 0 = 0 = 1 AND 0. Regardless of whether a 1 or zero moves across an element boundary into the next element, a zero is placed in the boundary bit in the next element, thus bits are prevented from propagating between elements.

[0105] By way of example, consider a left rotational vector shift operation of bit string a = 10111001, where a is an 8-bit vector comprising two 4-bit elements E± = 1011, and E2 = 1001. Consider also a shift count of sft_cnt = 0001 0011, comprising slices Si = 0001 and S2 = 0011. As above, slice Si applies to element Elt and slice S2 applies to element E2.

[0106] The expected result of a left vector rotation of a = 10111001, based on sft_cnt = 0001 0011 is: RoLVec(a,sft_cnt) = 0111 1100

[0107] In the output above, E1 has been left rotated by 1 bit (based on and E2 has been left rotated by 3 bits (based on S2).

[0108] The example above is now expanded. Since the operation is a left rotation, elm_left_sft_cnti for each element Et is equal to the corresponding sft_cnt slice St, and elm_right_sft_cnti for each element Et is equal to the invert of the corresponding sft_cnt slice Si. Note that element / slice bit width in this example is 4 bits, and therefore only the bottom 2 bits of each slice is required to calculate elm_left_sft_cnti and elm_right_sft_cnti.

[0109] For Elt elm_left_sft_cnt1 is therefore 01 (the bottom 2 bits of S^, and elm_right_sft_cnt1 is the invert thereof, i.e., 10.

[0110] For E2, elm_left_sft_cnt2 is 11 (the bottom 2 bits of S2), and elm_right_sft_cnt2 is the invert thereof: 00.

[0111] left_shift is then calculated as a concatenation of Ei « elm_left_sft_cnt1 = E1 « 1 and E2 « elm_left_sft_cnt2 = E2 « 11. Evaluating this gives left_shift = 0110 1000. Similarly, right_shift is calculated as a concatenation of E± » 10 and E2 » 0, giving right_shift = 0010 1001.

[0112] Left rotations are calculated as left_shift | (right_shift » 1). The calculation for right_shift» 1 includes implementation of an AND gate at the boundary of the two elements, as discussed above. Given the value of right_shift = 0010 1001, we can calculate right shift » 1 = 0001 0100. Note that AND logic is implemented on the boundary bit (bold and underlined). In the present example, a 0 moves from the left-hand to right-hand element during the constant right shift, so there is no discernible difference compared to a typical constant shift. However, if a 1 had moved into the boundary bit, that 1 would be subject to an AND with a zero, resulting in a zero.

[0113] Using left_shift = 0110 1000 and right shift » 1 = 0001 0100, the calculation of left_shift | (right_shift » 1) can be evaluated as a bitwise OR between the two bit strings above, giving 0110 1000 I 0001 0100 = 0111 1100

[0114] The bold answer above matches the expected result noted previously.

[0115] In some vector processing examples, an inverted version of the entire shift count signal may be received. The inverted shift count signal may be calculated as a bitwise NOT of the shift count, such that 1s in the shift count signal are flipped to 0s in the inverted shift count signal, and 0s in the shift count signal are flipped to 1s in the inverted shift count signal. The shift count and inverted shift count may both be received, and may be separately split into slices rather than splitting the shift count into slices and inverting each slice with multiple separate NOT gates when the invert is required.

[0116] Figure 4 shows a wider computing device 400 on which the techniques and logic described above may be implemented. The computing device 400 may comprise a processing device such as a CPU.

[0117] The computing device comprises initialisation logic 410, combined integer and rotational shift logic implemented in a shift operation module 420, and post-processing logic 430.

[0118] The initialisation logic may be configured to prepare input data for processing in the shift operation module 420. The initialisation logic 410 may be configured to receive first input data 412 comprising a bit string to be subject to a shift operation. The initialisation logic 410 may also be configured to receive second input data 414 indicating a shift count, and third input data 416 indicating a selected operation.

[0119] The input data 412, 414, 416 may be subject to initialisation operations to prepare the data in formats that the shift operation module 420 is configured to handle. For example, the first input data 412 may be in a floating point format and may comprise a sign, exponent and mantissa. Initialisation logic 410 may apply masks to remove the sign and exponent, outputting the mantissa as bit string a 316.

[0120] The second input data 414 indicating the shift count may comprise more bits than necessary, and may be truncated by initialisation logic 410 to comprise only the log2BVF least significant bits (LSBs) of the second input data 414, resulting in the sft_cnt signal 312.

[0121] The third input data 416 indicating a selected operation may be prepared by the initialisation logic 410 into a format that is interpretable by the shift operation module 420 (e.g., by the output MUX 390 and left-shift and right-shift MUXs 320, 330). The initialisation logic 410 may, for example convert the third input data 416 into a onehot signal.

[0122] Initialisation logic 410 may output the sft_cnt signal 312, op_select signal 314, and bit string 316 used by the shift system 420.

[0123] As discussed with reference to Figures 2-3b, the shift operation module 420 outputs a final result 392 based on the input bit string, shift count, and selected operation. The final result 392 may be subject to post processing logic 430, e.g., to apply formatting to the output signal 392. By way of example, a masked sign and mantissa bit, removed by the initialisation logic 410, may be re-applied in the post-processing logic 430. The post processing logic may output fourth data 432.

[0124] Figure 5 shows a computer system in which processing systems described herein may be implemented. The computer system comprises a CPU 502, a GPU 504, a memory 506, a neural network accelerator (NNA) 508 and other devices 514, such as a display 516, speakers 518 and a camera 522. A processing block 510 (corresponding to processing block 100) is implemented on the CPU 502. In other examples, one or more of the depicted components may be omitted from the system, and / or the processing block 510 may be implemented on the GPU 504 or within the NNA 508. The components of the computer system can communicate with each other via a communications bus 520. A store 512 is implemented as part of the memory 506.

[0125] The shift operation module (e.g., the logic of Figures 3a and 3b) is shown as comprising a number of functional blocks. This is schematic only and is not intended to define a strict division between different logic elements of such entities. Each functional block may be provided in any suitable manner. It is to be understood that intermediate values described herein as being formed by a shift operation module need not be physically generated by the shift operation module at any point and may merely represent logical values which conveniently describe the processing performed by the shift operation module between its input and output.

[0126] The shift operation module described herein may be embodied in hardware on an integrated circuit. The shift operation module described herein may be configured to perform any of the methods described herein. Generally, any of the functions, methods, techniques or components described above can be implemented in software, firmware, hardware (e.g., fixed logic circuitry), or any combination thereof. The terms “module,” “functionality,” “component”, “element”, “unit”, “block” and “logic” may be used herein to generally represent software, firmware, hardware, or any combination thereof. In the case of a software implementation, the module, functionality, component, element, unit, block or logic represents program code that performs the specified tasks when executed on a processor. The algorithms and methods described herein could be performed by one or more processors executing code that causes the processor(s) to perform the algorithms / methods. Examples of a computer-readable storage medium include a randomaccess memory (RAM), read-only memory (ROM), an optical disc, flash memory, hard disk memory, and other memory devices that may use magnetic, optical, and other techniques to store instructions or other data and that can be accessed by a machine.

[0127] The terms computer program code and computer readable instructions as used herein refer to any kind of executable code for processors, including code expressed in a machine language, an interpreted language or a scripting language. Executable code includes binary code, machine code, bytecode, code defining an integrated circuit (such as a hardware description language or netlist), and code expressed in a programming language code such as C, Java or OpenCL. Executable code may be, for example, any kind of software, firmware, script, module or library which, when suitably executed, processed, interpreted, compiled, executed at a virtual machine or other software environment, cause a processor of the computer system at which the executable code is supported to perform the tasks specified by the code.

[0128] A processor, computer, or computer system may be any kind of device, machine or dedicated circuit, or collection or portion thereof, with processing capability such that it can execute instructions. A processor may be or comprise any kind of general purpose or dedicated processor, such as a CPU, GPU, NNA, System-on-chip, state machine, media processor, an application-specific integrated circuit (ASIC), a programmable logic array, a field-programmable gate array (FPGA), or the like. A computer or computer system may comprise one or more processors.

[0129] It is also intended to encompass software which defines a configuration of hardware as described herein, such as HDL (hardware description language) software, as is used for designing integrated circuits, or for configuring programmable chips, to carry out desired functions. That is, there may be provided a computer readable storage medium having encoded thereon computer readable program code in the form of an integrated circuit definition dataset that when processed (i.e. run) in an integrated circuit manufacturing system configures the system to manufacture a shift operation module configured to perform any of the methods described herein, or to manufacture a shift operation module comprising any apparatus described herein. An integrated circuit definition dataset may be, for example, an integrated circuit description.

[0130] Therefore, there may be provided a method of manufacturing, at an integrated circuit manufacturing system, a shift operation module as described herein. Furthermore, there may be provided an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, causes the method of manufacturing a shift operation module to be performed.

[0131] An integrated circuit definition dataset may be in the form of computer code, for example as a netlist, code for configuring a programmable chip, as a hardware description language defining hardware suitable for manufacture in an integrated circuit at any level, including as register transfer level (RTL) code, as high-level circuit representations such as Verilog or VHDL, and as low-level circuit representations such as OASIS (RTM) and GDSII. Higher level representations which logically define hardware suitable for manufacture in an integrated circuit (such as RTL) may be processed at a computer system configured for generating a manufacturing definition of an integrated circuit in the context of a software environment comprising definitions of circuit elements and rules for combining those elements in order to generate the manufacturing definition of an integrated circuit so defined by the representation. As is typically the case with software executing at a computer system so as to define a machine, one or more intermediate user steps (e.g. providing commands, variables etc.) may be required in order for a computer system configured for generating a manufacturing definition of an integrated circuit to execute code defining an integrated circuit so as to generate the manufacturing definition of that integrated circuit.

[0132] An example of processing an integrated circuit definition dataset at an integrated circuit manufacturing system so as to configure the system to manufacture a shift operation module will now be described with respect to Figure 6.

[0133] Figure 6 shows an example of an integrated circuit (IC) manufacturing system 602 which is configured to manufacture a shift operation module as described in any of the examples herein. In particular, the IC manufacturing system 602 comprises a layout processing system 604 and an integrated circuit generation system 606. The IC manufacturing system 602 is configured to receive an IC definition dataset (e.g. defining a shift operation module as described in any of the examples herein), process the IC definition dataset, and generate an IC according to the IC definition dataset (e.g. which embodies a shift operation module as described in any of the examples herein). The processing of the IC definition dataset configures the IC manufacturing system 602 to manufacture an integrated circuit embodying a shift operation module as described in any of the examples herein.

[0134] The layout processing system 604 is configured to receive and process the IC definition dataset to determine a circuit layout. Methods of determining a circuit layout from an IC definition dataset are known in the art, and for example may involve synthesising RTL code to determine a gate level representation of a circuit to be generated, e.g. in terms of logical components (e.g. NAND, NOR, AND, OR, MUX and FLIP-FLOP components). A circuit layout can be determined from the gate level representation of the circuit by determining positional information for the logical components. This may be done automatically or with user involvement in order to optimise the circuit layout. When the layout processing system 604 has determined the circuit layout it may output a circuit layout definition to the IC generation system 606. A circuit layout definition may be, for example, a circuit layout description.

[0135] The IC generation system 606 generates an IC according to the circuit layout definition, as is known in the art. For example, the IC generation system 606 may implement a semiconductor device fabrication process to generate the IC, which may involve a multiple-step sequence of photo lithographic and chemical processing steps during which electronic circuits are gradually created on a wafer made of semiconducting material. The circuit layout definition may be in the form of a mask which can be used in a lithographic process for generating an IC according to the circuit definition. Alternatively, the circuit layout definition provided to the IC generation system 606 may be in the form of computer-readable code which the IC generation system 606 can use to form a suitable mask for use in generating an IC.

[0136] The different processes performed by the IC manufacturing system 602 may be implemented all in one location, e.g. by one party. Alternatively, the IC manufacturing system 602 may be a distributed system such that some of the processes may be performed at different locations, and may be performed by different parties. For example, some of the stages of: (i) synthesising RTL code representing the IC definition dataset to form a gate level representation of a circuit to be generated, (ii) generating a circuit layout based on the gate level representation, (iii) forming a mask in accordance with the circuit layout, and (iv) fabricating an integrated circuit using the mask, may be performed in different locations and / or by different parties.

[0137] In other examples, processing of the integrated circuit definition dataset at an integrated circuit manufacturing system may configure the system to manufacture a shift operation module without the IC definition dataset being processed so as to determine a circuit layout. For instance, an integrated circuit definition dataset may define the configuration of a reconfigurable processor, such as an FPGA, and the processing of that dataset may configure an IC manufacturing system to generate a reconfigurable processor having that defined configuration (e.g. by loading configuration data to the FPGA).

[0138] In some embodiments, an integrated circuit manufacturing definition dataset, when processed in an integrated circuit manufacturing system, may cause an integrated circuit manufacturing system to generate a device as described herein. For example, the configuration of an integrated circuit manufacturing system in the manner described above with respect to Figure 6 by an integrated circuit manufacturing definition dataset may cause a device as described herein to be manufactured.

[0139] In some examples, an integrated circuit definition dataset could include software which runs on hardware defined at the dataset or in combination with hardware defined at the dataset. In the example shown in Figure 6, the IC generation system may further be configured by an integrated circuit definition dataset to, on manufacturing an integrated circuit, load firmware onto that integrated circuit in accordance with program code defined at the integrated circuit definition dataset or otherwise provide program code with the integrated circuit for use with the integrated circuit.

[0140] The implementation of concepts set forth in this application in devices, apparatus, modules, and / or systems (as well as in methods implemented herein) may give rise to performance improvements when compared with known implementations. The performance improvements may include one or more of increased computational performance, reduced latency, increased throughput, and / or reduced power consumption. During manufacture of such devices, apparatus, modules, and systems (e.g. in integrated circuits) performance improvements can be traded-off against the physical implementation, thereby improving the method of manufacture. For example, a performance improvement may be traded against layout area, thereby matching the performance of a known implementation but using less silicon. This may be done, for example, by reusing functional blocks in a serialised fashion or sharing functional blocks between elements of the devices, apparatus, modules and / or systems. Conversely, concepts set forth in this application that give rise to improvements in the physical implementation of the devices, apparatus, modules, and systems (such as reduced silicon area) may be traded for improved performance. This may be done, for example, by manufacturing multiple instances of a module within a predefined area budget.

[0141] The applicant hereby discloses in isolation each individual feature described herein and any combination of two or more such features, to the extent that such features or combinations are capable of being carried out based on the present specification as a whole in the light of the common general knowledge of a person skilled in the art, irrespective of whether such features or combinations of features solve any problems disclosed herein. In view of the foregoing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the invention.

Claims

1. A computer-implemented method of performing a bitwise shift operation in a processing system comprising left integer shift logic, and right integer shift logic, the method comprising:receiving an input bit string, a shift count signal indicating a number of bits by which to perform a shift operation, and an operation selection signal indicating one of a left integer shift, a right integer shift, a left rotational shift, and a right rotational shift;generating a left-shift count signal and a right-shift count signal based on the shift count signal and the operation indication signal;using the left integer shift logic, performing a left integer shift operation based on the input bit string and the left-shift count signal, resulting in a left-shifted bit string signal;using the right integer shift logic, performing a right integer shift operation based on the input bit string and the right-shift count signal, resulting in a right-shifted bit string signal;generating a left constant-shift signal by performing a constant left integer shift of 1 bit on the left-shifted bit string signal, and generating a right constant-shift signal by performing a constant right integer shift of 1 bit on the right-shifted bit string signal;generating respective candidate results for each of a left integer shift, a right integer shift, a left rotational shift, and a right rotational shift, using the generated signals; andoutputting a final result signal based on the operation select signal, wherein the final result signal comprises one of the respective candidate result signals.

2. The method of claim 1, wherein generating respective candidate results comprises:generating a first candidate result comprising the left-shifted bit string signal,generating a second candidate result comprising the right-shifted bit string signal,generating a third candidate result by performing a bitwise OR between the left shift signal and the right constant-shift signal, andgenerating a fourth candidate result by performing a bitwise OR between the right shift signal and the left constant-shift signal.

3. The method of any preceding claim, wherein outputting a final result comprises receiving, at an output multiplexor of the processing system, the first, second, third, and fourth candidate result signals, and the operation indication signal.

4. The method of any preceding claim, wherein the operation select signal indicates a left integer shift, and the final result signal comprises the first candidate result.

5. The method of any preceding claim, wherein the operation select signal indicates a right integer shift, and the final result signal comprises the second candidate result.

6. The method of any preceding claim, wherein the operation select signal indicates a left rotational shift, and the final result signal comprises the third candidate result.7, The method of any preceding claim, wherein the operation select signal indicates a right rotational shift, and the final result signal comprises the fourth candidate result.

8. The method of any preceding claim, wherein the constant left integer shift of 1 bit on the left-shifted bit string signal is performed using hardware alignment circuitry, and wherein the constant right integer shift of 1 bit on the right-shifted bit string signal is performed using hardware alignment circuitry.

9. The method of any preceding claim, wherein the input bit string is a scalar bit string and the shift count signal is a scalar shift count signal, wherein performing the left integer shift operation comprises shifting the input bit string by a number of bits indicated in the left-shift count signal, and performing the right integer shift operation comprises shifting the input bit string by a number of bits indicated in the right-shift count signal.

10. The method of claim 9, wherein generating a left-shift count signal and right-shift count signal comprises:inverting the shift count signal by NOT logic, resulting in an inverted shiftcount signal;providing the inverted shift count signal and the shift count signal to a leftshift count multiplexor and, based on the operation selection signal, outputting one of the shift count signal or inverted shift count signal as the left-shift count signal; andproviding the inverted shift count signal and the shift count signal to a rightshift count multiplexor and, based on the operation selection signal, outputting the shift count signal or the inverted shift count signal as the right-shift count signal.

11. The method of claim 10, wherein the left-shift count multiplexor is configured to output the inverted shift count signal when the operation select signal indicates a right rotational shift, and to output the shift count signal if the operation select signal does not indicate a right rotational shift operation.

12. The method of claim 10 or 11, wherein the right-shift count multiplexor is configured to output the inverted shift count signal when the operation select signal indicates a left rotational shift, and to output the shift count signal if the operation select signal does not indicate a left rotational shift operation.

13. The method of any of claims 9-12, wherein the input bit string has a bit width of BW, and wherein the shift count has a bit width of log2 BW.

14. The method of claim 1, wherein the input bit string is a vector bit string comprising a plurality of elements, each with a common element bit width, and wherein the shift count signal is a vector signal comprising a plurality of slices, each slice indicating a number of bits by which to perform a shift operation on a corresponding element of the vector bit string;wherein generating the left-shift count signal comprises generating a respective element left-shift count signal corresponding to each element of the plurality of elements, based on the corresponding shift count slice for each element;wherein generating the right-shift count signal comprises generating a respective element right-shift count signal corresponding to each element of the plurality of elements, based on the corresponding shift count slice for each element;wherein performing the left integer shift operation comprises performing a left vector integer shift operation, wherein each element of the input bit string is shifted independently of the other elements, by a number of bits indicated by the corresponding element left-shift count;wherein performing the right integer shift operation comprises performing a right vector integer shift operation, wherein each element of the input bit string is shifted independently of the other elements, by a number of bits indicated by the corresponding element right-shift count;wherein generating the left-constant shift signal comprises applying AND logic to prevent propagation of bits between elements, and wherein generating the right-constant shift signal comprises applying AND logic to prevent propagation of bits between elements.

15. The method of claim 14, wherein the method further comprises receiving an inverted shift count signal equivalent to the invert of the shift count signal, and comprising a corresponding plurality of inverted slices,wherein the respective element left-shift signals and respective element right-shift signals are generated based on one of the corresponding shift count slice, and the corresponding inverted shift count slice.

16. The method of claim 15, wherein each element in the input bit string has a bit width of elm_bw, and wherein each respective element left-shift count and each respective element right-shift count is generated based on a bottom log2 elm_bw bits of a corresponding shift count slice or corresponding inverted shift count slice.

17. A processing system configured to perform the method of any preceding claim.

18. The processing system of claim 17, wherein the processing system is embodied in hardware on an integrated circuit.

19. A method of manufacturing, using an integrated circuit manufacturing system, a processing system as claimed in any of claims 17 or 18.

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