Runtime estimation of active working set size

Abstract

A data processing circuit includes estimation circuitry and combining circuitry. The estimation circuitry 208 receives message values in an interval that includes a subinterval and a prior interval an

Description

BACKGROUND

[0001] For a particular workload, the active working set size of a cache in a data processing system corresponds to the minimal cache capacity needed to avoid missing data blocks after they have been allocated. An estimation of this measure would enable a number of performance improvements such as automatic sizing of cache partitions or automatic setting of cache bypassing to prevent self-thrashing of the caches. Conventionally, estimation of the active working set size is obtained only as a worst case upper bound on the true size by progressively sizing up the cache capacity over several repeated trials until no misses are seen. This is a highly intrusive approach. Further, it is only feasible when the temporal dynamics of the workload can be ignored, since only an average value over a long term can be determined. The approach also requires the working set to fit into the overall available cache capacity and that the results are not distorted by background interfering workloads. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The accompanying drawings provide visual representations which will be used to describe various representative embodiments more fully and can be used by those skilled in the art to understand better the representative embodiments disclosed and their inherent advantages. In these drawings, like reference numerals identify corresponding or analogous elements.

[0003] FIG. 1 is a graph showing working set size (cardinality) as a function of the number of accesses.

[0004] FIG. 2 is a simplified block diagram of data processing circuit, in accordance with various representative embodiments.

[0005] FIG. 3 is a flow chart of a method of determining a statistical cardinality, in accordance with various embodiments.

[0006] FIG. 4 is a diagrammatic representation of a 58-bit hash value, in accordance with various representative embodiments.

[0007] FIG. 5 is a diagrammatic representation of memory region for storing maximum pattern match lengths.

[0008] FIG. 6 is a diagrammatic representation of a further memory region for storing maximum pattern match lengths.

[0009] FIG. 7 is a block diagram of a cardinality estimation circuit, in accordance with various representative embodiments.

[0010] FIG. 8 is a flow chart of a method of determining dual statistical cardinality counts, in accordance with various representative embodiments.

[0011] FIG. 9 is a block diagram of dual cardinality estimation circuitry, in accordance with various representative embodiments.

[0012] FIG. 10 shows a 58-bit hash value, in accordance with various representative embodiments.

[0013] FIG. 11 shows a memory organization, in accordance with various representative embodiments.

[0014] FIG. 12 is a block diagram of further dual cardinality estimation circuitry, in accordance with various representative embodiments.

[0015] FIG. 13 is a block diagram of a data processing system, in accordance with various representative embodiments.

[0016] FIG. 14 is a block diagram of a cardinality estimator circuit, in accordance with various representative embodiments.

[0017] FIG. 15 shows some example results of an experimental implementation of an active working set estimator, in accordance with various representative embodiments. DETAILED DESCRIPTION

[0018] The various apparatus and devices described herein provide mechanisms for determining an active working set size for a cache. More generally, the mechanisms may be used for estimating the number of message values occurring in both a first interval and a second interval.

[0019] While this present disclosure is susceptible of embodiment in many different forms, there is shown in the drawings and will herein be described in detail specific embodiments, with the understanding that the embodiments shown and described herein should be considered as providing examples of the principles of the present disclosure and are not intended to limit the present disclosure to the specific embodiments shown and described. In the description below, like reference numerals are used to describe the same, similar or corresponding parts in the several views of the drawings. For simplicity and clarity of illustration, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.

[0020] Various embodiments of the present disclosure provide a method and an apparatus for runtime estimation of the number of distinct message values in both a first subinterval and a subsequent second subinterval.

[0021] In some embodiments, the message values are memory addresses and the number of distinct message values in both a first subinterval and a subsequent second subinterval provide an estimation of the active working set size of a workload. The estimation is achieved without intruding upon the system on which this workload is executed.

[0022] For a particular workload, the active working set size of a cache in a data processing system corresponds to the minimal cache capacity needed to avoid missing data blocks after they have been allocated. An estimation of this measure would enable a number of performance improvements such as automatic sizing of cache partitions or automatic setting of cache bypassing to prevent self-thrashing of the caches.

[0023] In various other embodiments, a message may be a network access request from a first device of the data processing system to a second device of the data processing system. The associated message value may be an identifier of the first device, an identifier of a user of the first device, an identifier of the second device, or a value associated with the message content.

[0024] Various embodiments relate to a data processing circuit that includes estimation circuitry and combining circuitry. The estimation circuitry receives message values in an interval that includes a subinterval and a prior interval and generates a first statistical cardinality count, Ck, related to a number of distinct message values received in the interval, a second statistical cardinality count, Ck-\, related to a number of distinct message values received in the prior interval, and a third statistical cardinality count, Ck, related to a number of distinct message values received in the subinterval. The combining circuitry combines the first, second and third statistical cardinality counts to provide an estimate of the number of distinct message values received in both the prior interval and the subinterval. The estimate may be used to configure a data processing system. The cardinality counts may be generated by a HyperLogLog circuit, for example.

[0025] A message value may be a reference, a name or address of an object, for example, or the message values may include memory addresses associated with access requests to a memory of the data processing system. The number of distinct message values received in both the prior interval and the subinterval may provide an estimate of an active working set size of a cache of the data processing circuit where the cache is configured based on the estimate of the active working set size. For example, the size of a partition of the cache may be adjusted based on the estimate of the active working set size or a bypass circuit of the cache configured based on the estimate of the active working set size.

[0026] In one embodiment, the estimation circuitry includes a first HyperLogLog circuit configured to generate the first statistical cardinality count Gand the second statistical cardinality count Gi and a second HyperLogLog circuit configured to generate the third statistical cardinality count Ck. In a further embodiment, the estimation circuitry includes a single HyperLogLog circuit configured to generate the first statistical cardinality count Ck, the second statistical cardinality count Gi, and the third statistical cardinality count Ck.

[0027] In one embodiment, the estimation circuitry includes hash circuitry configured to generate a hash value from a message value, match circuitry configured to determine a pattern match length of at least a portion of the hash value, a first memory, configured to store maximum pattern lengths over the prior interval and over the interval, a second memory, configured to store maximum pattern lengths over the subinterval, sum update circuitry configured to update a first summation value based on maximum pattern lengths in the first memory and to update a second first summation value based on maximum pattern lengths in the second memory, and sequential logic circuitry. The sequential logic circuitry is configured to determine the first statistical cardinality count Gbased on the first summation value at the end of the subinterval, the second statistical cardinality count Gi based on the first summation value at the start of the subinterval, and the third statistical cardinality count Ck based on the second summation value at the end of the subinterval. The sequential logic circuitry may include a reciprocation circuit to compute the cardinality or a multiplication by a precomputed constant to compute the reciprocal of the cardinality.

[0028] Various embodiments of the present disclosure provide a computer-implemented method including processing a plurality of message values, each message value associated with a characteristic of a message in a data processing system, to generate and combining first, second and third statistical cardinality counts to provide an estimate of the number of distinct message values received in both the prior interval and the subinterval, and configure the data processing system based on the estimate of the number of distinct message values received in both the prior interval and the subinterval. The first statistical cardinality count, G, is related to a number of distinct message values in the plurality of message values received in an interval [Ao, Ak], the interval including a subinterval [Ak-i, Ak] and a prior interval [Ak-i, Ak], The second statistical cardinality count, Gi, is related to a number of distinct message values in the plurality of message values received in the prior interval. The third statistical cardinality count, Ck, is related to a number of distinct message values in the plurality of message values received in the subinterval.

[0029] The message values include memory addresses associated with access requests to a memory of the data processing system.

[0030] The number of distinct message values received in both the prior interval and the subinterval may provide an estimate of an active working set size of a cache. The cache may be configured based on the estimate of the active working set size, including adjusting the size of a partition of the cache based on the estimate of the active working set size or configuring a bypass circuit of the cache based on the estimate of the active working set size.

[0031] A message may be network access request from a first device of the data processing system to a second device of the data processing system, and where the associated message value is an identifier of the first device, an identifier of a user of the first device, or an identifier of the second device.

[0032] The message values may be processed in one or more HyperLogLog circuits.

[0033] In one embodiment, a first summation value is initialized at the start of the interval and processing a message value includes generating a hash value from the message value, the hash value including a first index from a first bit vector, determining a first pattern match length of the first bit vector, and comparing the first pattern match length to a maximum pattern length for the first index. When the first pattern match length is greater than the maximum pattern length for the first index, the first summation value is updated based on the maximum pattern match length for the first index and the first pattern match length and the maximum pattern match length for the first index is updated with the first pattern match length. Processing the message values may include generating the second statistical cardinality count Ck-i from a reciprocal of the first summation value at the start of the subinterval and generating the first statistical cardinality count Qfrom a reciprocal of the first summation value at the end of the subinterval.

[0034] A second summation value may be initialized at the start of the subinterval, where the hash value includes a second index and a second bit vector. Processing a message value of the plurality of message values may then also include determining a pattern match length of the second bit vector and comparing the second pattern match length to a maximum pattern length for the second index. When the second pattern match length is greater than the maximum pattern length for the second index, the second summation value is updated based on the maximum pattern match length for the second index and the second pattern match length and the maximum pattern match length for the second index is updated with the second pattern match length. Processing the plurality of message values includes generating the second statistical cardinality count Ck from a reciprocal the second summation value at the end of the subinterval.

[0035] In accordance with various embodiments, a data processing circuit includes match circuitry, memory update circuitry, sum update circuitry and sequential logic circuitry. The match circuitry is configured to generate a first pattern match length of a first bit vector, the first bit vector corresponding to an input message value. The memory update circuitry is configured to receive a first index, compare the first pattern match length to a maximum pattern length for the first index and update and the maximum pattern match length for the first index with the first pattern match length when the first pattern match length is greater than the maximum pattern length for the first index. The sum update circuitry is configured to update a first summation value based on the maximum pattern match length for the first index and the first pattern match length when the first pattern match length is greater than the maximum pattern length for the first index. The sequential logic circuitry is configured to generate a first statistical cardinality count from a scaled reciprocal of the first summation.

[0036] The data processing circuit may also include hash circuitry configured to generate a hash value from the message value, the hash value including the first index and the first bit vector. The hash value may also include a second index and a second bit vector, where the match circuitry is configured to generate a second pattern match length of the second bit vector. The memory update circuitry is then further configured to compare the second pattern match length of the second bit vector to a maximum pattern length for the second index and update and the maximum pattern match length for the second index with the second pattern match length when the second pattern match length is greater than the maximum pattern length for the second index. The sum update circuitry is further configured to update a second summation value based on the maximum pattern match length for the second index and the second pattern match length when the second pattern match length is greater than the maximum pattern length for the second index and the sequential logic circuitry is further configured to generate a second statistical cardinality count from a reciprocal of the second summation.

[0037] In the following description, the disclosure is described with reference to a memory access requests and the message values are associated memory addresses. However, it is to be understood that these techniques may be used for other monitoring other data values in a data processing system.

[0038] Conventionally, estimation of the active working set size is obtained only as a worst case upper bound on the true size by progressively sizing up the cache capacity over several repeated trials until no misses are seen. This is a highly intrusive approach. Further, it is only feasible when the temporal dynamics of the workload can be ignored, since only an average value over a long term can be determined. The approach also requires the working set to fit into the overall available cache capacity and that background interfering workloads and pathological conflict misses do not distort the results.

[0039] In contrast to prior approaches, the disclosed techniques operate independently of the cache and the rest of the system and can estimate active working set sizes with controllable precision on large workload.

[0040] Conventionally, system designers have tried to assess whether a cache is oversubscribed by estimating which working set size can justify seen cache misses. This approach of indirectly measuring the working set size has severe limitations, which make it unusable in newer systems that employ dynamic cache partitioning on general purpose workloads.

[0041] To overcome these limitations, the disclosed technique enables direct measurement of the working set size of a running workload employing a statistical cardinality estimator. A “set” of data values is a collection of distinct data values. The number of data values in a set is called the “cardinality” of the set. In a sequence of data addresses accessed in a data processing system, some addresses may be accessed more than once, so the cardinality of the corresponding set is less than or equal to the number of accesses. Thus, the cardinality of a sequence of data values is the number of distinct values in the sequence.

[0042] Estimation of the cardinality of sequence may be based on a ’’HyperLogLog” method. This method provides a statistical estimate of the cardinality based on measurement and can be performed by the hardware without causing any load on a central processing unit (CPU) of a data processing system, without interfering with the system and without being intrusive in any way for the measured workload.

[0043] The working set size alone is the set of addresses visited by a workload’s evolution over a timespan. This set includes memory blocks that will not be visited again for long time and could be safely evicted from a cache. These blocks, referred to as “dead blocks,” should not be considered if the estimate is to be used defining system properties such as cache partitions sizes. The size of the working set without these “dead blocks” is referred to herein as the “active working set size.”

[0044] Thus, the active working set is the set of addresses that need to be cached for best performance. Its size is a metric that can be fed into a plethora of algorithms for runtime system-level configuration.

[0045] Estimating the active working set size may use a prediction of how many blocks in the current working set are dead or, in other words, will not be re-visited in the medium term. This estimation is useful for example for dynamically and automatically defining cache partitions and cache bypassing policies.

[0046] It has been observed that the working set size does not fluctuate very quickly because processors need time to access all locations. If a fraction of the working set that has been recently re-visited by the workload is estimated, a very precise prediction of the active working set size in the next future can be determined by projecting the size measured in a recent past. In most cases it can be assumed that the active working set size in the future will be the same as in the past, so continuous measurement may be used to update the estimation. However, an expansion or reduction of the active working set size may be predicted based on past evolution. For example, if the working set size is increasing it could assume it keeps growing until it is measured that it has stopped its growth.

[0047] Based on previous reasoning that the active working set is the re-visited one, and estimation of the active working set size may be formulated as the estimation of the size of the working set re-visited after a given time.

[0048] Active Working Set Size and Cardinality.

[0049] The set of addresses visited in a first subinterval is denoted as Co with cardinality Co = Koi- The set of addresses visited in a second, subsequent, subinterval is denoted as W with cardinality Q = |W|. The set of addresses visited in the whole interval consisting of the first and second subintervals is denoted as = Co u W with cardinality Cx = Ki |. The inclusion-exclusion principle gives: KJ = IQ u w| = |W| + Koi - Ko n w|.

[0050] Here, U denotes union and D denotes intersection. The last term on the righthand side of the above equation corresponds to the number of distinct addresses visited in both the first subinterval and the second subinterval - i.e., the estimated size of the active working set. This is given by: % = Ko n w| = |W| + Koi - Ki I = G” + c0 - Cp

[0051] In accordance with embodiments of the disclosure, an active working set size VF0 is determined from measurements of the cardinality counts C15 Co and As will be described below, these measurements may be made using custom circuitry in a data processing system.

[0052] FIG. 1 is a graphical representation 100 of working set size (cardinality) as a function of a count value. The count value may be, for example, a number of accesses between two particular accesses (as referred as the “distance” between them) or a processor cycle count, or a timer value. FIG. 1 shows an interval 104 that includes most recent subinterval 106, between counts A3 and ^4, and prior interval 108 that includes subintervals between Ai and Az and between Az and A3. In general, the most recent subinterval with index k is denoted as being between counts Ak-i and Ak. Referring to FIG. 1, it can be seen from line 102 that at count Ak a working set Ck of size (or cardinality) Ck has been measured. Lines 110, 112 and 114 denote the cardinalities measured in the subintervals. Also, from line 102, at count Ak a new working set Ck of size Ck has been measured. Ck >Ck_} because £ Ck. In the subinterval between Ak_} and Ak a subset W c Q has been visited, as indicated by lines 110, 112 and 114. The subset W has size or cardinality Ck. This can be decomposed as the set of distinct accesses Wo £ (Ck_1 visited before count Ak-i, and the set Wx: Wx D Co = 0 of accesses to new distinct addresses visited in the subinterval between Ak_} and Ak, as indicted by counts 120, 122 and 124. In this formulation, an estimation may be performed for every Ak — Ak_} subinterval and re-visits qualify as being in an active working set only if they occur within this subinterval.

[0053] A dual cardinality estimator is used to estimate the cardinality of messages values (such as accessed addresses) in an interval and a subinterval. It may not be practical to maintain a list of accessed address, since the number of addresses may be exceptionally large. An aspect of the present disclosure is the use of a statistical cardinality estimator implemented in hardware. The dual cardinality estimator is used for estimating cardinalities of the working set and of the re-visited subset seen from cache look-ups.

[0054] Various embodiments employ the same hardware resources for computation of both cardinalities and use only slightly more memory space (20% in the example described below) for storing values.

[0055] In accordance with a further aspect of the present disclosure, an implementation of a statistical cardinality estimator is disclosed that accelerates the cardinality computation from thousands of cycles to just a few cycles (typically 1 to 4 cycles) and hence share the last step of computation within few clock cycles, with minor impact of the accuracy of the estimation.

[0056] FIG. 2 is a simplified block diagram of data processing circuit 200, in accordance with various representative embodiments. Data processing circuit 200 receives message values 202 (such as memory addresses) from data processing system 204. In the example shown, data processing circuit 204 is used to generate a configuration signal 206 that may be used to runtime configuration of data processing system 202.

[0057] Data processing circuit 200 includes dual cardinality estimation circuitry 208 that estimates the cardinality Ck of the working set Ck in an interval and the cardinality Ck of the subset W in a subinterval. These values are stored in registers 210 and 212, respectively. Registers 210 and 214 are configured to form a delay line, so register 210 stores a value Ck of the estimated cardinality at a count Ak, while register 214 stores a previous value Ck-i of the estimated cardinality at count Ao. In the embodiment shown, a second delay line consisting of registers 216 and 218 stores the corresponding count values A andAk-i. Alternatively, the difference Ak — Ak_x may be stored, indicating the number of message values in the subinterval between A and Ak-\.

[0058] The values Ck, Ck-i, Ck, At andAk-i are used in combining circuitry 220 to generate an estimate PFo of the size of the active working set. The value Wo is stored in register 222. Operation of combining circuitry 220 is discussed in more detail below.

[0059] The estimate Wo of the size of the active working set may be used by control logic circuitry 224 to produce configuration signal 206. For example, control logic circuitry 224 may be configured to determine, based at least in part on Wo, the size of a cache partition or to provide an indication of when to bypass a cache.

[0060] Optionally, the value 1¾ = Ck — Ck_x may be output and stored in register 226. This provides an estimate of the number of new distinct message values received in the subinterval.

[0061] Statistical Cardinality Count.

[0062] FIG. 3 is a flow chart of a method 300 of determining a statistical cardinality, in accordance with various embodiments. The method uses a modified HyperLogLog technique to estimate the cardinality of message values received in an interval. The interval may be a period of time or a specified number of message values, for example. A memory array, allocated to the cardinality estimator, is reset at block 302. This may be done by setting memory values to zero or by clearing validity bits for each memory location. A stored sum value is also reset to zero. The memory may be reset at the start of each interval. At block 304 a message value is received. A message value may be a memory address associated with a request by a cache client to access data associated with the memory address. A hash of the message value is generated at block 306. The hash may be generated by a circuit designed to randomize the message values. For example, the hash of a message value v may be calculated as 7i(v) = (av + b)%(261 — 1), for some integer values a and b. A cryptographic hash function may be used. Any suitable uniform hash may be used. There is an advantage in selecting a hash function at random (universal hashing) when starting the measurement, because this prevents that random pathological or malicious workload realizations cause static measurement errors due to a high amount of hash collisions. Optionally, when message values are uniformly distributed across a range of values, or approximately so, the hash operation may be omitted. At block 308, a pattern match length L and index i are determined from the hash value, as illustrated in FIG. 4.

[0063] FIG. 4 is a diagrammatic representation of a 58-bit hash value 400, in accordance with various representative embodiments. In this example, bits 46-57 of the hash value, denoted as 7 / (57:46), are used to indicate an index h and 7 / (45:0) is used to give a bit vector xi. The number of bits in xi that match a pattern, referred to as the pattern match length L, is then found. For example, the pattern may be all zeros, with the pattern match length given by the number of tailing zeros plus one (since the first bit adjacent the trailing zeros must be set, i.e., match “one”). Mathematically, this is given by: L(x) = max[log2(x&-(^x + 1)) + 1,0], where —x denotes the bit-wise complement of x. Hash value 400 may be apportioned in different ways. In one embodiment, for example, the trailing bits are used as the index so that xi=7 / [57:48] and X2=7 / [57:46],

[0064] The HyperLogLog method uses the maximum patch length for each of N indices and determines a statistical cardinality count C as: C = aWS'1, where is a scale factor, dependent upon N, and S is the summation value: N—1 n=0 and the value m\n\ is the maximum pattern match length for index n. The scale factor a(N) is a multiplicative constant that includes bias correction. This has a static value for all estimations of cardinalities above certain low threshold and may be read from a table. The value 2 L denotes the probability of L-l consecutive bits matching the chosen pattern and the next bit not matching the chosen pattern when the hash values are uniformly distributed.

[0065] Recursive Summation. In accordance with an aspect of the present disclosure, the summation value is calculated recursively on-line. The summation value at time k is given by: N-l N-l S(k) = 2~m^ = 2~mW + 2~m^, n=0 n=0 where N denotes the number of memory bins. When, at time k+1, m\i\ is replaced by L, the summation value is: S(k + 1) = ( N-l S(k + 1) = 2~m™ + 2-L = S(k) - 2“mW + 2~L. n=0 n^i

[0066] The sum may be reset to S(0) = N at the start of a measurement, corresponding to m[z]=0 for all indices i. Alternatively, the sum may be reset to zero and updated as: S(fc) + 2~L, when m[i] = 0 S(fc) — 2~m^ + 2~L, whenm[i] >0

[0067] Thus, the summation value may be computed recursively by updating a previous summation value S(k) whenever a new maximum is found. When N is large, this avoids a delay at the end of an interval while N values are summed.

[0068] Referring again to FIG. 3, the pattern match length L is compared with a previous maximum value m\i\ stored at index i in the memory at decision block 310. When the pattern match length L is greater than the previous maximum value m[i], as indicated by the positive branch from decision block 310, a summation value is updated at block 312 by subtracting the and adding the new value 2'L. The memory at index i is updated with the new maximum at block 314. When the pattern match length L is not greater than the previous maximum value m\i\ as indicated by the negative branch from decision block 310, flow continues to decision block 316. If the interval has not ended, as depicted by the negative branch from decision block 316, flow returns to block 304 to receive the next value. If the interval has ended, e.g., a designated time has passed or a designated number of message values have been processed, as depicted by the positive branch from decision block 316, the reciprocal S-1of the summation S is determined at block 318 and scaled by at block 320 to provide the statistical cardinality count C. In one embodiment, reciprocation is performed by a hardware implementation of “Newton-Raphson Reciprocation,” as discussed below.

[0069] In one embodiment, each estimation of the working set size is performed within a period of time. Within this period, an estimation of the re-visited subset size is performed at the end of every slot of time. Hence, the memory used for Ck is reset at the start of each interval or period. The memory used for Ck is reset at the start of each subinterval or slot. At the end of each subinterval, the reciprocation and scaling circuitry is triggered. Thus, computation of the complete sums is not needed at the end of each subinterval.

[0070] Accuracy of statistical cardinality depends on the number A of memory locations, m[i], and the length of time over which the cardinality is measured. Ck is used to measure a potentially small increase of the working set size and Ck is larger than W and its estimation needs a higher precision than the one for 1 / 7 to return an absolute error with similar magnitude. Thus, fewer memory locations are needed for estimating Ck. Referring again to FIG. 4, in the example embodiment, the index h is used for indexing 4096 memory locations for estimating Ck and Ck-\ while index / 2 is used for indexing 1024 memory locations for estimating Ck.

[0071] Other statistical estimators, such as the ones based on the Generalized DoubleDixie Cup Problem or based on the Generalized Birthday Problem and Multinomial Cumulative Distribution over cache ways may be used instead of the HyperLogLog estimator.

[0072] FIG. 5 is a diagrammatic representation of memory region 500 for storing maximum pattern match lengths for estimating Ck, in accordance with various embodiments. Memory region 500 is indexed by the 1 O-bit index / 2 and so has 210=1024 locations. In this example, the pattern length is given by the number of trailing zeros in the binary representation of bit vector X2. This is denoted by the function ctz(xz), for count trailing zeros.

[0073] FIG. 6 is a diagrammatic representation of a corresponding memory region 600 for storing maximum pattern match lengths for estimating Ck_} and Ck. Memory region 600 is indexed by the 12-bit index ii and so has 212=4096 locations. The pattern length is given by the number of trailing zeros in the binary representation of bit vector xi.

[0074] The number of trailing zeros in xi and X2 is the same except that the number of trailing zeros in xi cannot be greater than 46. Hence, can be computed from L2 as C = min[ctz(x2)> 46] + 1 = min[L2,47],

[0075] Single Cardinality Estimation Circuit.

[0076] FIG. 7 is a block diagram of a cardinality estimation circuit 700, in accordance with various embodiments. Cardinality estimation circuit 700 includes a counter 702 for counting the number of message values 216 received. Cardinality estimation circuit 700 also includes hash circuitry 704, match circuitry 708, memory array update circuitry 720 and sequential logic circuitry 730. Cardinality estimation circuit 700 also includes memory 724 for storing maximum pattern match values and storage 736 for storing a summation value. Message value 202 is passed to hash circuitry 704 to produce hash value 706. The hash value includes a bit vector x (706') and, optionally, an index i (706"). Bit vector x (706') is passed to match circuitry 708. Index circuitry 709 outputs index i (710) and match circuitry outputs pattern match length L, (712). Value m\i\ (716) is read from memory array 724 at index i. In an alternative embodiment, index i is obtained from a pseudo-random number generator. In a still further embodiment, where the message values are uniformly distributed, hash circuitry 704 may be omitted.

[0077] Pattern match length L and value m\i\ are compared in comparator 722 of memory update circuitry 720. When L >m[i], enable signals 726 and 728 are asserted. Enable signal 726 causes the pattern match length L to be written to the memory at index i and update the maximum value. When enable signal 728 asserted, update circuitry 732 reads a previous summation value S(k) (724) from storage 736 and computes a new summation value S(k+\) (738) based on the previous maximum value m\i\ and the new maximum value k, as described above. The new summation value 738 is saved in storage 736.

[0078] At the end of an interval, sequential logic circuitry (SLC) 740 is triggered by signal 742 to read the summation values and compute the cardinality value C = a(N)S~} (744) by determining the reciprocal S-1 and scaling by the factor a(N\

[0079] In this manner, computation of the summation S is not needed at the end of an interval. This makes it possible to obtain the cardinality value with very little delay.

[0080] Reciprocation Circuit

[0081] A summation value can be written in floating point form as S = 2E X m, with exponent A and normalized binary significand m = 1. d1d2d3d4d5d6 ..., where each di represents a binary digit. The reciprocal value is R = 2~E X m-1. In one embodiment, the value x = m-1 is computed in hardware by looking up an approximate initial value xo in a table and computing a Newton-Raphson update xn+1 = xn(2 — xnm) for one or more iterations, n. In one embodiment, the table Zis indexed by t significand bits d}... dt and the initial value is x0 = T[dt... dt] = (1. d}... dtl)-1. The hardware may be configured to compute the reciprocal values in other ways, without departing from the present disclosure. For example, an accelerated technique, such as the Goldschmidt division algorithm, may be implemented in hardware.

[0082] Dual Cardinality Estimation Circuit

[0083] FIG. 8 is a flow chart of a method 800 of determining dual statistical cardinality counts, in accordance with various embodiments. The method uses a modified HyperLogLog technique to estimate the cardinality counts of message values received in an overlapping interval. A first memory region is assumed to contain maximum pattern match lengths for a first subinterval, and a first storage is assumed to contain a summation value for the first subinterval. A second region memory array, for storing maximum match pattern lengths in a second subinterval, is reset at block 802 at the start of the second subinterval. A second stored summation value is also reset to zero. This may be done by setting memory values to zero or by clearing validity bits for each memory location. At block 804 a message value is received. A message value may be a memory address associated with a request by a cache client to access data associated with the memory address, for example. A hash of the message value is generated at block 806. At block 808, an index / 2 and a bit vector X2 are obtained from the hash value. A pattern match length L is determined for the bit vector. The pattern match length L is compared with a previous maximum value m\i2\ stored at index / 2 in the second memory region at decision block 810. When the pattern match length L is greater than the previous maximum value m[i2], as indicated by the positive branch from decision block 810, a summation value S2 is updated at block 812 by subtracting the 2~m^ and adding the new value 2~L. The second memory region at index 12 is updated with the new maximum at block 814. When the pattern match length L is not greater than the previous maximum value m\i2\ as indicated by the negative branch from decision block 810, flow continues to block 816.

[0084] At block 816, an index h and a bit vector xi are determined from the hash value. The pattern match length L is recalculated or determined from the match length for X2. The pattern match length, L, is compared with a previous maximum value m[ii] stored at index ii in the first memory region at block 818. When the pattern match length L is greater than the previous maximum value m[i2], as indicated by the positive branch from decision block 818, a summation value Si is updated at block 820 by subtracting the 2-777^1] and adding the new value 2~L. The first memory region at index h is updated with the new maximum at block 822. When the pattern match length L is not greater than the previous maximum value m[ii] as indicated by the negative branch from decision block 810, flow continues to block 824.

[0085] If the interval has not ended, as depicted by the negative branch from decision block 824, flow returns to block 804 to receive the next value. If the interval has ended, e.g., a designated time has passed or a designated number of message values have been processed, as depicted by the positive branch from decision block 824, the reciprocals S-j-1 and are determined at block 826 and scaled by a(N}) and a(A2), respectively, at block 828 to provide the statistical cardinality counts Ck and Ck. In one embodiment, reciprocation is performed by a hardware implementation of “Newton-Raphson Reciprocation,” as discussed below.

[0086] In the method of FIG. 8, the same hardware resources may be used for generating the hash, updating memory, updating summations and computing statistical cardinality counts from the summations. Alternatively, one or more of these components may be duplicated for parallel operation.

[0087] Dual Cardinality Estimation Circuitry

[0088] FIG. 9 is a block diagram of dual cardinality estimation circuitry 900, in accordance with various embodiments. Hashing, in hash circuitry 704. is only employed to scatter correlation among bits in the message value. As such, there is no drawback in using the same hash circuitry and same hashed message value to determine two cardinality counts. Operation of circuitry 900 is similar to that of circuitry 700. However, match circuitry 902 and index circuitry 903 are controlled by select signal 904 from controller 906 to compute index ii on line 908 and pattern match length Li one line 910 in one cycle and to compute index / 2 on line 908 and pattern match length L2 on line 910 in another cycle, as described above in reference to FIG. 8. Memory 912 is similarly controlled by select signal 904, to enable corresponding regions of memory (MEM 1 and MEM 2) to be updated with maximum pattern match lengths. Summation store 914 is also controlled by select signal 904 to select a corresponding store location for summation values. At the end of each subinterval, the sequential logic circuitry (SLC 922) is triggered by signal 924 to read summation values Si and S2 on line 926. The statistical cardinality counts Ck and Ck are then generated sequentially by circuitry 922.

[0089] Example Memory Organization

[0090] FIG. 10 shows a 58-bit hash value 1000, in accordance with various representative embodiments. The hash value includes a 46-bit bit vector xi, a 1 O-bit row index i and a 2-bit column index j. Hash value 100 also includes a 48-bit bit vector X2.

[0091] FIG. 11 shows a memory organization, in accordance with various representative embodiments. The memory (e.g., 912 in FIG. 9) is organized as a block with 210=1024 rows and 22+l=5 columns. The first column is used to store maximum pattern match lengths / .2 for X2, while the other four columns are used to store maximum pattern match lengths L\ for xi. In this example, the pattern match lengths are no more than 48-bit, so 6-bits suffice to store the maximum lengths. In general, if p bins are used for Z2, n X p bins are used for L\ storage, and q bits are used to store each value, a single memory with p x (n + 1) x q bits can be used. No drawback occurs because the same hashed memory address can access the same memory row and an output multiplexer can select one of the n columns used for the estimation of the working set. The sizes of the estimators for subset size (p entries) and set size (n x p rows) are different because the set is larger than the subset and needs more rows to achieve a comparable absolute error to the one achieved in the estimation of the subset size.

[0092] Rather than zeroing p fields of q bits in the memory, which would require accessing all p rows of the memory, p validity bits may be implemented using flip-flop registers, for example. The validity bits can all be reset to zero at once. When set to zero, a read from the memory returns zero. The validity bit is set when the corresponding entry in the memory is written.

[0093] In the above description, operations are performed serially. However, some of the simpler operations may be performed in parallel as shown in FIG. 12.

[0094] FIG. 12 shows a dual cardinality estimation circuit 1200, in accordance with various representative embodiments. As above, a single counter 702 and a single hash circuit 704 is used. From hash value 706, match circuitry MATCH 1 and MATCH 2 produce pattern match lengths (1204) and L2 (1206), respectively. Index generators INDEX 1 and INDEX 2 produce corresponding indices / 1 and / 2, respectively. A first memory update circuit 1208 updates memory MEM 1 when exceeds a previous maximum value 711(^). A second memory update circuit 1210 updates memory MEM 2 when L2 exceeds a previous maximum value m(i2). Thus, the memory updates are performed in parallel. First sum update circuitry 1212 updates a first summation value Si whenever the first memory is updated. Second sum update circuitry 1214 updates a second summation value S2 whenever the second memory is updated. Thus, sum updates may be performed in parallel when both memories are updated.

[0095] The reciprocation and de-bias operation, performed by sequential logic circuitry, is a more costly computation. In the embodiment shown, single sequential logic circuitry (SLC 1220) is used. When triggered by signal 1222 at the end of a subinterval, sequential logic circuitry 1220 reads the first and second summation values and determines the statistical cardinality counts Ck and Ck sequentially from them by reciprocation and scaling. Alternatively, two circuits 1220 may be used when latency is more important than chip area.

[0096] Operating Modes

[0097] In an embodiment of the disclosure, dual cardinality estimation circuitry 1200 may be operated in several different modes:

[0098] rates: in this mode, the circuitry provides two estimations: - the size 1¾ of the working set having been visited for the first time within the interval [Ak_1,Ak], and - the size 1¾ of the working set having been visited before Ak_1 and re-visited for at least a second time after Ak_1, until Ak.

[0099] The value IV = 1¾ + 1¾ is the working set size visited within an interval [Ak_v Ak], but the value 1¾ indicates whether the workload is in a transient phase. In this case, 1¾ and Ck_1 — 1¾ provide estimations of the rates A and / / at which data blocks are “born” (referenced for the first time) and “dead” (referenced for the last time). These estimations deliver the mean life distance of a data block. In this mode, the estimation algorithm can be executed in adjacent intervals Vfc G N to deliver a gauge value updated at subinterval boundaries Ak.

[0100] When the birth rate drops close enough to zero, it can be assumed that the workload has left its transient behavior and will remain stable: in this case the filter can transition to the “reuses” mode, which delivers a more precise estimation for stable workloads.

[0101] singles: in this mode the design delivers running estimations of the size Ck of the visited working set and of the size Ck — (1¾ + 1¾) of the set of data blocks referenced only once up to the count Ak_±. This functionality is a side effect of selectively updating HyperLogLog memory arrays. However, data blocks referenced only once should not be cached, so this functionality is useful along with a filter on references for examining whether streams within workloads presents this cache-unfriendly behavior.

[0102] reuses: in this mode, the logic delivers an estimation of the size Wo (being 1¾ = 0) of the working set reused within the interval [ / 1).^,¾] from Ak-i, with A / ^ >Ak_1. Operations within this mode can transition across the following three phases: warmup: During this phase only Ck is measured. hold: During this phase nothing is measured. estimation: During this phase, only those references which do not change the memory array for Ck are used to update the maximum length table for Wo.

[0103] During the warmup phase, an increase of Ck is an indication of a transient behavior. Upon speculation that the future behavior will still be transient, this indication should lead to a transition to the “rates” mode for estimating the active working set size during transient behaviors.

[0104] The default functionality is to drive the mode “rates”. The mode “singles” may by an explicit choice of the user, because it is demanded upon intention of the user to investigate a specific workload and potentially needs coordination with filters on the channels transporting memory references. The mode “reuses” can be driven by the user for any methodology and can cycle across the submodes “warmup” -> “hold” -> “estimation”.

[0105] Referring again to FIG. 12, a mode signal 1228 is used to control filter 1230 to provide enablement signals em and em. These are used enable writing to memories MEM 1 and MEM 2, respectively, and to trigger sum update circuits 1212 and 1214, respectively. In one embodiment, memory update circuitries 1208 and 1210 assert comparator outputs and / or c2 when a new maximum pattern length is found and the enablement signals em and em are generated as listed in TABLE 1.

[0106] TABLE 1: Operating Modes mode em em rates Cl c2 sizes Cl Cl &c2 reuse:warmup Cl 0 reuse:hold Cl 0 reuse: estimate 0 Ci &c2

[0107] Estimation Bounds

[0108] Since estimates are affected by statistical fluctuations, there is a small probability that subtraction of estimates deliver a result which cannot occur in reality. For example, if the working set expands from to Ck with Ck_1 £ Ck, then the estimation of Ck — Ck_x may not be negative, although in statistical counting there is a small probability that this actually happens. Similarly, if Ak — Ak_1 accesses to the cache have been seen, the working set size Ck — Ck_x may not have increased more than the number of accesses Ak — Ak_x. For this reason, the estimates 1¾ and Wo are bounded by maximum and minimum operators as follows: 1¾ = min[max(Ck - ,0),Ak - A^J, % = max{W - 0}.

[0109] While the estimation of the working set size proceeds, the estimation of the revisited subset size is performed in subintervals or slots.

[0110] Memory Size and Error Rate

[0111] The logic memory size may be selected dependent on a desired statistical error rate. This error rate is a statistical probability of relative error on the measurement, between 0 and 1. Since the memory sizes must be integer numbers, the actual error rate is the same or lower than the given one. Once the memory size is computed, the actual error can be obtained as memory dimension = 2l g2lerrorrate. x 21og2 1.04 error rate

[0112] Consequently, the size of the bit vector in which the first or last set bit is searched is: 1.04 pattern length = address width — 21og2 \error rate /

[0113] For a memory of depth d, the error rate can be obtained solving the equation: l2log2( 104 JI U = / 1 kerror rate / I.

[0114] When d is a power of two, the solution has the simple form: 1.04 error rate =

[0115] For t / =4096 memory locations, for example, the error rate is 1.625%.

[0116] Application to Cache Configuration

[0117] FIG. 13 is a block diagram of a data processing system 1300, in accordance with various representative embodiments. Data processing system 1300 includes cache or caching system 1302 that is responsive to addresses on line 1304 requested by a cache client 1306. Data processing circuit 200 receives the addresses on line 1304 and from them estimates the size Wo of the active working set for cache 1302. The value Wo is stored in register 222 and is used by control logic circuitry 1310 to determine configuration signal 1312 for cache 1302. In one embodiment, configuration signal 1312 is used, at least in part, to determine when a subset of allocations to cache 1302 should be bypassed. In a further embodiment, configuration signal 1312 is used, at least in part, to determine a cache partition size. In a still further embodiment, configuration signal 1312 is used, at least in part, to adjust a cache eviction policy of cache 1302. Other ways of using the active working set size Ho to adjust operation of the cache will be apparent to those of skill in the art. Configuration of cache 1302 may also be controlled by signals on configuration bus 1314. Selector 1316 may be used to select whether the cache is configured in a predetermined manner or configured dynamically in response to measurements of the active working set size Ho.

[0118] An advantage of the approach shown in FIG. 13 is that an intrusion into the cache design is not required to access information and steer control of the cache.

[0119] While not shown in FIG. 13, data processing circuit 200 may also be configured to allow reading of the internal value I / Pj = Ck — Wo to estimate when the working set is in a transient phase.

[0120] FIG. 14 is a block diagram of an example implementation of a cardinality estimator, in accordance with various representative embodiments. In this example, the hash value output from hash circuit 1402 has 58 bits, 12 of which are as an index and the remaining 46 as a bit vector. The index is used first as a read address to read a previous maximum pattern length from the memory and then as a write address if the maximum length is to be updated, as indicated by the output from comparator 1404. The pattern match length is given by the position of the first set bit in the bit vector. The online sum circuit 1406 is implemented using a fix-point counter 1408, that is updated when a new maximum length is found. Circuit 1410 performs reciprocation and de-bias at the end of an interval to produce estimated cardinality 1412. An interval may be a designated number of message values received, for example. Circuit 1410 performs an iterative computation using fixed-point arithmetic for a designated precision p and data width w. The sum S is initially normalized by 2W a factor 2P, where p is the length of the prefix of zeros. An initial reciprocal R = is found from a lookup table in circuit 1414, where w is a fix-point shift. Integer fix-point multiplication circuit 1416 performs a Newton-Raphson iteration, while circuit 1418 performs de-biasing, and shifts for de-normalizing and fix-point. Optionally, reciprocation circuit 1410 may be omitted and sum 1420, or a scaled version thereof, output to provide a value related to the reciprocal of the cardinality.

[0121] Example Results

[0122] FIG. 15 shows some example results of an experimental implemented of an active working set estimator, in accordance with various representative embodiments. An experiment was performed on a complete production run of widely used image processing software ‘ffrnpeg.” A statistical bound on the error of the estimation of the data working was set at 5%. Graph (a) shows the actual (measured) size of the work set in successive intervals as a function of the number of references over a span of 400 million references. Graph (b) shows the measured and estimated working set size for subintervals, together with the measured and estimated active working set size for subintervals. Graph (c) shows the percentage error in the estimation of the active work set size on a logarithmic scale. This show that, apart from initial outliers during initialization, the error is consistently controlled below the selected statistical bound.

[0123] In this document, relational terms such as first and second, top and bottom, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element preceded by “comprises .. .a” does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0124] Reference throughout this document to “one embodiment,” “certain embodiments,” “an embodiment,” “implementation(s),” “aspect(s),” or similar terms means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of such phrases or in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments without limitation.

[0125] The term “or,” as used herein, is to be interpreted as an inclusive or meaning any one or any combination. Therefore, “A, B or C” means “any of the following: A; B; C; A and B; A and C; B and C; A, B and C ” An exception to this definition will occur only when a combination of elements, functions, steps or acts are in some way inherently mutually exclusive.

[0126] As used herein, the term “configured to,” when applied to an element, means that the element may be designed or constructed to perform a designated function, or that is has the required structure to enable it to be reconfigured or adapted to perform that function.

[0127] Numerous details have been set forth to provide an understanding of the embodiments described herein. The embodiments may be practiced without these details. In other instances, well-known methods, procedures, and components have not been described in detail to avoid obscuring the embodiments described. The disclosure is not to be considered as limited to the scope of the embodiments described herein.

[0128] Those skilled in the art will recognize that the present disclosure has been described by means of examples. The present disclosure could be implemented using hardware component equivalents such as special purpose hardware and / or dedicated processors which are equivalents to the present disclosure as described and claimed. Similarly, dedicated processors and / or dedicated hard wired logic may be used to construct alternative equivalent embodiments of the present disclosure.

[0129] Dedicated or reconfigurable hardware components used to implement the disclosed mechanisms may be described, for example, by instructions of a hardware description language (HDL), such as VHDL, Verilog or RTL (Register Transfer Language), or by a netlist of components and connectivity. The instructions may be at a functional level or a logical level or a combination thereof. The instructions or netlist may be input to an automated design or fabrication process (sometimes referred to as high-level synthesis) that interprets the instructions and creates digital hardware that implements the described functionality or logic.

[0130] The HDL instructions or the netlist may be stored on non-transitory computer readable medium such as Electrically Erasable Programmable Read Only Memory (EEPROM); non-volatile memory (NVM); mass storage such as a hard disc drive, floppy disc drive, optical disc drive; optical storage elements, magnetic storage elements, magnetooptical storage elements, flash memory, core memory and / or other equivalent storage technologies without departing from the present disclosure. Such alternative storage devices should be considered equivalents.

[0131] Various embodiments described herein are implemented using dedicated hardware, configurable hardware or programmed processors executing programming instructions that are broadly described in flow chart form that can be stored on any suitable electronic storage medium or transmitted over any suitable electronic communication medium. A combination of these elements may be used. Those skilled in the art will appreciate that the processes and mechanisms described above can be implemented in any number of variations without departing from the present disclosure. For example, the order of certain operations conducted can often be varied, additional operations can be added, or operations can be deleted without departing from the present disclosure. Such variations are contemplated and considered equivalent.

[0132] The various representative embodiments, which have been described in detail herein, have been presented by way of example and not by way of limitation. It will be understood by those skilled in the art that various changes may be made in the form and details of the described embodiments resulting in equivalent embodiments that remain within the scope of the appended claims.

Claims

s claimed is:

1. A data processing circuit comprising:estimation circuitry configured to receive a plurality of message values in an interval from count Ao to count Ak, where is an index, the interval including a subinterval from count Ak-i to count Ak and a prior interval from count Ao to count Ak-i, and each message value associated with a characteristic of a message in a data processing system, and generate therefrom:a first statistical cardinality count, Ck, related to a number of distinct message values received in the interval;a second statistical cardinality count, Ck-i, related to a number of distinct message values received in the prior interval; anda third statistical cardinality count, Ck, related to a number of distinct message values received in the subinterval; andcombining circuitry configured to combine the first, second and third statistical cardinality counts to provide an estimate Wo of the number of distinct message values received in both the prior interval and the subinterval,where the data processing system is configured based on the estimate Wo of the number of distinct message values received in both the prior interval and the subinterval.

2. The data processing circuit of claim 1, where the plurality of message values include memory addresses associated with access requests to a memory of the data processing system.

3. The data processing circuit of claim 2, where the estimate Wo of the number of distinct message values received in both the prior interval and the subinterval provides an estimate of an active working set size of a cache, the data processing circuit including:a cache, where the cache is configured based on the estimate of the active working set size.

4. The data processing circuit of claim 3, where the size of a partition of the cache is adjusted based on the estimate of the active working set size.13 03 265. The data processing circuit of claim 3, where a bypass circuit of the cache is configured based on the estimate of the active working set size.

6. The data processing circuit of any of claims 1-5, where the message value is a reference, a name or address of an object.

7. The data processing circuit of any of claims 1 to 6, where the estimation circuitry includes:a first HyperLogLog circuit configured to generate the first statistical cardinality count Gand the second statistical cardinality count Gi; anda second HyperLogLog circuit configured to generate the third statistical cardinality count Ck.

8. The data processing circuit of any of claims 1 to 6, where the estimation circuitry includes a single HyperLogLog circuit configured to generate the first statistical cardinality count Ck, the second statistical cardinality count Gi, and the third statistical cardinality count Ck.

9. The data processing circuit of any of claims 1 to 6, where the estimation circuitry includes:hash circuitry configured to generate a hash value from a message value;match circuitry configured to determine a pattern match length of at least a portion of the hash value;a first memory, configured to store maximum pattern lengths over the prior interval and over the interval;a second memory, configured to store maximum pattern lengths over the subinterval;sum update circuitry configured to update a first summation value based on maximum pattern lengths in the first memory and to update a second first summation value based on maximum pattern lengths in the second memory; andsequential logic circuitry configured to determine:the first statistical cardinality count Gbased on the first summation value at the end of the subinterval;the second statistical cardinality count Gi based on the first summation value at the start of the subinterval; andthe third statistical cardinality count Ck based on the second summation value at the end of the subinterval.13 03 2610. The data processing circuit of claim 9, where the sequential logic circuitry includes a reciprocation circuit.

11. A computer-implemented method comprising:processing a plurality of message values, each message value associated with a characteristic of a message in a data processing system, to generate:a first statistical cardinality count, Ck, related to a number of distinct message values in the plurality of message values received in an interval [Ao, Ak], the interval including a subinterval [Ak-i, Ak] and a prior interval [Ao, Ak-i];a second statistical cardinality count, Ck-i, related to a number of distinct message values in the plurality of message values received in the prior interval; anda third statistical cardinality count, Ck, related to a number of distinct message values in the plurality of message values received in the subinterval;combining the first, second and third statistical cardinality counts to provide an estimate Wo of the number of distinct message values received in both the prior interval and the subinterval, andconfiguring the data processing system based on the estimate Wo of the number of distinct message values received in both the prior interval and the subinterval.

12. The computer-implemented method of claim 11, where the plurality of message values include memory addresses associated with access requests to a memory of the data processing system.

13. The computer-implemented method of claim 12, where the estimate Wo of the number of distinct message values received in both the prior interval and the subinterval provides an estimate of an active working set size of a cache, the method also including:configuring the cache based on the estimate of the active working set size.13 03 2614. The computer-implemented method of claim 13, where configuring the cache based on the estimate of the active working set size includes adjusting the size of a partition of the cache based on the estimate of the active working set size.

15. The computer-implemented method of claim 13, where configuring the cache based on the estimate of the active working set size includes configuring a bypass circuit of the cache based on the estimate of the active working set size.

16. The computer-implemented method of claim 11, where a message is a network access request from a first device of the data processing system to a second device of the data processing system, and where the associated message value is an identifier of the first device, an identifier of a user of the first device, or an identifier of the second device.

17. The computer-implemented method of any of claims 11 to 16, where processing a plurality of message values includes processing the message values in one or more HyperLogLog circuits.

18. The computer-implemented method of any of claims 11 to 17, further comprising initializing a first summation value at the start of the interval, where processing a message value of the plurality of message values includes:generating a hash value from the message value, the hash value including a first index from a first bit vector;determining a first pattern match length of the first bit vector;comparing the first pattern match length to a maximum pattern length for the first index; andwhen the first pattern match length is greater than the maximum pattern length for the first index:updating the first summation value based on the maximum pattern match length for the first index and the first pattern match length; andupdating the maximum pattern match length for the first index with the first pattern match length;where processing the plurality of message values includes:13 03 26generating the second statistical cardinality count G-i from a reciprocal of the first summation value at the start of the subinterval; andgenerating the first statistical cardinality count Qfrom a reciprocal of the first summation value at the end of the subinterval.

19. The computer-implemented method of claim 18, further comprising initializing a second summation value at the start of the subinterval, where the hash value includes a second index and a second bit vector, and where processing a message value of the plurality of message values includes:determining a pattern match length of the second bit vector;comparing the second pattern match length to a maximum pattern length for the second index;when the second pattern match length is greater than the maximum pattern length for the second index:updating the second summation value based on the maximum pattern match length for the second index and the second pattern match length; andupdating the maximum pattern match length for the second index with the second pattern match length;where processing the plurality of message values includes generating the second statistical cardinality count Ck from a reciprocal the second summation value at the end of the subinterval.

20. The data processing circuit of any of claims 1 to 6, where the estimation circuitry includes:match circuitry configured to generate a first pattern match length of a first bit vector, the first bit vector corresponding to an input message value;memory update circuitry configured to:receive a first index;compare the first pattern match length to a maximum pattern length for the first index; and13 03 26update and the maximum pattern match length for the first index with the first pattern match length when the first pattern match length is greater than the maximum pattern length for the first index;sum update circuitry configured to update a first summation value based on the maximum pattern match length for the first index and the first pattern match length when the first pattern match length is greater than the maximum pattern length for the first index; andsequential logic circuitry configured to generate the first statistical cardinality count, Ck, from a scaled reciprocal of the first summation.

21. The data processing circuit of claim 20, where the estimation circuitry also includes hash circuitry configured to generate a hash value from the message value, the hash value including the first index and the first bit vector.

22. The data processing circuit of claim 21, where:the hash value includes a second index and a second bit vector,the match circuitry is configured to generate a second pattern match length of the second bit vector;the memory update circuitry is further configured to:compare the second pattern match length of the second bit vector to a maximum pattern length for the second index; andupdate and the maximum pattern match length for the second index with the second pattern match length when the second pattern match length is greater than the maximum pattern length for the second index;the sum update circuitry is further configured to update a second summation value based on the maximum pattern match length for the second index and the second pattern match length when the second pattern match length is greater than the maximum pattern length for the second index; andthe sequential logic circuitry is further configured to generate a third statistical cardinality count, Ck, from a reciprocal of the second summation.

23. A non-transitory computer-readable medium storing computer-readable code for fabrication of a data processing circuit comprising:13 03 26estimation circuitry configured to receive a plurality of message values in an interval from count Ao to count Ak, where is an index, the interval including a subinterval from count Ak-i to count Ak and a prior interval from count Ao to count Ak-i having one or more subintervals, each message value associated with a characteristic of a message in a data processing system, and generate therefrom:a first statistical cardinality count, Ck, related to a number of distinct message values received in the interval;a second statistical cardinality count, Ck-i, related to a number of distinct message values received in the prior interval; anda third statistical cardinality count, Ck, related to a number of distinct message values received in the subinterval; andcombining circuitry configured to combine the first, second and third statistical cardinality counts to provide an estimate Woof the number of distinct message values received in both the prior interval and the subinterval for configuring the data processing system,where, in operation, the data processing system is configurable based on the estimate Wo.

24. The non-transitory computer-readable medium of claim 23, where:the data processing circuit includes a cache having a configurable partition size or a configurable bypass circuit,the plurality of message values includes memory addresses, andthe cache is configured based, at least in part, on the number of distinct message values received in both the prior interval and the subinterval.

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