Encoding-based signal operation sequence and integrity checking method for rail transit

Abstract

This invention relates to a coding-based method for checking the order and integrity of rail transit signal operations. The method first calculates a compensation value using offline tools, then calculates a verification word using online tools in conjunction with the compensation value, and finally provides the verification word to the system for subsequent safety processing. Compared with existing technologies, this invention offers advantages such as effectively checking and ensuring the "order and integrity of operations," meeting stringent safety requirements, and being applicable not only to single-core CPU safety systems but also to dual-core and multi-core CPU cloud security systems (such as cloud interlocking systems).

Description

Technical Field

[0001] This invention relates to rail transit signal control systems, and more particularly to a method for checking the operation sequence and integrity of rail transit signals based on coding. Background Technology

[0002] In the rail transit industry, embedded systems are generally used for the safe processing of signal logic. These embedded systems typically execute a "acquisition (input) - operation (logic processing) - drive (output)" process periodically. For most signal operation (logic processing) applications, ensuring the order and integrity of operations is a crucial issue that needs to be considered during system design.

[0003] Currently, the following situations exist: 1) The application layer is relatively simple, with no sequential dependencies between operations, so there is no need to consider the order of operations. Operational integrity is handled by guiding to the safety side, that is, periodically assigning safety values ​​to all output variables before the operation, so that even if the corresponding operation is not executed, its output is still safe. 2) Operations at the application layer have sequential dependencies, and the order and integrity of operations are guaranteed by multi-channel platforms such as 2oo2 / 2oo3. The industry often avoids multi-channel common-mode failure through differentiated design; when the operation order of a single channel is abnormal or incomplete, consistency comparison of multiple channels will guide the result to safety. 3) Operations at the application layer have sequential dependencies, and the order and integrity of operations are achieved by using redundant coding of the source code (such as VCP coding). This scheme adds extra redundant coding to the logic processing source code, so that abnormalities in the execution order of the software source code can be directly reflected in abnormal calculation results or in the check words, and then handled by the subsequent application for safety.

[0004] The aforementioned existing technologies all have certain limitations. The first type has limitations on application logic and cannot handle more complex applications that include self-locking logic; the second type is platform-dependent and cannot be used on non-2oo2 / 2oo3 multi-channel platforms; the third type has redundant coding in the software source code, which leads to a significant decrease in computational efficiency and requires high platform computing performance.

[0005] The self-locking logic in type 1) can be roughly exemplified as follows: There are three operation expressions, B = Func(A,M), A = Func(X,Y), and C = Func(A,N). The application layer requires that the three operations must be ordered. When calculating B, A uses the value of the previous cycle. When calculating C, A uses the value updated after Func(X,Y) operation in the current cycle. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the existing technology by providing a coding-based method for checking the operation order and integrity of rail transit signals.

[0007] The objective of this invention can be achieved through the following technical solutions:

[0008] According to a first aspect of the present invention, a method for checking the operation order and integrity of rail transit signals based on coding is provided. The method first calculates the compensation value using an offline tool, then calculates the check word using an online tool in combination with the compensation value, and finally provides the check word to the system for subsequent safety processing.

[0009] As a preferred technical solution, the specific process by which the offline tool calculates the compensation value is as follows:

[0010] Step S101: Poll all expressions to obtain their respective security-side redundancy codes;

[0011] Step S102: Starting from the first expression, calculate a new "check code sum" using the current "check code sum" and the current expression's security-side redundancy code;

[0012] Step S103: Continue in this manner until all expressions have been processed, and calculate the final "check code sum".

[0013] Step S104: Calculate the verification word compensation value based on the selected verification word value and the "check code operation sum" in step S103;

[0014] Step S105: Store the verification word compensation value and the expression security side redundancy code in the offline configuration for online calculation.

[0015] As a preferred technical solution, before calculation, the offline tool uses a predefined logical operation table, which defines the order of operations and contains all the operation expressions.

[0016] As a preferred technical solution, the offline tool reads each expression and substitutes it with a check code one by one, where the check code indicates whether the expression has been processed or not.

[0017] As a preferred technical solution, the offline tool uses a dual-chain tool method in accordance with the requirements of signal system security standards.

[0018] As a preferred technical solution, the online tool calculates the verification character through the following process:

[0019] Step S201: Poll all expressions to obtain the memory storage address of the corresponding expression result and the information of the security redundancy code;

[0020] Step S202: Starting from the first expression, assign the result storage memory to the corresponding security redundancy code of the expression, then read the stored value from the address and calculate the new "check code sum" with the existing "check code sum", then perform the expression operation, and then update the storage memory to the actual operation result;

[0021] Step S203, and so on, until all expressions are processed and the final "check code sum" is calculated;

[0022] Step S204: Calculate the verification word based on the compensation value calculated by the offline tool and the "check code operation sum" in step S203;

[0023] Step S205: The calculated verification word is used by the system for subsequent security processing.

[0024] As a preferred technical solution, the calculation method in steps S102 and S202 is based on the summation operation of 32-digit polynomial division.

[0025] As a preferred technical solution, step S202 combines the functions of assigning a safe value to the expression and checking memory. If memory hardening causes the storage memory to fail to be assigned a value, the corresponding memory value read out will be a hardened value, resulting in an error in the final verification word, and the system will redirect to the safe side.

[0026] As a preferred technical solution, step S204 uses forward operation based on polynomial division, which can calculate a unique verification word based on the compensation value and the "check code operation sum".

[0027] As a preferred technical solution, step S104 uses the inverse operation based on polynomial division, which can calculate a unique compensation value based on the target verification word and the "check code operation sum".

[0028] According to a second aspect of the present invention, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the program to implement the method described thereon.

[0029] According to a third aspect of the present invention, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the method described thereon.

[0030] Compared with the prior art, the present invention has the following advantages:

[0031] (1) This invention uses an offline + online matching method and a checksum calculation method to effectively check and ensure the "order and completeness of operations";

[0032] (2) This invention is based on the redundancy coding (NISAL) technology, which has the characteristics of low error undetectability rate and high security; it has strong applicability to the logic processing of rail transit signals.

[0033] (3) This invention does not rely on 2oo2 or 2oo3 security platforms, does not have the requirement for multi-channel differential processing, and is suitable for single-CPU 1oo1 systems as well as multi-core CPU MooN systems.

[0034] (4) The present invention has limited encoding operations, and the increased amount of computation is limited, so it has little impact on the performance of embedded systems.

[0035] (5) This invention can be used as one of the core verification functions, applicable to cloud interlocking systems based on coding, to achieve effective verification and guarantee of "the order and completeness of operations". Attached Figure Description

[0036] Figure 1 This is a flowchart of the offline computing software of the present invention;

[0037] Figure 2 This is a flowchart of the online computing software of the present invention. Detailed Implementation

[0038] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0039] This invention provides a method for checking the order and integrity of operations based on encoding, which is mainly achieved by calculating compensation values ​​offline and checking words online.

[0040] The offline calculation of the compensation value involves an offline tool that reads each expression from a predefined logical operation table (which defines the order of operations and contains all the operational expressions), substituting each expression into a check code (indicating whether the expression has been processed), and then calculating a final "check code sum" through recursive operations based on polynomial division. Finally, the compensation value is calculated by inverse operation using the "check code sum" and the target verification word.

[0041] The online calculation method is similar. First, the calculation is performed online, and the "check code sum" is calculated simultaneously. Then, the verification word is calculated using the online calculated "check code sum" and the compensation value in the offline configuration data. The verification word will be provided to the system for subsequent security processing.

[0042] This invention is applicable to 1001 systems. By adding a limited set of check codes, it enables the checking of whether application logic operations are executed sequentially and completely. This invention includes the following steps.

[0043] Offline computing component:

[0044] (1) Poll all expressions to obtain their respective security-side redundancy codes;

[0045] (2) Starting from the first expression, calculate a new "check code sum" using the current "check code sum" and the current expression's security-side redundancy code;

[0046] (3) Continue in this manner until all expressions have been processed, and calculate the final "check code sum";

[0047] (4) Calculate the verification word compensation value based on the selected verification word value and the "check code operation sum" in (3);

[0048] (5) The above compensation values ​​and expression security-side redundancy codes are stored in the offline configuration for online calculation.

[0049] Online calculation section:

[0050] (a) Poll all expressions to obtain information such as the memory storage address of the corresponding expression result and the security redundancy code;

[0051] (b) Starting with the first expression, the result of the expression is stored in memory and assigned the corresponding security redundancy code. Then, the stored value is read from that address and the new "check code sum" is calculated by adding the new "check code sum" to the existing "check code sum". The expression is then performed, and the stored memory is updated with the actual result.

[0052] (c) Continue in this manner until all expressions have been processed, and calculate the final "check code sum";

[0053] (d) Calculate the verification word based on the compensation value in the offline configuration data and the "check code operation" in step (c);

[0054] (e) The calculated verification word is used by the system for subsequent security processing;

[0055] The above steps include the following characteristics:

[0056] According to the requirements of signal system security standards, the offline tool steps described above can use a dual-chain tool approach.

[0057] Step (b) has the functions of assigning a safe value to the expression and checking memory. If memory hardening causes the storage memory to fail to be assigned a value, the corresponding memory value will be read as a hardened value, which will also cause the final check word to be wrong, and the system will be redirected to the safe side.

[0058] The calculation method used in steps (2) and (b) is a summation operation based on 32-bit polynomial division. The actual algorithm used is the correlation PD algorithm based on NISAL code, which has an extremely low undetectability rate for errors in the order of operations or incomplete operations.

[0059] The step (d) described above uses a forward operation based on polynomial division, which can calculate a unique check word based on the compensation value and the "check code operation sum".

[0060] The step (4) uses a reverse operation based on polynomial division, which can calculate a unique compensation value based on the target verification word and the "check code operation and sum"; it is the reverse algorithm of the algorithm in (d).

[0061] Figure 1 and Figure 2 The diagram illustrates the specific flow of the encoding-based method for checking the order and integrity of operations according to the present invention. The following sections describe each step in both offline and online processing in detail:

[0062] like Figure 1 As shown, the offline computing part:

[0063] In Seq1, the logical operation table definition file is read in, the first expression is read in according to the agreed text file format, memory is dynamically allocated, the corresponding data structure is generated, and the temporary pointer points to the data structure of the first expression.

[0064] In Seq2, check if the temporary pointer in Seq1 is null. If it is not null, proceed to Seq3 for processing. If it is null, proceed to Seq5 for processing. If the temporary pointer is null, it means that the expression has been read completely or memory allocation has failed.

[0065] In Seq3, the PD operation is performed. The current "check code checksum" midValue and the current expression redundancy code false value are used as inputs to the PD operation; the result of the PD operation is reassigned to midValue.

[0066] In Seq4, the next expression is read in, memory is dynamically allocated, the corresponding data structure is generated, and a temporary pointer points to the data structure of the first expression; then the process jumps to the Seq2 step and executes in a loop.

[0067] In Seq5, after the entire expression has been read, the "checksum" is assigned to the variable PDSum.

[0068] In Seq6, the compensation value rectifyValue is calculated by using the PD_Reverse operation with the input parameters PDsum and the selected check word THE_CHKW.

[0069] In Seq7, the compensation values ​​calculated by the above process, along with other information, are stored in the offline data configuration file.

[0070] like Figure 2 As shown, the online calculation part:

[0071] In step 1, the offline configuration file is read into memory, and the data structure pointer of the first expression is obtained according to the data structure of the offline configuration file;

[0072] In step 2, it is determined whether the pointer in step 1 is null. If it is not null, proceed to step 3 for processing; if it is null, proceed to step 5 for processing. If the pointer is null, it means that the expression has been read.

[0073] In step 3, the memory storage of the expression result in the structure pointer is assigned a false value;

[0074] In step 4, the PD operation is performed, the value stored at the memory address of the expression result is read, and the current "checksum" midValue is used as the input for the PD operation; the result of the PD operation is reassigned to midValue.

[0075] In step 5, the actual calculation of the expression is performed, and the result stored in memory is updated based on the actual calculation.

[0076] In step 6, based on the linked list design in the data structure, the data structure pointer for the next expression is found; then, the process jumps back to step 2 and executes in a loop.

[0077] In step 7, all expressions are processed, and the "checksum" is assigned to the variable PDSum.

[0078] In step 8, the verification word CAL_CHKW is calculated using PD calculation, with the input parameters being PDsum and the compensation value rectifyValue from the offline configuration data.

[0079] In step 9, a decision is made based on CAL_CHKW whether to perform a safety-guided process; then, after other processing tasks within the cycle, the process repeats periodically.

[0080] This invention has the advantages of effectively checking and ensuring the "order and integrity of operations", meeting stringent security requirements, and being applicable not only to security systems with single-core CPUs, but also to cloud security systems with dual-core and multi-core CPUs (such as cloud interlocking systems).

[0081] The above is an introduction to the method embodiments. The following embodiments using electronic devices and storage media will further illustrate the solution of the present invention.

[0082] The electronic device of this invention includes a central processing unit (CPU), which can perform various appropriate actions and processes according to computer program instructions stored in read-only memory (ROM) or loaded from a storage unit into random access memory (RAM). The RAM may also store various programs and data required for device operation. The CPU, ROM, and RAM are interconnected via a bus. Input / output (I / O) interfaces are also connected to the bus.

[0083] Multiple components in the device are connected to the I / O interface, including: input units such as keyboards and mice; output units such as various types of displays and speakers; storage units such as disks and optical discs; and communication units such as network interface cards (NICs), modems, and wireless transceivers. The communication unit allows the device to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0084] The processing unit performs the various methods and processes described above, such as the methods of the present invention. For example, in some embodiments, the methods of the present invention may be implemented as computer software programs tangibly contained in a machine-readable medium, such as a storage unit. In some embodiments, part or all of the computer program may be loaded and / or installed on the device via ROM and / or a communication unit. When the computer program is loaded into RAM and executed by the CPU, one or more steps of the methods of the present invention described above may be performed. Alternatively, in other embodiments, the CPU may be configured to execute the methods of the present invention by any other suitable means (e.g., by means of firmware).

[0085] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), System-on-Chip (SoCs), Complex Programmable Logic Devices (CPLDs), and so on.

[0086] The program code used to implement the methods of the present invention can be written in any combination of one or more programming languages. This program code can be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code can be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine, server, or cloud platform.

[0087] In the context of this invention, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0088] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for checking the operation order and integrity of rail transit signals based on coding, characterized in that, The method first calculates the compensation value using an offline tool, then calculates the verification word using an online tool in conjunction with the compensation value, and finally provides the verification word to the system for subsequent security processing. The specific process by which the offline tool calculates the compensation value is as follows: Step S101: Poll all expressions to obtain their respective security-side redundancy codes; Step S102: Starting from the first expression, calculate a new "check code sum" using the current "check code sum" and the current expression's security-side redundancy code; Step S103: Continue in this manner until all expressions have been processed, and calculate the final "check code sum". Step S104: Calculate the verification word compensation value based on the selected verification word value and the "check code operation sum" in step S103; Step S105: Store the verification word compensation value and the expression security side redundancy code in the offline configuration for online calculation. The online tool calculates the verification characters as follows: Step S201: Poll all expressions to obtain the memory storage address of the corresponding expression result and the information of the security redundancy code; Step S202: Starting from the first expression, assign the result storage memory to the corresponding security redundancy code of the expression, then read the stored value from the address and calculate the new "check code sum" with the existing "check code sum", then perform the expression operation, and then update the storage memory to the actual operation result; Step S203: Continue in this manner until all expressions have been processed, and calculate the final "check code sum". Step S204: Calculate the verification word based on the compensation value calculated by the offline tool and the "check code operation sum" in step S203; Step S205: The calculated verification word is used by the system for subsequent security processing.

2. The method for checking the operation order and integrity of rail transit signals based on coding according to claim 1, characterized in that, Before the calculation, the offline tool uses a predefined logical operation table, which defines the order of operations and contains all the operation expressions.

3. The method for checking the operation order and integrity of rail transit signals based on coding according to claim 1, characterized in that, The offline tool reads each expression and substitutes it with a check code, where the check code indicates whether the expression has been processed or not.

4. The method for checking the operation order and integrity of rail transit signals based on coding according to claim 1, characterized in that, The offline tool described herein uses a dual-chain tool approach in accordance with signal system security standards.

5. The method for checking the operation order and integrity of rail transit signals based on coding according to claim 1, characterized in that, The calculation methods in steps S102 and S202 are based on the summation operation of 32-digit polynomial division.

6. The method for checking the operation order and integrity of rail transit signals based on coding according to claim 1, characterized in that, Step S202 includes both security-side assignment and memory checking functions for the expression. If memory hardening causes the storage memory to fail to be assigned a value, the corresponding memory value read out will be a hardened value, resulting in an error in the final verification word, and the system will redirect to the security side.

7. The method for checking the operation order and integrity of rail transit signals based on coding according to claim 1, characterized in that, Step S204 uses forward operation based on polynomial division, and a unique verification word can be calculated based on the compensation value and the "check code operation sum".

8. The method for checking the operation order and integrity of rail transit signals based on coding according to claim 1, characterized in that, Step S104 uses the inverse operation based on polynomial division, which calculates a unique compensation value based on the target verification word and the "check code operation sum".

9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the program, it implements the method as described in any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 1 to 8.

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