Staged gate voltage control

Abstract

An electro-optic display and a method of driving the same are disclosed. The electro-optic display includes a layer of electrophoretic material disposed between a common electrode and a backplane. The backplane includes an array of pixel electrodes, each pixel electrode coupled to a pixel transistor. The controller provides a time-varying voltage to the gate line, the source line, and the common electrode of each pixel transistor. The driving method includes applying a first stage voltage to the gate line. The first stage voltage has a first magnitude that is substantially half of a gate low voltage required to place the pixel transistor in a non-conductive state. The first stage voltage is maintained on the gate line for a first period of time. Then, a second stage voltage is applied to the gate line, where the second stage voltage has a second magnitude that is substantially the gate low voltage used to place the pixel transistor in the non-conductive state.

Description

(19) State Intellectual Property Office (12) Invention Patent Application (10) Application Publication Number (43) Application Publication Date (21) Application Number 202480061121.9 (22) Application Date 2024.10.02 (30) Priority Data 63 / 588290 2023.10.05 US (85) PCT International Application Entering National Phase Date 2026.03.24 (86) PCT International Application Application Data PCT / US2024 / 049557 2024.10.02 (87) PCT International Application Publication Data WO2025 / 076061 EN 2025.04.10 (71) Applicant Eink Company Address Massachusetts, USA (72) Inventors K.R. Amundsen Y. Ben-Doff (74) Patent Agency Beijing Panhua Weiye Intellectual Property Agency Co., Ltd. 11280 Patent Attorney Wang Bo (51) Int.Cl. G09G 3 / 34 (2006.01) (54) Invention Title: Staged Gate Voltage Control (57) Abstract: Discloses an electro-optic display and a driving method thereof. The electro-optic display includes a layer of electrophoretic material disposed between a common electrode and a backplane. The backplane includes a pixel electrode array, each pixel electrode being coupled to a pixel transistor. A controller provides a time-varying voltage to the gate line, source line, and common electrode of each pixel transistor. The driving method includes applying a first stage voltage to the gate line. The first stage voltage has a first amplitude, which is approximately half of the gate low voltage required to place the pixel transistor in a non-conducting state. The first stage voltage is maintained on the gate line for a first time period. Then, a second stage voltage is applied to the gate line, wherein the second stage voltage has a second amplitude, which is approximately the gate low voltage required to place the pixel transistor in the non-conducting state. Claims 2 pages, Description 19 pages, Drawings 8 pages, CN 121889848 A 2026.04.17 CN 1 21 88 98 48 A 1. A method for driving an electro-optic display, the electro-optic display comprising an electrophoretic material layer disposed between a common electrode and a backplane, the backplane comprising a pixel electrode array, wherein each pixel electrode is coupled to a pixel transistor comprising a source electrode, a gate electrode, and a drain electrode, wherein the gate electrode is coupled to a gate line, the source electrode is coupled to a source line, and the drain electrode is coupled to the pixel electrode, wherein a controller provides a time-varying voltage to the gate line, the source line, and the common electrode, the driving method comprising: applying a first stage voltage to the gate line, wherein the first stage voltage has a first amplitude, the first amplitude being approximately half of a gate low voltage used to place the pixel transistor in a non-conducting state;1. The method of claim 1, wherein the first stage voltage is maintained on the gate line for a first time period; and a second stage voltage is applied to the gate line, wherein the second stage voltage has a second amplitude, the second amplitude being approximately the gate low voltage used to place the pixel transistor in the non-conducting state. 2. The method of claim 1, wherein the amplitude of the gate low voltage is approximately -35V. 3. The method of claim 1, wherein the pixel transistor is an n-type transistor and the gate low voltage is negative. 4. The method of claim 1, wherein the pixel transistor is a p-type transistor and the gate low voltage is positive. 5. The method of claim 1, wherein the first time period is between 30 ms and 50 ms. 6. The method of claim 1, wherein the second time period is between 30 ms and 50 ms. 7. The method of claim 1, wherein applying the first stage voltage to the gate line causes a first voltage artifact on the electrophoretic material layer. 8. The method of claim 7, wherein the first time period is greater than or equal to the discharge time of the first voltage artifact. 9. The method of claim 1, wherein applying the second stage voltage to the gate line causes a second voltage artifact on the electrophoretic material layer. 10. The method of claim 9, wherein the second time period is greater than or equal to the discharge time of the second voltage artifact. 11. An electro-optic display, comprising: a transparent common electrode; a backplate including an array of pixel electrodes; an electro-optic material layer disposed between the common electrode and the array of pixel electrodes, wherein each pixel electrode is coupled to a pixel transistor including a source electrode, a gate electrode, and a drain electrode, and wherein the gate electrode is coupled to a gate line, the source electrode is coupled to a source line, and the drain electrode is coupled to the pixel electrode; and a controller capable of applying a time-varying voltage to the gate line, the source line, and the common electrode, the controller being configured to: apply a first stage voltage to the gate line, wherein the first stage voltage has a first amplitude, the first amplitude being approximately half of a gate low voltage used to place the pixel transistor in a non-conducting state; maintain the first stage voltage on the gate line for a first time period; and apply a second stage voltage to the gate line, wherein the second stage voltage has a second amplitude, the second amplitude being approximately half of the gate low voltage used to place the pixel transistor in the non-conducting state. 12. The electro-optic display of claim 11, wherein the amplitude of the gate low voltage is approximately -35V. (Claims 1 / 2 page 2 CN 121889848 A) 13. The electro-optic display of claim 11, wherein the pixel transistor is an n-type transistor, and the gate low voltage has a negative polarity.14. The electro-optic display of claim 11, wherein the pixel transistor is a p-type transistor and the gate low voltage has a positive polarity. 15. The electro-optic display of claim 11, wherein the first time period is between 30 ms and 50 ms. 16. The electro-optic display of claim 11, wherein the second time period is between 30 ms and 50 ms. 17. The electro-optic display of claim 11, wherein applying the first stage voltage to the gate line causes a first voltage artifact on the electrophoretic material layer. 18. The electro-optic display of claim 17, wherein the first time period is greater than or equal to the discharge time of the first voltage artifact. 19. The electro-optic display of claim 11, wherein applying the second stage voltage to the gate line causes a second voltage artifact on the electrophoretic material layer. 20. The electro-optic display of claim 19, wherein the second time period is greater than or equal to the discharge time of the second voltage artifact. Claims 2 / 2 Page 3 CN 121889848 A Cross-Reference to Related Applications for Staged Gate Voltage Control

[0001] This application claims priority to U.S. Provisional Application No. 63 / 588,290, filed October 5, 2023, the entire contents of which are incorporated herein by reference. Furthermore, the entire contents of any patent, publication, or other publication cited herein are also incorporated herein by reference in their entirety. Technical Field

[0002] The subject matter disclosed herein relates to electro-optic displays and methods for driving electro-optic displays. Specifically, the subject matter disclosed herein relates to electro-optic displays and methods for driving electro-optic displays, the method of powering on and off a gate voltage to reduce or eliminate the amplitude of voltage artifacts induced on the electrophoretic medium of an active matrix display. Background Art

[0003] Electro-optic displays typically comprise a layer of electro-optic material. The term "electro-optic material" is used herein in its conventional sense in the field of imaging, referring to a material having a first display state and a second display state that are different in at least one optical property, which can be changed from the first display state to the second display state by applying an electric field to the material. While optical properties generally refer to color perceptible to the naked eye, they can also be other optical properties, such as light transmittance, reflectance, luminance, or, for displays intended for machine reading, pseudo-color manifested by changes in reflectance at electromagnetic wavelengths outside the visible light range.

[0004] The terms "bistable" and "bistable" are used herein in their conventional sense in the art, referring to a display comprising display elements having a first display state and a second display state that are different in at least one optical property, and such that either given element is driven to present its first display state or second display state by an address pulse of finite duration.After the state is reached, the state will persist for at least several times (e.g., at least four times) the minimum duration of the addressing pulse required to change the state of the display element. U.S. Patent No. 7,170,670 shows that some particle-based electrophoretic displays capable of displaying grayscale are stable not only in their extreme black and white states but also in their intermediate gray states, as are some other types of electro-optic displays. This type of display is aptly referred to as “multistable” rather than bistable, but for convenience, the term “bistable” may be used herein to encompass both bistable and multistable displays.

[0005] Regardless of whether the electro-optic medium used is bistable, to achieve a high-resolution display, individual pixels of the display must be addressable and not interfered with by adjacent pixels. One way to achieve this is to provide an array of nonlinear elements (e.g., transistors or diodes), with each pixel associated with at least one nonlinear element to produce an “active matrix” display. The addressing electrode or pixel electrode that addresses a pixel is connected to a suitable voltage source via the associated nonlinear element. Although it is arbitrary in nature and the pixel electrode can be connected to the source of a transistor, typically when the nonlinear element is a transistor, the pixel electrode is connected to the drain of the transistor, and this arrangement will be assumed in the following description.

[0006] Conventionally, in high-resolution arrays, pixels are arranged in a two-dimensional array of rows and columns such that any particular pixel is uniquely defined by the intersection of a designated row and a designated column. The sources of all transistors in each column are connected to a single column electrode, while the gates of all transistors in each row are connected to a single row electrode; similarly, it is conventional to assign sources to rows and gates to columns, but are arbitrary in nature and can be interchanged if desired. The row electrodes are connected to a row drive circuitry system that essentially ensures that only one row is selected at any given time, i.e., a voltage is applied to the selected row electrode to ensure that all transistors in the selected row are in the on state, while a voltage is applied to all other rows to ensure that all transistors in these unselected rows remain in the off state. Column electrodes are connected to a column drive circuitry that applies a selected voltage to each column electrode to drive the pixels in the selected row to their desired optical state. (This voltage is relative to a common front electrode, which is typically positioned on the side of the electro-optical medium opposite the nonlinear array and extends as a substantially flat layer across the entire display.) After a preselection interval called the “line addressing time,” the selected row is deselected, the next row is selected, and the voltage on the column driver is changed, thus writing to the next line of the display. This process is repeated to write to the entire display line by line.

[0007] Typically, electro-optic displays are enclosed by a frame or bezel to conceal the electrical connections required for the display's row and column drive circuitry, which are typically laid out along the perimeter of the display. However, for some applications, it is preferable to make almost the entire visible area of ​​the electro-optic display optically effective. As an example, active billboards can be created by splicing multiple electro-optic displays together to create a large-size display. Preferably, in such applications, the gaps between the spliced ​​displays are minimized. Furthermore, even for monolithic panel displays, it is generally preferable to minimize the size of the display frame or bezel that overlaps with the effective area of ​​the display to maximize the visible area.

[0008] To meet these requirements, one strategy for reducing or eliminating the need for bezels or edge frames that extend beyond the pixels themselves is to lay out numerous traces or wires (e.g., "T-wires") controlling the switching of the pixel thin-film transistors ("TFTs") on the back of the display panel (i.e., on the opposite side of the display pixels on the front of the panel) and extend to the front of the display panel through one or more vias (sometimes referred to as "through holes" or "conductive vias"). For example, such T-wires can be routed along the back of the display panel, perpendicular to the TFT gate lines on the front of the display panel, to provide an electrical connection to the row selection signal of the driver IC, and vias can be used to connect each gate line to its respective row selection signal T-wire.

[0009] Typically, a single T-wire and a single via are used to establish a connection to each individual gate line, but multiple T-wires may be present near each pixel of the display. Since the display substrate is typically made of a non-conductive material, capacitance is generated between the pixel electrode and the nearby T-wires. This capacitive coupling can lead to undesirable optical defects, such as inconsistent optical characteristics or responses in different areas of the display due to certain operations.

[0010] For example, before updating an electrophoretic display, any voltage plane or data and control signals used to drive the pixels of an active matrix display must be adjusted from a “standby voltage” or downvoltage (e.g., ground voltage) of approximately zero volts to a known initial voltage value. As an example, the gate line of each pixel TFT in the active matrix can be driven from a power-down voltage to a “gate low voltage,” which is the voltage typically applied to the gate lines of the “non-addressed” or deselected rows of the active matrix during display updates.

[0011] Conventional display driving techniques initially drive the pixel TFT gate lines continuously from a power-down voltage to a gate low voltage, the magnitude or voltage value of which is sufficiently negative to keep the pixel TFT in a non-conductive state. After an electrophoretic display update is complete, the voltage applied to the gate lines typically returns to the controller ground voltage (e.g., approximately) in a similar manner.Zero volts), that is, the pixel TFT gate line is continuously driven from the gate low voltage back to the next power-up voltage.

[0012] The gate low voltage is fed to the gate line of the active matrix display through the display selection driver circuitry. When the gate low voltage is adjusted from zero volts to a negative value in preparation for an update, the gate line and any associated T-wires used to connect to the gate line are also adjusted in the same way. Because these gate lines and associated T-wires are either capacitively coupled to the pixel electrode or directly coupled to the electrophoretic layer through the dielectric layer in the backplane, the electrophoretic layer will experience a transient negative impulse or voltage artifact during this "power-on" event. After the update, when the gate low voltage is adjusted back to zero volts, the electrophoretic layer will experience a positive voltage transient or artifact. Both of these voltage artifacts can cause the optical state of the electrophoretic medium near the artifact to shift and degrade.

[0013] Conventional techniques seek to mitigate transient voltage surges when powering down the display voltage plane and data and control signals by using components configured to slowly dissipate the surges (e.g., resistors located within a circuitry controlling the voltage applied to each pixel). However, such solutions are inherently passive and cannot adapt to demand fluctuations due to changes in environmental conditions or differences in the electrical characteristics of the electrophoretic layer. Furthermore, such solutions cannot address voltage artifacts induced when signals such as gate lines are set to an initial state before updating the display. Summary of the Invention

[0014] Therefore, there is a need for an electro-optic display that powers on and off low gate voltages in a manner that reduces the magnitude of voltage artifacts induced in the electrophoretic layer of an active matrix display, and a method for driving the electro-optic display.

[0015] Accordingly, in one aspect, the subject matter disclosed herein includes a method for driving an electro-optic display. The electro-optic display includes an electrophoretic material layer disposed between a common electrode and a backplane. The backplane includes an array of pixel electrodes. Each pixel electrode is coupled to a pixel transistor including a source electrode, a gate electrode, and a drain electrode. The gate electrode is coupled to a gate line, the source electrode is coupled to a source line, and the drain electrode is coupled to a pixel electrode. A controller provides a time-varying voltage to the gate line, source line, and common electrode. The driving method includes applying a first-stage voltage to the gate line, wherein the first-stage voltage has a first amplitude, the first amplitude being approximately half of a gate low voltage used to place the pixel transistor in a non-conducting state. The driving method further includes maintaining the first-stage voltage on the gate line for a first time period and applying a second-stage voltage to the gate line, wherein the second-stage voltage has a second amplitude, the second amplitude being approximately half of a gate low voltage used to place the pixel transistor in the non-conducting state.

[0016] In another aspect, the subject matter disclosed herein includes an electro-optic display comprising a light-transmitting common electrode.The electro-optic display also includes a backplane comprising a pixel electrode array. The electro-optic display further includes an electro-optic material layer disposed between the common electrode and the pixel electrode array, wherein each pixel electrode is coupled to a pixel transistor comprising a source electrode, a gate electrode, and a drain electrode, and wherein the gate electrode is coupled to a gate line, the source electrode is coupled to a source line, and the drain electrode is coupled to the pixel electrode. The electro-optic display also includes a controller capable of applying a time-varying voltage to the gate line, the source line, and the common electrode. The controller is configured to apply a first-stage voltage to the gate line, wherein the first-stage voltage has a first amplitude, the first amplitude being approximately half of a gate low voltage used to place the pixel transistor in a non-conducting state. The controller is further configured to maintain the first-stage voltage on the gate line for a first time period and apply a second-stage voltage to the gate line, wherein the second-stage voltage has a second amplitude, the second amplitude being approximately a gate low voltage used to place the pixel transistor in a non-conducting state.

[0017] All aspects disclosed herein may include additional features. In some embodiments, the amplitude of the gate low voltage is approximately -35V. In some embodiments, the pixel transistor is an n-type transistor and the gate low voltage has a negative polarity. In some embodiments, the pixel transistor is a p-type transistor and the gate low voltage has a positive polarity.

[0018] In some embodiments, the first time period is between 30 ms and 50 ms. In some embodiments, the second time period is between 30 ms and 50 ms.

[0019] In some embodiments, applying a first stage voltage to the gate line causes a first voltage artifact on the electrophoretic material layer. In some embodiments, the first time period is greater than or equal to the discharge time of the first voltage artifact.

[0020] In some embodiments, applying a second stage voltage to the gate line causes a second voltage artifact on the electrophoretic material layer. In some embodiments, the second time period is greater than or equal to the discharge time of the second voltage artifact. Brief Description of the Drawings

[0021] Various aspects and embodiments of this application will be described with reference to the following drawings. It should be understood that the drawings are not necessarily drawn to scale.

[0022] FIG1A is a representative cross-section of a four-particle electrophoretic display in which the electrophoretic medium is encapsulated in a capsule. The structure of Figure 1A can be used in multi-particle electrophoretic media that simultaneously contain both reflective and hypochromic pigment particles.

[0023] Figure 1B is a representative cross-section of a four-particle electrophoretic display, in which the electrophoretic medium is encapsulated in microcells. The structure of Figure 1B can be used in multi-particle electrophoretic media that simultaneously contain both reflective and hypochromic pigment particles.

[0024] Figure 2 is a schematic diagram of an exemplary driving system for controlling the voltage supplied to the pixel electrodes in an active matrix device. The resulting driving voltage can be used to set the optical state of the multi-particle electrophoretic medium.

[0025] FIG3 illustrates an exemplary electrophoretic display including a display module. The electrophoretic display also includes a processor, non-transitory memory, one or more power supplies, and a controller. The electrophoretic display may also include sensors to allow the electrophoretic display to adjust operating parameters based on the surrounding environment (e.g., temperature and lighting).

[0026] FIG4A is a schematic diagram illustrating an exemplary gate and source signal layout for an active matrix backplane of an electro-optic display according to the subject matter disclosed herein.

[0027] FIG4B is a schematic diagram of an exemplary display pixel according to the subject matter disclosed herein.

[0028] FIG5A is a signal waveform diagram illustrating voltage artifacts experienced by the electrophoretic material when a low voltage is applied to the gate in a single stage using a conventional driving method.

[0029] FIG5B is a signal waveform diagram illustrating voltage artifacts experienced by the electrophoretic material when a low voltage is applied to the gate in two stages according to the driving method disclosed herein.

[0030] FIG5C is a signal waveform diagram showing the voltage artifact experienced by the electrophoretic material when the gate is powered on at a low voltage in three stages according to the driving method disclosed herein.

[0031] FIG6A is a signal waveform diagram showing the voltage artifact experienced by the electrophoretic material when the gate is powered on at a low voltage in a single stage using a conventional driving method.

[0032] FIG6B is a signal waveform diagram showing the voltage artifact experienced by the electrophoretic material when the gate is powered on at a low voltage in two stages according to the driving method disclosed herein.

[0033] FIG6C is a signal waveform diagram showing the voltage artifact experienced by the electrophoretic material when the gate is powered on at a low voltage in three stages according to the driving method disclosed herein. Detailed Description

[0034] The application of electro-optic display technology is expanding beyond “typical” display applications such as television screens and monitors to include display products such as e-books, product labels, retail shelf labels, device monitoring indicators, watches, signage, and promotional or advertising displays. Typically, electro-optic displays are enclosed by a frame or bezel to conceal the electrical connections that are usually laid out along the perimeter of the display. In some applications, particularly large video wall displays, it is generally preferable to make the entire viewable area of ​​the electro-optic display optically effective; for example, active billboards made by splicing multiple electro-optic displays together to create a large-size display. In such applications, consumer preferences favor making the entire viewing surface of each individual display optically effective and minimizing the gaps between the spliced ​​displays. When properly handled, the spliced ​​display presents the appearance of a single, continuous display. Specification 4 / 19 pages 7 CN 121889848 A

[0035] An electro-optic display (“EPD”) is an electro-optic display that changes color by altering the position of one or more charged colored particles relative to a light-transmitting viewing surface. Such electro-optic displays are often referred to as “electronic paper” or “ePaper”.Because the resulting display has high contrast and can be read in sunlight, much like ink on paper. Electrophoretic displays have been widely adopted in e-readers because they provide a book-like reading experience, consume little power, and allow users to carry a library of hundreds of books in a lightweight handheld device. Such devices are increasingly being used to display outdoor (OOH) digital content, such as shelf labels, outdoor advertising, and traffic signs.

[0036] For many years, electrophoretic displays have contained only two types of charged colored particles, black and white. (Of course, “colored” as used herein includes both black and white.) White particles are typically light-scattering and contain, for example, titanium dioxide, while black particles are absorbent across the entire visible spectrum and may contain carbon black or absorbent metal oxides, such as copper chromite. In its simplest sense, a black-and-white electrophoretic display requires only a light-transmitting electrode, a back electrode, and an electrophoretic medium containing white and black particles with opposite charges at the viewing surface. When a voltage of one polarity is provided, the white particles move to the viewing surface, and when a voltage of the opposite polarity is provided, the black particles move to the viewing surface. If the back electrode contains controllable regions (pixels)—whether segmented electrodes or an active matrix of pixel electrodes controlled by transistors—a pattern can be electronically displayed on the viewing surface. The pattern can be, for example, text in a book.

[0037] Recently, electrophoretic displays with a variety of color options have become commercially available, including three-color displays (black, white, red; black, white, yellow) and four-color displays (black, white, red, yellow). Similar to the operation of a black-and-white electrophoretic display, an electrophoretic display with three or four reflective pigments operates similarly to a simple black-and-white display because the desired colored particles are driven onto the viewing surface. The driving scheme is far more complex than with only black and white, but ultimately, the optical function of the particles is the same.

[0038] Advanced Color Electronic Paper (ACeP™) also contains four particles, but the cyan, yellow, and magenta particles are subtractive rather than reflective, thus allowing thousands of colors to be produced at each pixel. This color processing is functionally equivalent to printing methods long used in offset printing and inkjet printers. A given color is produced by using the correct proportions of cyan, yellow, and magenta on a bright white paper background. In the ACeP example, the relative positions of cyan, yellow, magenta, and white particles with respect to the observation surface determine the color of each pixel. While this type of electrophoretic display allows for thousands of colors at each pixel, the key is to carefully control the position of each pigment (50 to 500 nanometers in size) within a working space approximately 10 to 20 micrometers thick. Clearly, variations in pigment position will result in an incorrect color being displayed at a given pixel. Therefore, this system requires precise voltage control. Further details about this system can be found in the following U.S. patent.All of these patents are incorporated herein by reference in their entirety: U.S. Patent Nos. 9,361,836, 9,921,451, 10,276,109, 10,353,266, 10,467,984, 10,593,272, and 10,657,869.

[0039] The term “gray state” is used herein in its conventional sense in the field of imaging, referring to a state between the two extreme optical states of a pixel, and does not necessarily imply a black-and-white transition between these two extreme states. For example, several of the Einkel patents and publications mentioned below describe electrophoretic displays with extreme states of white and dark blue, such that the intermediate gray state would actually be light blue. In fact, as previously stated, a change in optical state may not be a color change at all. The terms “black” and “white” can be used below to refer to the two extreme optical states of a display and should be understood to generally include extreme optical states that are not strictly black and white, such as the aforementioned white and dark blue states.

[0040] The term “impulse,” when used to refer to driving an electrophoretic display, is here used to refer to the integral of the voltage applied during driving the display with respect to time.

[0041] Particles that absorb, scatter, or reflect light (whether over a wide band or at a selected wavelength) are referred to herein as colored particles or pigment particles. Various light-absorbing or reflecting materials other than pigments (strictly defined as insoluble colored materials), such as dyes or photonic crystals, can also be used in the electrophoretic media and displays of the present invention.

[0042] Particle-based electrophoretic displays have been a subject of extensive research and development for many years. In such displays, multiple charged particles (sometimes called pigment particles) move through a fluid under the influence of an electric field. Compared to liquid crystal displays, electrophoretic displays can have excellent brightness as well as contrast, wide viewing angles, bistable states, and low power consumption. However, problems with the long-term image quality of these displays have hindered their widespread application. For example, the particles constituting an electrophoretic display are prone to settling, resulting in a short lifespan for these displays.

[0043] As mentioned above, the electrophoretic medium requires the presence of a fluid. In most prior art electrophoretic media, this fluid is a liquid, but gaseous fluids can also be used to produce the electrophoretic medium; see, for example, Kitamura, T. et al., "Electrical toner movement for electronic paper-like display", IDW Japan, 2001, paper number HCS1-1; and Yamaguchi, Y. et al., "Toner display using insulative particles"."Charged triboelectrically", IDW Japan, 2001, paper number AMD4-4. See also U.S. Patent Nos. 7,321,459 and 7,236,291. When such gas-based electrophoretic media are used in a direction that allows such sedimentation, for example in a sign where the medium is set in a vertical plane, they appear to be susceptible to the same type of problems caused by particle sedimentation as liquid-based electrophoretic media. Indeed, particle sedimentation appears to be more severe in gas-based electrophoretic media than in liquid-based electrophoretic media because the lower viscosity of gaseous suspensions allows electrophoretic particles to settle more rapidly compared to liquid suspensions.

[0044] Numerous patents and applications assigned to or in the name of MIT and Einkel describe various techniques used in encapsulated electrophoresis and other electro-optic media. Such encapsulated media comprise a number of small capsules, each capsule itself containing an inner phase containing particles that are electrophoretically mobile in a fluid medium, and a capsule wall surrounding said inner phase. Typically, the capsule itself is held within a polymer adhesive to form a coherent layer between the two electrodes. The technologies described in these patents and applications include:

[0045] (a) electrophoretic particles, fluids, and fluid additives; see, for example, U.S. Patent Nos. 7,002,728 and 7,679,814;

[0046] (b) capsules, adhesives, and encapsulation processes; see, for example, U.S. Patent Nos. 6,922,276 and 7,411,719;

[0047] (c) microcell structures, wall materials, and methods of forming microcells; see, for example, U.S. Patent Nos. 7,072,095 and 9,279,906;

[0048] (d) methods for filling and sealing microcells; see, for example, U.S. Patent Nos. 7,144,942 and 7,715,088;

[0049] (e) films and subassemblies containing electro-optic materials; see, for example, U.S. Patent Nos. 6,982,178 and 7,839. 564;

[0050] (f) Backplate, adhesive layer and other auxiliary layers for a display, and methods thereof; see, for example, U.S. Patent Nos. 7,116,318 and 7,535,624;

[0051] (g) Color formation and color adjustment; see, for example, U.S. Patent Nos. 6,017,584; 6,545,797; 6,664,944; 6,788,452; 6,864,875; 6,914,714; 6,972,893; 7,038,656; 7,038,670; 7,046,228; 7,052,571; 7,075,502; 7,167,155; 7,385,751; 7,492,505; 7 667,684;7 ,684 ,108;7 ,791 , 789;7,800,813;7,821,702;7,839,564;7,910,175;7,952,790;7,956,841;7,982,941;8, 040,594;8,054 ,526;8,098,418;8,159,636;8,213,076;8,363,299;8,422,116;8,441 , Instruction manual 6 / 19 page 9 CN 121889848 A 714;8,441,716;8,466,852;8,503,063;8,576,470;8,576,475;8,593,721;8,605,354;8,649,084;8,670,174;8,704 ,756;8,717 ,664;8,786,935;8,797 ,634;8,810,899;8,830, 559;8,873,129;8,902,153;8,902,491;8,917,439;8,964,282;9,013,783;9,116,412;9, 146,439;9,164 ,207; 9,170,467; 9,170,468; 9,182,646; 9,195,111; 9,199,441; 9,268, 191; 9,285,649; 9,293,511; 9,341,916; 9,360,733; 9,361,836; 9,383,623; and 9,423,666; and U.S. Patent Application Publication Nos. 2008 / 0043318; 2008 / 0048970; 2009 / 0225398; 2010 / 0156780; 2011 / 0043543; 2012 / 0326957; 2013 / 0242378; 2013 / 0278995; 2014 / 0055840; 2014 / 0078576; 2014 / 0340430; 2014 / 0340736; 2014 / 0362213; 2015 / 0103394; 2015 / 0118390; 2015 / 0124345; 2015 / 0198858; 2015 / 0234250; 2015 / 0268531; 2015 / 0301246; 2016 / 0011484; 2016 / 0026062; 2016 / 0048054; 2016 / 0116816; 2016 / 0116818; and 2016 / 0140909;

[0052] (h)Methods for driving a display; see, for example, U.S. Patents 5,930,026; 6,445,489; 6,504,524; 6,512,354; 6,531,997; 6,753,999; 6,825,970; 6,900,851; 6,995,550; 7,012,600; 7,023,420; 7,034,783; 7,061,166; 7,061,662; 7,116,466; 7,119,772; 7,177,066; 7,193, 625;7,202,847;7,242,514;7,259,744;7,304,787;7,312,794;7,327,511;7,408,699;7, 453,445;7,492,339;7,528,822;7,545,358;7,583,251;7,602,374;7,612,760;7,679, 599;7,679,813;7,683,606;7,688,297;7,729,039;7,733,311;7,733,335;7,787,169;7, 859,742;7 ,952,557;7 ,956,841;7 ,982,479;7 ,999,787;8,077 ,141;8,125,501;8,139, 050;8,174,490;8,243,013;8,274,472;8,289,250;8,300,006;8,305,341;8,314,784;8, 373,649;8,384 ,658;8,456,414;8,462,102;8,514 ,168;8,537 ,105;8,558,783;8,558, 785;8,558,786;8,558,855;8,576,164;8,576,259;8,593,396;8,605,032;8,643,595;8,665,206;8,681,191;8,730,153;8,810,525;8,928,562;8,928,641;8,976,444;9,013,394;9,019,197;9,019,198;9,019,318;9,082,352;9,171,508;9,218,773;9,224,338;9,224,342;9,224 ,344;9,230,492;9,251 ,736;9,262,973;9,269,311;9,299,294;9,373, 289;9 ,390,066; 9,390,661; and 9,412,314; and U.S. Patent Application Publication Nos. 2003 / 0102858; 2004 / 0244652; 2005 / 0253777; 2007 / 0091418; 2007 / 0103427; 2007 / 0176912; 2008 / 0024429; 2008 / 0024482; 2008 / 0136774; 2008 / 0291129; 2008 / 0303780; 2009 / 0174651; 2009 / 0195568; 2009 / 0322721; 2010 / 0194733; 2010 / 0194789; 2010 / 0220121; 2010 / 0265561; 2010 / 0283804; 2011 / 0063314; 2011 / 0175875; 2011 / 0193840; 2011 / 0193841; 2011 / 0199671; 2011 / 0221740; 2012 / 0001957; 2012 / 0098740; 2013 / 0063333; 2013 / 0194250; 2013 / 0249782; 2013 / 0321278; 2014 / 0009817; 2014 / 0085355; 2014 / 0204012; 2014 / 0218277; 2014 / 0240210; 2014 / 0240373; 2014 / 0253425; 2014 / 0292830; 2014 / 0293398; 2014 / 0333685; 2014 / 0340734; 2015 / 0070744; 2015 / 0097877; 2015 / 0109283; 2015 / 0213749; 2015 / 0213765; 2015 / 0221257; 2015 / 0262255; 2015 / 0262551; 2016 / 0071465; 2016 / 0078820; 2016 / 0093253; 2016 / 0140910; and 2016 / 0180777 (these patents and applications may be referred to hereinafter as MEDEOD (method for driving an electro-optic display) applications);

[0053] (i) Applications of the display; see, for example, U.S. Patent Nos. 7,312,784 and 8,009,348; and

[0054] (j) Non-electrophoretic displays, such as U.S. Patent No. 6,241 As described in No. 921; and U.S. Patent Application Publication No. 2015 / 0277160; and U.S. Patent Application Publication Nos. 2015 / 0005720 and 2016 / 0012710.

[0055] Many of the aforementioned patents and applications recognize that the walls surrounding discrete microcapsules in an encapsulated electrophoretic medium can be replaced by a continuous phase, resulting in a so-called polymer dispersion electrophoretic display, wherein the electrophoretic medium comprises a plurality of discrete electrophoretic fluid droplets and a continuous phase of polymeric material, and the discrete electrophoretic fluid droplets within such a polymer dispersion electrophoretic display can be considered as capsules or microcapsules, even if no discrete capsule membrane is associated with each individual droplet; see, for example, U.S. Patent No. 6,866,760. Thus, for the purposes of this application, such a polymer dispersion electrophoretic medium is considered a subclass of encapsulated electrophoretic media.

[0056] A related type of electrophoretic display is the so-called microcell electrophoretic display. In a microcell electrophoretic display, charged particles and fluid are not encapsulated within microcapsules, but are retained within a plurality of cavities formed within a carrier medium (typically a polymer membrane). See, for example, U.S. Patent Nos. 6,672,921 and 6,788,449.

[0057] While electrophoretic media are typically opaque (because, for example, in many electrophoretic media, particles essentially block visible light from passing through the display) and operate in reflective mode, many electrophoretic displays can be manufactured to operate in so-called shutter mode, where one display state is substantially opaque and the other is translucent. See, for example, U.S. Patents 5,872,552; 6,130,774; 6,144,361; 6,172,798; 6,271,823; 6,225,971; and 6,184,856. Dielectrophoretic displays, similar to electrophoretic displays but dependent on changes in electric field strength, can operate in a similar mode; see U.S. Patent 4,418,346. Other types of electro-optic displays may also operate in shutter mode. Electro-optic media operating in shutter mode can be used in multilayer structures of full-color displays; in such structures, at least one layer adjacent to the viewing surface of the display operates in shutter mode to expose or conceal a second layer farther from the viewing surface.

[0058] Encapsulated electrophoretic displays are generally not plagued by the clustering and settling failure modes of conventional electrophoretic equipment and offer further advantages, such as the ability to print or coat displays on a variety of flexible and rigid substrates. (The term “printing” is intended to include all forms of printing and coating, including but not limited to: pre-load coating, such as die-cast coating, slot or extrusion coating, slide coating or stack coating, curtain coating; roll coating, such as roller blade coating, forward and reverse roller coating; gravure coating; dip coating; spray coating; meniscus coating; spin coating; brush coating; air knife coating; screen printing process; electrostatic coating.)Printing processes; thermal printing processes; inkjet printing processes; electrophoretic deposition (see U.S. Patent No. 7,339,715); and other similar techniques.) Therefore, the resulting display can be flexible. Furthermore, because the display medium can be printed (using various methods), the display itself can be manufactured inexpensively.

[0059] As mentioned above, most simple prior art electrophoretic media essentially display only two colors. Such electrophoretic media either use a single type of electrophoretic particles with a first color in a colored fluid with a different second color (in this case, the first color is displayed when the particles are adjacent to the viewing surface of the display, and the second color is displayed when the particles are spaced apart from the viewing surface), or use a first type and a second type of electrophoretic particles with different first and second colors in an uncolored fluid (in this case, the first color is displayed when the first type of particles are adjacent to the viewing surface of the display, and the second color is displayed when the second type of particles are adjacent to the viewing surface of the display). Typically, these two colors are black and white. If a full-color display is required, a colored filter array can be placed on the viewing surface of a monochrome (black and white) display. Displays with colored filter arrays rely on area sharing and color mixing to generate color stimuli. Available display areas are shared among three or four primary colors, such as red / green / blue (RGB) or red / green / blue / white (RGBW), and the filters can be arranged in a one-dimensional (stripes) or two-dimensional (2x2) repeating pattern. Other options of primary colors or more than three primary colors are also known in the art. Three (for RGB displays) or four (for RGBW displays) subpixels are chosen to be small enough that at the intended viewing distance, they visually blend together to form a single pixel with a uniform color stimulus (“color mixing”). An inherent drawback of area sharing is that a colorant is always present, and color can only be modulated by switching the corresponding pixel of the underlying monochrome display to white or black (turning the corresponding primary color on or off). Instruction manual, page 8 / 19, CN 121889848 A. For example, in an ideal RGBW monitor, the primary colors red, green, blue, and white each occupy one-quarter of the display area (one of four sub-pixels). The white sub-pixel is as bright as the underlying monochrome white, and the brightness of each colored sub-pixel does not exceed one-third of the monochrome white. The overall white brightness of the monitor cannot exceed half the brightness of the white sub-pixels (the white area of ​​the monitor is formed by displaying one white sub-pixel out of every four sub-pixels, plus each colored sub-pixel in its colored state is equivalent to one-third of a white sub-pixel, so the combined contribution of three colored sub-pixels does not exceed one white sub-pixel). The brightness and saturation of the colors share areas with colored pixels that have switched to black.The area sharing is particularly problematic when mixing yellow, as it is brighter than any other color of equal brightness, and saturated yellow is almost as bright as white. Switching blue pixels (a quarter of the display area) to black makes the yellow too dark.

[0060] U.S. Patent Nos. 8,576,476 and 8,797,634 describe a multicolor electrophoretic display having a single backplate including independently addressable pixel electrodes and a common transparent front electrode. Multiple electrophoretic layers are disposed between the backplate and the front electrode. The displays described in these applications are capable of displaying any primary color (red, green, blue, cyan, magenta, yellow, white, and black) at any pixel location. However, there are disadvantages to using multiple electrophoretic layers located between a single addressable electrode group. The electric field experienced by particles in a particular layer is lower than that in the case of a single electrophoretic layer addressed with the same voltage. Furthermore, optical losses in the electrophoretic layer closest to the observation surface (e.g., caused by light scattering or undesirable light absorption) may affect the appearance of the image formed in the underlying electrophoretic layer.

[0061] Attempts have been made to provide full-color electrophoretic displays using a single electrophoretic layer. For example, U.S. Patent No. 8,917,439 describes a color display comprising an electrophoretic fluid containing one or two types of pigment particles dispersed in a transparent, colorless, or colored solvent, the electrophoretic fluid being disposed between a common electrode and a plurality of pixel electrodes or driving electrodes. The driving electrodes are arranged to expose a background layer. U.S. Patent No. 9,116,412 describes a method for driving a display unit filled with an electrophoretic fluid containing two types of charged particles carrying opposite charge polarities and having two contrasting colors. The two types of pigment particles are dispersed in a colored solvent, or dispersed in a solvent containing uncharged or slightly charged colored particles. The method comprises driving the display unit by applying a driving voltage of about 1% to about 20% of the full driving voltage to display the solvent color or the color of the uncharged or slightly charged colored particles. U.S. Patent Nos. 8,717,664 and 8,964,282 describe an electrophoretic fluid and a method for driving an electrophoretic display. The fluid contains first, second, and third types of pigment particles, all dispersed in a solvent or solvent mixture. The first and second types of pigment particles carry opposite charge polarities, and the third type of pigment particles has a charge level less than 50% of the charge level of the first or second type. The three types of pigment particles have different levels of threshold voltage or different levels of mobility, or both.

[0062] U.S. Patent Nos. 10,475,399 and 10,678,111 describe electrophoretic displays capable of displaying any color at any pixel location. In patent No. '399, a display is described in which white (light-scattering) pigment is applied...When addressing with a low voltage, the particle moves in a first direction, and when addressing with a higher voltage, it moves in the opposite direction. Patent '111 describes a full-color electrophoretic display with four pigments: white, cyan, magenta, and yellow, two of which are positively charged and two are negatively charged. US Patent Publication 2022 / 0082896 describes a full-color electrophoretic display with four pigments: white, cyan, magenta, and yellow, three of which are positively charged and the white pigment is negatively charged. Such embodiments of the invention are referred to as CMYW embodiments.

[0063] Furthermore, there are multi-particle display designs in which colored pigments scatter light (i.e., reflective colored particles). US Patent No. 10,339,876 describes this type of display having black, white, and red particles capable of displaying three states. A similar display design containing four pigments can display four different colors, see, for example, U.S. Patent No. 9,922,603, page 9 / 19, CN 121889848 A; or, by using translucent colored particles, such a display can display six colors, see, for example, U.S. Patent No. 11,640,803.

[0064] The electrophoretic medium used herein comprises charged particles having different colors, reflective or absorptive properties, charge densities, and mobility in an electric field (measured in zeta potential). Particles that absorb, scatter, or reflect light, whether over a wide band or at a selected wavelength, are referred to herein as colored particles or pigment particles. Various light-absorbing or light-reflecting materials other than pigments (strictly defined as insoluble colored materials), such as dyes, photonic crystals, quantum dots, etc., may also be used in the electrophoretic medium and display of the present invention. For example, the electrophoretic medium may include a fluid, a plurality of first particles and a plurality of second particles dispersed in the fluid, the first and second particles carrying opposite charges, the first particles being light-scattering particles, the second particles having one of the subtractive primary colors, and a plurality of third particles and a plurality of fourth particles dispersed in the fluid, the third and fourth particles carrying opposite charges, each of the third and fourth particles having a subtractive primary color different from and different from the second particles, wherein the electric field required to separate aggregates formed by the third and fourth particles is greater than the electric field required to separate aggregates formed by any other two types of particles.

[0065] The electrophoretic medium of the present invention may contain any additives used in prior art electrophoretic media, such as those described in the aforementioned Einkel and MIT patents and applications. Thus, for example, the electrophoretic medium of the present invention will generally contain at least one charge control agent to control the charge on a plurality of particles, and the fluid may contain polymers with a number average molecular weight greater than about 20,000 and substantially non-absorbed on the particles to improve the bistable state of the display, as described in the aforementioned U.S. Patent No.As described in 7,170,670.

[0066] In one embodiment, the present invention uses a light-scattering particle that is generally white and three basic non-light-scattering particles. Of course, there are no completely light-scattering particles or completely non-light-scattering particles, and the minimum light scattering of the light-scattering particles used in the electrophoretic medium of the present invention and the maximum light scattering that the basic non-light-scattering particles can tolerate may vary due to factors such as the exact pigment used, its color, and the user's or application's tolerance for some deviation from the desired color. The scattering and absorption properties of a pigment can be evaluated by measuring the diffuse reflectance of a pigment sample dispersed in a suitable matrix or liquid on white and black backgrounds. The results of such measurements can be interpreted according to many models known in the art, such as one-dimensional Kubelka-Munk processing. In the present invention, preferably, when a white pigment is distributed approximately isotropically at a volume fraction of about 15% in a layer of 1 µm thickness containing the pigment and a liquid with a refractive index of less than 1.55, the measured reflectance on a black background exhibits at least 5% diffuse reflectance at a wavelength of 550 nm. Under the same conditions, measured against a black background, yellow, magenta, and cyan pigments preferably exhibit diffuse reflectance of less than 2.5% at wavelengths of 650, 650, and 450 nm, respectively. (The wavelengths selected above for measuring yellow, magenta, and cyan pigments correspond to the spectral regions where these pigments absorb the least.) Colored pigments that meet these criteria are referred to below as “non-scattering” or “essentially non-scattering.” Specific examples of suitable particles are disclosed in U.S. Patent No. 9,921,451, which is incorporated herein by reference.

[0067] Alternative groups of particles may also be used, including four groups of reflective particles, or one absorbing particle with three or four different groups of reflective particles, i.e., as described in U.S. Patent Nos. 9,922,603 ​​and 10,032,419, which are incorporated herein by reference. For example, white particles can be formed from inorganic pigments such as TiO2, ZrO2, ZnO, Al2O3, Sb2O3, BaSO4, PbSO4, etc., while black particles can be formed from CI pigments such as Black 26 or 28 (e.g., manganese ferrite black spinel or copper chromite black spinel) or carbon black. The third / fourth / fifth type of particles can be colors such as red, green, blue, magenta, cyan, or yellow. Pigments used for this type of particle may include, but are not limited to, CI pigments PR 254, PR122, PR149, PG36, PG58, PG7, PB28, PB15:3, PY138, PY150, PY155, or PY20. Specific examples include Clariant Hostaperm Red D3G 70-EDS, Hostaperm Pink E-EDS, PV fast red D3G, etc.Hostaperm red D3G 70, Hostaperm Blue B2G-EDS, Hostaperm Yellow H4G-EDS, Hostaperm Green GNX, BASF Irgazine red L 3630, Cinquasia Red L 4100 HD and Irgazin Red L 3660 HD; Sun Chemical Phthalocyanine Blue, Phthalocyanine Green, Benzidine Yellow or Benzidine AAOT Yellow.

[0068] As shown in Figures 1A and 1B, the electrophoretic display (101, 102) typically includes a top transparent electrode 110, an electrophoretic medium 120 and a bottom electrode 130, the bottom electrode 130 being typically a pixel electrode of a pixel active matrix controlled by a thin-film transistor (TFT). In the electrophoretic medium 120 described herein, there are four different types of particles 121, 122, 123, and 124; however, the methods and displays described herein can use more (or fewer) groups of particles. For example, the technique of the present invention can be used with a set of three types of particles, such as white, black, and red, wherein one of the three different particle types has a lower charge than the other two types. In some instances, two particles will be positively charged, and one (or two) particles will be negatively charged. In some instances, one particle will be positively charged, and three particles will be negatively charged. In some instances, one particle will be negatively charged, and three particles will be positively charged. The electrophoretic medium 120 is typically separated by the walls of microcapsules 126 or microunits 127. An optional adhesive layer 140 may be disposed adjacent to any of the layers; however, it is typically adjacent to the electrode layers (110 or 130). A given electrophoretic display (105, 106) may have more than one adhesive layer 140, but more commonly there is only one. The entire display stack is typically disposed on a substrate 150, which may be rigid or flexible. The displays (101, 102) typically also include a protective layer 160, which may simply protect the top electrode 110 from damage, or it may enclose the entire display (101, 102) to prevent the intrusion of substances such as water. The electrophoretic displays (101, 102) may also include a sealing layer 180 if desired. In some embodiments, the adhesive layer 140 may contain a primer component to improve adhesion to the electrode layer 110, or a separate primer layer may be used (not shown in Figure 1B). The structure and components of the electrophoretic display, pigments, adhesives, electrode materials, etc., are described in numerous patents and patent applications published by Einkel, such as U.S. Patents 6,922,276; 7,002,728; 7,072,Patents 095; 7,116,318; 7,715,088; and 7,839,564, all of which are incorporated herein by reference in their entirety.

[0069] In some embodiments, such as as shown in FIG1A, an electrophoretic display may include a light-transmitting electrode, an electrophoretic medium, and a plurality of rear pixel electrodes. In order to produce a high-resolution display, for example, for displaying images, each pixel electrode 130 may be individually addressed without interference from adjacent pixels in order to faithfully reproduce the image file on the display. One way to achieve this is to provide an array of nonlinear elements, such as transistors or diodes, with each pixel associated with at least one nonlinear element to produce an “active matrix” display. (See FIG2.) The addressing electrode or pixel electrode 130 that addresses a pixel is connected to a suitable voltage source via the associated nonlinear element. Although it is arbitrary in nature and the pixel electrode may be connected to the source of a transistor, typically when the nonlinear element is a transistor, the pixel electrode is connected to the drain of the transistor, and this arrangement will be assumed in the following description.

[0070] It should be noted that the voltage amplitude that can be provided in such row-column drive may be limited by the material used to manufacture the nonlinear element (e.g., thin-film transistor). In many embodiments, the semiconductor material is silicon, particularly amorphous silicon, which is capable of controlling a drive voltage of approximately ±15V. In other embodiments, the semiconductor of the thin-film transistor may be a metal oxide, such as indium gallium zinc oxide (IGZO), which allows for a wider range of drive voltages, such as up to ±30V, as described in U.S. Patent Publication No. 2022-0084473. This design feature is particularly important when driving waveforms to sort pigments in multi-particle systems. In such systems, it is beneficial to provide at least five voltage levels (high positive, low positive, zero, low negative, high negative), and the higher the total voltage, the easier it is to separate particles. For further details, see U.S. Patent Publication No. 2021-0132459. In some embodiments, during row-column driving, a voltage with an amplitude greater than ±30V (e.g., ±35V, ±45V) can be applied by applying a voltage that is not approximately grounded (e.g., 0V) to a common voltage reference power supply while driving the display.

[0071] In conventional electrophoretic displays using an active matrix backplane, each pixel electrode is associated with a capacitor electrode (storage capacitor), such that the pixel electrode and the capacitor electrode form a capacitor; see, for example, International Patent Application WO 01 / 07961. In some embodiments, N-type semiconductors (e.g., amorphous silicon) can be used to form transistors, and the “selected” and “unselected” voltages applied to the gate electrode can be positive and negative, respectively.

[0072] Figure 2 shows more details of row-column addressing for an “active matrix” display. Addressing a pixelThe addressing electrodes or pixel electrodes are fabricated on substrate 202 and connected to an appropriate voltage via lines 204 and 206 through associated nonlinear elements. It should be understood that the voltages provided on lines 204 and 206 may originate from individual circuit elements or may be transmitted with the assistance of a single power supply and power management integrated circuit (“PMIC”). In some instances, an intermediate source controller 220 and a gate controller 230 are used to control the voltages supplied to the source and gate lines; however, in other embodiments, controller 260 is configured to control the entire addressing process, including coordinating the gate and source lines.

[0073] Those skilled in the art will understand that controller 260 of the present invention can be implemented in a variety of different physical forms and can utilize a variety of analog and digital components. For example, controller 260 may include a general-purpose microprocessor combined with suitable peripheral components (e.g., one or more digital-to-analog converters, “DACs”) to convert digital output from the microprocessor into an appropriate voltage applied to the pixel. Alternatively, the display controller circuitry may be implemented in an application-specific integrated circuit (“ASIC”) or a field-programmable gate array (“FPGA”). Those skilled in the art will understand that the display controller circuitry may include processing components and power management circuitry, such as the PMIC described above.

[0074] It should also be understood that FIG2 is an exemplary layout schematic of the active matrix backplane 200, but in practice, the active matrix has depth, and some elements, such as TFTs, may actually be below the pixel electrodes, providing electrical connections from the drain to the pixel electrodes above via vias. Furthermore, the traces that route signals from the gate and / or source controllers to the corresponding row select and column select signals of the active matrix backplane 200 may be T-shaped conductors running perpendicular to the signals to which they are connected.

[0075] Conventionally, in high-resolution arrays, pixels are arranged in a two-dimensional array of rows and columns such that any particular pixel is uniquely defined by the intersection of a designated row and a designated column. The sources of all transistors in each column are connected to a single column (scan) line 206, while the gates of all transistors in each row are connected to a single row (gate) line 208; similarly, assigning sources to rows and gates to columns is conventional, but is arbitrary in nature and can be interchanged if desired. Gate line 208 is optionally connected to gate line driver 212, which essentially ensures that only one row is selected at any given time; that is, a selected voltage is applied to the selected row electrode to ensure that all transistors in the selected row are turned on, while a non-selected voltage is applied to all other rows to ensure that all transistors in these non-selected rows remain off. Column scan lines 206 are optionally connected to scan line driver 210, which applies a selected voltage to each scan line 206 to select...The pixels in a row are driven to their desired optical state. (The voltages mentioned above are relative to a common top electrode (e.g., VCOM), which is not shown in Figure 2.)

[0076] With conventional driving, after a preselection interval called “line addressing time”, the selected row is deselected, the next row is selected, and the voltage on the column driver changes, thereby writing the next line of the display. This process is repeated linearly, so that the entire display is written line by line. As shown in Figure 2, the time interval between the gate voltage pulses of each frame is generally constant, representing the rhythm of line addressing. It is worth noting that the present invention does not achieve a uniform interval between the individual gate voltage pulses for a given addressing row of pixel electrodes.

[0077] The active matrix backplane shown in Figure 2 is coupled to an electro-optic medium, such as shown in Figures 1A and 1B, and is generally sealed to create a display module 55, as shown in Figure 3. This display module 55 forms the core of the electrophoretic display 40. The electrophoretic display 40 typically includes a processor 50 configured to coordinate numerous functions related to displaying content on the display module 55 and to convert "standard" images, such as sRGB images, into a color system that best reproduces the image on the display module 55. Of course, if the electrophoretic display is used as a sensor or counter, the content may be correlated with other inputs. The processor is typically a mobile processor chip, such as those manufactured by Freescale or Qualcomm, but other manufacturers are also known. The processor frequently communicates with a non-transitory memory 70, from which image files and / or lookup tables are extracted to perform the color image conversion described on page 12 / 19 of the specification, CN 121889848 A. The non-transitory memory 70 may also include gate drive instructions where different gate drive modes may be required for specific color conversions. The electrophoretic display 40 may have more than one non-transitory memory chip. The non-transitory memory 70 may be flash memory. In many embodiments, the non-transitory memory 70 is directly incorporated into the end consumer device by incorporating all the elements of FIG. 3 into a circuit board or package. However, in some instances, the drive circuitry is not directly integrated into the display, for example, when the display is an external component of an object such as a car.

[0078] Waveforms (discussed below) are typically stored in non-transitory memory 70, but they may also be integrated into controller 60 or processor 50, or they may be stored in the cloud and downloaded via communication 85. Multiple lookup tables can be used to assist the method of the invention, particularly to provide time-shifted waveforms to controller 60 as needed. In particular, for a given transition from a first color to a second color in an electrophoretic medium with eight primary colors, the lookup table may include: for the first to eighth...The lookup table contains instructions to update from color 1 to a subsequent color (without time offset) in lookup slots; instructions to update from color 1 to a subsequent color (with a first time offset) in lookup slots 9 to 16; and instructions to update from color 1 to a subsequent color (with a second time offset) in lookup slots 17 to 24, and so on. Of course, such lookup tables can also be indexed to improve performance, taking into account operating conditions such as device temperature, battery health, front light color, front light intensity, etc.

[0079] Once the desired image has been converted for display on display module 55, specific image instructions are sent to controller 60, which assists in sending voltage sequences to their respective thin-film transistors (as described above). Such voltages typically originate from one or more power supplies 80, which may include, for example, a power management integrated circuit or a PMIC. The electrophoretic display 40 may also additionally include communication 85, which may be, for example, a WIFI protocol or Bluetooth, and allows the electrophoretic display 40 to receive images and instructions, which may also be stored in memory 70. The electrophoretic display 40 may also include one or more sensors 90, which may include temperature sensors and / or light sensors, and such information may be fed to the processor 50 when such a lookup table is indexed for ambient temperature or incident light intensity or spectrum, allowing the processor to select the best lookup table. In some instances, multiple components of the electrophoretic display 40 may be embedded in a single integrated circuit. For example, an application-specific integrated circuit may implement the functions of the processor 50 and the controller 60.

[0080] The layout of the active matrix backplane 200 shown in FIG. 2 and various components of the electrophoretic display 40 shown in FIG. 3 are provided as examples to help the reader understand the possible configurations of these structures. FIG. 2 and FIG. 3 do not necessarily include all elements and components that may be present in an actual electrophoretic display incorporated into the active matrix backplane, nor do they necessarily include all electrical traces and connections between different elements of the backplane.

[0081] FIG. 4A is a schematic diagram 10 showing an exemplary gate and source signal layout of an active matrix backplane of an electro-optical display. As shown in FIG4A, a series of T-shaped conductors 16 extend from the driver chip or IC 12 along the back side of the display panel 14, and are then electrically coupled to specific gate lines 18 on the front side of the display panel 14 through various conductive vias 22. In some embodiments, the T-shaped conductors 16 are used not only for the gate lines 18, or, in lieu of the gate lines 18, for routing connections to the source lines 20. In some embodiments, the IC 12 shown in FIG4A is located on the front or back of the display panel substrate.

[0082] As shown in FIG4A, typically a single T-shaped conductor 16 and a single via 22 are used to establish connections to each individual gate line 18. In the arrangement shown in FIG4A, most pixel columns (i.e., pixel lines in the long dimension, in FIG4A) are connected to each individual gate line 18.(Seen vertically arranged in FIG4A) is associated with three separate T-shaped conductors 16; in various embodiments, each pixel column may be associated with other numbers of T-shaped conductors 16 (e.g., 2, 4, or more). As shown in FIG4A, the grouping of vertically running T-shaped conductors 16 typically corresponds to adjacent source lines 20.

[0083] FIG4B is a schematic diagram 32 of an exemplary display pixel, which includes a TFT 24 for applying a voltage waveform from the source line 20 to the pixel electrode 30 when the gate line 18 is set to a voltage sufficient to turn on the TFT 24. In addition, a storage capacitor 26 is formed between the pixel electrode 32 and a common voltage or VCOM voltage supply terminal or plane. In some embodiments, direct or indirect coupling between the gate electrode of the TFT 24 and the pixel electrode 32 forms a parasitic capacitance (not shown in FIG4B). Three T-shaped conductors 16 (e.g., T1, T2, and T3) are vertically arranged near the display pixels to provide a connection point between the row selection signal driven by the driver IC 12 and the gate line 18 of the display.

[0084] When using the configuration shown in Figures 4A and 4B, capacitance is generated between the pixel electrode 32 and the multiple T-shaped conductors 16 because the display substrate is typically made of a non-conductive material. For example, as shown in Figure 4B, three parasitic capacitances 28 (e.g., CpT1, CpT2, and CpT3) are formed between the T-shaped conductors 16 and the pixel electrode 30. Since the T-shaped conductors 16 are typically arranged in an ordered manner, it is common practice for multiple adjacent T-shaped conductors 16 to be energized simultaneously as they are used to drive the switching of nearby pixel neighbors in the pixel array. This capacitive coupling can lead to undesirable optical defects, such as inconsistent optical characteristics or responses in different areas of the display due to certain operations.

[0085] As described above, when driving an electrophoretic display using conventional methods, the portion of the electrophoretic layer located above the gate line, above the pixel electrode located above the gate line, and above the T-shaped conductor connecting the gate line and / or source line, experiences voltage artifacts induced by powering on and off the gate low voltage before updating the display. The invention described herein reduces or minimizes the adverse effects of voltage artifacts induced on the electrophoretic layer by conventional driving methods. Specifically, the invention provides a method for powering on and off the gate low voltage in a phased manner, which decomposes the experienced voltage artifacts into multiple voltage artifacts of lower amplitude. It has been observed that the electrophoretic layer responds much less to a series of consecutive voltage impulses with small time intervals than to a single voltage impulse of higher amplitude. Therefore, the phased powering on and off method for the gate low voltage described herein results in fewer optical artifacts on the display.

[0086] According to the invention, the powering on of the gate low voltage of an active matrix display is performed in two or more phases to...The gate line voltage is adjusted from zero volts to a negative value to prepare for the display update cycle. The voltage applied to the gate line of the pixel TFT increases in magnitude at each stage, and these stages are time-spaced, with the interval being at least a large portion of the natural relaxation time of the voltage artifacts induced on the electrophoretic layer. In this way, most or all of the voltage associated with the voltage artifacts can decay or discharge within the time of the stage interval. Preferably, the time of the stage interval is approximately the natural relaxation time, more preferably, it is significantly greater than the relaxation time value exhibited by the electro-optical display device over at least a portion of its operating temperature range. This allows all voltages associated with the voltage artifacts to discharge within the time of the stage interval.

[0087] The power-down of the gate low voltage of the active matrix display is also performed in two or more stages to bring the gate line voltage back from the gate low voltage value to zero volts after the display update cycle ends. The voltage applied to the gate line of the pixel TFT decreases in magnitude at each stage, and the stages for powering down the gate low voltage are time-spaced in a manner similar to the power-up stages described above.

[0088] FIG5A is a signal waveform diagram 500a, which shows the voltage artifact experienced by the electrophoretic material when the gate low voltage is applied in a single stage using a conventional driving method. Signal trace 510 shows the voltage of the gate line, and signal trace 515 shows the voltage measured across the electrophoretic material of the display. Referring to signal trace 510, at time t1, the gate line is driven to the gate low voltage in a single stage. Referring to signal trace 515, it can be seen that applying the gate low voltage in this way induces a voltage artifact on the electrophoretic material, the magnitude of which is close to half the amplitude of the gate low voltage applied to the gate line.

[0089] In some embodiments, the gate low voltage applied to the gate line is -35V. However, as mentioned above, the voltages applied to the row (e.g., gate) signal and the column (e.g., source) signal may be different (e.g., ±15V, ±30V, ±35V, ±45V), depending on the material used to manufacture the TFT.

[0090] Figure 5B is a signal waveform diagram 500b, which illustrates the voltage artifacts experienced by the electrophoretic material when the gate low voltage is applied in two stages according to the driving method disclosed herein. Referring to signal trace 515, at time t1, the gate line is driven to the first stage voltage, which induces a voltage artifact (e.g., a first voltage artifact) on the electrophoretic material. In some embodiments, the amplitude of the first stage voltage is approximately half of the gate low voltage. The gate line voltage is maintained at the first stage voltage for a first time period, and then driven to the gate low voltage at time t2, which induces a voltage artifact (e.g., a second voltage artifact) on the electrophoretic material. The gate line is then maintained at the gate low voltage for a second time period, in this case, the remainder of the driving cycle.The remaining time, but in some embodiments it can be shorter. As shown in FIG5B, the first time period is greater than or equal to the time required for the first voltage artifact to dissipate or discharge (e.g., decay to approximately 0V or decay to the reference voltage of the display). Similarly, the second time period is greater than or equal to the time required for the second voltage artifact to decay or discharge.

[0091] Referring to signal trace 515 in FIG5B, it can be seen that applying a gate low voltage in two stages induces first and second voltage artifacts on the electrophoretic material at the beginning of each corresponding stage, and the amplitude of each voltage artifact is close to half the amplitude of the voltage difference applied to the gate line in each stage. Taking a gate low voltage of -45V as an example, if the gate line is driven from 0V to -22.5V at the beginning of the first stage, the voltage difference is 22.5V, and the amplitude of the voltage artifact induced on the electrophoretic material is less than half of -22.5V. Then, when the gate line is driven from -22.5V to -45V at the start of the second stage, the voltage difference between the first and second stages is also 22.5V, and the amplitude of the voltage artifact induced on the electrophoretic material is also less than half of -22.5V. Furthermore, as can be seen from signal trace 515, the voltage artifact induced at time t1 has discharged or decayed back to approximately 0V before time t2, and the voltage artifact induced at time t2 has also discharged or decayed back to approximately 0V within a similar timeframe after time t2.

[0092] Figure 5C is a signal waveform diagram 500c, which illustrates the voltage artifacts experienced by the electrophoretic material when the gate low voltage is applied in three stages according to the driving method disclosed herein. Referring to signal trace 515, at time t1, the gate line is driven to the first stage voltage, which induces a voltage artifact (e.g., a first voltage artifact) on the electrophoretic material. In some embodiments, the amplitude of the first stage voltage is approximately one-third of the gate low voltage. The gate line voltage is maintained at the first stage voltage for a first time period and then driven to the second stage voltage at time t2, which induces voltage artifacts (e.g., a second voltage artifact) on the electrophoretic material. In some embodiments, the amplitude of the second stage voltage is approximately two-thirds of the gate low voltage. The gate line voltage is maintained at the second stage voltage for a second time period and then driven to the gate low voltage at time t3, which induces voltage artifacts (e.g., a third voltage artifact) on the electrophoretic material. The gate line is then maintained at the gate low voltage for a third time period, in this case the remaining time of the drive cycle, but in some embodiments it can be shorter.

[0093] As shown in FIG5C, the first time period is greater than or equal to the time required for the first voltage artifact to decay or discharge. Similarly, the second time period is greater than or equal to the time required for the second voltage artifact to decay or discharge, and the third time period is greater than or equal to the time required for the third voltage artifact to decay or discharge.

[0094] Referring to signal trace 515 in Figure 5C, it can be seen that applying a low voltage to the gate in three stages induces first, second, and third voltage artifacts on the electrophoretic material at the beginning of each corresponding stage, and the amplitude of each voltage artifact is approximately half the amplitude of the voltage difference applied to the gate line in each stage. For example, if the gate line is driven from 0V to -15V at the beginning of the first stage, the voltage difference is 15V, and the amplitude of the voltage artifact induced on the electrophoretic material is less than half of -15V. When the gate line is driven from -15V to -30V at the beginning of the second stage, the voltage difference between the first and second stages is also 15V, and the amplitude of the voltage artifact induced on the electrophoretic material is also less than half of -15V. Finally, when the gate line is driven from -30V to -55V at the beginning of the third stage, the voltage difference is also 15V, and the amplitude of the voltage artifact induced on the electrophoretic material is also less than half of -15V.

[0095] As can be seen from signal trace 515, the voltage artifact induced at time t1 has discharged or decayed back to approximately 0V before time t2, the voltage artifact induced at time t2 has discharged or decayed back to approximately 0V before time t3, and the voltage artifact induced at time t3 has also discharged or decayed back to approximately 0V after time t3 for a similar period as the other two stages.

[0096] As described above, the voltage applied to the gate line in each stage is maintained for a period of time before the voltage of the next stage is applied. In some embodiments, the stages are time-separated by at least a large portion of the decay time of the voltage artifacts they induced. For example, the voltage artifact decay time after each stage (and thus the minimum time delay between stages) can be approximately 30 to 50 ms, depending on factors such as the backplane structure and the conductivity of the electrophoretic material. Therefore, in some embodiments, the increased time delay of powering on the gate low voltage in two stages compared to a conventional single-stage routine is approximately 30-50 ms. In some embodiments, powering on the gate low voltage in three stages increases the time delay by approximately 60-100 ms compared to a conventional single-stage routine. In some embodiments, powering on the gate low voltage in four stages increases the time delay by approximately 90-150 ms compared to a conventional single-stage routine. The invention is not limited to using only 2 or 3 stages. Those skilled in the art will understand that, depending on the system requirements of the display, a greater delay in powering on the gate low voltage may be tolerable, and any number of stages may be used.

[0097] Figures 6A-6C are signal waveform diagrams illustrating powering on the gate low voltage in a single stage (Figure 6A), powering on the gate low voltage in two stages (Figure 6B), and powering on the gate low voltage in three stages (Figure 6C) using a conventional driving method.The voltage artifact experienced by the electrophoretic material. In Figures 6A-6C, signal trace 610 shows the voltage of the gate line, and signal trace 615 shows the voltage measured across the electrophoretic material of the display. Referring to signal trace 615 in each figure, it can be seen that the voltage artifact induced on the electrophoretic material by applying a low gate voltage in one, two, or three stages is substantially similar to the voltage artifact induced by the corresponding method of applying a low gate voltage in Figures 5A-5C above, except that the amplitude of the voltage artifact induced by the low gate voltage is positive rather than negative.

[0098] It should be noted that this disclosure is primarily directed to active matrix displays that use n-type thin-film transistors in their pixel arrays. However, those skilled in the art will understand that the electro-optical displays and methods for driving electro-optical displays disclosed herein are equally applicable to active matrix displays based on p-type TFTs and applying a "gate high voltage" to the gate line of each pixel TFT to achieve a non-addressed or deselected state for each row.

[0099] Therefore, the invention described herein reduces or minimizes undesirable optical artifacts caused by the capacitance coupling between the gate line and its associated T-wire to the pixel electrode above or the electrophoretic material above. Phased power-on and power-off of the gate at low voltages decomposes the experienced voltage artifacts into a series of lower-amplitude voltage artifacts to which the electrophoretic layer responds much less strongly than to a single higher-amplitude voltage impulse.

[0100] It will be apparent to those skilled in the art that numerous changes and modifications can be made to specific embodiments of the above invention without departing from the scope of the invention. Therefore, the entire foregoing description should be interpreted as illustrative rather than restrictive.

[0101] This disclosure provides aspects and embodiments as described in the following clauses:

[0102] Clause 1: A method for driving an electro-optic display, the electro-optic display including an electrophoretic material layer disposed between a common electrode and a backplane, the backplane including a pixel electrode array, wherein each pixel electrode is coupled to a pixel transistor including a source electrode, a gate electrode, and a drain electrode, wherein the gate electrode is coupled to a gate line, the source electrode is coupled to a source line, and the drain electrode is coupled to the pixel electrode, wherein a controller provides a time-varying voltage to the gate line, the source line, and the common electrode, the driving method comprising: applying a first stage voltage to the gate line, wherein the first stage voltage has a first amplitude, the first amplitude being approximately half of a gate low voltage used to place the pixel transistor in a non-conducting state; maintaining the first stage voltage on the gate line for a first time period; and applying a second stage voltage to the gate line, wherein the second stage voltage has a second amplitude, the second amplitude being approximately half of the gate low voltage used to place the pixel transistor in the non-conducting state.

[0103] Clause 2: The method according to Clause 1, wherein the amplitude of the gate low voltage is approximately -35V or -45V.

[0104] Clause 3: The method according to Clause 1 or 2, wherein the pixel transistor is an n-type transistor and the gate low voltage has a negative polarity.

[0105] Clause 4: The method according to Clause 1, wherein the pixel transistor is a p-type transistor and the gate low voltage has a positive polarity.

[0106] Clause 5: The method according to any one of Clauses 1-4, wherein the first time period is between 30ms and 50ms.

[0107] Clause 6: The method according to any one of Clauses 1-5, wherein the second time period is between 30ms and 50ms.

[0108] Clause 7: The method according to any one of Clauses 1-6, wherein applying the first stage voltage to the gate line causes a first voltage artifact on the electrophoretic material layer.

[0109] Clause 8: The method according to any one of Clauses 1-7, wherein the first time period is greater than or equal to the discharge time of the first voltage artifact.

[0110] Clause 9: The method according to any one of Clauses 1-8, wherein applying the second stage voltage to the gate line causes a second voltage artifact on the electrophoretic material layer.

[0111] Clause 10: The method according to any one of Clauses 1-9, wherein the second time period is greater than or equal to the discharge time of the second voltage artifact.

[0112] Clause 11: An electro-optic display comprising: a transparent common electrode; a backplate including a pixel electrode array; an electro-optic material layer disposed between the common electrode and the pixel electrode array, wherein each pixel electrode is coupled to a pixel transistor including a source electrode, a gate electrode, and a drain electrode, and wherein the gate electrode is coupled to a gate line, the source electrode is coupled to a source line, and the drain electrode is coupled to the pixel electrode; and a controller capable of applying a time-varying voltage to the gate line, the source line, and the common electrode, the controller being configured to: apply a first stage voltage to the gate line, wherein the first stage voltage has a first amplitude, the first amplitude being approximately half of a gate low voltage used to place the pixel transistor in a non-conducting state; maintain the first stage voltage on the gate line for a first time period; and apply a second stage voltage to the gate line, wherein the second stage voltage has a second amplitude, the second amplitude being approximately the gate low voltage used to place the pixel transistor in the non-conducting state.

[0113] Clause 12: The electro-optic display according to Clause 11, wherein the amplitude of the gate low voltage is approximately -35V.

[0114] Clause 13: The electro-optic display according to Clause 11 or 12, wherein the pixel transistor is an n-type transistor.And the gate low voltage has a negative polarity.

[0115] Clause 14: The electro-optic display according to Clause 11, wherein the pixel transistor is a p-type transistor, and the gate low voltage has a positive polarity.

[0116] Clause 15: The electro-optic display according to any one of Clauses 11-14, wherein the first time period is between 30 ms and 50 ms.

[0117] Clause 16: The electro-optic display according to any one of Clauses 11-15, wherein the second time period is between 30 ms and 50 ms.

[0118] Clause 17: The electro-optic display according to any one of Clauses 11-16, wherein applying the first stage voltage to the gate line causes a first voltage artifact on the electrophoretic material layer.

[0119] Clause 18: The electro-optic display according to any one of Clauses 11-17, wherein the first time period is greater than or equal to the discharge time of the first voltage artifact.

[0120] Clause 19: An electro-optic display according to any one of Clauses 11-18, wherein applying the second stage voltage to the gate line causes a second voltage artifact on the electrophoretic material layer. Specification 17 / 19 pages 20 CN 121889848 A

[0121] Clause 20: An electro-optic display according to any one of Clauses 11-19, wherein the second time period is greater than or equal to the discharge time of the second voltage artifact.

[0122] Clause 21: A method for driving an electro-optic display, the electro-optic display comprising an electrophoretic material layer disposed between a common electrode and a backplane, the backplane comprising an array of pixel electrodes, wherein each pixel electrode is coupled to a pixel transistor comprising a source electrode, a gate electrode and a drain electrode, wherein the gate electrode is coupled to a gate line, the source electrode is coupled to a source line and the drain electrode is coupled to the pixel electrode, wherein a controller provides a time-varying voltage to the gate line, the source line and the common electrode, the driving method comprising: applying a first stage voltage to the gate line, wherein the first stage voltage has a first amplitude, the first amplitude being approximately for... The pixel transistor is placed at one-third of the gate low voltage in the non-conducting state; the first stage voltage is maintained on the gate line for a first time period; a second stage voltage is applied to the gate line, wherein the second stage voltage has a second amplitude, the second amplitude being approximately two-thirds of the gate low voltage used to place the pixel transistor in the non-conducting state; the second stage voltage is maintained on the gate line for a second time period; and a third stage voltage is applied to the gate line, wherein the third stage voltage has a third amplitude, the third amplitude being approximately equal to the gate low voltage used to place the pixel transistor in the non-conducting state.

[0123] Clause 22: The method according to Clause 21, wherein the amplitude of the gate low voltage is approximately -35V or -45V.

[0124] Clause 23: The method according to Clause 21 or 22, wherein the pixel transistor is an n-type transistor and the gate low voltage is negative.

[0125] Clause 24: The method according to Clause 21, wherein the pixel transistor is a p-type transistor and the gate low voltage is positive.

[0126] Clause 25: The method according to any one of Clauses 21-24, wherein the first time period is between 30ms and 50ms.

[0127] Clause 26: The method according to any one of Clauses 21-25, wherein the second time period is between 30ms and 50ms.

[0128] Clause 27: The method according to any one of Clauses 21-26, wherein the third time period is between 30ms and 50ms.

[0129] Clause 28: The method according to any one of Clauses 21-27, wherein applying the first stage voltage to the gate line causes a first voltage artifact on the electrophoretic material layer.

[0130] Clause 29: The method according to any one of Clauses 21-28, wherein the first time period is greater than or equal to the discharge time of the first voltage artifact.

[0131] Clause 30: The method according to any one of Clauses 21-29, wherein applying the second stage voltage to the gate line causes a second voltage artifact on the electrophoretic material layer.

[0132] Clause 31: The method according to any one of Clauses 21-30, wherein the second time period is greater than or equal to the discharge time of the second voltage artifact.

[0133] Clause 32: The method according to any one of Clauses 21-31, wherein applying the third stage voltage to the gate line causes a third voltage artifact on the electrophoretic material layer.

[0134] Clause 33: The method according to any one of Clauses 21-32, wherein the third time period is greater than or equal to the discharge time of the third voltage artifact.

[0135] Clause 34: An electro-optic display comprising: a light-transmitting common electrode; a backplate including a pixel electrode array; an electro-optic material layer disposed between the common electrode and the pixel electrode array, wherein each pixel electrode is coupled to a pixel transistor including a source electrode, a gate electrode, and a drain electrode, wherein the gate electrode is coupled to a gate line, the source electrode is coupled to a source line, and the drain electrode is coupled to the pixel electrode; and a controller capable of applying a time-varying voltage to the gate line, the source line, and the common electrode, the controller being configured to perform the method described in any one of Clauses 21-33. (Pages 19-19, CN 121889848 A, Figure 1A)Instruction manual, Figure 1 / 8, page 23, CN 121889848 A, Figure 1B; Instruction manual, Figure 2 / 8, page 24, CN 121889848 A, Figure 2; Instruction manual, Figure 3 / 8, page 25, CN 121889848 A, Figure 3; Instruction manual, Figure 4 / 8, page 26, CN 121889848 A, Figure 4A; Instruction manual, Figure 5 / 8, page 27, CN 121889848 A, Figure 4B, Figure 5A; Instruction manual, Figure 6 / 8, page 28, CN 121889848 A, Figure 5B, Figure 5C, Figure 6A; Instruction manual, Figure 7 / 8, page 29, CN 121889848 A, Figure 6B, Figure 6C; Instruction manual, Figure 8 / 8, page 30, CN 121889848 A

Claims

1. A method for driving an electro-optic display, the electro-optic display including an electrophoretic material layer disposed between a common electrode and a backplane, the backplane including a pixel electrode array, wherein each pixel electrode is coupled to a pixel transistor including a source electrode, a gate electrode, and a drain electrode, wherein the gate electrode is coupled to a gate line, the source electrode is coupled to a source line, and the drain electrode is coupled to the pixel electrode, wherein a controller provides a time-varying voltage to the gate line, the source line, and the common electrode, the driving method comprising: A first stage voltage is applied to the gate line, wherein the first stage voltage has a first amplitude, which is approximately half of the low gate voltage used to put the pixel transistor in a non-conducting state; The first stage voltage is maintained on the gate line for a first time period. as well as A second stage voltage is applied to the gate line, wherein the second stage voltage has a second amplitude, which is approximately the gate low voltage used to place the pixel transistor in the non-conducting state.

2. The method of claim 1, wherein the magnitude of the gate low voltage is approximately -35V.

3. The method of claim 1, wherein the pixel transistor is an n-type transistor and the gate low voltage has a negative polarity.

4. The method of claim 1, wherein the pixel transistor is a p-type transistor and the gate low voltage has a positive polarity.

5. The method according to claim 1, wherein the first time period is between 30ms and 50ms.

6. The method according to claim 1, wherein the second time period is between 30ms and 50ms.

7. The method of claim 1, wherein applying the first stage voltage to the gate line causes a first voltage artifact on the electrophoretic material layer.

8. The method according to claim 7, wherein the first time period is greater than or equal to the discharge time of the first voltage artifact.

9. The method of claim 1, wherein applying the second stage voltage to the gate line causes a second voltage artifact on the electrophoretic material layer.

10. The method of claim 9, wherein the second time period is greater than or equal to the discharge time of the second voltage artifact.

11. An electro-optical display, comprising: Transparent common electrode; Including the backplate of the pixel electrode array; An electro-optic material layer is disposed between the common electrode and the pixel electrode array, wherein each pixel electrode is coupled to a pixel transistor including a source electrode, a gate electrode and a drain electrode, and wherein the gate electrode is coupled to a gate line, the source electrode is coupled to a source line and the drain electrode is coupled to the pixel electrode; as well as A controller capable of applying a time-varying voltage to the gate line, the source line, and the common electrode, the controller being configured to: A first stage voltage is applied to the gate line, wherein the first stage voltage has a first amplitude, which is approximately half of the low gate voltage used to put the pixel transistor in a non-conducting state; The first stage voltage is maintained on the gate line for a first time period. as well as A second stage voltage is applied to the gate line, wherein the second stage voltage has a second amplitude, which is approximately the gate low voltage used to place the pixel transistor in the non-conducting state.

12. The electro-optic display of claim 11, wherein the amplitude of the gate low voltage is approximately -35V.

13. The electro-optic display of claim 11, wherein the pixel transistor is an n-type transistor and the gate low voltage has a negative polarity.

14. The electro-optic display of claim 11, wherein the pixel transistor is a p-type transistor and the gate low voltage has a positive polarity.

15. The electro-optical display according to claim 11, wherein the first time period is between 30 ms and 50 ms.

16. The electro-optical display according to claim 11, wherein the second time period is between 30 ms and 50 ms.

17. The electro-optic display of claim 11, wherein applying the first stage voltage to the gate line causes a first voltage artifact on the electrophoretic material layer.

18. The electro-optical display of claim 17, wherein the first time period is greater than or equal to the discharge time of the first voltage artifact.

19. The electro-optic display of claim 11, wherein applying the second stage voltage to the gate line causes a second voltage artifact on the electrophoretic material layer.

20. The electro-optical display of claim 19, wherein the second time period is greater than or equal to the discharge time of the second voltage artifact.

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