Radio frequency frontend circuit

Abstract

A radio frequency (RF) front-end circuit is provided. The RF front-end circuit may be disposed in a wireless device to support parallel time division duplex (TDD) and frequency division duplex (FDD) communications. In particular, the RF front-end circuit shares multiple antennas between communicating TDD sounding reference signals (SRS) in a TDD uplink and communicating FDD signals in an FDD downlink / uplink. In embodiments disclosed herein, the RF front-end circuit is configured to reduce phase / gain hopping in downlink / uplink FDD signals while switching TDD SRS transmissions between shared antennas. By reducing the phase / gain hopping in the FDD signal during SRS transmission, it is possible to improve the error vector magnitude (EVM) and / or signal-to-noise ratio (SNR) of the downlink / uplink FDD signal to thereby maintain FDD flux during FDD communication.

Description

(19) State Intellectual Property Office (12) Invention Patent Application (10) Application Publication Number (43) Application Publication Date (21) Application Number 202480060294.9 (22) Application Date 2024.10.16 (30) Priority Data 63 / 594,395 2023.10.30 US 63 / 572,664 2024.04.01 US (85) PCT International Application Entering National Phase Date 2026.03.20 (86) PCT International Application Application Data PCT / US2024 / 051579 2024.10.16 (87) PCT International Application Publication Data WO2025 / 096201 EN 2025.05.08 (71) Applicant: QORVO, Inc., USA (72) Inventors: Li Yuyong, D. Lu, C. Bildell, G. C. Gago, R. Dijoma, S. M. Vigand, S. E. Richard (74) Patent Agency: China Council for the Promotion of International Trade Patent & Trademark Office Co., Ltd., 11038 Patent Attorney: Zhang Xiaowen (51) Int.Cl. H04B 1 / 10 (2006.01) H04B 1 / 18 (2006.01) H04B 7 / 0413 (2017.01) H04B 7 / 06 (2006.01) H04B 7 / 08 (2006.01) H04B 1 / 00 ​​(2006.01) (54) Invention Title: Radio Frequency Front-End Circuit (57) Abstract: A radio frequency (RF) front-end circuit is provided. The RF front-end circuitry can be disposed in a wireless device to support parallel time-division duplex (TDD) and frequency-division duplex (FDD) communication. Specifically, the RF front-end circuitry shares multiple antennas between transmitting a TDD sounding reference signal (SRS) in the TDD uplink and transmitting FDD signals in the FDD downlink / uplink. In the embodiments disclosed herein, the RF front-end circuitry is configured to reduce phase / gain hopping in the downlink / uplink FDD signals while switching TDD SRS transmissions between the shared antennas. By reducing the phase / gain hopping in the FDD signals during SRS transmission, it is possible to improve the error vector magnitude (EVM) and / or signal-to-noise ratio (SNR) of the downlink / uplink FDD signals, thereby maintaining FDD throughput during FDD communication.Claims 4 pages, Description 10 pages, Drawings 10 pages, CN 121889998 A 2026.04.17 CN 1 21 88 99 98 A 1. A radio frequency (RF) front-end circuit, comprising: a first antenna, a second antenna, a third antenna, and a fourth antenna, each configured to transmit a corresponding of a first SRS, a second SRS, a third SRS, and a fourth SRS in a corresponding of a first SRS, a second SRS, a third SRS, and a fourth SRS in a plurality of time-division duplex (TDD) frames; and a first front-end module (FEM), comprising: a first frequency-division duplex (FDD) transmit-receive filter coupled to the first antenna and configured to transmit and receive FDD signals at an FDD transmit frequency and an FDD receive frequency, respectively; and a TDD transmit-receive filter, comprising: A TDD transmit filter, switchable between a first antenna and a second antenna and configured to provide the second SRS to the second antenna for transmission in a second SRS time slot following the first SRS time slot in each of the plurality of TDD frames; and a TDD receive filter, coupled to the first antenna and configured to present substantially the same impedance to the first antenna at the FDD receive frequency as the TDD transmit filter when the first FEM switches from transmitting the first SRS from the first antenna to transmitting the second SRS from the second antenna. 2. The RF front-end circuit of claim 1, wherein the first FDD transmit-receive filter and the TDD transmit-receive filter are disposed in different filter dies. 3. The RF front-end circuit of claim 1, wherein the TDD transmit filter and the TDD receive filter are disposed in the same filter die to eliminate material variation. 4. The RF front-end circuit of claim 1, wherein: the TDD transmit filter includes a transmit matching circuit; and the TDD receive filter includes a receive matching circuit; wherein the transmit matching circuit and the receive matching circuit are symmetrical and tuned to present substantially the same capacitance at the FDD transmit frequency and the FDD receive frequency. 5. The RF front-end circuit of claim 1, wherein: the TDD transmit filter includes a transmit matching circuit; and the TDD receive filter includes a receive matching circuit; wherein the transmit matching circuit and the receive matching circuit are asymmetrical, but tuned to present substantially the same capacitance at the FDD receive frequency.6. The RF front-end circuit of claim 1, further comprising a second FEM coupled to the third antenna and the fourth antenna and configured to: provide the third SRS to the third antenna for transmission in a third SRS time slot following the second SRS time slot in each of the plurality of TDD frames; and provide the fourth SRS to the fourth antenna for transmission in a fourth SRS time slot following the third SRS time slot in each of the plurality of TDD frames. 7. The RF front-end circuit of claim 6, wherein the TDD transmit filter is further configured to forward the third SRS and the fourth SRS to the second FEM for transmission via the third antenna and the fourth antenna, respectively. 8. The RF front-end circuit of claim 6, wherein the second FEM is further configured to receive the third SRS and the fourth SRS via a high-frequency band switch coupled to the input of the TDD transmit filter. Claims 1 / 4 Page 2 CN 121889998 A 9. The RF front-end circuit of claim 8, wherein the second FEM further comprises: an FDD transmit-receive filter coupled to the third antenna; and a TDD receive filter coupled to the third antenna. 10. The RF front-end circuit of claim 1, wherein: the first FEM further comprises an FDD transmit-receive filter coupled to the second antenna and configured to transmit and receive the FDD signal at the FDD transmit frequency and the FDD receive frequency; an FDD low-noise amplifier (LNA) coupled to the FDD transmit-receive filter and configured to amplify the FDD signal received via the first antenna; a TDD LNA coupled to the TDD receive filter; and a TDD power amplifier (PA) coupled to the TDD transmit filter. 11. The RF front-end circuit of claim 10, wherein the first FEM further comprises: an input tuning circuit coupled to the first antenna; and an output tuning circuit coupled to the output of the FDD LNA.12. A radio frequency (RF) front-end circuit comprising: a first antenna, a second antenna, a third antenna, and a fourth antenna, each configured to transmit a corresponding of a first SRS, a second SRS, a third SRS, and a fourth SRS in a corresponding of a first SRS, a second SRS, a third SRS, and a fourth SRS in a plurality of time-division duplex (TDD) frames; and a first front-end module (FEM) comprising: a frequency-division duplex (FDD) transmit-receive filter coupled to the first antenna and configured to transmit and receive FDD signals at an FDD transmit frequency and an FDD receive frequency, respectively; an FDD low-noise amplifier (LNA) coupled to the FDD transmit-receive filter; an input tuning circuit coupled to the first antenna; an output tuning circuit coupled to the output of the FDD LNA; and a TDD transmit-receive filter coupled to the first antenna and the second antenna and configured to: provide the first SRS to the first antenna for the first SRS in each of the plurality of TDD frames. Transmit in a time slot; and provide the second SRS to the second antenna for transmission in the second SRS time slot following the first SRS time slot in each of the plurality of TDD frames. 13. The RF front-end circuit of claim 12, wherein the TDD transmit-receive filter is disposed in a single filter die separate from the FDD transmit-receive filter.14. A wireless device comprising a radio frequency (RF) front-end circuit, the RF front-end circuit including: a first antenna, a second antenna, a third antenna, and a fourth antenna, each configured to transmit a corresponding of a first sounding reference signal (SRS) time slot, a second SRS time slot, a third SRS time slot, and a fourth SRS time slot in a plurality of time division duplex (TDD) frames; and a first front-end module (FEM) including: a first frequency division duplex (FDD) transmit-receive filter coupled to the first antenna and configured to transmit and receive FDD signals at an FDD transmit frequency and an FDD receive frequency, respectively; and a TDD transmit-receive filter including: a TDD transmit filter switchable between the first antenna and the second antenna and configured to transmit the signal at a frequency specified in the claims. A second SRS is provided to the second antenna for transmission in a second SRS time slot following the first SRS time slot in each of the plurality of TDD frames; and a TDD receive filter coupled to the first antenna and configured to present substantially the same impedance to the first antenna at the FDD receive frequency as the TDD transmit filter when the first FEM switches from transmitting the first SRS from the first antenna to transmitting the second SRS from the second antenna. 15. The wireless device of claim 14, wherein the first FDD transmit-receive filter and the TDD transmit-receive filter are disposed in different filter dies. 16. The wireless device of claim 14, wherein the TDD transmit filter and the TDD receive filter are disposed in the same filter die to eliminate material variation.17. A wireless device comprising a radio frequency (RF) front-end circuit, the RF front-end circuit including: a first antenna, a second antenna, a third antenna, and a fourth antenna, each configured to transmit a corresponding of a first sounding reference signal (SRS) time slot, a second SRS time slot, a third SRS time slot, and a fourth SRS time slot in each of a plurality of time-division duplex (TDD) frames; and a first front-end module (FEM) including: a frequency-division duplex (FDD) transmit-receive filter coupled to the first antenna and configured to transmit and receive FDD signals at an FDD transmit frequency and an FDD receive frequency, respectively; an FDD low-noise amplifier (LNA) coupled to the FDD transmit-receive filter; an input tuning circuit coupled to the first antenna; an output tuning circuit coupled to the output of the FDD LNA; and a TDD transmit-receive filter coupled to the first antenna and the second antenna and configured to: provide the first SRS to the first antenna for the first SRS in each of the plurality of TDD frames. Transmit in a time slot; and provide the second SRS to the second antenna for transmission in the second SRS time slot following the first SRS time slot in each of the plurality of TDD frames. 18. A method for configuring a radio frequency (RF) front-end circuit, comprising: configuring each of a first antenna, a second antenna, a third antenna, and a fourth antenna to transmit a first SRS, a second SRS, a third SRS, and a fourth SRS in a corresponding of a first sounding reference signal (SRS) time slot, a second SRS time slot, a third SRS time slot, and a fourth SRS time slot in a plurality of time-division duplex (TDD) frames; coupling a first frequency-division duplex (FDD) transmit-receive filter to the first antenna to transmit and receive FDD signals at an FDD transmit frequency and an FDD receive frequency, respectively; coupling a TDD transmit filter to the second antenna to provide a second SRS to the second antenna for transmission in a second SRS time slot following the first SRS time slot in the plurality of TDD frames; and coupling a TDD receive filter to the first antenna to present a substantially the same impedance to the first antenna at the FDD receive frequency as the TDD transmit filter during a switch from transmitting the first SRS from the first antenna to transmitting the second SRS from the second antenna. 19. The method of claim 18, further comprising placing the TDD transmit filter and the TDD receive filter in the same filter die to eliminate material variations.20. A method for configuring a radio frequency (RF) front-end circuit, comprising: configuring each of a first antenna, a second antenna, a third antenna, and a fourth antenna to transmit a corresponding of a first SRS, a second SRS, a third SRS, and a fourth SRS in a corresponding of a first SRS, a second SRS, a third SRS, and a fourth SRS in a plurality of time-division duplex (TDD) frames; coupling a frequency-division duplex (FDD) transmit-receive filter to the first antenna to transmit and receive FDD signals at an FDD transmit frequency and an FDD receive frequency, respectively; coupling an FDD low-noise amplifier (LNA) to the FDD transmit-receive filter; coupling an input tuning circuit to the first antenna; and coupling an output tuning circuit to the FDD... The output of the LNA; and the coupling of the TDD transmit-receive filter to the first antenna and the second antenna to provide the first SRS to the first antenna for transmission in the first SRS time slot of each of the plurality of TDD frames, and to provide the second SRS to the second antenna for transmission in the second SRS time slot following the first SRS time slot of each of the plurality of TDD frames. Claims 4 / 4 Page 5 CN 121889998 A Radio Frequency Front-End Circuit

[0001] Related Applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 594,395, filed October 30, 2023, and U.S. Provisional Patent Application No. 63 / 572,664, filed April 1, 2024, the disclosures of which are hereby incorporated herein by reference in their entirety. Technical Field

[0003] The technology disclosed herein generally relates to radio frequency (RF) front-end circuits capable of supporting multiple RF bands. Background Art

[0004] Mobile communication devices are becoming increasingly common in modern society for providing wireless communication services. The widespread use of these mobile communication devices is partly due to the many functions they possess. Improving the processing power of such devices means that mobile communication devices have evolved from simple communication tools into sophisticated mobile multimedia centers that enhance user experience.

[0005] Advanced mobile communication devices must be able to communicate (multiple) radio frequency (RF) signals in various wireless communication systems (e.g., Long Term Evolution (LTE) and New Radio (NR)) based on various transmit / receive configurations (e.g., Multiple Input Multiple Output (MIMO), Dual Connectivity (DC), and Diversity Receiver). Furthermore, advanced mobile communication devices are required to transmit (multiple) RF signals across a wide range of RF spectrum that can be roughly classified as low frequency band (LB), mid-high frequency band (MHB), and ultra-high frequency band (UHB).Conventionally, LB refers to the RF spectrum below 1 GHz, MHB refers to the RF spectrum between 1 and 3 GHz, and UHB refers to the RF spectrum between 3 and 5 GHz. MHB can be further divided into a mid-frequency band (MB) between 1 and 2 GHz and a high-frequency band (HB) between 2 and 3 GHz.

[0006] Each of the RF spectra of LB, MB, MHB, HB, and UHB can be further configured to include one or more RF bands. As an example, LB can include RF bands 5 (Bn5), 8 (Bn8), 20 (Bn20), and 28 (Bn28), MB can include RF bands 1 (Bn1), 3 (Bn3), 25 (Bn25), and 66 (Bn66), HB can include RF bands 40 (Bn40) and 41 (Bn41), and UHB can include RF bands 77 (n77) and 79 (n79).

[0007] In order to transmit or receive (multiple) RF signals in an LTE or NR system, the mobile communication device needs to periodically report channel quality to the base station (e.g., an eNB in ​​LTE or a gNB in ​​NR). More specifically, in a time-division duplex (TDD) system with channel reciprocity, the mobile communication device measures the channel quality (e.g., received power) of the downlink channel at all receiving antennas and reports such measurements to the base station using the uplink in a predefined periodic uplink sounding reference signal (SRS). Therefore, the base station can calculate the quality of the uplink channel, such as the Physical Uplink Shared Channel (PUSCH), across subcarrier segments in the frequency domain. Furthermore, due to channel reciprocity in the TDD bands occupying the same downlink and uplink RF frequencies, the uplink SRS can also be used by the base station to estimate the channel state information and intrinsic modes of the downlink channel (e.g., the Physical Downlink Shared Channel (PDSCH)). Such estimations help the base station determine downlink and uplink channel allocation and the beamforming configuration of the mobile communication device. In this regard, the mobile communication device must periodically transmit uplink SRS.

[0008] Figure 1 is a schematic diagram illustrating an exemplary illustration of (multiple) TDD frames 10, in which the mobile communication device can report downlink channel quality measurements in multiple SRS slots SRS0 to SRS3. Hereinafter, (multiple) TDD frames 10 may be transmitted in HB (e.g., RF bands 40 (n40) and 41 (n41)). Specification 1 / 10 page 6 CN 121889998 A

[0009] In this exemplary illustration, (multiple) TDD frames 10 are divided into twenty orthogonal frequency division multiplexing (OFDM) slots (labeled "0" to "19").In OFDM time slots, some are downlink time slots (denoted as "D"), some are uplink time slots (denoted as "U"), and some others are flexible time slots (denoted as "F"). According to the 3GPP standard, mobile communication devices are required to report uplink channel quality measurements in each of the flexible time slots. For example, a mobile communication device will transmit SRS0, SRS1, SRS2, and SRS3 in OFDM time slots 3, 8, 13, and 18, respectively.

[0010] Furthermore, mobile communication devices typically need to communicate simultaneously in multiple Frequency Division Duplex (FDD) frames 12, which may not be time-aligned with multiple TDD frames 10. In this document, the multiple FDD frames 12 may be transmitted in MB (e.g., RF bands 1 (n1), 3 (n3), 25 (n25), and 66 (n66)).

[0011] Understandably, various combinations of communication systems, transmit / receive technologies, and / or RF bands can substantially increase the implementation complexity, bill of materials (BoM) cost, and footprint of the RF front-end circuitry. Furthermore, given the coexistence of TDD and FDD, it is necessary to share limited resources (e.g., antennas, switches, etc.) between TDD and FDD to help reduce the complexity, BoM cost, and footprint of the RF front-end circuitry. Summary of the Invention

[0012] Embodiments of this disclosure relate to radio frequency (RF) front-end circuitry. The RF front-end circuitry can be disposed in a wireless device to support parallel time-division duplex (TDD) and frequency-division duplex (FDD) communication. Specifically, the RF front-end circuitry shares multiple antennas between transmitting a TDD sounding reference signal (SRS) in the TDD uplink and transmitting FDD signals in the FDD downlink / uplink. In the embodiments disclosed herein, the RF front-end circuitry is configured to reduce phase / gain hopping in the downlink / uplink FDD signals while switching TDD SRS transmission between the shared antennas. By reducing the phase / gain transition in the downlink / uplink FDD signal during SRS transmission, it is possible to improve the error vector magnitude (EVM) and / or signal-to-noise ratio (SNR) of the downlink / uplink FDD signal, thereby maintaining FDD throughput during FDD communication.

[0013] In one aspect, this document provides an RF front-end circuit. The RF front-end circuit includes a first antenna, a second antenna, a third antenna, and a fourth antenna. Each of the first antenna, the second antenna, the third antenna, and the fourth antenna is configured to transmit a corresponding of a first SRS, a second SRS, a third SRS, and a fourth SRS in a corresponding of a first SRS time slot, a second SRS time slot, a third SRS time slot, and a fourth SRS time slot in a plurality of TDD frames. The RF front-end circuit also includes a first front-end module (FEM).The first FEM includes a first FDD transmit-receive filter coupled to the first antenna. The first FDD transmit-receive filter is configured to transmit and receive FDD signals at both the FDD transmit frequency and the FDD receive frequency. The first FEM also includes a TDD transmit-receive filter. The TDD transmit-receive filter includes a TDD transmit filter switchable between the first antenna and the second antenna. The TDD transmit filter is configured to provide the second SRS to the second antenna for transmission in the second SRS time slot following the first SRS time slot in each of the plurality of TDD frames. The TDD transmit-receive filter also includes a TDD receive filter coupled to the first antenna. The TDD receive filter is configured to present substantially the same impedance to the first antenna at the FDD receive frequency as the TDD transmit filter when the first FEM switches from transmitting the first SRS from the first antenna to transmitting the second SRS from the second antenna.

[0014] In another aspect, this document provides an RF front-end circuit. The RF front-end circuit includes a first antenna, a second antenna, a third antenna, and a fourth antenna. Each of the first, second, third, and fourth antennas is configured to transmit a corresponding SRS in a corresponding SRS time slot of the first, second, third, and fourth SRS timeslot in a plurality of TDD frames. The RF front-end circuitry further includes a first FEM. The first FEM includes an FDD transmit-receive filter coupled to the first antenna. The FDD transmit-receive filter is configured to transmit and receive FDD signals at the FDD transmit frequency and FDD receive frequency, respectively. The first FEM also includes an FDD low-noise amplifier (LNA) coupled to the FDD transmit-receive filter. The first FEM also includes an input tuning circuit coupled to the first antenna. The first FEM also includes an output tuning circuit coupled to the output of the FDD LNA. The first FEM also includes TDD transmit-receive filters coupled to the first and second antennas. The TDD transmit-receive filter is configured to provide the first SRS to the first antenna for transmission in the first SRS time slot of each of the plurality of TDD frames. The TDD transmit-receive filter is also configured to provide the second SRS to the second antenna for transmission in the second SRS time slot following the first SRS time slot of each of the plurality of TDD frames.

[0015] In another aspect, a wireless device is provided herein.The wireless device includes an RF front-end circuit. The RF front-end circuit includes a first antenna, a second antenna, a third antenna, and a fourth antenna. Each of the first, second, third, and fourth antennas is configured to transmit a corresponding first SRS, second SRS, third SRS, and fourth SRS in a corresponding slot of a first SRS, second SRS, third SRS, and fourth SRS in a plurality of TDD frames. The RF front-end circuit also includes a first FEM. The first FEM includes a first FDD transmit-receive filter coupled to the first antenna. The first FDD transmit-receive filter is configured to transmit and receive FDD signals at an FDD transmit frequency and an FDD receive frequency, respectively. The first FEM also includes a TDD transmit-receive filter. The TDD transmit-receive filter includes a TDD transmit filter switchable between the first and second antennas. The TDD transmit filter is configured to provide a second SRS to the second antenna for transmission in a second SRS slot following the first SRS slot in a plurality of TDD frames. The TDD transmit-receive filter further includes a TDD receive filter coupled to the first antenna. The TDD receive filter is configured to present substantially the same impedance to the first antenna at the FDD receive frequency as the TDD transmit filter when the first FEM switches from transmitting the first SRS from the first antenna to transmitting the second SRS from the second antenna.

[0016] In another aspect, this document provides a wireless device. The wireless device includes RF front-end circuitry. The RF front-end circuitry includes a first antenna, a second antenna, a third antenna, and a fourth antenna. Each of the first antenna, the second antenna, the third antenna, and the fourth antenna is configured to transmit a corresponding of the first SRS, the second SRS, the third SRS, and the fourth SRS in a corresponding of a first SRS time slot, a second SRS time slot, a third SRS time slot, and a fourth SRS time slot in a plurality of TDD frames. The RF front-end circuitry further includes a first FEM. The first FEM includes an FDD transmit-receive filter coupled to the first antenna. The FDD transmit-receive filter is configured to transmit and receive FDD signals at an FDD transmit frequency and an FDD receive frequency, respectively. The first FEM further includes an FDD LNA coupled to the FDD transmit-receive filter. The first FEM also includes an input tuning circuit coupled to the first antenna. The first FEM further includes an output tuning circuit coupled to the output of the FDD LNA. The first FEM also includes a TDD transmit-receive filter coupled to both the first antenna and the second antenna.The TDD transmit-receive filter is configured to provide the first SRS to the first antenna for transmission in the first SRS time slot of each of the plurality of TDD frames. The TDD transmit-receive filter is also configured to provide the second SRS to the second antenna for transmission in the second SRS time slot following the first SRS time slot of each of the plurality of TDD frames.

[0017] In another aspect, this document provides a method for configuring RF front-end circuitry. The method includes configuring each of a first antenna, a second antenna, a third antenna, and a fourth antenna to transmit a first SRS, a second SRS, a third SRS, and a fourth SRS in a corresponding of a first SRS time slot, a second SRS, a third SRS, and a fourth SRS time slot of each of the plurality of TDD frames. The method further includes coupling a first FDD transmit-receive filter to the first antenna to transmit and receive FDD signals at an FDD transmit frequency and an FDD receive frequency, respectively. The method further includes coupling a TDD transmit filter to the second antenna to provide the second SRS to the second antenna for transmission in the second SRS time slot following the first SRS time slot in each of the plurality of TDD frames. The method also includes coupling a TDD receive filter to the first antenna to present substantially the same impedance to the first antenna at the FDD receive frequency as the TDD transmit filter during a switch from transmitting the first SRS from the first antenna to transmitting the second SRS from the second antenna.

[0018] In another aspect, this document provides a method for configuring RF front-end circuitry. The method includes configuring each of a first antenna, a second antenna, a third antenna, and a fourth antenna to transmit a first SRS, a second SRS, a third SRS, and a fourth SRS in a corresponding of a first SRS time slot, a second SRS, a third SRS, and a fourth SRS time slot in each of the plurality of TDD frames. The method further includes coupling an FDD transmit-receive filter to the first antenna to transmit and receive FDD signals at the FDD transmit frequency and FDD receive frequency, respectively. The method further includes coupling an FDD LNA to the FDD transmit-receive filter. The method further includes coupling an input tuning circuit to the first antenna. The method further includes coupling an output tuning circuit to the output of the FDD LNA.The method further includes coupling a TDD transmit-receive filter to the first antenna and the second antenna to provide the first SRS to the first antenna for transmission in the first SRS time slot of each of the plurality of TDD frames, and to provide the second SRS to the second antenna for transmission in the second SRS time slot following the first SRS time slot of each of the plurality of TDD frames.

[0019] Those skilled in the art will understand the scope of this disclosure and realize its additional aspects after reading the following preferred embodiments in conjunction with the accompanying drawings. Brief Description of the Drawings

[0020] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate various aspects of this disclosure and explain the principles of this disclosure in conjunction with embodiments.

[0021] Figure 1 is a schematic diagram illustrating an exemplary illustration of providing multiple Time Division Duplex (TDD) frames and time slots, wherein a mobile communication device can report downlink channel quality measurements in multiple Sounding Reference Signal (SRS) symbols;

[0022] Figure 2 is a schematic diagram of an exemplary conventional radio frequency (RF) front-end circuit, wherein a large phase / gain jump may occur at the output of a Frequency Division Duplex (FDD) Low Noise Amplifier (LNA) when switching TDD uplink SRS transmissions between multiple antennas;

[0023] Figure 3 is a table illustrating the potential impact of large phase / gain jumps on the overall FDD system throughput;

[0024] Figure 4 is a schematic diagram of an exemplary RF front-end circuit configured to reduce large phase / gain jumps in the conventional RF front-end circuit of Figure 2 according to an embodiment of the present disclosure;

[0025] Figure 5 is a schematic diagram illustrating an exemplary illustration of a High Frequency Band (HB) transmit-receive filter that may be provided in the RF front-end circuit of Figure 2 to help reduce large phase / gain jumps;

[0026] Figure 6 is a schematic diagram of an exemplary RF front-end circuit configured according to another embodiment of the present disclosure;

[0027] Figure 7 is a schematic diagram of an exemplary RF front-end circuit configured according to another embodiment of the present disclosure;

[0028] Figure 8 is a schematic diagram of an exemplary communication device in which the RF front-end circuits of Figures 4, 6 and 7 can be configured;

[0029] Figure 9 is a flowchart of an exemplary process for configuring the RF front-end circuits of Figures 4 and 6; and

[0030] Figure 10 is a flowchart of an exemplary process for configuring the RF front-end circuit of Figure 7. Specification 4 / 10 pages 9 CN 121889998 A Detailed Description

[0031] The embodiments described below represent the information required to enable those skilled in the art to practice the embodiments and illustrate the best mode for practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will understand the application of these concepts specifically set forth herein.It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0032] It will be understood that although terms such as first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish different elements. For example, a first element may be referred to as a second element; similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0033] It should be understood that when an element (e.g., a layer, region, or substrate) is referred to as “on (another element)” or “extends to (another element)”, the element may be directly on or directly to the other element, or there may also be an intermediate element. In contrast, when an element is referred to as “directly on (another element)” or “directly to (another element)”, there is no intermediate element. Similarly, it should be understood that when an element (e.g., a layer, region, or substrate) is referred to as “above (another element)” or “extends to (another element)”, the element may be directly above or directly to the other element, or there may be an intermediary element present. In contrast, when an element is referred to as “directly above (another element)” or “directly to (another element)”, there is no intermediary element. It should also be understood that when an element is referred to as “connected” or “coupled” to another element, the element may be directly connected or coupled to the other element or there may be an intermediary element present. In contrast, when an element is referred to as “directly connected” or “directly coupled” to another element, there is no intermediary element.

[0034] Relative terms (e.g., “below” or “above” or “top” or “bottom” or “horizontal” or “vertical”) may be used herein to describe the relationship of an element, layer, or region to another element, layer, or region, as illustrated in the figures. It should be understood that, in addition to the orientations depicted in the figures, these terms and the terms discussed above are also intended to cover different orientations of the device.

[0035] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. As used herein, unless clearly indicated otherwise in the context, the singular forms “a,” “an,” and “the” are also intended to include the plural forms. It will be further understood that the terms “comprising,” “including,” and / or “containing,” as used herein, indicate the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0036] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art.It will be further understood that the terms used herein should be interpreted in a meaning consistent with the context of this specification and related prior art, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0037] Embodiments of this disclosure relate to radio frequency (RF) front-end circuitry. The RF front-end circuitry may be disposed in a wireless device to support parallel time division duplex (TDD) and frequency division duplex (FDD) communication. Specifically, the RF front-end circuitry shares multiple antennas between transmitting a TDD sounding reference signal (SRS) in the TDD uplink and transmitting FDD signals in the FDD downlink / uplink. In the embodiments disclosed herein, the RF front-end circuitry is configured to reduce phase / gain hopping in the downlink / uplink FDD signals while switching TDD SRS transmission between the shared antennas. By reducing the phase / gain transition in the downlink / uplink FDD signal during SRS transmission, it is possible to improve the error vector magnitude (EVM) and / or signal-to-noise ratio (SNR) of the downlink / uplink FDD signal, thereby maintaining FDD throughput during FDD communication.

[0038] Before discussing the RF front-end circuitry of this disclosure starting with FIG4, a brief overview of existing RF front-end circuitry is first provided with reference to FIG2 and 3 to help explain the technical problem to be solved by the RF front-end circuitry of this disclosure. Specification 5 / 10 pages 10 CN 121889998 A

[0039] FIG2 is a schematic diagram of an exemplary existing RF front-end circuitry 14, wherein a phase / gain transition may occur at the output 16 of an FDD intermediate band (MB) low noise amplifier (LNA) 18 when switching multiple TDD uplink SRS transmissions from SRS0 to SRS3 between multiple antennas ANT0 to ANT3. The existing RF front-end circuitry 14 includes a first front-end module (FEM) 20 and a second FEM 22. The first FEM 20 is coupled to antenna ANT0 (also referred to as the first antenna) and antenna ANT1 (also referred to as the second antenna). The second FEM 22 is coupled to antenna ANT2 (also referred to as the third antenna) and antenna ANT3 (also referred to as the fourth antenna). Antennas ANT0 to ANT3 are shared between transmitting SRS SRS0 to SRS1 in, for example, the TDD high-frequency band (HB) of band 40 / 41 and transmitting / receiving FDD signal 24 in, for example, the FDD MB of band 1 / 3 / 25 / 66.

[0040] In the FDD MB, the existing RF front-end circuitry 14 is configured to transmit and receive FDD signal 24 via the first antenna ANT0, the second antenna ANT1, the third antenna ANT2 and the fourth antenna ANT3 based on a multiple-input multiple-output (MIMO) scheme. The existing RF front-end circuitry 14 is also configured to receive FDD signal 24 via the first antenna ANT0 based on a diversity reception (DRX) scheme.In this document, the first antenna ANT0 is coupled to the FDD MB LNA 18 (also referred to as the MB LNA) via a first FDD MB transmit-receive filter 26 (also referred to as the first FDD transmit-receive filter) configured to transmit a signal (e.g., FDD signal 24) in the MB. In this respect, the first FDD MB transmit-receive filter 26 may also be referred to as the FDD MB transmit-receive filter. The second antenna ANT1, the third antenna ANT2, and the fourth antenna ANT3 are coupled to the second FDD MB transmit-receive filter 28 (also referred to as the second FDD transmit-receive filter), the third FDD MB transmit-receive filter 30A (also referred to as the third FDD transmit-receive filter), and the fourth FDD MB transmit-receive filter 30B (also referred to as the fourth FDD transmit-receive filter), respectively. The second FDD MB transmit-receive filter 28, the third FDD MB transmit-receive filter 30A, and the fourth FDD MB transmit-receive filter 30B are configured to exclusively transmit the FDD signal 24 in the MB. More specifically, the first FDD MB transmit-receive filter 26 and the second FDD MB transmit-receive filter 28 are coupled to the first antenna ANT0 and the second antenna ANT1 via the first antenna switching circuit 32, respectively, while the third FDD MB transmit-receive filter 30A and the fourth FDD MB transmit-receive filter 30B are coupled to the third antenna ANT2 and the fourth antenna ANT3 via the second antenna switching circuit 34, respectively.

[0041] In TDD HB, the existing RF front-end circuit 14 is configured to transmit SRS0 via the first antenna ANT0 during OFDM time slot 3 in FIG. 1, transmit SRS1 via the second antenna ANT1 during OFDM time slot 8 in FIG. 1, transmit SRS2 via the third antenna ANT2 during OFDM time slot 13 in FIG. 1, and transmit SRS3 via the fourth antenna ANT3 during OFDM time slot 18 in FIG. 1. As shown in FIG. 1, each of OFDM time slots 3, 8, 13 and 18 is a flexible time slot (F). In this regard, the existing RF front-end circuit 14 needs to be switched sequentially between the first antenna ANT0, the second antenna ANT1, the third antenna ANT2, and the fourth antenna ANT3 based on the sequential order of OFDM slots 3, 8, 13, and 18 in (multiple) TDD frames 10.

[0042] The existing RF front-end circuit 14 also includes a TDD HB transmit-receive filter 36, which is also coupled to the first antenna ANT0 and the second antenna ANT1 via the first antenna switching circuit 32. Hereinafter, the TDD HB transmit-receive filter 36 is configured to provide SRS0 and SRS1 to the first antenna ANT0 and the second antenna ANT1 for transmission in OFDM slots 3 and 8 in (multiple) TDD frames 10, respectively.Furthermore, the TDD HB transmit-receive filter 36 is also configured to provide SRS2 and SRS3 to the third antenna ANT2 and the fourth antenna ANT3 via the second antenna switching circuit 34 for transmission in OFDM slots 13 and 18 of the (multiple) TDD frames 10, respectively.

[0043] It is worth noting that a phase / gain transition may occur at output 16, especially when the existing RF front-end circuit 14 switches from transmitting SRS0 via the first antenna ANT0 to transmitting SRS1 via the second antenna ANT1. This is because, during the switch from the first antenna ANT0 to the second antenna ANT1, the TDD HB transmit-receive filter 36 at the first antenna ANT0 is momentarily decoupled from the first FDD MB transmit-receive filter 26, thereby causing impedance mismatch to the first FDD MB transmit-receive filter 26 in the absence of the TDD HB transmit-receive filter 36. Such transient impedance mismatches can cause phase / gain jumps at output 16 of FDD MB LNA 18, which can negatively affect the throughput of FDD signal 24 due to EVM and / or SNR degradation in FDD signal 24. Furthermore, since each of antennas ANT0 to ANT3 also switches between transmitting in one of the corresponding SRS time slots SRS0 to SRS3 and transmitting / receiving in non-SRS time slots (e.g., FDD TX / RX / DRX), multiple phase / gain jumps may occur at output 16 of FDD MB LNA 18 during each SRS cycle (SRS0 SRS1 SRS2 SRS3).

[0044] Figure 3 is Table 38, which illustrates the potential impact of phase / gain jumps at output 16 of FDD MB LNA 18 on the throughput of FDD signal 24 in a specific scenario involving only the first antenna ANT0 and the second antenna ANT1. As illustrated herein, the throughput of the FDD signal 24 will be impaired when the phase jump is greater than two degrees (2°) and / or when the gain jump is greater than two decibels (2 dB). Therefore, when switching from transmitting SRS0 via the first antenna ANT0 to transmitting SRS1 via the second antenna ANT1 and returning from the fourth antenna ANT3 to the first antenna ANT0 at the end of each SRS cycle (SRS0 SRS1 SRS2 SRS3), it is necessary to limit the phase jump to less than 2° and the gain jump to less than 2 dB.

[0045] In this regard, FIG4 is a schematic diagram of an exemplary RF front-end circuit 40 configured to reduce the phase / gain jump experienced in the conventional RF front-end circuit 14 of FIG2 according to an embodiment of the present disclosure.It is worth noting that the RF front-end circuitry 40 is configured to reuse as many components and / or circuitry systems as possible from the existing RF front-end circuitry 14 to maximize backtracking compatibility and minimize design changes. Therefore, common elements between Figures 2 and 4 are shown with common element designations and will not be described further herein.

[0046] Hereinafter, the RF front-end circuitry 40 includes a first FEM 42 and a second FEM 44. The first FEM 42 includes a first antenna switching circuitry 46 coupled to a first antenna ANT0 and a second antenna ANT1. The second FEM 44 includes a second antenna switching circuitry 48 coupled to a third antenna ANT2, a fourth antenna ANT3, and optionally a fifth antenna ANT4. As illustrated below, the optional fifth antenna ANT4 may be removed in some embodiments of this disclosure.

[0047] Each of the first antenna switching circuitry 46 and the second antenna switching circuitry 48 may include any number and type of switches configured to provide the desired switching functionality in embodiments of this disclosure. In other words, the first antenna switching circuit 46 and the second antenna switching circuit 48 can be configured using any suitable number and type of switches based on any suitable layout without changing the operating principle of the RF front-end circuit 40.

[0048] The first FEM 42 differs from the first FEM 20 in the existing RF front-end circuit 14 in that the TDD HB transmit-receive filter 50 in the first FEM 42 replaces the TDD HB transmit-receive filter 36 in the first FEM 20. Hereinafter, the TDD HB transmit-receive filter 50 includes a TDD HB receive filter 52 and a TDD HB transmit filter 54 that are separate from each other. Specifically, the TDD HB receive filter 52 can be coupled to the first antenna ANT0 via the first antenna switching circuit 46, while the TDD HB transmit filter 54 can be switched between the first antenna ANT0 and the second antenna ANT1 simultaneously via the first antenna switching circuit 46.

[0049] In one embodiment, the RF front-end circuit 40 reuses the first FDD MB transmit-receive filter 26, the second FDD MB transmit-receive filter 28, the third FDD MB transmit-receive filter 30A, and the fourth FDD MB transmit-receive filter 30B from the existing RF front-end circuit 14 of FIG2 to maximize component reuse and achieve backtracking compatibility. Specifically, the first FDD MB transmit-receive filter 26 and the second FDD MB transmit-receive filter 28 are coupled to the first antenna ANT0 and the second antenna ANT1, respectively, via the first antenna switching circuit 46, while the third FDD MB transmit-receive filter 30A and the fourth FDD MB transmit-receive filter 30B are coupled to the fifth antenna ANT4 and the fourth antenna ANT3, respectively, via the second antenna switching circuit 48.

[0050] The RF front-end circuit 40 may further include a second TDD HB receiving filter 56, a third TDD HB receiving filter 58, and a fourth TDD HB receiving filter 60. The second TDD HB receiving filter 56 is coupled to the second antenna ANT1 via the first antenna switching circuit 46, while the third TDD HB receiving filter 58 and the fourth TDD HB receiving filter 60 are coupled to the third antenna ANT2 and the fourth antenna ANT3 via the second antenna switching circuit 48, respectively. In one embodiment, each of the first FDD MB transmit-receive filter 26, the second FDD MB transmit-receive filter 28, the third FDD MB transmit-receive filter 30A, and the fourth FDD MB transmit-receive filter 30B may include a corresponding FDD transmit filter 62T and a corresponding FDD receive filter 62R. In other words, each of the first FDD MB transmit-receive filter 26, the second FDD MB transmit-receive filter 28, the third FDD MB transmit-receive filter 30A, and the fourth FDD MB transmit-receive filter 30B can be a duplex filter or a multiplexed filter. In this regard, the FDD transmit filter 62T and the FDD receive filter 62R can be configured to share one of the antennas ANT0, ANT1, ANT2, and ANT3 via the respective common antenna ports (not shown) of each FDD TRX filter. For example, the Bn1 TX, Bn1 RX, Bn3 TX, and Bn3 RX filters can share the respective antennas ANT0, ANT1, ANT2, and ANT3 via antenna ports.

[0051] When the RF front-end circuitry 40 switches from transmitting SRS0 via the first antenna ANT0 to transmitting SRS1 via the second antenna ANT1, the TDD HB receive filter 52 switches to the first antenna ANT0. In one embodiment, the TDD HB receive filter 52 can be switched to the first antenna ANT0 via a switch 64. The switch 64, which is open before the RF front-end circuit 40 switches from the first antenna ANT0 to the second antenna ANT1, closes when the RF front-end circuit 40 switches from the first antenna ANT0 to the second antenna ANT1. By coupling the TDD HB receive filter 52 to the first antenna ANT0 via the switch 64, the TDD HB receive filter 52 can provide a load similar to the FDD receive filter 62R in the first FDD MB transmit-receive filter 26, thus helping to reduce the phase / gain jump at the output 16 of the FDD MB LNA 18.

[0052] FIG5 is a schematic diagram providing an exemplary illustration of the TDD HB transmit-receive filter 50 in the RF front-end circuit 40 of FIG4.Common components between Figures 4 and 5 are shown with common component labels and will not be described further herein.

[0053] In one embodiment, the TDD HB receive filter 52 includes an RX filter 66 and an RX matching circuit 68. Similarly, the TDD HB transmit filter 54 includes a TX filter 70 and a TX matching circuit 72. Understandably, to provide matching impedance with the first HB transmit filter 54, the TDD HB receive filter 52 needs to have the same or substantially the same impedance as the TDD HB transmit filter 54 at the FDD MB transmit and receive frequencies, respectively, after passing through the FDD transmit filter 62T and the FDD receive filter 62R. Hereinafter, the impedance provided by the TDD HB receive filter 52 is considered substantially the same as the impedance of the TDD HB transmit filter 54 when the difference between the two impedances is less than 7%. In this regard, in one embodiment, the TDD HB receive filter 52 and the TDD HB transmit filter 54 are integrated into a single filter die to help eliminate any potential material variations. Furthermore, the TDD HB receive filter 52 and the TDD HB transmit filter 54 need to have appropriate topology, layout, and component values. Additionally, the RX matching circuit 68 and the TX matching circuit 72 must be fine-tuned to present the same or substantially the same effective capacitance at the MB (e.g., bands 1 / 3 / 25 / 66) transmit and receive frequencies. Specifically, the RX matching circuit 68 and the TX matching circuit 72 must be as symmetrical as possible. Simultaneously, the RX matching circuit 68 and the TX matching circuit 72 must be able to compensate for the difference between the RX trace (denoted as TRACERX) and the TX trace (denoted as TRACETX).

[0054] Referring back to FIG4, the first FEM 42 further includes a TDD HB LNA 74 and a TDD HB PA 76. The TDD HB LNA 74 is coupled to the TDD HB receive filter 52, thus enabling the RF front-end circuitry to receive HB signals via the first antenna ANT0. The TDD HB PA 76 is directly coupled to the TDD HB transmit filter 54 for transmitting SRS1 and other HB signals.

[0055] FIG6 is a schematic diagram of an exemplary RF front-end circuit 78 configured according to another embodiment of the present disclosure. Common elements between FIG4 and 6 are shown with common element reference numerals and will not be described again herein.

[0056] In this document, the RF front-end circuit 78 includes a first FEM 80 and a second FEM 82. The main difference between the RF front-end circuit 40 of FIG4 and the RF front-end circuit 78 herein is that the RF front-end circuit 78 no longer has a fifth antenna ANT4. It is worth noting that this is achieved by some rearrangement of the first FEM 80 and the second FEM 82.Specifically, in the first FEM 80, an HB switch 84 is added between the TDD HB PA 76 and the input 86 of the HB transmit filter 54. The HB switch 84 is also coupled to the third antenna ANT2 and the fourth antenna ANT3 via the second TDD HB transmit filter 87 and the second antenna switching circuit 48. Either the TDD HB transmit filter 87, the third TDD HB receive filter 58, or the fourth TDD HB receive filter 60 can be configured in the same manner as the TDD HB transmit-receive filter 50 to provide impedance matching between the second TDD HB transmit filter 87 and the third FDD MB transmit-receive filter 30A and the fourth FDD MB transmit-receive filter 30B at the MB FDD frequency, and to minimize phase and amplitude jumps at the third antenna ANT2 or the fourth antenna ANT3 during the transition from transmit SRS3 to transmit SRS4.

[0057] In one embodiment, the first FEM 80 may further include an input tuning circuit 88 and an output tuning circuit 90. In a non-limiting example, each of the input tuning circuit 88 and the output tuning circuit 90 may be a parallel inductor-capacitor (LC) circuit. Specifically, the input tuning circuit 88 is coupled to the first antenna ANT0, and the output tuning circuit 90 is coupled to the output 16 of the FDD MB LNA 18. The input tuning circuit 88 and the output tuning circuit 90 together may further compensate for the load at the MB frequency and minimize the phase / gain jump at the output 16 of the FDD MB LNA 18.

[0058] FIG7 is a schematic diagram of an exemplary RF front-end circuit 92 configured according to another embodiment of the present disclosure. Compared with the RF front-end circuit 40 of FIG4 and the RF front-end circuit 78 of FIG6, the RF front-end circuit 92 involves minimal changes from the existing RF front-end circuit 14 of FIG2. Common elements between Figures 2, 4, 6, and 7 are shown with common element labels and will not be described again herein.

[0059] Specifically, the RF front-end circuit 92 reuses the second FEM 22 in the existing RF front-end circuit 14 of Figure 2. The RF front-end circuit 92 includes a first FEM 94, which is modified from the first FEM 20 in Figure 2 by adding the input tuning circuit 88 and the output tuning circuit 90 from Figure 6. Hereinafter, the TDD HB transmit-receive filter 36 is coupled to the first antenna ANT0 and the second antenna ANT1 via the first antenna switching circuit 32. Therefore, the TDD HB transmit-receive filter 36 is configured to provide SRS0 and SRS1 to the first antenna ANT0 and the second antenna ANT1 for transmission during OFDM slots 3 and 8 in the (multiple) TDD frames 10 of Figure 1, respectively.

[0060] The RF front-end circuit 40 of FIG. 4, the RF front-end circuit 78 of FIG. 6, and the RF front-end circuit 92 of FIG. 7 can be disposed in a communication device to support the embodiments described above. In this regard, FIG. 8 is a schematic diagram of an exemplary communication device 100 in which the RF front-end circuit 40 of FIG. 2, the RF front-end circuit 78 of FIG. 6, and the RF front-end circuit 92 of FIG. 7 can be provided.

[0061] In this document, the communication device 100 can be any type of communication device, such as a mobile communication terminal, a smartwatch, a tablet computer, a computer, a navigation device, an access point, a base station (e.g., an eNB, gNB, etc.), and any other wireless communication device that supports wireless communication, such as a cellular mobile phone, a wireless local area network (WLAN), Bluetooth, ultra-wideband (UWB), and near-field communication. The communication device 100 typically includes a control system 102, a baseband processor 104, a transmitting circuit system 106, a receiving circuit system 108, an antenna switching circuit system 110, multiple antennas 112, and a user interface circuit system 114. In a non-limiting example, for example, the control system 102 may be a field-programmable gate array (FPGA). In this regard, the control system 102 may include at least one microprocessor(s), one or more embedded memory circuits, and one or more communication bus interfaces. The receiving circuitry system 108 receives radio frequency signals from one or more base stations via multiple antennas 112 and via an antenna switching circuitry system 110. A low-noise amplifier and filter work together to amplify and eliminate broadband interference in the received signal for processing. Then, a down-conversion and digitization circuitry system (not shown) down-converts the filtered received signal to an intermediate frequency or baseband frequency signal, and then digitizes it into one or more digital streams using an analog-to-digital converter (ADC).

[0062] The baseband processor 104 processes the digitized received signal to retrieve information or data bits transmitted in the received signal. This processing typically includes demodulation, decoding, and error correction operations, as will be discussed in more detail below. The baseband processor 104 is typically implemented in one or more digital signal processors (DSPs) and application-specific integrated circuits (ASICs).

[0063] For transmission, the baseband processor 104 receives digitized data representing voice, data, or control information from the control system 102 and encodes it for transmission. The encoded data is output to the transmission circuitry system 106, where a plurality of digital-to-analog converters (DACs) convert the digitized data into analog signals, and a modulator modulates the analog signals into carrier signals at one or more desired transmission frequencies. A power amplifier amplifies the modulated carrier signals to a level suitable for transmission and delivers the modulated carrier signals to the antenna 112 via the antenna switching circuitry system 110.Multiple antennas 112 and the reconfigured transmit and receive circuit systems 106, 108 can provide spatial versatility. Those skilled in the art will understand the modulation and processing details.

[0064] In one embodiment, each of the RF front-end circuits 40, 78, and 92 may be located between the antenna switching circuit system 110 and the transmit circuit system 106 and / or between the antenna switching circuit system 110 and the receive circuit system 108. In another embodiment, each of the RF front-end circuits 40, 78, and 92 may be located within the antenna switching circuit system 110. Understandably, antenna 112 may include a first antenna ANT0, a second antenna ANT1, a third antenna ANT2, and a fourth antenna ANT3. Antenna 112 may further include a fifth antenna ANT4.

[0065] The RF front-end circuit 40 of FIG. 4 and the RF front-end circuit 78 of FIG. 6 may each be configured according to the process. In this regard, FIG9 is a flowchart of an exemplary process 200 for configuring the RF front-end circuit 40 of FIG4 and the RF front-end circuit 78 of FIG6.

[0066] Hereinafter, process 200 includes configuring each of the first antenna ANT0, the second antenna ANT1, the third antenna ANT2 and the fourth antenna ANT3 to transmit a corresponding of the first SRS SRS0, the second SRS SRS1, the third SRS SRS2 and the fourth SRS SRS3 in a corresponding of the first SRS time slot, the second SRS time slot, the third SRS time slot and the fourth SRS time slot in the TDD frame 10 (step 202). Process 200 also includes coupling a first FDD MB transmit-receive filter 26 to the first antenna ANT0 to transmit and receive FDD signal 24 at the FDD transmit frequency and the FDD receive frequency, respectively (step 204). Process 200 further includes coupling the TDD transmit filter 54 to the second antenna ANT1 to provide the second SRS SRS1 to the second antenna ANT1 for transmission in the second SRS time slot following the first SRS time slot in each of the TDD frames 10 (step 206). Process 200 further includes coupling the TDD receive filter 52 to the first antenna ANT0 to present substantially the same impedance to the first antenna ANT0 at the FDD receive frequency as the TDD transmit filter 54 during the switch from transmitting the first SRS SRS0 from the first antenna ANT0 to transmitting the second SRS SRS1 from the second antenna ANT1 (step 208).

[0067] The RF front-end circuitry 92 of FIG7 can also be configured according to the process. In this regard, FIG10 is a flowchart of an exemplary process 210 for configuring the RF front-end circuitry 92 of FIG7.

[0068] In this document, process 210 includes configuring each of the first antenna ANT0, the second antenna ANT1, the third antenna ANT2, and the fourth antenna ANT3 to transmit a corresponding of the first SRS SRS0, second SRS SRS1, third SRS SRS2, and fourth SRS SRS3 in a corresponding of the first SRS time slot, second SRS time slot, third SRS time slot, and fourth SRS time slot in the TDD frame 10 (step 212). Process 210 also includes coupling a first FDD MB transmit-receive filter 26 to the first antenna ANT0 to transmit and receive FDD signal 24 at the FDD transmit frequency and FDD receive frequency, respectively (step 214). Process 210 also includes coupling an FDD LNA 18 to the first FDD MB transmit-receive filter 26 (step 216). Process 210 also includes coupling an input tuning circuit 88 to the first antenna ANT0 (step 218). Process 210 further includes coupling the output tuning circuit 90 to the output 16 of the FDD LNA 18 (step 220). Process 210 further includes coupling the TDD HB transmit-receive filter 36 to the first antenna ANT0 and the second antenna ANT1 to provide the first SRS SRS0 to the first antenna ANT0 for transmission in the first SRS time slot of each of the TDD frames 10, and to provide the second SRS SRS1 to the second antenna ANT1 for transmission in the second SRS time slot following the first SRS time slot of each of the TDD frames 10 (step 222).

[0069] Those skilled in the art will understand improvements and modifications to the preferred embodiments of this disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the appended claims.Instruction manual, page 10 / 10, 15 CN 121889998 A, Figure 1; Instruction manual, Figure 1 / 10, page 16 CN 121889998 A, Figure 2; Instruction manual, Figure 2 / 10, page 17 CN 121889998 A, Figure 3; Instruction manual, Figure 3 / 10, page 18 CN 121889998 A, Figure 4; Instruction manual, Figure 4 / 10, page 19 CN 121889998 A, Figure 5; Instruction manual, Figure 5 / 10, page 20 CN 121889998 A, Figure 6; Instruction manual, Figure 6 / 10, page 21 CN 121889998 A, Figure 7; Instruction manual, Figure 7 / 10, page 22 CN 121889998 A, Figure 8; Instruction manual, Figure 8 / 10, page 23 CN 121889998 A, Figure 9; Instruction manual, Figure 9 / 10, page 24 CN 121889998 A, Figure 10 The instruction manual includes attached figures on page 10 / 10, 25 CN 121889998 A.

Claims

1. A radio frequency (RF) front-end circuit, comprising: The first antenna, the second antenna, the third antenna, and the fourth antenna are each configured to transmit a corresponding one of the first SRS, the second SRS, the third SRS, and the fourth SRS in a corresponding one of the first SRS, the second SRS, the third SRS, and the fourth SRS in a plurality of time-division duplex (TDD) frames. and The first front-end module, FEM, includes: A first frequency division duplex (FDD) transmit-receive filter is coupled to the first antenna and configured to transmit and receive FDD signals at the FDD transmit frequency and the FDD receive frequency, respectively; and TDD transmit-receive filters, which include: A TDD transmit filter, capable of switching between a first antenna and a second antenna and configured to provide the second SRS to the second antenna for transmission in the second SRS slot following the first SRS slot in each of the plurality of TDD frames; and A TDD receive filter, coupled to the first antenna and configured to present substantially the same impedance to the first antenna at the FDD receive frequency as the TDD transmit filter when the first FEM switches from transmitting the first SRS from the first antenna to transmitting the second SRS from the second antenna.

2. The RF front-end circuit according to claim 1, wherein the first FDD transmit-receive filter and the TDD transmit-receive filter are disposed in different filter dies.

3. The RF front-end circuit according to claim 1, wherein the TDD transmit filter and the TDD receive filter are disposed in the same filter die to eliminate material variation.

4. The RF front-end circuit according to claim 1, wherein: The TDD transmit filter includes a transmit matching circuit; and The TDD receiver filter includes a receiver matching circuit; The transmit matching circuit and the receive matching circuit are symmetrical and tuned to present substantially the same capacitance at the FDD transmit frequency and the FDD receive frequency.

5. The RF front-end circuit according to claim 1, wherein: The TDD transmit filter includes a transmit matching circuit; and The TDD receiver filter includes a receiver matching circuit; The transmit matching circuit and the receive matching circuit are asymmetrical, but are tuned to present substantially the same capacitance at the FDD receive frequency.

6. The RF front-end circuit of claim 1, further comprising a second FEM, the second FEM being coupled to the third antenna and the fourth antenna and configured to: The third SRS is provided to the third antenna for transmission in the third SRS slot following the second SRS slot in each of the plurality of TDD frames; and The fourth SRS is provided to the fourth antenna for transmission in the fourth SRS slot following the third SRS slot in each of the plurality of TDD frames.

7. The RF front-end circuit of claim 6, wherein the TDD transmit filter is further configured to forward the third SRS and the fourth SRS to the second FEM for transmission via the third antenna and the fourth antenna, respectively.

8. The RF front-end circuit of claim 6, wherein the second FEM is further configured to receive the third SRS and the fourth SRS via a high-frequency band switch coupled to the input of the TDD transmit filter.

9. The RF front-end circuit of claim 8, wherein the second FEM further comprises: An FDD transmit-receive filter, which is coupled to the third antenna; and The TDD receiver filter is coupled to the third antenna.

10. The RF front-end circuit according to claim 1, wherein: The first FEM further includes an FDD transmit-receive filter coupled to the second antenna and configured to transmit and receive the FDD signal at the FDD transmit frequency and the FDD receive frequency; An FDD low-noise amplifier (LNA) coupled to the FDD transmit-receive filter and configured to amplify the FDD signal received via the first antenna; TDD LNA, which is coupled to the TDD receiver filter; and A TDD power amplifier (PA) coupled to the TDD transmit filter.

11. The RF front-end circuit of claim 10, wherein the first FEM further comprises: An input tuning circuit is coupled to the first antenna; and An output tuning circuit is coupled to the output of the FDD LNA.

12. A radio frequency (RF) front-end circuit, comprising: The first antenna, the second antenna, the third antenna, and the fourth antenna are each configured to transmit a corresponding one of the first SRS, the second SRS, the third SRS, and the fourth SRS in a corresponding one of the first SRS, the second SRS, the third SRS, and the fourth SRS in a plurality of time-division duplex (TDD) frames. and The first front-end module, FEM, includes: A frequency division duplex (FDD) transmit-receive filter is coupled to the first antenna and configured to transmit and receive FDD signals at the FDD transmit frequency and the FDD receive frequency, respectively. The FDD low-noise amplifier (LNA) is coupled to the FDD transmit-receive filter; An input tuning circuit is coupled to the first antenna; Output tuning circuitry, coupled to the output of the FDD LNA; and A TDD transmit-receive filter, coupled to the first antenna and the second antenna, and configured to: The first SRS is provided to the first antenna for transmission in the first SRS time slot of each of the plurality of TDD frames; and The second SRS is provided to the second antenna for transmission in the second SRS slot following the first SRS slot in each of the plurality of TDD frames.

13. The RF front-end circuit of claim 12, wherein the TDD transmit-receive filter is disposed in a single filter die separate from the FDD transmit-receive filter.

14. A wireless device comprising a radio frequency (RF) front-end circuit, the RF front-end circuit including: The first antenna, the second antenna, the third antenna, and the fourth antenna are each configured to transmit a corresponding one of the first SRS, the second SRS, the third SRS, and the fourth SRS in a corresponding one of the first SRS, the second SRS, the third SRS, and the fourth SRS in a plurality of time-division duplex (TDD) frames. and The first front-end module, FEM, includes: A first frequency division duplex (FDD) transmit-receive filter is coupled to the first antenna and configured to transmit and receive FDD signals at the FDD transmit frequency and the FDD receive frequency, respectively; and TDD transmit-receive filters, which include: A TDD transmit filter, capable of switching between a first antenna and a second antenna and configured to provide the second SRS to the second antenna for transmission in the second SRS slot following the first SRS slot in each of the plurality of TDD frames; and A TDD receive filter, coupled to the first antenna and configured to present substantially the same impedance to the first antenna at the FDD receive frequency as the TDD transmit filter when the first FEM switches from transmitting the first SRS from the first antenna to transmitting the second SRS from the second antenna.

15. The wireless device of claim 14, wherein the first FDD transmit-receive filter and the TDD transmit-receive filter are disposed in different filter dies.

16. The wireless device of claim 14, wherein the TDD transmit filter and the TDD receive filter are disposed in the same filter die to eliminate material variations.

17. A wireless device comprising a radio frequency (RF) front-end circuit, the RF front-end circuit including: The first antenna, the second antenna, the third antenna, and the fourth antenna are each configured to transmit a corresponding one of the first SRS, the second SRS, the third SRS, and the fourth SRS in a corresponding one of the first SRS, the second SRS, the third SRS, and the fourth SRS in a plurality of time-division duplex (TDD) frames. and The first front-end module, FEM, includes: A frequency division duplex (FDD) transmit-receive filter is coupled to the first antenna and configured to transmit and receive FDD signals at the FDD transmit frequency and the FDD receive frequency, respectively. An FDD low-noise amplifier (LNA) coupled to the FDD transmit-receive filter; An input tuning circuit is coupled to the first antenna; Output tuning circuitry, coupled to the output of the FDD LNA; and A TDD transmit-receive filter, coupled to the first antenna and the second antenna, and configured to: The first SRS is provided to the first antenna for transmission in the first SRS time slot of each of the plurality of TDD frames; and The second SRS is provided to the second antenna for transmission in the second SRS slot following the first SRS slot in each of the plurality of TDD frames.

18. A method for configuring a radio frequency (RF) front-end circuit, comprising: Configure one of the first antenna, the second antenna, the third antenna and the fourth antenna to transmit one of the first SRS, the second SRS, the third SRS and the fourth SRS in one of the corresponding slots of the first detection reference signal SRS, the second SRS, the third SRS and the fourth SRS in one of the multiple time division duplex (TDD) frames. The first frequency division duplex (FDD) transmit-receive filter is coupled to the first antenna to transmit and receive FDD signals at the FDD transmit frequency and the FDD receive frequency, respectively. A TDD transmit filter is coupled to the second antenna to provide the second SRS to the second antenna for transmission in the second SRS slot following the first SRS slot in each of the plurality of TDD frames; and The TDD receive filter is coupled to the first antenna so that, during the switch from transmitting the first SRS from the first antenna to transmitting the second SRS from the second antenna, it presents substantially the same impedance to the first antenna at the FDD receive frequency as the TDD transmit filter.

19. The method of claim 18, further comprising placing the TDD transmit filter and the TDD receive filter in the same filter die to eliminate material variations.

20. A method for configuring a radio frequency (RF) front-end circuit, comprising: Configure one of the first antenna, the second antenna, the third antenna and the fourth antenna to transmit one of the first SRS, the second SRS, the third SRS and the fourth SRS in one of the corresponding slots of the first detection reference signal SRS, the second SRS, the third SRS and the fourth SRS in one of the multiple time division duplex (TDD) frames. A frequency division duplex (FDD) transmit-receive filter is coupled to the first antenna to transmit and receive FDD signals at the FDD transmit frequency and the FDD receive frequency, respectively. Couple the FDD low-noise amplifier (LNA) to the FDD transmit-receive filter; Couple the input tuning circuit to the first antenna; Couple the output tuning circuit to the output of the FDD LNA; and A TDD transmit-receive filter is coupled to the first antenna and the second antenna to provide the first SRS to the first antenna for transmission in the first SRS time slot of each of the plurality of TDD frames, and to provide the second SRS to the second antenna for transmission in the second SRS time slot following the first SRS time slot of each of the plurality of TDD frames.

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