LED arrays

Abstract

An LED array and a method of manufacturing an LED array, the method comprising the steps of: forming a semiconductor layer (100) from a group III nitride material; forming a dielectric mask layer (104) over the semiconductor layer, the dielectric mask layer having an array of holes therethrough, each hole exposing a region of the semiconductor layer; and causing an LED structure (108) to be grown in each of the holes.

Description

(19) State Intellectual Property Office (12) Invention Patent Application (10) Application Publication Number (43) Application Publication Date (21) Application Number 202511004658.4 (22) Application Date 2019.10.08 (30) Priority Data 1816455.8 2018.10.09 GB (62) Divisional Application Data 201980066550.4 2019.10.08 (71) Applicant Snapp Company Address California, USA (72) Inventor Wang Tao (74) Patent Agency Beijing Kangxin Intellectual Property Agency Co., Ltd. 11240 Patent Attorney Shi Jingjing (51) Int.Cl. H10H 29 / 14 (2025.01) H10H 29 / 01 (2025.01) (54) Title of Invention: LED Array (57) Abstract: An LED array and a method of manufacturing an LED array, the method comprising the steps of: forming a semiconductor layer (100) from a group III nitride material; forming a dielectric mask layer (104) above the semiconductor layer, the dielectric mask layer having an array of holes through the dielectric mask layer, each hole exposing a region of the semiconductor layer; and growing an LED structure (108) in each hole. Claims (2 pages), Description (6 pages), Drawings (8 pages), CN 121038476 A, 2025.11.28, CN 1 21 03 84 76 A. 1. An LED array, comprising: a semiconductor layer including a first sublayer and a second sublayer; a dielectric layer extending over the semiconductor layer and having an array of holes through the dielectric layer, each hole exposing a corresponding region of the first sublayer; and LED devices formed on each exposed region; wherein each LED device includes a first layer having p-type or n-type conductivity, at least one active layer formed over the first layer, and a second layer formed over the active layer, the second layer having n-type or p-type conductivity opposite to the conductivity type of the first layer; wherein the conductivity type of the first sublayer of the exposed semiconductor layer is the same as the conductivity type of the first layer in the LED device that is in contact with the first sublayer of the exposed semiconductor layer; 1. The first sublayer of the exposed semiconductor layer comprises the same Group III nitride material as the first layer of the LED device; and the upper surface of the second sublayer of the semiconductor layer is not higher than the upper surface of the first layer of the LED device. 2. The LED array of claim 1, wherein the upper surface of the at least one active layer is below the upper surface of the dielectric layer. 3. The LED array of claim 1, wherein the semiconductor layer provides a common contact to all the LED devices.4. The LED array of claim 1, wherein the semiconductor layer is doped. 5. The LED array of any one of claims 1 to 4, wherein the heterogeneous interface between the first sublayer and the second sublayer is arranged to form a two-dimensional charge carrier gas. 6. The LED array of any one of claims 1 to 4, wherein the LED device is a micro LED device, and the array is a regular array with a spacing of 4 μm to 500 μm. 7. The LED array of any one of claims 1 to 4, further comprising: a plurality of contact layer regions formed above the LED devices, wherein each contact layer region is in electrical contact with a corresponding set of the LED devices. 8. A method of manufacturing a light-emitting diode (LED) array, the method comprising: forming a semiconductor layer including a first sublayer and a second sublayer; forming a dielectric layer above the semiconductor layer having an array of holes through the dielectric layer, each hole exposing a region of the first sublayer of the semiconductor layer; and growing an LED device in each exposed region. Each of the LED devices includes a first layer having p-type or n-type conductivity, at least one active layer formed above the first layer, and a second layer formed above the active layer, the second layer having n-type or p-type conductivity opposite to that of the first layer; wherein the conductivity type of the first sublayer of the exposed semiconductor layer is the same as the conductivity type of the first layer in the LED device that is in contact with the first sublayer of the exposed semiconductor layer; wherein the first sublayer of the exposed semiconductor layer and the first layer of the LED device contain the same Group III nitride material; and wherein the upper surface of the second sublayer of the semiconductor layer is not higher than the upper surface of the first layer of the LED device. 9. A method according to claim 8, wherein the step of forming the dielectric layer includes: growing a layer of dielectric material and etching an array of holes into the layer of dielectric material. Claims 1 / 2 Page 2 CN 121038476 A 10. A method according to claim 8 or 9, further comprising: etching each region of the exposed region of the first sublayer of the semiconductor layer before growing the LED device in each of the holes. Claims 2 / 2 Page 3 CN 121038476 A LED Array

[0001] This application is a divisional application of Chinese application No. 201980066550.4, filed on October 8, 2019, entitled "LED Array", the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention relates to light-emitting diodes (LEDs) and methods for manufacturing LED arrays. The present invention has specific applications in micron-scale LED arrays.Background Art

[0003] The development demand for micron-sized group III nitride light-emitting diodes (LEDs) (also known as micro-sized LEDs or micro-LEDs (μ LEDs)) has increased significantly. Micro-LEDs are key components for next-generation displays and visible light communication (VLC) applications. Compared to organic light-emitting diodes (OLEDs) and liquid crystal displays (LCDs), group III nitride μ LEDs exhibit many unique characteristics for display applications. Unlike LCDs, group III nitride microdisplays, with μ LEDs as the main component, are self-emitting. Monochrome displays using μ LEDs exhibit high resolution, high efficiency, and high contrast. OLEDs typically operate at current densities several orders of magnitude lower than semiconductor LEDs to maintain a reasonable lifespan. Therefore, OLEDs have relatively low brightness, typically 3000 cd / m² for full-color displays, while group III nitride μ LEDs exhibit high brightness exceeding 10⁵ cd / m². Of course, compared to OLEDs, group III nitride μ LEDs inherently exhibit longer operating lifespan and chemical robustness. Therefore, it is expected that in the near future, group III nitride μLEDs will likely replace LCDs and OLEDs for high-resolution and high-brightness displays in various applications such as smartphones. In addition to display applications, μLEDs exhibit significantly reduced junction capacitance due to their smaller size compared to wide-area LEDs, and thus may lead to high-speed transmission with GHz modulation bandwidth in VLC applications.

[0004] Currently, group III nitride μLEDs are specifically fabricated on standard group III nitride LED wafers by means of a combination of standard lithography and subsequent dry etching processes, which is similar to the fabrication of conventional wide-area LEDs with a device area of ​​300 μm × 300 μm or even larger. (Z.Y.Fan, J.Y.Lin and H.X.Jiang, J.Phys.D: Appl.Phys.41,094001 (2008); HXJiang and JYLin, Optical Express 21,A476 (2013)). The only major difference in device manufacturing between wide-area LEDs and μLEDs is device size. Typically, μLEDs range in diameter from 50 μm to several micrometers.

[0005] There are many fundamental problems with current methods for manufacturing group III nitride μLEDs. First, in the semiconductor industry, dry etching processes such as inductively coupled plasma (ICP) dry etching have been widely used to define large-area LED mesa and μLED mesa.Therefore, surface and sidewall damage caused by dry etching processes significantly increases nonradiative recombination rates (F. Olivier, A. Daami, C. Licitra and F. Templier, Appl. Phys. Lett. 111, 022104 (2017); S. Konoplev, K. A. Bulashevich and S. Y. Karpov, Phys. Status Solidi A 215, 1700508 (2017); W. Chen, G. Hu, J. Lin, J. Jiang, M. Liu, Y. Yang, G. Hu, Y. Lin, Z. Wu, Y. Liu and B. Zhang, Appl. Phys. Express 8, 032102 (2015); C.-M. Yang, D.-S. Kim, Y. SPark, J.-H. Lee, Y. Slee and J. H. Lee, Opt. Photonics J. 2, 185 (2012); Y. Zhang, E. Guo, Z. Li, T. Wei, J. Li, X. Ye and G. Wang, IEEE Photonics Technol. Lett. 24, 243 (2012); P. Zuo, B. Zhao, S. Yan, G. Yue, H. Yang, Y. Li, H. Wu, Y. Jiang, H. Jia, J. Zhou and H. Chen, Specification 1 / 6 page 4 CN 121038476 A Opt. Quantum Electron. 48, 1 (2016)). This problem becomes more severe in LEDs with reduced size, especially for μLEDs with a large surface area to volume ratio.To date, all reports indicate that the peak external quantum efficiency (EQE) decreases with decreasing μLED size (D. Hwang, A. Mughal, C. D. Pynn, S. Nakamura and S. P. DenBaars, Appl. Phys. Express 10, 032101 (2017); P. Zuo, B. Zhao, S. Yan, G. Yue, H. Yang, Y. Li, H. Wu, Y. Jiang, H. Jia, J. Zhou and H. Chen, Opt. Quantum Electron. 48, 1 (2016); F. Olivier, S. Tirano, L. Dupré, B. Aventurier, C. Largeron and F. Templier , J. Lumin. 191, 112 (2017); P. Tian, ​​JJDMcKendry, J. Herrnsdorf, S. Watson, R. Ferreira, IMWatson, E. Gu, A.E. Kelly and M.Dawson, Appl. Phys. Lett. 105, 171107 (2014)).

[0006] The reason for this reduction is due to surface recombination and mesa sidewall damage caused by dry etching, resulting in non-radiative recombination sidewall defects. Although sidewall passivation using dielectric materials can reduce the impact of plasma damage in LEDs to some extent, this improvement is negligible even if advanced atomic layer deposition (ALD) technology is used instead of standard plasma enhanced chemical vapor deposition (PECVD) technology for surface passivation.

[0007] Secondly, the current method often results in the waste of large areas of epitaxial wafers, which involves a combination of standard photolithography and subsequent dry etching processes. For example, to fabricate a μLED array with a diameter of 12 μm and a spacing of 15 μm (further reducing the spacing using current photolithography techniques is very challenging), 50% of the epitaxial wafer material needs to be etched away, which means wasting 50% of the epitaxial wafer.

[0008] Again, future smart displays, including microdisplays and VLCs, need to operate with ultra-high response speeds. Therefore, ultra-fast electrical channels are required for the interconnection between the LED driver transistors and the individual LED components.

[0009] Current μLED arrays are electrically connected via n-GaN on a group III nitride LED wafer, wherein the typical manufacturing process for a μLED array is to use a dry etching process to etch the LED wafer down to the n-GaN, which is the only electrical channel connecting all the μLEDs.

[0010] Therefore, to address these issues, it is desirable to develop different methods for growing and then manufacturing μLED arrays. To meet industry needs, any new method must be scalable. Summary of the Invention

[0011] The present invention provides a method for manufacturing a light-emitting diode (LED) array, the method comprising the steps of: forming a semiconductor layer from a group III nitride material; forming a dielectric mask layer above the semiconductor layer, the dielectric mask layer having an array of holes passing through the dielectric mask layer, each hole exposing a region of the semiconductor layer; and growing an LED structure in each of the holes.

[0012] The LED structure can be grown on the exposed region of the semiconductor layer. Growth is typically in an upward direction because growth from the dielectric sidewalls of the holes does not occur. Therefore, upward growth of the LED structure within the holes results in a layered LED structure, and each of the layers is typically flat or planar with a substantially constant thickness.

[0013] The semiconductor layers may be formed, for example, on a group III nitride (such as GaN), or on sapphire, silicon (Si), silicon carbide (SiC), or a glass substrate.

[0014] The step of growing the LED structure in each of the holes may include: growing an n-type layer, at least one active layer, and a p-type layer in each of the holes. At least one active layer may be located between the n-type layer and the p-type layer. At least one active layer may include at least one quantum well layer and may include multiple quantum well layers. These may be formed, for example, by InGaN or another suitable group III nitride material. The n-type layer and the p-type layer may also be formed by group III nitride materials (such as GaN, InGaN, or AlGaN). Specification 2 / 6 pages 5 CN 121038476 A

[0015] The upper surface of at least one active layer may be below the top of the dielectric layer. In the case of a single quantum well layer, the upper surface is the upper surface of the quantum well layer. In the case of multiple quantum well layers, the upper surface is the upper surface of the uppermost quantum well layer. The upward direction can be defined as the growth direction of the semiconductor layer and / or the LED structure.

[0016] The step of forming the dielectric mask layer may include the following steps: growing a dielectric material layer; for example, forming a mask over the dielectric mask layer using photolithography; and using the mask to etch an array of holes into the dielectric material layer.Alternatively, the dielectric layer can be grown around the region forming the aperture, with the aperture formed during the growth of the dielectric layer, for example, using a mask formed by photolithography, followed by growth and / or etching.

[0017] The method may also include etching each of the exposed regions of the semiconductor layer before growing the LED structure in each of the apertures.

[0018] The semiconductor layer can provide common contact with all LED structures.

[0019] The semiconductor layer may be doped. For example, the semiconductor layer may comprise a monolayer of n-type or p-type group III nitride material. Alternatively, the semiconductor layer may comprise a first sublayer and a second sublayer having a heterojunction between them, the heterojunction being arranged to form a two-dimensional charge carrier gas at the heterojunction. The sublayer may form a buffer layer and a barrier layer. The two-dimensional charge carrier gas may, for example, be a two-dimensional electron gas (2DEG). Two-dimensional hole gas (2DHG) may also be used, but typically these hole gases have lower charge carrier density and / or mobility. It is well known that 2DEGs can be formed at the interface between two layers of a heterostructure, including, for example, a GaN layer and an AlGaN layer or an InGaN layer, or more generally, two AlGaN layers with different Al contents or two InGaN layers with different In contents, and the electron density in the 2DEG varies with many factors, including the Al content in the AlGaN layer or the In content in the InGaN layer. Other group III nitride heterointerfaces with the same effect can be used.

[0020] The method may also include forming one or more contact layer regions over the LED structure. The contact layer regions, or each contact layer region, may extend over at least one of the LED structures to make electrical contact with at least one of the LED structures. The contact layer regions may be electrically isolated from each other.

[0021] The holes and the LED structures may be arranged in a regular array. The array may be a square array, or it may be a rectangular array or a hexagonal array. The spacing of the array (i.e., the distance between the centers of each pair of closest holes or LEDs) may be from 4 μm to 500 μm. The maximum diameter of the holes and LED structures can be from 1 μm to 500 μm, or from 5 μm to 500 μm.

[0022] The present invention also provides for manufacturing an LED display comprising an LED array according to the present invention.

[0023] The present invention also provides an LED array comprising a semiconductor layer, a dielectric layer extending over the semiconductor layer and having an array of holes therethrough, and LED devices formed in each of the holes.

[0024] The present invention also provides an LED display comprising an LED array according to the present invention.

[0025] FIG1a shows an as-grown template formed in a process according to a first embodiment of the present invention;

[0026] FIG1b shows the template of FIG1a, in which a mask pattern is formed in a mask layer;

[0027] FIG1c shows the template of FIG1a, which has micro-LEDs grown in the apertures of the mask layer;

[0028] FIG1d shows the template of FIG1c, on which electrical contacts are formed;

[0029] FIG2a shows an as-grown template formed in a process according to a second embodiment of the present invention;

[0030] FIG2b shows the template of FIG2a, in which a mask pattern is formed in a mask layer;

[0031] FIG2c shows the template of FIG2a, which has micro-LEDs grown in the apertures of the mask layer;

[0032] FIG2d shows the template of FIG2c, on which electrical contacts are formed;

[0033] FIG3 is a cross-sectional view of the LED structure of the template of FIG2d; Specification 3 / 6 pages 6 CN 121038476 A

[0034] FIG4 is a scanning electron microscope image of an LED array according to an embodiment of the present invention;

[0035] FIG5 shows the electroluminescence spectrum of an LED array according to an embodiment of the present invention; and

[0036] FIG6 shows the variation of the internal quantum efficiency of an embodiment of the present invention as a function of LED diameter. Detailed Description

[0037] Referring to FIG1a, in a first embodiment of the present invention, a semiconductor layer (e.g., a standard n-type GaN (n-GaN) layer 100) is first grown on a substrate 102. The substrate 102 may be a GaN substrate, or may be any heterostructure substrate (such as sapphire, silicon (Si), silicon carbide (SiC), or even glass). The GaN layer 100 may be grown by means of any standard GaN growth method using metal-organic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MBE), or any other suitable growth technique. The thickness of the resulting “grown n-GaN template” may be greater than 10 μm, but typically, the thickness is in the range of 500 nm to 10 μm. Subsequently, a dielectric layer 104, such as silicon dioxide (SiO2) or silicon nitride (SiN), or any other suitable dielectric material, is deposited on the n-GaN layer 100 using PECVD or any other suitable deposition technique. The thickness of the dielectric layer can range from 20 nm to 500 μm.

[0038] Referring to FIG1b, an array of holes 106 is then formed in the dielectric layer 104. The holes 106 are typically on the micrometer scale, hence the term micro-holes. This can be accomplished by means of photolithography and subsequent etching processes (which can be dry etching or wet etching). The use of photolithography is advantageous because it allows holes to be formed precisely in the desired location, shape, and size, and thus LEDs to be formed within the holes.When forming the microvia 106, the entire thickness of the dielectric layer 104 is etched down to the upper surface of the n-GaN layer 100. The diameter of the microvia can be from 1 μm to 500 μm, or from 3 μm to 500 μm, and the spacing (i.e., the distance between the centers of the closest adjacent microvias) can be, for example, from 4 μm to 500 μm. The remaining dielectric layer 104 can be used as a mask to perform further etching only on the n-GaN layer 100 within the microvia region. Depending on the thickness of the n-GaN layer, the etching depth of the n-GaN can range from zero (meaning no GaN etching) to 10 μm. Typically, the optimal etching method or conditions for the n-GaN layer differ from those for the dielectric layer. For example, SF6 etching can be used to etch the dielectric layer 104 but not the n-GaN layer 100. Therefore, it is easy to etch all the way through the dielectric layer 104 and stop at the top surface of the semiconductor layer 100. This is also advantageous for the quality of the LED structure grown in the aperture 106.

[0039] In the illustrated embodiment, the aperture 106 has a round (specifically, circular) cross-section, but other cross-sections (e.g., elliptical or square) may also be used.

[0040] Next, referring to FIG1c, a standard group III nitride LED structure is grown on the exposed area of ​​the GaN layer 100. However, because only discrete areas of the GaN layer 100 are exposed by the micro-apertures 106 in the dielectric layer or mask, the LED structure is formed as an array of discrete LEDs 108 separated by the remainder of the dielectric layer 104 between the micro-apertures 106. The LED structure 108 is grown using MOVPE or MBE technology or any other suitable growth technique. Growth occurs upward from the exposed area of ​​the GaN (or other semiconductor) layer, rather than upward from the sidewalls of the aperture 106. Therefore, a layered LED structure can be built inside each of the holes 106, and each of the layers is substantially flat or planar. The LED structure may include an n-GaN layer 110, an active region 112, and a final p-doped GaN layer 114. The active region 112 may include an InGaN prelayer, an InGaN-based multiple quantum well (MQW), and a thin p-type AlGaN layer as a barrier layer (not shown). An example of the LED structure is described in more detail below with reference to FIG3. As previously mentioned, due to the dielectric mask 104, the LED structure can only be grown within the micro-holes 106, thereby forming a μLED array as shown in FIG1c.

[0041] Importantly, the uppermost layer of the InGaN MQW 112 should not extend above the upper surface of the dielectric layer 104, which could lead to a short-circuit effect after the template is made into the final μLED array.Equally important, each overgrown n-GaN 110 in the micro-aperture region is in direct contact with the n-GaN layer 100 in the unetched portion of the template beneath the dielectric mask 104, such that all individual μLEDs are electrically connected to each other through the n-GaN layer 100 in the unetched portion beneath the dielectric mask 104.

[0042] Referring to FIG1d, once the LED array structure is completed, further device fabrication is performed, which includes forming electrical contacts for the array. For example, an upper contact layer 116 may be formed over the dielectric mask layer 104 and over the upper p-GaN layer of the individual microLED devices 108. Thus, the upper contact layer 116 forms a common p-contact for all LED devices 108. The upper contact layer 116 may be formed of ITO or a Ni / Au alloy. An anode 118 may then be formed on the p-contact layer 116. For example, a portion of the dielectric layer 104 can be etched away, and then a portion of the LED structure on the etched dielectric layer portion can be etched down into the n-GaN, exposing a region 120 of the n-GaN 100, and forming a cathode 122 on the exposed region 120 of the n-GaN.

[0043] If the LED array is to be used for a display, the continuous contact layer 116 can be replaced by a plurality of separate contact layer regions, each of which covers a corresponding set of LED structures 108. Each set may include only one LED structure 108, or each set may include multiple LED structures (e.g., two, three, or four LED structures). The contact layer regions are electrically isolated from each other, for example, by being spaced apart from each other. This allows each set of LED structures to be addressable (i.e., turned on and off independently of other sets). Specifically, each of the contact layer regions can be connected to a corresponding switching device to form a display in which each of the LEDs or each of the LED groups forms a pixel. The precise control over the position, size, and shape of the LED structure provided by photolithography is important for ensuring that the contact layer regions can be correctly aligned with the LED structure so that they can be individually addressed.

[0044] It has been found that, since the overgrowth of the LED structure occurs only within the micro-hole region 106, the growth rate during LED device formation is significantly increased, in some cases approximately four times faster, compared to those grown under the same conditions on a planar template without any patterned features.

[0045] It should be understood that various modifications can be made to the above embodiments. For example, in one variant, the structure is inverted, a p-GaN layer is grown on the substrate and covered by a dielectric layer, and then, the p-GaN layer of the LED device 108 is formed first, followed by the formation of a multi-quantum well layer, and then the formation of an n-GaN layer.Then, an n-contact layer is formed above the dielectric layer to replace the p-contact layer, and the positions of the anode and cathode are reversed.

[0046] In the configurations of Figures 1a to 1d, the overgrown n-GaN 110 within the micro-hole 106 must match the n-GaN of the unetched portion of the n-GaN layer 100 below the dielectric mask 104, such that all individual μLEDs 108 are electrically connected to each other through the n-GaN layer 100. The n-GaN 100, replacing the unetched n-GaN portion below the dielectric mask 104, serves as an electrical connection channel. In another embodiment, a Group III nitride heterostructure with a two-dimensional electron gas (2DEG) at the heterojunction is used as the semiconductor layer instead of the n-GaN layer. In this embodiment, a standard AlGaN / GaN HEMT structure is used. An electron gas (2DEG) with high plate carrier density and high electron mobility, formed at the interface between the AlGaN barrier and the GaN buffer layer of the HEMT structure, serves as an electrical connection channel.

[0047] Referring to Figures 2a to 2d, to fabricate such a device, a standard AlGaN / GaN HEMT structure is first grown on a GaN substrate or any heterostructure substrate such as sapphire, Si, SiC, or even glass using any standard GaN growth method employing MOVPE or MBE technology or any other epitaxial technology. Specifically, in this embodiment, a GaN layer 200 forming the buffer layer is grown on a substrate 202, and then an AlGaN layer 201 forming the barrier layer is grown on the GaN layer 200. This structure is referred to herein as the “grown HEMT template”. Subsequently, a dielectric layer 204, such as SiO2 or SiN, or any other dielectric material, in the range of 2 nm to 500 μm thickness, is deposited on the grown HEMT template using PECVD or any other suitable deposition technique. Subsequently, using photolithography and then an etching process (either dry or wet etching), the dielectric layer 204 is etched down to the surface of the HEMT structure to form a microvia array 206 in the dielectric layer 204. The microvia diameter can range from several μm to 500 μm, and the spacing between the centers of adjacent microvias can range from 10 μm to 500 μm. The remaining area of ​​the dielectric layer 204 can be used as a mask to perform further etching on the grown HEMT within the microvia region. The etching depth of the grown HEMT can range from zero (meaning no etching) to 10 μm, depending on the AlGaN barrier location of the grown HEMT template.However, generally, the etching will extend at least down to the heterogeneous interface between the two layers 200, 201 of the grown HEMT structure to provide good electrical contact between each of the LED structures and the 2DEG.

[0048] Next, a standard group III nitride LED structure is grown on a HEMT template patterned with a dielectric mask featuring micro-holes, using MOVPE or MBE technology or any other epitaxial technique. This may, for example, involve growing an n-GaN layer, an InGaN prelayer, an InGaN-based MQW as the active region, and then growing a thin p-type AlGaN as a barrier layer, and finally growing p-doped GaN. Due to the dielectric mask, the LED structure is grown only within the micro-holes 206, as shown in FIG2c, thereby forming discrete micro-LED devices 208 within the micro-holes.

[0049] As with the embodiments of Figures 1a to 1d, it is important that the upper surface of the InGaN MQW 212 is located below the upper surface of the dielectric layer 204 to avoid short-circuit effects after the final μLED array is fabricated.

[0050] Referring to Figure 3, the LED structure in the LED arrays of Figures 1a to 1d and 2a to 2d can have any suitable structure, but in one example, the LED structure may include an n-GaN layer 310, an InGaN pre-layer 316 formed above the n-GaN layer 310, a plurality of InGaN quantum well layers 312 formed above the pre-layer 316, a p-doped barrier layer 318 of, for example, p-AlGaN, and then a p-GaN layer 314. It will be understood that the structure can vary in many ways. As mentioned above, it is preferred that the top of the uppermost layer in the quantum well layers 312 is below the top of the dielectric layer. It is also preferred that the top of the barrier layer 318 is also below the top of the dielectric layer.

[0051] Another important point is that the overgrown n-GaN in the micropore region directly contacts the interface between the GaN buffer layer of the initially grown HEMT structure and the unetched portion below the AlGaN barrier and the dielectric mask 204, such that all individual μLEDs are electrically connected via 2DEG at the interface formed between the GaN buffer layer of the HEMT structure (i.e., the unetched portion) below the AlGaN barrier and the dielectric mask. Once the LED structure is complete, any suitable standard device fabrication can be performed, as shown in the embodiments of Figures 1a to 1d, and each device will include multiple individual μLED components as shown in Figure 2d, wherein all individual μLEDs 208 separated by the remaining dielectric mask 204 to eliminate short circuits in each device share a common p-contact layer 216.

[0052] It should be noted that in the embodiments of Figures 2a to 2d, selective etching of the dielectric mask 204 may be necessary prior to any standard LED manufacturing steps to expose a portion of the surface of the HEMT structure, wherein, as shown in Figure 2d, cathode contacts 222 will be fabricated on the exposed surface of the HEMT. Selective etching can be dry etching or wet etching.

[0053] As an example, Figure 4 shows a typical scanning microscope image of a μLED array epitaxial wafer fabricated as described above, wherein each μLED has a diameter of 40 μm.

[0054] As an example, Figure 5 shows the electroluminescence spectrum of a 40 μm diameter μLED, varying with the injection current.

[0055] Figure 6 shows the internal quantum efficiency (IQE) of the μLED formed as described above, measured as a function of the μLED diameter. This shows that the IQE of the LED increases as the μLED diameter decreases. The result differs from the results of all previous μLEDs fabricated using conventional methods. This indicates that the above method avoids sidewall damage caused by dry etching, which is typically produced during conventional manufacturing processes.Instruction Manual 6 / 6 Page 9 CN 121038476 A Figure 1a Figure 1b Instruction Manual Figure 1 / 8 Page 10 CN 121038476 A Instruction Manual Figure 2 / 8 Page 11 CN 121038476 A Figure 2a Instruction Manual Figure 3 / 8 Page 12 CN 121038476 A Figure 2b Instruction Manual Figure 4 / 8 Page 13 CN 121038476 A Figure 2c Instruction Manual Figure 5 / 8 Page 14 CN 121038476 A Figure 2d Figure 3 Instruction Manual Figure 6 / 8 Page 15 CN 121038476 A Figure 4 Figure 5 Instruction Manual Figure 7 / 8 Page 16 CN 121038476 A Figure 6 Instruction Manual Figure 8 / 8 Page 17 CN 121038476 A Abstract An LED array and a method for manufacturing the LED array, the method comprising the steps of: forming a semiconductor layer (100) from a Group III nitride material; forming a dielectric mask layer (104) over the semiconductor layer, the dielectric mask layer having an array of apertures extending through the dielectric mask layer, each aperture exposing a region of the semiconductor layer; and growing an LED structure (108) in each aperture..

Claims

1. An LED array, comprising: The semiconductor layer includes a first sublayer and a second sublayer; A dielectric layer extends above the semiconductor layer and has an array of holes through the dielectric layer, each hole exposing a corresponding region of the first sublayer; as well as LED devices are formed on each exposed area; Each of the LED devices includes a first layer having p-type or n-type conductivity, at least one active layer formed above the first layer, and a second layer formed above the active layer, the second layer having n-type or p-type conductivity opposite to that of the first layer. The conductivity type of the first sublayer of the exposed semiconductor layer is the same as the conductivity type of the first layer in the LED device that is in contact with the first sublayer of the exposed semiconductor layer. The first sublayer of the exposed semiconductor layer contains the same Group III nitride material as the first layer of the LED device; and Wherein, the upper surface of the second sub-layer of the semiconductor layer is not higher than the upper surface of the first layer of the LED device.

2. The LED array according to claim 1, wherein, The upper surface of the at least one active layer is below the upper surface of the dielectric layer.

3. The LED array according to claim 1, wherein, The semiconductor layer provides a common contact to all of the LED devices.

4. The LED array according to claim 1, wherein, The semiconductor layer is doped.

5. The LED array according to any one of claims 1 to 4, wherein, The heterogeneous interface between the first sublayer and the second sublayer is arranged to form a two-dimensional charge carrier gas.

6. The LED array according to any one of claims 1 to 4, wherein, The LED device is a micro LED device, and the array is a regular array with a spacing of 4μm to 500μm.

7. The LED array according to any one of claims 1 to 4, further comprising: Multiple contact layer regions are formed above the LED devices, wherein each contact layer region is in electrical contact with a corresponding set of the LED devices.

8. A method for manufacturing a light-emitting diode (LED) array, the method comprising: Forming a semiconductor layer comprising a first sublayer and a second sublayer; A dielectric layer is formed above the semiconductor layer, the dielectric layer having an array of holes through the dielectric layer, each hole exposing a region of a first sublayer of the semiconductor layer; as well as This allows LED devices to be grown in each exposed area. Each of the LED devices includes a first layer having p-type or n-type conductivity, at least one active layer formed above the first layer, and a second layer formed above the active layer, the second layer having n-type or p-type conductivity opposite to that of the first layer. The conductivity type of the first sublayer of the exposed semiconductor layer is the same as the conductivity type of the first layer in the LED device that is in contact with the first sublayer of the exposed semiconductor layer. The first sublayer of the exposed semiconductor layer contains the same Group III nitride material as the first layer of the LED device; and Wherein, the upper surface of the second sub-layer of the semiconductor layer is not higher than the upper surface of the first layer of the LED device.

9. A method according to claim 8, wherein, The step of forming the dielectric layer includes: growing a layer of dielectric material and etching the array of holes into the layer of dielectric material.

10. A method according to claim 8 or 9, further comprising: Before growing the LED device in each of the holes, each region of the exposed area of ​​the first sublayer of the semiconductor layer is etched.

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