Chiplet arrangement

Abstract

A chiplet arrangement (100) is presented. The chiplet arrangement (100) is controllable by an external communication interface (150). The chiplet arrangement (100) comprises at least one chiplet (110a, 110b, 110c) connected to a chiplet network (120), where the at least one chiplet (110a, 110b, 110c) comprises at least one hardware resource (112a... 112e). The chiplet arrangement (100) is provided with a chiplet control plane (300), the chiplet control plane (300) being configured to orchestrate one or more microsystems (210, 220, 230). Each microsystem (210, 220, 230) includes at least one hardware resource (112a... 112e) and an addressable connection at the chiplet network (120). The control plane (300) is further configured to expose the one or more microsystems (210, 220, 230) as microservices (410... 440) at the external communication interface (150).

Description

(19) State Intellectual Property Office (12) Invention Patent Application (10) Application Publication Number (43) Application Publication Date (21) Application Number 202480026912.8 (22) Application Date 2024.04.14 (30) Priority Data 23168999.3 2023.04.20 EP (85) PCT International Application Entering National Phase Date 2025.10.20 (86) PCT International Application Application Data PCT / EP2024 / 060105 2024.04.14 (87) PCT International Application Publication Data WO2024 / 218022 EN 2024.10.24 (71) Applicant LTU Licensing Ltd. Address Sweden (72) Inventors Jack Delsin Christina Paniaguashailes Singchohan (74) Patent Agency China Patent & Trademark Agency Co., Ltd. 11021 Patent Attorneys Luo Songmei and Feng Wei (51) Int.Cl. G06F 15 / 78 (2006.01) (54) Title of Invention Chipset Arrangement (57) Abstract A chipset arrangement (100) is proposed. The chipset arrangement (100) is controllable by an external communication interface (150). The chipset arrangement (100) includes at least one chip (110a, 110b, 110c) connected to a chipset network (120), wherein the at least one chip (110a, 110b, 110c) includes at least one hardware resource (112a...112e). The chipset arrangement (100) provides a chipset control plane (300) configured to orchestrate one or more microsystems (210, 220, 230). Each microsystem (210, 220, 230) includes at least one hardware resource (112a ... 112e) and an addressable connection at a chiplet network (120). The control plane (300) is also configured to expose one or more microsystems (210, 220, 230) as microservices (410 ... 440) at an external communication interface (150).Claims 2 pages, Description 15 pages, Drawings 5 ​​pages, CN 121039653 A 2025.11.28 CN 1 21 03 96 53 A 1. A chiplet arrangement (100) controllable via an external communication interface (150), wherein the chiplet arrangement (100) includes at least one chiplet (110) connected to a chiplet network (120), and wherein the at least one chiplet (110) includes at least one hardware resource (112); and wherein the chiplet arrangement (100) has a chiplet control plane (300) configured to: - orchestrate one or more microsystems (200), each microsystem (200) including at least one hardware resource (112) and addressable connections at the chiplet network (120), and - expose one or more microsystems (200) as microservices (400) at the external communication interface (150). 2. The chiplet arrangement (100) of claim 1, comprising two or more chipsets (110) connected via the chiplet network (120). 3. The chiplet arrangement (100) of claim 1 or 2, wherein the chiplet control plane (300) is configured to configure the instantiation of a microsystem (200) based on the availability and / or utilization of hardware resources (112). 4. The chiplet arrangement (100) of any preceding claim, wherein the chiplet control plane (300) is configured to configure the instantiation of a microservice (400) based on the availability and / or utilization of hardware resources (112). 5. The chiplet arrangement (100) of any preceding claim, wherein the chiplet control plane (300) comprises: - a resource orchestrator (410) configurable to instantiate the microsystem (200) of the chiplet arrangement (100). 6. The chiplet arrangement (100) of claim 5, wherein the resource orchestrator (410) includes pre-configured microsystems (200) of the chiplet arrangement (100), the pre-configured microsystems (200) being associated with one or more pre-configured microservices (400) of the chiplet arrangement (100). 7. The chiplet arrangement (100) of claim 5 or 6, wherein the resource orchestrator (410) is further configured to instantiate microservices (400) associated with a particular microsystem (200). 8. The chiplet arrangement (100) of any of the preceding claims, wherein at least one microsystem (200) is configured to consume or generate one or more microservices (400) associated with the at least one microsystem (200).9. The chiplet arrangement (100) according to any one of the preceding claims, wherein the chiplet control plane (300) comprises: - a network manager (440) configured to control communication between the microsystem (200) and the external communication interface (150) of the chiplet arrangement (100). 10. The chiplet arrangement (100) according to claim 9, wherein the network manager (440) is a pre-configured microsystem (200) of the chiplet arrangement (100), the pre-configured microsystem (200) being associated with one or more pre-configured microservices (400) of the chiplet arrangement (100). 11. The chiplet arrangement (100) according to any one of the preceding claims, wherein the control plane (300) includes a resource registry (430) including data indicating at least some hardware resources (112) of the hardware resources (112) of the chiplet arrangement (100), preferably, the resource registry (430) including data indicating all hardware resources (112) of all chips (110) of the chiplet arrangement (100). 12. The chiplet arrangement (100) according to any one of the preceding claims, wherein the control plane (300) includes a resource scheduler (420) configured to schedule the utilization of the hardware resources (112). 13. The chiplet arrangement (100) according to claim 12, wherein the resource scheduler (420) is a pre-configured microsystem (200) of the chiplet arrangement (100), the pre-configured microsystem (200) being associated with one or more pre-configured microservices (400) of the chiplet arrangement (100). Claims 1 / 2 Page 2 CN 121039653 A 14. The chiplet arrangement (100) according to any of the preceding claims, wherein the at least one hardware resource (112) is a network interface configured to connect the chiplet (110) to the chiplet network (120).15. The chiplet arrangement (100) according to any one of the preceding claims, wherein at least one hardware resource (112) is a computing hardware resource such as a CPU, GPU, or microcontroller, and / or wherein at least one hardware resource (112) is a memory hardware resource such as volatile memory or non-volatile memory, and / or wherein at least one hardware resource (112) is a sensor hardware resource (112) such as a temperature sensor, pressure sensor, light sensor, optical sensor, or fingerprint sensor, and / or wherein at least one hardware resource (112) is a peripheral hardware resource (112) such as an interrupt controller, DMA controller, digital I / O, DAC, ADC, or clock, and / or wherein at least one hardware resource (112) is a communication hardware resource (112) such as an I2C interface, PCIe interface, or UCIe interface, and / or wherein at least one hardware resource (112) is an actuator hardware resource (112) such as a speaker, buzzer, light source, or display. 16. A chiplet arrangement (100) according to any one of the preceding claims, wherein each hardware resource (112) provides at least one dedicated hardware function. 17. A chiplet arrangement (100) according to any one of the preceding claims, wherein the chiplet arrangement (100) is a chiplet package forming part of an integrated circuit IC. 18. A method (500) for configuring a chiplet arrangement (100) according to any one of the preceding claims, the method (500) being performed by the control plane (300) of the chiplet arrangement (100) and comprising: obtaining (510) a request to instruct a microsystem (200) to be instantiated; and instantiating (520) the microsystem (200) according to the obtained request. 19. The method (500) of claim 18, wherein the request includes a resource scheme (105) indicating one or more hardware requirements of the microsystem (200) to be instantiated, and the instantiation (520) further includes: selecting (522) a hardware resource (112) that satisfies the indicated hardware requirements; and obtaining (524) allocated scheduling data associated with the selected hardware resource (112). 20. The method (500) of claim 19, wherein at least one of the hardware resources (112) is selected as a computing hardware resource, the request further includes program instructions that, when executed by the selected computing hardware resource, instantiate the microsystem (200) indicated by the request, and the instantiation (510) further includes: deploying (526) the microsystem by executing the program instructions through the selected computing hardware resource.21. The method (500) according to any one of claims 18 to 20, wherein the instantiation (520) of the microsystem (200) is based on the availability and / or utilization of the hardware resources (112). Claims 2 / 2 Page 3 CN 121039653 A Chipset Arrangement Technical Field

[0001] This disclosure relates to chiplets. More specifically, this disclosure relates to a microservice architecture of chipset arrangement. Embodiments of the invention include, for example, chipset arrangement and methods for configuring such chipset arrangement. Background Art

[0002] According to Moore's Law, the number of transistors in an integrated circuit (IC) doubles every two years. However, due to high costs, the pace of improvement in silicon manufacturing is slowing down, and the commercial production of increasingly smaller chips is becoming increasingly challenging. The current development of monolithic chips faces not only economic constraints but also supply and demand, flexibility, and competitiveness constraints. Typically, from the early design stages, the conception of the chip does not take into account the possibility of future changes or developments. This hinders the reuse of hardware.

[0003] In response to this situation, chiplets have emerged as a promising solution. Typically, a chiplet is a modular semiconductor component configured to perform specific functions or subsets of functions of a larger integrated circuit. Chipslets can be combined with other chiplets to form more complex integrated circuits, thus providing greater flexibility in design and manufacturing.

[0004] The concept of chiplets has existed for decades, with the first examples appearing in the 1980s. At that time, chiplets were primarily used for memory and I / O functions and were mounted on separate packages connected to the main processor via a bus interface. In recent years, chiplets have regained interest due to advancements in semiconductor manufacturing technology and the increasing complexity of modern electronic devices. By breaking down complex systems or systems-on-a-chip (SoCs) into smaller, more manageable components, chiplets offer several advantages.

[0005] To facilitate the use of chiplets, industry organizations and standards bodies have developed interfaces and protocols for interconnection and communication between chiplets. Examples include the Semiconductor Industry Association's (SIA) Chiplet Integration Interface (CII) and the Open Compute Project's (OCP) Advanced Interface Bus (AIB). Chiplets are a promising approach for designing and manufacturing complex semiconductor devices, offering greater flexibility, efficiency, yield, scalability, optimized performance, and reliability.

[0006] The flexibility in designing and manufacturing chiplets facilitates the provision of hardware that can be configured to perform a wide range of different tasks. However, chiplets are a lock-in solution, such as creating a PCB that serves a specific task or function. Despite progress in standardization efforts, the full potential of chiplets has not yet been fully realized. Summary of the Invention

[0007] Various embodiments of this disclosure have been made in view of the foregoing considerations and other factors.Therefore, this disclosure recognizes the need for alternatives (e.g., improvements) to the aforementioned prior art.

[0008] Some embodiments aim to address, mitigate, alleviate, or eliminate at least some of the aforementioned defects or other disadvantages. To this end, a novel chiplet arrangement is proposed. More specifically, the object of the invention is to provide a configurable chiplet arrangement that can be utilized more efficiently than the prior art. These objects are achieved by the techniques set forth in the appended independent claims and the preferred embodiments defined in the related dependent claims.

[0009] In a first aspect, a chiplet arrangement is proposed. The chiplet arrangement can be controlled by an external communication interface. The chiplet arrangement includes at least one chiplet connected to a chiplet network. The at least one chiplet includes at least one hardware resource. The chiplet arrangement provides a chiplet control plane configured to orchestrate one or more microsystems. Each microsystem includes at least one hardware resource and an addressable connection at the chiplet network. The chiplet control plane is also configured to expose one or more microsystems as microservices at an external communication interface.

[0010] In some variations, the chiplet arrangement includes two or more chipsets connected via a chiplet network. This is advantageous because additional chipsets enable greater flexibility in providing microsystems and microservices.

[0011] In some variations, the chiplet control plane is configured to configure the instantiation of microsystems based on the availability and / or utilization of hardware resources. This is advantageous because it allows for optimized resource utilization (i.e., resource efficiency), thereby saving power.

[0012] In some variations, the chiplet control plane is configured to configure the instantiation of microservices based on the availability and / or utilization of hardware resources. This is advantageous because it allows for optimized resource utilization, thereby reducing power consumption.

[0013] In some variations, the chiplet control plane includes a resource orchestrator configurable to instantiate the microsystems of the chiplet arrangement. The resource orchestrator provides benefits such as optimized, increased, or improved resource utilization, automated management, improved scalability, flexible deployment, and high availability and resilience (to long-term, changing, and / or disruptive resource demands).

[0014] In some variations, the resource orchestrator includes pre-configured microsystems of chiplet arrangement associated with one or more pre-configured microservices of chiplet arrangement.

[0015] In some variations, the resource orchestrator may also be configured to instantiate microservices associated with a particular microsystem.

[0016] In some variations, each instantiated microsystem is configured to consume or generate one or more microservices associated with that microsystem.

[0017] In some variations, at least one microsystem is configured to consume or generate one or more microservices associated with the at least one microsystem.

[0018] In some variations, the chiplet control plane includes a network manager configured to control communication between the microsystem and the external communication interface of the chiplet arrangement. This is advantageous because the network administrator can provide centralized control, improved network security, enhanced network performance and reliability, and simplified network management.

[0019] In some variations, the network manager is a pre-configured microsystem of the chiplet arrangement associated with one or more pre-configured microservices of the chiplet arrangement.

[0020] In some variations, the control plane includes a resource registry that includes data indicating at least some of the hardware resources of the chiplet arrangement. The resource registry is advantageous because it provides centralized visibility and management of resources, simplified resource discovery and allocation, and improved resource utilization and efficiency.

[0021] In some variations, the resource registry includes data indicating all hardware resources of all chips in the chiplet arrangement.

[0022] In some variations, the control plane includes a resource scheduler configured to schedule resource utilization. The resource scheduler is advantageous because it provides optimized resource allocation, improved resource utilization and performance, and automated management of resource allocation and scheduling.

[0023] In some variations, the resource scheduler is a pre-configured microsystem of a chiplet layout associated with one or more pre-configured microservices of the chiplet layout.

[0024] In some variations, at least one hardware resource is a network interface configured to connect the chiplet to a chiplet network.

[0025] In some variations, at least one hardware resource is a computing hardware resource such as a CPU, GPU, or microcontroller. Specification 2 / 15 pages 5 CN 121039653 A

[0026] In some variations, at least one hardware resource is a memory hardware resource such as a data storage unit, volatile memory, or non-volatile memory.

[0027] In some variations, at least one hardware resource is a sensor hardware resource such as a data acquisition unit, a temperature sensor, a pressure sensor, a light sensor, an optical sensor, or a fingerprint sensor.

[0028] In some variations, at least one hardware resource is a peripheral hardware resource such as an interrupt controller, a DMA controller, a digital I / O, a DAC, an ADC, or a clock.

[0029] In some variations, at least one hardware resource is a communication hardware resource such as an I2C interface, a PCIe interface, or a UCIe interface.

[0030] In some variations, at least one hardware resource is an actuator hardware resource such as a speaker, buzzer, light source, or display.

[0031] In some variations, each hardware resource provides at least one dedicated hardware function.

[0032] In some variations, the chiplet arrangement is a chiplet package forming part of an integrated circuit (IC).

[0033] In a second aspect, a method for configuring a chiplet arrangement according to the first aspect is proposed. The method is performed by a control plane of the chiplet arrangement. The method includes: obtaining a request instructing a microsystem to be instantiated, and instantiating the microsystem according to the obtained request.

[0034] In some variations, the request includes a resource scheme instructing one or more hardware requirements of the microsystem to be instantiated.

[0035] In some variations, instantiation further includes: selecting a hardware resource that satisfies the indicated hardware requirements, and obtaining allocated scheduling data associated with the selected hardware resource.

[0036] In some variations, at least one hardware resource is selected as the computing hardware resource, and the request further includes program instructions that, when executed by the selected computing hardware resource, will instantiate the microsystem indicated by the request.

[0037] In some variations, instantiation further includes deploying the microsystem by executing the program instructions through the selected computing hardware resource.

[0038] In some variations, the instantiation of the microsystem is based on the availability and / or utilization of the hardware resources. Brief Description of the Drawings

[0039] Embodiments of the invention will now be described; reference is made to the accompanying schematic diagrams, which illustrate non-limiting examples of how the inventive concept can be put into practice.

[0040] FIG1 is a schematic diagram of a chiplet arrangement according to some examples of the present disclosure;

[0041] FIG2 is a schematic diagram of a chiplet according to some embodiments of the present disclosure;

[0042] FIG3 is a schematic diagram of a microsystem associated with microservices according to some embodiments of the present disclosure;

[0043] FIG4 is a schematic diagram of a chiplet arrangement according to some examples of the present disclosure;

[0044] FIG5 is a schematic diagram of a control plane according to some embodiments of the present disclosure;

[0045] FIG6 is a SysML sequence diagram of dynamic instantiation of a microsystem according to some embodiments of the present disclosure;

[0046] FIG7 is a SysML model of a resource security microsystem within a chiplet arrangement according to some examples of the present disclosure; and

[0047] FIG8 is a schematic diagram of a method for configuring a chiplet arrangement according to some examples of the present disclosure. Specification 3 / 15 pages 6 CN 121039653 A Detailed Description

[0048] Hereinafter, certain embodiments will be described more fully with reference to the accompanying drawings.However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided by way of example so that this disclosure will be thorough and complete and will fully convey to those skilled in the art the scope of the invention (e.g., as defined in the appended claims).

[0049] Similarly, the term “connected” or “operably connected” is defined as a connection, although not necessarily a direct connection and not necessarily a mechanical connection. Two or more “coupled” or “connected” items may be integral with each other. Unless expressly required otherwise by this disclosure, the terms “a” and “an” are defined as one or more. The terms “substantially,” “generally,” and “about” are defined as substantially but not necessarily fully specified, as understood by those skilled in the art. The terms “comprising” (and any form thereof), “having” (and any form thereof), “including” (and any form thereof), and “containing” (and any form thereof) are open-ended conjunctions. Thus, a method that “comprising,” “having,” “including,” or “containing” one or more steps has, but is not limited to, having only, those steps.

[0050] For the purposes of this disclosure, a chiplet is typically a micro-integrated circuit (IC) that includes a well-defined subset of functions. It is designed to be combined with other chiplets to form a chiplet arrangement. A chiplet arrangement may (but is not required to) be situated on a common interposer layer within a single package.

[0051] For example, compared to large-scale integrated circuits (ICs), chiplet arrangements offer several advantages. Because chiplet arrangements separate different functions into discrete chips, they make it easier to isolate and fix defects during manufacturing. This can result in higher overall yields and lower costs. By mixing and matching different chiplets, designers are able to create custom chiplet arrangements in the form of a system-on-a-chip (SoC) optimized for specific applications. This can lead to more efficient, higher-performance devices. By using smaller, more manageable chiplet components, designers are able to iterate more quickly and test individual components more thoroughly before integrating them into a larger system of chiplet arrangements 100. Designers are also able to dynamically add or remove components from the SoC if needed. This allows design engineers to easily scale the performance and complexity of the entire system. Chiplets enable companies to leverage economies of scale and reuse existing chip designs, which reduces the cost of new development. Chiplets support a wide range of applications, from high-powered devices (servers in data centers) to battery-powered devices (smartwatches). The philosophy behind chiplets allows for interoperability between different chiplet vendors. This can result in improved performance compared to a single monolithic chip solution.

[0052] From a hardware perspective, the configurability of chiplets has historically been separate from the corresponding software configurability.The software functionality of a chiplet is typically limited to the functionality provided by each chiplet in a different chiplet. Each chiplet is addressed using a Hardware Abstraction Layer (HAL) that is typically specific to each chiplet. To allow for full flexibility of the chiplets and also improve the resource utilization of the SoC, the inventors of this disclosure have realized that multiple microservices can be used to share and utilize chiplets or collections of chiplets.

[0053] Generally, microservices are a software architecture approach in which large applications are broken down into small, independent, and loosely coupled services that can be developed, deployed, and maintained independently. Each microservice typically performs a specific function (e.g., a business function, etc.) and communicates with other microservices via lightweight mechanisms such as HTTP or messaging protocols. This approach allows for faster and more efficient development, deployment, and scaling of applications and improves resilience and fault tolerance. Microservices also enable teams to work independently on different parts of the application, with each team responsible for developing and maintaining its own microservice. This approach can improve overall development speed and reduce the risk of conflict or dependency between teams. Overall, microservices can provide greater flexibility, scalability, and reliability in large and complex information systems / computer systems.

[0054] Historically, microservices have been designed to be deployed as independent, lightweight components capable of running on distributed systems on commercial hardware. This allows for greater scalability and fault tolerance compared to running monolithic applications on a single server. A common hardware configuration for microservices is cloud-based infrastructure. A common choice is to deploy microservices in the cloud using services such as Amazon Web Services (AWS), Microsoft Azure, or Google Cloud Platform (GCP). These cloud providers offer a variety of services and tools for running and managing microservices, including container orchestration platforms such as Kubernetes. Alternatively, microservices can also run on virtual machines (VMs) using hypervisors such as VMware or Hyper-V. This allows for greater flexibility in deploying and scaling microservices across different hardware configurations. In some cases, microservices can be deployed on edge devices such as Internet of Things (IoT) devices or embedded systems. This requires a lightweight runtime environment capable of running on resource-constrained hardware.

[0055] It is generally believed that microservices evolved from service-oriented architecture (SOA) and are often regarded as a subset of SOA. Microservices and SOA share many attributes and non-functional requirements that are provided by the architecture and are key to its operation. For example, a system can discover services at runtime without fixing their addresses at design time.This is typically achieved through some type of service registry, in which service producers advertise their services, enabling consumers to find them even in dynamic environments. Typically, services communicate only through designed APIs, thus employing the concept of information hiding and encapsulation. In this way, services do not share dependencies with each other and can be modified internally as needed without affecting the behavior of other services. Furthermore, service exchange typically occurs at runtime and can change based on the current state. Therefore, services do not need to be aggregated before deployment as in earlier bindings, thus enabling application self-healing and optimization within the execution environment. These capabilities require more logic that can be added to each system or delegated to intermediaries that will organize the network.

[0056] Figure 1 shows a simplified diagram of a chiplet arrangement 100. The chiplet arrangement 100 includes multiple chipsets 110a, 110b, 110c, 110d, and 110e. The chiplet arrangement 100 in Figure 1 is disclosed to include multiple chips 110a, 110b, 110c, 110d, and 110e, i.e., two or more chips. However, those skilled in the art will understand that the chiplet arrangement 100 may sometimes include a single chiplet 110a, 110b, 110c, 110d, and 110e. Chips 110a, 110b, 110c, 110d, and 110e are connected via a chiplet network 120, thereby enabling communication between chips 110a, 110b, 110c, 110d, and 110e. The chiplet arrangement 100 can be controlled by an external interface 150, thereby enabling the chiplet arrangement 100 to control, be controlled by, or otherwise interact with one or more external systems 10. Chipsets 110a, 110b, 110c, 110d, and 110e of chipset arrangement 100 may all be arranged on a common interposer layer 130 and optionally form a chip package 140. In other examples of this disclosure, chipset arrangement 100 may include multiple chips 110a, 110b, 110c, 110d, and 110e arranged on different interposer layers 130 and / or forming different chipset packages 140. Regardless of the arrangement or number of chips 110a, 110b, 110c, 110d, and 110e, chips 110a, 110b, 110c, 110d, and 110e are connected via chipset network 120. Chipset arrangement 100 according to this disclosure may be referred to as one or more of a multi-chip module (MCM), hybrid IC, 2.5D IC, or advanced package.

[0057] The chiplet network 120 can be any suitable network or corresponding connection capable of enabling communication between chipsets 110a, 110b, 110c, 110d, 110e and / or between chipsets 110a, 110b, 110c, 110d, 110e and external interface 150. In some examples, the chiplet network 120 can be a network configured according to one or more network standards such as UCIe, Bundle Wire (BoW), OpenHBI, or OIF XSR. The chiplet network 120 is not necessarily formed by a single physical or virtual network, but can be a combination of one or more physical networks and / or one or more virtual networks. This will be further explained in later sections.

[0058] In Figure 1, a chiplet arrangement 100 comprising five chipsets 110a, 110b, 110c, 110d, 110e is shown. This is for illustrative purposes only, and those skilled in the art will understand that chiplet arrangement 100 may include any number of chips 110a, 110b, 110c, 110d, 110e. In fact, as will be apparent from the above and upon reading the full disclosure, the teachings presented herein also apply to individual chips 110a, 110b, 110c, 110d, 110e.

[0059] Those skilled in the art will understand that the chips 110a, 110b, 110c, 110d, 110e, chiplet arrangement 100, and other features presented herein may be presented in a simplified and / or abbreviated form to make this disclosure as efficient as possible. For example, the chiplet arrangement 100 of FIG1 typically requires some form of power distribution to provide power to and / or control power to chips 110a, 110b, 110c, 110d, 110e. These features and configurations are known to those skilled in the art and do not require further explanation.

[0060] In FIG2, an exemplary simplified block diagram of chiplet 110 is shown. Chiplet 110 includes at least one hardware resource 112a, 112b, 112c. Chiplet 110 of FIG2 is shown as having three hardware resources 112a, 112b, 112c, but any number of hardware resources is applicable. At least one of the hardware resources 112a, 112b, 112c of chiplet 110 is addressable at chiplet network 120. Therefore, the first hardware resource 112a can be a network interface hardware resource configured to connect the chiplet 110 to the chiplet network 120 and communicate via the chiplet network 120. The second hardware resource 112b can be a computing hardware resource such as a CPU, GPU, or microcontroller.The third hardware resource 112c can be a data storage unit, i.e., a memory hardware resource such as volatile or non-volatile memory. Chip 110, including network interface hardware resources, computing hardware resources, and memory hardware resources, can be considered the smallest chip 110. However, not all hardware resources 112a, 112b, and 112c are addressable through chip network 120, and from the perspective of chip arrangement 100, a particular chip 110 may only include computing hardware resources as the sole addressable resource for that particular chip 110.

[0061] Chip 110 may include additional hardware resources 112a, 112b, and 112c, such as, but not limited to, sensor hardware resources. Sensor hardware resources (i.e., data acquisition units) can be exemplified as temperature sensors, pressure sensors, light sensors, optical sensors, voltage sensors, fingerprint sensors, etc. Additionally or alternatively, chip 110 may include hardware resources 112a, 112b, and 112c in the form of peripheral hardware resources. Peripheral hardware resources may include, but are not limited to, interrupt controllers, DMA controllers, digital / analog I / O, DACs, ADCs, clocks, peripheral I / O devices, peripheral storage devices, peripheral display devices, peripheral communication devices, etc. Additionally or alternatively, chip 110 may include hardware resources 112a, 112b, 112c in the form of communication hardware resources. Communication hardware resources may include, but are not limited to, PCIe interfaces or UCIe interfaces. Additionally or alternatively, chip 110 may include hardware resources 112a, 112b, 112c in the form of actuator hardware resources. Actuator hardware resources may include, but are not limited to, speakers, buzzers, switches, light sources, displays, etc.

[0062] The inventors of this disclosure have realized that chip 110 can not only deploy and execute microservices, but chip 110 itself can be managed and controlled in correspondence with microservices. That is, the hardware resources 112 of one or more chips 110 can be configured to form a microsystem 200, see FIG3.

[0063] Figure 3 illustrates a microsystem 200 according to the present disclosure. Microsystem 200 provides behavior based on stored or acquired data and its computations. The resulting capabilities are exposed externally through one or more generated microservices 400. Microsystem 200 comprises one or more hardware resources 112 (e.g., including or configured with one or more hardware resources 112), which perform one or more tasks and processes to form a function. A particular microsystem 200 may be associated with one or more hardware resources 112 from a particular chiplet 110 in chiplet arrangement 100, or with hardware resources 112 from two or more chipslet 110s in chiplet arrangement 100.As will be taught in later sections, microsystem 200 can be dynamically instantiated and subsequently reused at runtime. This enables flexible use and reuse of the occupied hardware resources 112. Microsystem 200 may include configurable or static software (program instructions) stored and executable by the hardware resources of microsystem 200. It should be mentioned that microsystem 200 is defined solely by hardware resources 112 and does not require a software specification (6 / 15 pages, 9 CN 121039653 A) to provide the desired functionality.

[0064] The orchestration of microsystem 200 is provided by control plane 300. The orchestration of one or more microsystems 200 by control plane 300 may include, but is not limited to, managing microsystem 200, orchestrating the deployment of microsystem 200, scaling microsystem 200, and / or controlling the operation of microsystem 200. Control plane 300 is also advantageously configured to orchestrate microservices 400 exposed at external communication interface 150. The orchestration of one or more microservices 400 by the control plane 300 may include, but is not limited to, managing microservices 400, orchestrating the deployment of microservices 400, extending microservices 400, and / or controlling the operation of microservices 400. The control plane 300 is also advantageously configured to orchestrate bindings (associations) between a particular microsystem 200 and one or more microservices 400.

[0065] Advantageously, microservices 400 are registered at an external resource registry associated with the external system 10. Registration of microservices 400 at the external resource registry of the external system 10 may be provided by the control plane 300. One or more microsystems 200 may provide software instructions that enable one or more microsystems 200 to register their associated microservices 400 at the external resource registry of the external system 10 (via the control plane 300).

[0066] The control plane 300 may be configured as a centralized control plane and will generally be described as such. However, it should be emphasized that this disclosure also applies to, but is not limited to, decentralized or distributed implementations of the control plane 300.

[0067] To illustrate the functionality of the control plane, control plane 300 can be configured to discover and manage available hardware resources 112 and microsystems 200. This means monitoring resource usage and availability, and allocating and releasing resources as needed. Control plane 300 can be additionally or alternatively configured to deploy and manage microservices 400 on available hardware resources 112 through its associated microsystems 200. This means ensuring that each microservice 400 is deployed in the appropriate location and can communicate with other microservices 400 as needed. Control plane 300 can be additionally or alternatively configured to provide service scaling. That is, as the demand for a particular microservice 400 increases or decreases, control plane 300 can be configured to scale up or down the microservice 400 accordingly. This can involve adding or removing instances of microservice 400, and / or adjusting the microsystems allocated to each instance of microservice 400.Control plane 300 may be additionally or alternatively configured to provide health monitoring of chiplet arrangement 100. This may include monitoring the health status of each microservice 400 and / or microsystem 200, and detecting and advantageously responding to failures or other problems. This may involve performing automated health checks, restarting failed microsystems 200 and / or microservices 400, and / or triggering alert notifications when problems occur. Control plane 300 may additionally or alternatively be configured to manage updates to microservices 200 and / or microsystems 400 to ensure that new versions of services are deployed and rolled out in a controlled and secure manner.

[0068] Control plane 300 may be created from a set of microsystems 200 with associated microservices 400 by using an SOA approach. This is schematically illustrated in Figure 4. It may be assumed that control plane 300 is locally instantiated and executed at each chiplet arrangement 100.

[0069] Referring to FIG4, an exemplary embodiment of a chiplet arrangement 100 including an advantageous control plane 300 will be presented. In FIG4, the control plane 300 includes a resource orchestrator 410. The resource orchestrator 410 can be configured to orchestrate and coordinate the integration and instantiation of the microsystem 400 and the microservices 200 it generates and consumes. Microsystem integration can be requested by the resource orchestrator 410 of the associated microservice 410 exposed at an external communication interface 150. Such integration requests can indicate which hardware resources 112 of the chiplet arrangement 100 to be integrated, and, if applicable, provide any suitable microsystem executable code. Additionally, lifecycle data ranging from the completion of the first service request to the maximum lifecycle can also be provided. The maximum lifecycle can be determined by the edge or cloud ServiceRegistry and SystemRegistry that the microsystem may have to register with. If needed, advanced security deployment schemes can be deployed, which will be further described in later sections. It should be noted that the microsystem 200 of the chiplet arrangement 100 is not necessarily static. In other words, the microsystem 200 can be configured as a static structure, dynamic structure, fluid structure, flexible layout, evolving structure, or a combination thereof. The orchestration of the microsystem 200 can be dynamically updated, upgraded, or changed through new requests to the resource orchestrator 410. The resource orchestrator can provide orchestration information to the network manager 440 of the control plane 300. This functionality can be provided to configure appropriate communication between integrated hardware resources 112. Service integration requests typically integrate and instantiate the microsystem 200, which consists of a defined set of hardware resources 112 (e.g., CPU, timers, memory, ADC, etc.).

[0070] Resource orchestrator 410 may include pre-configured microsystems 200 of chiplet arrangement 200 associated with one or more pre-configured microservices 410 of chiplet arrangement 100. That is, the resource orchestrator may be pre-configured. In FIG. 4, resource orchestrator 410 is shown as microservice 400. Those skilled in the art will understand that microservice 410 is associated with a particular microsystem 200. Microservice 400 will be exposed through control plane 300, and control plane 300 will provide an interface between microservice 400 and the particular microsystem 200.

[0071] In FIG. 4, control plane 300 is also shown as including resource scheduler 420. Resource scheduler 420 may be provided to ensure the timely availability of the desired microsystem 200. Scheduling hardware resources is advantageous in order to achieve the requested performance and get the most benefit from the potential of chiplet arrangement 100. Resource scheduler is advantageously configured to balance stringent real-time requirements with other types of priorities and / or strategies. Those skilled in the art should understand that such scheduling depends on application strategies, policies, and regulations. A wide range of such scheduling algorithms are available and have been previously published (all references in the footnotes are incorporated herein by reference to provide context for embodiments of this disclosure: S. Singh and I. Chana, “A survey on resource scheduling in cloud computing: Issues and challenges,” Journal of Grid Computing, No. DOI 10.1007 / s10723-015-9359-2, pp. 217–264, 2016; Z.-H. ZHAN, X.-F. LIU, Y.-J. GONG, J. ZHANG, H.S.-H. CHUNG, and Y. LI, “Cloud computing resource scheduling and a survey of its evolutionary approaches,” ACM Computing Surveys, vol. 47, No. 4, July 2015; M. Kumar, S.C. Sharma, A. Goel, and S.P. .Singh's "A comprehensive survey for scheduling techniques in cloud computing", Journal of Network and Computer Applications, vol.143, pp.1–33, 2019).Therefore, resource scheduling can be considered an engineering optimization problem and will not be further detailed in this disclosure.

[0072] It should be mentioned that the resource scheduler 420 can reside inside or outside the chiplet arrangement 100. In FIG. 4, the resource scheduler 420 is shown inside the chiplet arrangement 100, but this is only one alternative and other implementations may be considered depending on the application.

[0073] For the resource orchestrator 410, the resource scheduler 420 can be pre-configured. In FIG. 4, the resource scheduler 420 is shown as a microservice 400, but those skilled in the art will understand that the microservice 420 is associated with a specific microsystem 200.

[0074] The exemplary control plane 300 in FIG. 4 includes a resource registry 430. The resource registry 430 can be configured to store data related to the hardware resources 112 of the chiplet arrangement 100. Advantageously, the data includes information indicating one or more of the following: resource ID for each hardware resource 112, physical address of each hardware resource 112 of chiplet arrangement 100, and / or electronic address of each hardware resource 112 of chiplet arrangement 100. The resource registry may include additional data associated with the hardware resources of chiplet arrangement 100, such as resource specifications, configuration data, and / or metadata. This data is typically generated at design time and advantageously deployed to resource registry 430 during chiplet production. It should be noted that resource registry 430 does not need to include data associated with all hardware resources 112 of chiplet arrangement 100.

[0075] In the chiplet arrangement 100 of FIG. 4, control plane 300 also includes network manager 440. Network manager 440 is advantageously configured to dynamically configure network connectivity of chiplet arrangement 100. That is, network manager 440 is configured to create communication channels suitable for the microsystem 200 of the chiplet arrangement. The network manager may be configured to interface with various bus technologies, such as, but not limited to, PCI or UCPI. The network manager 440 can also be configured to communicate with various components (hardware resources 112, chiplet network 120, external communication interface 150, etc.) of the chiplet arrangement 100 (see page 8 / 15 of CN 121039653 A). Advantageously, each chiplet 110 and the instantiated microsystem 200 are identified at the external communication interface 150 that exposes its associated microservice 400. The network manager is advantageously configured to ensure efficient and reliable communication between internal devices of the chiplet arrangement 100 and between internal devices of the chiplet arrangement 100 and external devices. This may involve measures such as implementing efficient protocols for sending data through the chiplet network 120, minimizing latency, and / or maximizing bandwidth.In addition, error correction mechanisms, flow control mechanisms, and mechanisms for handling errors and exceptions can be implemented to improve efficiency and reliability in communication.

[0076] For the resource orchestrator 410, the network manager 440 can be pre-configured. The microservice 400 will be exposed through the control plane 300, and the control plane 300 will provide the interface between the microservice 400 and the specific microsystem 200. This is illustrated in Figure 4, where the network manager 440 (microservice 200 of the control plane) provides the external communication interface 150 at the application level (dashed line in Figure 4). The physical connection of the external communication interface 150 is provided by the appropriate hardware resources 112e (solid line in Figure 4) included in the microsystem 230. In Figure 4, the network manager 440 is shown as the microservice 400, but those skilled in the art will understand that the microservice 440 is associated with the specific microsystem 200.

[0077] The chiplet arrangement 100 of FIG4 is an exemplary chiplet arrangement 100, and the features described with reference to FIG4 are optional and can be freely combined with each other or with any other features described herein.

[0078] Referring to FIG5, some additional exemplary microservices 400 will be presented. In FIG5, the control plane 300 of the chiplet arrangement 100 includes a resource monitor 450 associated with a particular microsystem 200 (not shown in FIG5). The resource monitor 450 can be configured to capture the status of a wide variety of hardware resources 112 and their current and / or specified capabilities. Thus, the status type and capability type are advantageously part of the metadata registered in the resource registry 430 for each hardware resource 112. The transmission of such status data can be provided via electrical communication and / or by monitoring microservice requests. The resource monitor 450 can be configured to provide access to historical data. Historical data can be accessed for predictive maintenance, optimization, etc. Advantageously, historical data is only available for a limited time, which is typically determined by the capacity of the storage device associated with the amount of historical data generated. Resource monitor 450 advantageously resides in chiplet arrangement 100 to enable proper monitoring of its hardware resources 112.

[0079] In FIG. 5, the control plane 300 of chiplet arrangement 100 also includes a resource security microservice 460 associated with a specific microsystem 200 (not shown in FIG. 5). Typically, some form of security is advantageous in most applications. Depending on application requirements and hardware capabilities, chiplet security measures of interest may include one or more of the following: physical tamper detection, encryption of data transmitted via chiplet electrical communication (chiplet network 120, etc.), secure software uptime, enabling, for example, over-the-air (OTA) software updates, secure hardware uptime, etc. Such security detection and action are advantageously initiated and monitored by resource security microservice 460.Advantageously, any available security issue detection and action types provided by the resource security microservice 460 can form part of the metadata registered in the resource registry 430.

[0080] In FIG. 5, the control plane 300 of the chiplet arrangement 100 also includes a debugger 470 with an associated microsystem 200 (not shown in FIG. 5). The debugger 470 advantageously supports, for example, testing and verification of the chiplet arrangement 100, the control plane 300, and the instantiated microsystem 200. The debugger 470 can be configured to track the execution of software instructions in real time, thereby allowing developers to identify potential problems with hardware access, timing, and / or synchronization. The debugger 470 can be configured to monitor memory access in real time, thereby allowing developers to detect and diagnose problems such as memory corruption, buffer overflows, or other memory-related issues. The debugger 470 can be configured to examine the values ​​of hardware registers of one or more hardware resources 112 in real time, thereby allowing developers to diagnose problems related to hardware configuration or control. Debugger 470 can be configured to set breakpoints and / or watchpoints at specific points in program instructions or at memory addresses, allowing developers to pause execution and inspect system status at critical points. Debugger 470 can be configured to provide detailed performance analysis information, allowing developers to identify performance bottlenecks and optimize code for better hardware utilization.

[0081] As described above, the microservice 400 and associated microsystem 200 in the above examples are for illustrative purposes only and should not be construed as limiting in any way. As shown in FIG5, control plane 300 may include other microservices 200 with associated microsystems 200. Examples presented, for example, in FIG4 and FIG5, can be freely combined with each other.

[0082] Generally, dynamic instantiation refers to the ability to create and configure instances of a design or component during runtime. In the present disclosure and associated architecture, it refers to the ability to dynamically create and configure instances of microsystem 200. The use of dynamic instantiation will allow for flexibility and scalability in system design, as it allows for the creation of customized microsystems 200 as needed, and can further reduce costs by allowing the reuse of existing chiplets 110. For this purpose, the chiplet arrangement 100 is advantageously configured to host one or more microsystems 200. Each microsystem 200 is configured to produce and / or consume one or more microservices 400. Advantageously, such microsystems 200 are configured to be dynamically instantiated during runtime. To achieve this instantiation, the chiplet arrangement 100 can be configured to expose its hardware resources 112 and their allocation to the integrated microsystems, as well as their current usage status / availability.

[0083] Therefore, in order to instantiate the microsystems 200, the chiplet arrangement 100 is advantageously configured to dynamically integrate the chiplets 110 and necessary program instructions at runtime to form the microsystems 200.Additionally, this architecture allows the use of resources allocated to non-running microsystems. This is provided by the control plane 300 of this disclosure.

[0084] An exemplary process of dynamic instantiation of a microsystem will be illustrated with reference to FIG6. FIG6 shows a System Modeling Language (SysML) sequence diagram. As known to those skilled in the art, a SysML diagram is a diagram that illustrates the interactions of system components or participants over time. In FIG6, the interactions between system components or participants are shown as a series of events, where arrows indicate the control flow between them. The events are organized chronologically from top to bottom over time. The sequence begins with the receipt of an integration request, indicated by the arrow in the upper left corner of FIG6. This process will be described below.

[0085] (1) Resource orchestrator 410 receives a service request with microsystem scheme 105. Microsystem scheme 105 includes data required to instantiate the new microsystem 200 and its microservices 400. Such data may indicate, for example, scheduling conditions, program instructions, configuration parameters, policies, security certificates, etc.

[0086] (2) The resource orchestrator 410 queries the resource registry 430 to find available hardware resources 112 that match the microsystem scheme 105. The resource orchestrator 410 checks the list of available resources and selects the list of available resources that meet the requirements of the specific microsystem scheme 105. This part of the process ensures that the selected hardware resources 112 are available and meet the requirements of the microsystem scheme 105, thereby enabling their composability.

[0087] (3) After determining that the hardware resources 112 that will meet the requirements of the microsystem scheme 105 are selected, the resource orchestrator 410 requests the resource scheduler 420 to allocate the scheduled time and time slots. This may include tasks such as resource scheduling, prioritization, etc.

[0088] (4) The operation result of the resource scheduler 420 provides microsystem deployment data. The microsystem deployment data is provided to the network manager 440. Network manager 440 is configured to deploy communication integration between orchestrated hardware resources 112 based on microsystem deployment data and to begin execution of instantiated microsystem 200. This deployment will be configured for the lifecycle requested in the persistent resource scheme.

[0089] (5) Microsystem 200 can be deployed in response to resources configured using parameters indicated in microsystem scheme 105, and program instructions are executed by processing circuitry (hardware resources 112 in the form of processing circuitry). Advantageously, deployment is performed in response to hardware resources 112 being scheduled and chiplet network 120 being established for them.

[0090] (6) Advantageously, instantiated microsystem 200 is tested before it is determined to be ready for use. Tests can be performed to ensure that the overall operation of the microsystem conforms to the service request and microsystem scheme 105.Instruction manual, pages 10 / 15, 13 CN 121039653 A

[0091] (7) If the test result is positive, the microsystem 200 is set up and a registry update is sent to the resource registry 430 to list and store information about the microsystem 200, the microservice instance, and the hardware resources 112 used for the task.

[0092] (8) In response to the microsystem 200 coming online, microservice operation can begin.

[0093] As illustrated in the process in FIG6, the operation and utilization of the microsystem 200 can begin in response to the deployed microsystem 200 reaching a static state. In a stable state, the microsystem 200 is configured as needed and provides the software required to use the microsystem. Once the intended microsystem 200 is instantiated, the microservice 400 associated with the microsystem 200 is exposed to and available on the external communication interface 150 and / or the chiplet network 120. As can be seen from the above, the architecture that exposes hardware capabilities as a set of microservices 400 can be dynamically updated and expanded according to the current needs of the chiplet arrangement 100. The operation of the available microservices 400 can include management in multiple dimensions such as functionality, security, maintenance, evolution, redesign and deployment.

[0094] The microservices 400 are exposed on the chiplet network 120 and / or external communication interface 150 through a network manager 440. The network manager 440 is advantageously configured to provide IP addresses to the chiplet arrangement 100, thereby making it accessible at the external communication interface 150. The network manager 440 is advantageously configured to provide the ability to communicate locally with other chips 110 in the same chiplet arrangement 100. The control plane 300 allows the orchestration and registration of microservices 200. The control plane is based on SOA principles, which is a mature technology, and therefore will only be briefly introduced here.

[0095] The system of systems (SoS) functionality refers to the collective behavior and capabilities of a set of interconnected software systems that together form a larger, more complex system. SoS functionality focuses on how these individual systems work together to achieve a common goal or a set of goals and how they transmit and share information to achieve this. This includes issues such as interoperability, data exchange, and system integration. SoS functionality is often important in large software systems where multiple independent systems need to work together to achieve a common goal. As those skilled in the art will understand, effective SoS functionality requires careful design and planning, as well as robust communication protocols and system interfaces, to ensure that each system can interact effectively with other systems.

[0096] To integrate chiplet arrangement 100 into SoS functionality, SoS functionality advantageously supports the fundamental lookup, loose coupling, and late-binding nature of SOA.The Eclipse Arrowhead architecture is well-known and provides a basic control plane that conforms to SOA principles, such as lookup, late binding, loose coupling, and security measures (e.g., authentication, authorization, etc.), as well as optional additional security measures. As an example, the basic control plane functionality in the Eclipse Arrowhead architecture reference implementation is provided by the mandatory microsystems ServiceRegistry (lookup), Orchestration (late binding, loose coupling), and Authorisation (authorisation, authentication). SoS functionality can be provided by the following (based on Eclipse Arrowhead terminology):

[0097] • ServiceRegistry and its associated ServiceDiscovery microservice

[0098] • Orchestration system and its associated Orchestration microservice, namely resource orchestrator 410 and its associated microsystem 200.

[0099] • AA security (authentication, authorization) can be provided by the authorization system and the associated microservice GetPublicKey.

[0100] • Additional control plane 300 services, such as online security, interoperability converters and adapters, workflow management and execution 2 (all references in the footnotes are incorporated herein to provide context for embodiments of this disclosure, 2 “Workflow management solutions based on microservices”, Applied Sciences), autonomous SoS maintenance and redesign 3 (all references in the footnotes are incorporated herein to provide context for embodiments of this disclosure, 3 “Dynamical orchestration and configuration services in industrial iot systems: An autonomic approach”, IEEE Open Journal of the Industrial Electronics Society, vol.3, pp.128–145, 2022).

[0101] The SysML model shown in Figure 7 illustrates some details of how these microservices are consumed by chiplet microsystems. Figure 7 shows an exemplary implementation of the ResourceSecurity microsystem within chiplet arrangement 100.In the example of Figure 7, the ability of the ResourceSecurity microsystem to consume the exemplary ServiceDiscovery, Orchestration, and GetPublicKey microservices is advantageous for control plane 300.

[0102] A method 500 for configuring chiplet arrangement 100 will be presented with reference to Figure 8. Chiplet arrangement 100 can be any chiplet arrangement 100 configured with any chiplet 110 and / or features presented herein with reference to any of the accompanying drawings or examples. Method 500 is advantageously performed by control plane 300 of chiplet arrangement 100. Method 500 includes obtaining 510 a request, such as a service request, instructing microsystem 200 to be instantiated. Microsystem 200 can be indirectly instructed by instructing specific functions that microsystem 200 should be configured to perform. Alternatively, microsystem 200 can also be directly instructed by specifying specific hardware resources 112 that correspond to forming microsystem 200. A portion of microsystem 200 can be indirectly instructed, and another portion of microsystem 200 can be directly instructed. Advantageously, the request includes a resource scheme 105 indicating one or more hardware functions required by the microsystem 200. Hardware functions can be directly indicated by specifying one or more specific hardware resources 112.

[0103] Method 500 also includes instantiating the microsystem 200 520 according to the obtained request. Instantiation 520 may further include: selecting 522 one or more hardware resources 112 that satisfy the hardware requirements indicated by the request, and obtaining 524 allocated scheduling data associated with the selected hardware resources 112. Advantageously, the request (e.g., resource scheme 105) also includes program instructions. These program instructions may be adapted to at least one of the indicated hardware resources 112 (hardware functions) and configured to instantiate the microsystem 200 when executed by the hardware resources 112. For this purpose, instantiation 520 also includes deploying the microsystem 200 526 by executing the program instructions via the hardware resources 112.

[0104] As previously described, the control plane 300 and chiplet arrangement 100 of this disclosure allow for unparalleled flexibility in the instantiation of the microsystem 200 and associated microservices 400. Instantiation of the microsystem 200 and / or microservices 400 can be based on the availability and / or utilization of hardware resources 112. This enables the control plane 300 of the chiplet arrangement 100 to optimize the utilization of hardware resources 112 based on any measurable parameter. For example, the control plane 300 may include a reward-driven agent that can control the instantiation, reconfiguration, and / or interruption of the microsystem 200 and / or microservices 400. The reconfigurability of the chiplet arrangement 100 allows it to adapt and change in response to new information or changes in its environment.This can be referred to as adaptive hardware, flexible hardware, reconfigurable hardware, or a plastic system. A plastic system is able to modify its behavior, structure, or function to adapt to new inputs or demands without having to undergo permanent changes. Plasticity is often associated with highly flexible and adaptive systems, such as biological systems, cognitive systems, or neural networks. These systems are able to learn from experience, reorganize their structure, and modify their behavior in response to new inputs or stimuli. Overall, the plasticity of a system is a key factor in its ability to cope with changing conditions or demands and can be a key determinant of its overall functionality and success. The chiplet arrangement 100 of this disclosure provides plasticity for hardware.

[0105] The following is a general architectural analysis of what has been presented herein. The proposed architecture described in the previous sections can be considered as a theoretical framework for the design and development of future electronic systems. To demonstrate its feasibility, the following sections analyze the most relevant aspects of its implementation and propose solutions based on currently available technologies. Service requests trigger the instantiation of microsystem 200. Service requests are an advantageous part of the integration of hardware resources 112 because they include the information required to build, configure, and test microsystem 200. The request can be sent externally to the resource orchestrator 410 that initiates the instantiation of the chiplet 100 via an interface. The request includes the resource scheme 105 proposed herein. The request may also include code (program instructions, software, software code) and instructions required to establish the microsystem 200 and provide the necessary computation. This code is adapted to the CPU type specified in the resource scheme 105 specification (pages 12 / 15, CN 121039653 A). The request may also include configuration parameters. Hardware resources 112 typically require configuration parameters. The request may include a list of parameters associated with each hardware resource 112. Examples of parameters include sampling rate, time, precision, etc. The request may also include one or more policies. In addition to configuration parameters, the request may include other types of general policies that need to be satisfied. Policies manage the operation of the chiplet 110. These policies can be set by system administrators, other authorized personnel, or system developers. The architecture proposed herein is based on the use of policies to address orchestration, composability, security, quality of service (QoS), prioritization, and resource management. Policies can be communicated to a monitoring system to ensure their long-term execution. The request may also include testing. Testing is an advantageous part of dynamic instantiation. It is provided to ensure that the microsystem operates with the expected capabilities and functions. Further details regarding the types of tests that need to be included are provided in the following sections. The same service request can be reused to configure several chiplets 110 or chiplet arrangements 100.

[0106] For successful dynamic instantiation, resource availability is advantageously carefully considered.During the initial steps of instantiation, the resource registry 430 can be used to determine whether composability is feasible based on the requirements specified in resource scheme 105 and the availability of hardware resources 112 in chiplet arrangement 100. The resource registry 430 advantageously includes the available hardware resources 112 at a given time, the type of hardware resources 112, and their technical characteristics. This information can be cross-referenced, and the required resources can be selected. Several options can be configured in cases where some resources are unavailable. If a resource of a certain type is unavailable, microsystem 200 cannot be instantiated. There are at least two solutions to this problem: (i) terminating microsystem 200 based on predefined criteria such as priority settings and data availability; or (ii) using a queue. Instantiation can be paused until hardware resources 112 are released. The resource scheduler 420 can be queried to obtain the expected lifecycle of microsystem 200 and make informed decisions. When chiplet arrangement 100 is built (produced, manufactured, sold, installed), information about hardware resources can be stored in the resource registry 430. The internal components of chiplet arrangement 100 remain unchanged over time; only their configuration and composability change with the use of microsystem 200. Therefore, resource registry 430 can include all the necessary information to determine whether composability between hardware resources 112 is feasible and whether it meets the expected service capabilities.

[0107] Network management is one aspect of the presented architecture. The microservice architecture is designed to operate in a fully connected, wireless open network. However, in chiplet arrangement 100, the network faces many constraints and limitations. Furthermore, the nature of chiplet arrangement 100 involves managing the network between chiplets 110 to integrate smaller, independent chips into a larger chiplet arrangement 100. To demonstrate the feasibility of this approach and analyze the potential limitations of current technology, we propose two methods.

[0108] The first method involves Peripheral Component Interconnect (PCI). The PCI bus is a standard bus architecture that provides a high-speed communication channel between the processor and other peripheral devices. The PCI bus can be used as a communication network between chiplet 110 and other components of the system. Therefore, the network manager 400 will act as the PCI bus master, initiating transactions on the bus and managing data transfer between the chiplet and other components.

[0109] The second method includes Universal Chiplet Interconnect (UCPI). UCPI is a high-speed, low-latency interconnect technology specifically designed for chiplet 110. In this method, the network manager 440 will act as the UCPI controller, managing communication between chiplet 110 and other components of the system.

[0110] Regardless of the specific technology used, the network manager 440 advantageously ensures efficient, reliable, and secure communication between chiplet 110 and other components.This can involve implementing error correction and flow control mechanisms, prioritizing different types of data, and handling issues such as congestion or network failures.

[0111] In the context of the proposed architecture, during microsystem instantiation, it typically occurs to integrate the microsystem 200 and individual chips 110 into a larger system and test it. Therefore, to ensure proper operation of the entire system, it is advantageous to develop robust system testing strategies. In chiplet technology, the most commonly used built-in system testing strategies for microsystem instantiation are software code unit testing, built-in self-test (BIST), boundary scan, error correction code (ECC), and post-silicon verification, as described on pages 13 / 15 of the specification, CN 121039653 A.

[0112] Regarding software code unit testing, in this case, the microsystem code introduced in the service request is tested to ensure correct microsystem operation. These tests can be included in the service request in the form of unit tests.

[0113] BIST involves designing self-test circuitry and mechanisms that can perform diagnostic tests and identify any defects or problems within the chiplet 110. BIST can help detect faults in various parts of chiplet arrangement 100 (e.g., memory arrays or logic blocks).

[0114] Boundary scan involves incorporating boundary scan units into the chiplet design. These units can be used to perform structural testing on chiplet arrangement 100 and can assist in identifying any faults in the interconnects between chiplets 110.

[0115] ECC can be incorporated into the chip design to detect and correct errors that may occur in the memory or data paths of the chiplets.

[0116] Once chiplet 110 is integrated into a larger system, extensive post-silicon verification testing can be performed to ensure the system functions as expected. This can include running a suite of functional tests, performance tests, and stress tests to verify the reliability and robustness of the system.

[0117] When microsystem 200 or all its associated microservices 400 are no longer requested or needed, the microsystem can be released. This means that hardware resources 112 are released from microsystem 200 (de-associated with microsystem 200) and control plane 300 is updated to reflect the release of microsystem 200.

[0118] The lifecycle of the microsystem 200 can be divided into four phases: (1) microsystem instantiation, (2) service deployment, (3) operation, and (4) release. The utilization of resources in these phases is different. Computation and communication between components in the control plane 300 may result in overhead and latency; however, the heaviest load is concentrated in the first two phases. Instantiation and deployment are temporary phases that are only needed when the chiplet arrangement 100 is updated or reused for other functions. Therefore, operation remains unaffected by the new architecture, and once the microsystem 200 is instantiated and the chiplet 110 communicates via the microservice 400, the electronic system continues to operate as a monolithic architecture.

[0119] The microservice-based chiplet implementations proposed herein can be adopted in a wide range of fields.

[0120] In the telecommunications field, the microservice-based chiplet arrangement 100 proposed herein can be used in telecommunications systems to provide different functions, such as network processors / processes, communication blocks and RF systems, routing, switching, security, etc. This allows the industry to easily replace or substitute newer versions, as the newer versions are designed to be independent of the entire system.

[0121] In the automotive field, the microservice-based chiplet arrangement 100 can be used in automotive systems to provide different functions, such as driver assistance, navigation, entertainment, health monitoring, infotainment systems, autonomous driving systems, maintenance systems, power / energy management systems, etc. These implementations can be easily integrated into the system as services, making the entire design process more modular and flexible.

[0122] In the field of industrial automation, the microservice-based chiplet arrangement 100 can be used in industrial automation systems to provide different functions, such as control (indoor and remote), monitoring, data analysis, machine vision, condition monitoring, predictive maintenance, etc. As mentioned above, the microservice-based chiplet arrangement 100 can be easily integrated into the system as a service, making the overall design process more modular and flexible, thus contributing to the Industry 4.0 concept.

[0123] In high-performance computing, the microservice-based chiplet arrangement 100 can be used to build high-performance computing systems capable of processing large amounts of data and performing complex calculations, system management, fault tolerance, AI / HW acceleration, memory management, energy management, etc.

[0124] In the field of artificial intelligence (AI), the microservice-based chiplet arrangement 100 can help build AI-based systems that will be able to perform complex tasks, such as image and speech recognition, natural language processing, joint learning, security, interpretability, edge computing, optimization, etc.

[0125] In the field of robotics, a microservice-based chiplet arrangement 100 will enable robots to adapt more easily to changing environments and needs through modular and flexible construction provided by the concepts herein, providing motor control, sensor fusion, computer vision, edge intelligence, energy management, etc.

[0126] In the consumer electronics field, a microservice-based chiplet arrangement 100 provides the ability to transfer system control to the consumer. Therefore, consumers can design and reuse gadgets according to their needs.

[0127] It should be mentioned that the above examples are only a few examples of areas where a microservice-based chiplet arrangement 100 is of importance. Many more possible use cases exist in different fields.All of this is thanks to a key aspect of the microservice-based chiplet arrangement 100, which provides a way to manage communication and interaction between different chiplets and microsystems in a more modular, flexible, and scalable manner.

[0128] The embodiments, examples, features, and concepts presented herein implement an architecture in which a control plane 300 can organize and instantiate (e.g., orchestrate) any suitable hardware and / or software resources in the form of microsystems 200. These microsystems 200 can be configured to consume one or more microservices 400 and / or generate one or more microservices 400.

[0129] Modifications and other variations of the described embodiments will occur to those skilled in the art, taking advantage of the teachings presented in the foregoing description and associated drawings. Therefore, it should be understood that the embodiments are not limited to the specific example embodiments described in this disclosure, and modifications and other variations are intended to be included within the scope of this disclosure. For example, while embodiments of the invention have been described with reference to chiplets and chiplet arrangements, those skilled in the art will understand that embodiments of the invention can be equivalently applied to any suitable computer system, rather than being specific to chiplets.

[0130] By way of example only, it is conceivable to provide a computer system that can be controlled by an external communication interface. The computer system includes multiple hardware resources, each providing at least one dedicated hardware function. The hardware resources are connected via a hardware network. The computer system provides a control plane configured to orchestrate one or more microsystems, each microsystem including at least one hardware resource and addressable connectivity at the network. The control plane is also configured to expose one or more microsystems as microservices at an external communication interface.

[0131] Furthermore, although specific terminology may be used herein, it is used only in a general and descriptive sense and not for limiting purposes. Therefore, those skilled in the art will recognize that various variations of the described embodiments still fall within the scope of the appended claims. Furthermore, although individual features may be included in different claims (or embodiments), they can be advantageously combined, and including different claims (or embodiments) does not imply that feature combinations are unfeasible and / or disadvantageous. Additionally, singular references do not exclude plural references. Finally, the reference numerals in the claims are provided only as clarifying examples and should not be construed as limiting the scope of the claims in any way.Instruction manual, page 15 / 15, 18 CN 121039653 A, Figure 1, Figure 2, Figure 3; Instruction manual, Figure 1 / 5, page 19 CN 121039653 A, Figure 4, Figure 5; Instruction manual, Figure 2 / 5, page 20 CN 121039653 A, Figure 6; Instruction manual, Figure 3 / 5, page 21 CN 121039653 A, Figure 7; Instruction manual, Figure 4 / 5, page 22 CN 121039653 A, Figure 8; Instruction manual, Figure 5 / 5, page 23 CN 121039653 A.

Claims

1. A small chip arrangement (100) controllable via an external communication interface (150), wherein, The chiplet arrangement (100) includes at least one chiplet (110) connected to a chiplet network (120), and wherein the at least one chiplet (110) includes at least one hardware resource (112); and wherein the chiplet arrangement (100) has a chiplet control plane (300) configured to: -Organize one or more microsystems (200), each microsystem (200) including at least one hardware resource (112) and addressable connections at the chiplet network (120), and - Expose one or more microsystems (200) as microservices (400) at the external communication interface (150).

2. The chiplet arrangement (100) according to claim 1, comprising two or more chipslets (110) connected via the chiplet network (120).

3. The chiplet arrangement (100) according to claim 1 or 2, wherein, The chiplet control plane (300) is configured to configure the instantiation of the microsystem (200) based on the availability and / or utilization of hardware resources (112).

4. The chiplet arrangement (100) according to any one of the preceding claims, wherein, The chiplet control plane (300) is configured to configure the instantiation of microservices (400) based on the availability and / or utilization of hardware resources (112).

5. The chiplet arrangement (100) according to any one of the preceding claims, wherein, The chiplet control plane (300) includes: - A resource orchestrator (410) is configured to instantiate a microsystem (200) of the chiplet arrangement (100).

6. The chiplet arrangement (100) according to claim 5, wherein, The resource orchestrator (410) includes pre-configured microsystems (200) of the chiplet arrangement (100), the pre-configured microsystems (200) being associated with one or more pre-configured microservices (400) of the chiplet arrangement (100).

7. The chiplet arrangement (100) according to claim 5 or 6, wherein, The resource orchestrator (410) can also be configured to instantiate microservices (400) associated with a specific microsystem (200).

8. The chiplet arrangement (100) according to any one of the preceding claims, wherein, At least one microsystem (200) is configured to consume or generate one or more microservices (400) associated with the at least one microsystem (200).

9. The chiplet arrangement (100) according to any one of the preceding claims, wherein, The chiplet control plane (300) includes: - A network manager (440) is configured to control communication between the microsystem (200) and the external communication interface (150) of the chiplet arrangement (100).

10. The chiplet arrangement (100) according to claim 9, wherein, The network manager (440) is a pre-configured microsystem (200) of the chiplet arrangement (100), which is associated with one or more pre-configured microservices (400) of the chiplet arrangement (100).

11. The chiplet arrangement (100) according to any one of the preceding claims, wherein, The control plane (300) includes a resource registry (430) which includes data indicating at least some of the hardware resources (112) of the chiplet arrangement (100). Preferably, the resource registry (430) includes data indicating all the hardware resources (112) of all the chipsets (110) of the chiplet arrangement (100).

12. The chiplet arrangement (100) according to any one of the preceding claims, wherein, The control plane (300) includes a resource scheduler (420) configured to schedule the utilization of the hardware resources (112).

13. The chiplet arrangement (100) according to claim 12, wherein, The resource scheduler (420) is a pre-configured microsystem (200) of the chiplet arrangement (100), which is associated with one or more pre-configured microservices (400) of the chiplet arrangement (100).

14. The chiplet arrangement (100) according to any one of the preceding claims, wherein, The at least one hardware resource (112) is a network interface configured to connect the chiplet (110) to the chiplet network (120).

15. The chiplet arrangement (100) according to any one of the preceding claims, wherein, At least one hardware resource (112) is a computing hardware resource such as a CPU, GPU, or microcontroller, and / or wherein at least one hardware resource (112) is a memory hardware resource such as volatile memory or non-volatile memory, and / or wherein at least one hardware resource (112) is a sensor hardware resource (112) such as a temperature sensor, pressure sensor, light sensor, optical sensor, or fingerprint sensor, and / or wherein at least one hardware resource (112) is a peripheral hardware resource (112) such as an interrupt controller, DMA controller, digital I / O, DAC, ADC, or clock, and / or wherein at least one hardware resource (112) is a communication hardware resource (112) such as an I2C interface, PCIe interface, or UCIe interface, and / or wherein at least one hardware resource (112) is an actuator hardware resource (112) such as a speaker, buzzer, light source, or display.

16. The chiplet arrangement (100) according to any one of the preceding claims, wherein, Each hardware resource (112) provides at least one dedicated hardware function.

17. The chiplet arrangement (100) according to any one of the preceding claims, wherein, The chiplet arrangement (100) is a chiplet package that forms part of an integrated circuit IC.

18. A method (500) for configuring a chiplet arrangement (100) according to any one of the preceding claims, the method (500) being performed by the control plane (300) of the chiplet arrangement (100) and comprising: Obtain (510) a request to instruct (200) the microsystem to be instantiated; as well as Instantiate the microsystem (200) (520) according to the request received.

19. The method (500) according to claim 18, wherein, The request includes a resource scheme (105) indicating one or more hardware requirements of the microsystem (200) to be instantiated, and the instantiation (520) further includes: Select (522) hardware resources (112) that meet the indicated hardware requirements; and Obtain (524) the allocated scheduling data associated with the selected hardware resource (112).

20. The method (500) according to claim 19, wherein, The request further includes program instructions that, when executed by the selected computing hardware resource, instantiate the microsystem (200) indicated by the request, and the instantiation (510) further includes: The microsystem is deployed (526) by executing the program instructions using the selected computing hardware resources.

21. The method (500) according to any one of claims 18 to 20, wherein, The instantiation (520) of the microsystem (200) is based on the availability and / or utilization of the hardware resources (112).

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