Time delay relay

Abstract

An electronic time delay relay comprising: a set of timing resistors arranged in a series circuit between a first, input node and a second, output node; at least one strap for selecting a subset of said timing resistors to provide an electrical pathway between a first input node and a second output node, wherein positioning of each said strap determines a voltage drop across said set of timing resistors; a voltage input providing an input voltage to said first input node; an analogue to digital converter (ADC) for receiving an analogue output voltage from said set of timing resistors and outputting a digital output voltage; a set of contacts; a microcontroller configured to receive as an input said digital output voltage, said microcontroller including: a processor; and storage means for storing a mathematical equation and computer-readable instructions that when executed on the processor perform the steps of: utilising said digital output voltage as an input parameter to said mathematical equation to calculate a time delay implemented by the positioning of each said strap; and changing the state of at least one of said contacts when said time delay expires.

Description

Abstract An electronic time-delay relay includes: a set of timing resistors connected in series in a circuit between a first input node and a second output node; at least one jumper wire for selecting a subset of the timing resistors to provide an electrical path between the first input node and the second output node, wherein the positioning of each jumper wire determines a voltage drop across the set of timing resistors; a voltage input terminal for providing an input voltage to the first input node; an analog-to-digital converter (ADC) for receiving an analog output voltage from the set of timing resistors and outputting a digital output voltage; a set of contacts; a microcontroller configured to receive the digital output voltage as input, the microcontroller including: a processor; and a storage device for storing mathematical equations and computer-readable instructions, which, when executed on the processor, perform the following steps: using the digital output voltage as input parameters to the mathematical equations to calculate a time delay achieved by the positioning of each jumper wire; and changing the state of at least one of the contacts when the time delay expires.

Claims

AMENDED CLAIMS received by the International Bureau on 18 September 2024 (18.09.2024)We claim:

1. An electronic time delay relay comprising: a set of timing resistors arranged in a series circuit between a first, input node and a second, output node; at least one strap for selecting a subset of said timing resistors to provide an electrical pathway between a first input node and a second output node, wherein positioning of each said strap determines a voltage drop across said set of timing resistors; a voltage input providing an input voltage to said first input node; an analogue to digital converter (ADC) for receiving an analogue output voltage from said set of timing resistors and outputting a digital output voltage; a set of contacts; a microcontroller configured to receive as an input said digital output voltage, said microcontroller including: a processor; and storage means for storing a mathematical equation and computer-readable instructions that when executed on the processor perform the steps of: utilising said digital output voltage as an input parameter to said mathematical equation to calculate a time delay implemented by the positioning of each said strap; and changing the state of at least one of said contacts when said time delay expires.

2. The electronic time delay relay of claim 1, wherein said voltage input is a precision voltage input.

3. The electronic time delay relay of either one of claim 1 or claim 2, wherein said set of timing resistors includes: a set of coarse timing resistors and an associated coarse adjustment strap, wherein positioning of said coarse adjustment strap defines a coarse adjustment electrical path including at least one of said coarse timing resistors; and a set of fine timing resistors and an associated fine adjustment strap, wherein positioning of said fine adjustment strap defines a fine adjustment electrical path including at least one of said fine timing resistors.AMENDED SHEET (ARTICLE 19)4. The electronic time delay relay of claim 3, wherein there are 13 coarse timing resistors and 2 fine timing resistors.

5. The electronic time delay relay of either one of claim 3 or claim 4, wherein the timing resistors have resistances in the range of 220kQ to 1MQ.

6. The electronic time delay relay of any one of claims 1 to 5, further comprising: a fine-tuning adjustment including a bank of at least one user-selectable switch.

7. The electronic time delay relay of claim 6, wherein said fine tuning adjustment includes a bank of DIP switches.

8. The electronic time delay relay of either one of claims 6 and 7, wherein: said storage means further stores a look-up table providing an association between permutations of the positions of each user- selectable switch and a corresponding fine time delay; and said computer-readable instructions when executed on the processor perform the further steps of: receiving switch values for each user-selectable switch; determining a fine time delay value based on said received switch values and said look-up table; and adding said fine time delay to said calculated time delay to determine an overall time delay.

9. The electronic time delay relay of any one of claims 1 to 8, further comprising: a visual display configured to display said determined time delay.

10. The electronic time delay relay according to claim 9, wherein said visual display is selected from the group consisting of: seven-segment LED display, LCD screen, or LED screen.AMENDED SHEET (ARTICLE 19)11. The electronic time delay relay according to either one of claim 9 or claim 10, wherein said microcontroller is programmed to control the visual display, said microcontroller decrementing a displayed time as time passes.

12. The electronic time delay relay according to any one of claims 9 to 11, wherein said visual display includes a plurality of seven-segment LED displays.

13. The electronic time delay relay of any one of claims 1 to 12, further comprising: diagnostic software executing on said microcontroller to determine a fault status of the relay.

14. The electronic time delay relay of any one of claims 1 to 13, wherein: said set of contacts is associated with a corresponding set of FET drivers, wherein an activation signal received by one of said FET drivers causes a change of state of a corresponding contact.

15. A composite, fail-safe electronic time delay relay comprising: a set of relay contacts and a corresponding set of activation inputs; a set of timing resistors arranged in a series circuit between a first, input node and a second, output node, at least one strap for selecting a subset of said timing resistors to provide an electrical pathway between a first input node and a second output node, wherein positioning of each said strap determines a voltage drop across said set of timing resistors; a voltage input providing an input voltage to said first input node; an analogue to digital converter (ADC) for receiving an analogue output voltage from said set of timing resistors and outputting a digital output voltage; a high current FET board for controlling states of the respective relay contacts, based on states of the respective activation inputs; a first system board that includes: a first microcontroller configured to receive as an input said digital output voltage, said first microcontroller including: a first processor; andAMENDED SHEET (ARTICLE 19)first storage means for storing a mathematical equation and computer- readable instructions that when executed on the first processor perform the steps of: utilising said digital output voltage as an input parameter to said stored mathematical equation to calculate a first coarse time delay implemented by the positioning of each said strap; and determining a first total time delay based on said first coarse time delay; a second system board that includes: a second microcontroller configured to receive as an input said digital output voltage, said second microcontroller including: a second processor; and second storage means for storing said mathematical equation and computer-readable instructions that when executed on the second processor perform the steps of: utilising said digital output voltage against as an input parameter to said stored mathematical equation to calculate a second coarse time delay implemented by the positioning of each said strap; determining a second total time delay based on said second coarse time delay; and a display module for displaying an overall time delay based on said first total time delay and said second total time delay; wherein, upon detection of an activation voltage at one of said activation inputs, said first microcontroller and said second microcontroller detect said activation voltage and send a corresponding activation signal to said FET board to change the state of a contact associated with the activation input to which the activation voltage was applied.

16. The relay of claim 15, wherein: the first system board further includes a first fine adjustment device, wherein the first microcontroller reads the first fine adjustment device to determine a fine time delay and adds the first fine time delay to the first coarse time delay to determine said first total time delay; andAMENDED SHEET (ARTICLE 19)the second system board further includes a second fine adjustment device, wherein the second microcontroller reads the second fine adjustment device to determine a second fine time delay and adds the second fine time delay to the second coarse time delay to determine said second total time delay.

17. The relay of claim 16, wherein each of the first fine adjustment device and the second fine adjustment device is implemented using a bank of switches, wherein the bank of switches is implemented using at least one of dual in-line (DIP) switches, and jumper blocks.

18. The relay of claim 16, wherein said first and second system boards communicate with each other to confirm the accuracy of the determined time delay by utilising software executing on the first microcontroller and the second microcontroller to comparing the first total time delay and the second total time delay, wherein the overall time delay corresponds to one of the first total time delay and the second total time delay when the difference between the first total time delay and the second total time delay is within a predefined margin for error.

19. The relay of claim 18, wherein the first microcontroller blows a first fuse on the first system board when the first microcontroller determines that the first total time delay and the second total time delay differ by more than said predefined margin for error.

20. The relay of claim 18, wherein the second microcontroller blows a second fuse on the second system board when the second microcontroller determines that the first total time delay and the second total time delay differ by more than said predefined margin for error.

21. The relay of any one of claims 15 to 20, wherein: the first system board further includes a first fuse configured to blow when an error state occurs on said first system board; and the second system board further includes a second fuse configured to blow when an error state occurs on said second system board; and further wherein the FET board returns each of the relay contacts to a default safe state when at least one of the first fuse or the second fuse blows.AMENDED SHEET (ARTICLE 19)22. The relay of any one of claims 15 to 21, wherein said high current FET board includes a set of two pairs of MOSFETs in series for each relay contact, wherein the first microcontroller controls a first pair of MOSFETs for each relay contact and the second microcontroller controls a second pair of MOSFETs for each relay contact, and wherein when the first microcontroller activates the first pair of MOSFETs for a particular relay contact and the second microcontroller activates the second pair of MOSFETs for that particular relay contact, then the FET board changes the state of that particular relay contact.

23. The relay of any one of claims 15 to 22, wherein the set of relay contacts includes at least one normally open contact and the FET board includes at least one enhancement mode MOSFET associated with each normally open contact.

24. The relay of any one of claims 15 to 23, wherein the set of relay contacts includes at least one normally closed contact and the FET board includes at least one depletion mode MOSFET associated with each normally closed contact.

25. An electronic time delay relay comprising: a time delay unit with an associated set of time delay controls, said time delay unit being positioned between a first, input node and a second, output node; a set of contacts; a microcontroller including a processor; and storage means for storing computer-readable instructions that when executed on the processor perform the steps of: determining an overall time delay for the relay as set by the time delay controls by utilising one or more mathematical equations, one or more look-up tables, or any combination thereof; upon receipt of an activation control corresponding to one of said contacts, changing the state of that contact when said determined overall time delay expires; wherein said electronic time delay relay further comprises: a display unit for displaying said determined time delay; andAMENDED SHEET (ARTICLE 19)wherein said time delay controls include at least one of: a set of resistors and associated strappings; a General Purpose Input / Output (GPIO); a bank of switches; and a voltage input providing an input voltage to said first, input node; an analogue to digital converter (ADC) for receiving an analogue output voltage from said time delay unit at said second, output node and outputting a digital output voltage.

26. The electronic time delay relay according to claim 25, wherein said time delay controls include a set of timing resistors arranged in a series circuit between said first, input node and said second, output node; at least one strap for selecting a subset of said timing resistors to provide an electrical pathway between said first, input node and said second, output node, wherein positioning of each said strap determines a voltage drop across said set of timing resistors; and further wherein said computer-readable instructions, when executed on the processor perform the further step of: determining a first coarse time delay associated with said set of timing resistors by utilising said digital output voltage derived from said second, output node as an input to one of: a first look-up table stored in said storage means; and a mathematical equation, wherein said overall time delay is based on said first coarse time delay.

27. The electronic time delay relay according to claim 26, wherein said mathematical equation is selected from the group consisting of: linear equation; quadratic equation; cubic equation; and quartic equation.

28. The electronic time delay relay according to any one of claims 25 to 27, wherein said time delay controls include a GPIO positioned between said first, input node and said second, output node, and further wherein said computer-readable instructions, when executed on the processor perform the further steps of: determining a second coarse time delay associated with said GPIO by utilising said digital output voltage as an input to a second look-up table stored in said storage means, wherein said overall time delay is based on said second coarse time delay.

28. The electronic time delay relay according to any one of claims 25 to 27, wherein:AMENDED SHEET (ARTICLE 19)said time delay controls include bank of switches; said storage means further stores a third look-up table providing an association between permutations of the positions of each switch and a corresponding fine time delay; and further wherein said computer-readable instructions, when executed on the processor perform the further step of: receiving switch values for each user-selectable switch; and determining a fine time delay value based on said received switch values and said third look-up table, wherein said overall time delay is based on said fine time delay.

29. The electronic time delay relay of claim 28, wherein said bank of switches includes at least one bank of DIP switches.

30. A composite, fail-safe electronic time delay relay comprising: a set of relay contacts and a corresponding set of activation inputs; a time delay unit with an associated set of time delay controls, said time delay unit being positioned between a first, input node and a second, output node; a high current FET board for controlling states of the respective relay contacts, based on states of the respective activation inputs; a first system board that includes: a first microcontroller including: a first processor; and first storage means for storing computer-readable instructions that when executed on the first processor perform the steps of: determining a first total time delay for the relay as set by the time delay controls by utilising one or more mathematical equations, one or more look-up tables, or any combination thereof; a second system board that includes: a second microcontroller configured to receive as an input said digital output voltage, said second microcontroller including: a second processor; and second storage means for storing computer-readable instructions that when executed on the second processor perform the steps of:AMENDED SHEET (ARTICLE 19)determining a second total time delay for the relay as set by the time delay controls by utilising one or more mathematical equations, one or more look-up tables, or any combination thereof; a display module for displaying an overall time delay based on said first total time delay and said second total time delay; wherein, upon detection of an activation voltage at one of said activation inputs, said first microcontroller and said second microcontroller detect said activation voltage and send a corresponding activation signal to said FET board to change the state of a contact associated with the activation input to which the activation voltage was applied, once the overall time delay has expired.AMENDED SHEET (ARTICLE 19)

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