Package comprising dummy silicon structure located between integrated devices

Abstract

A package includes: a package interposer; a first integrated device, the first integrated device being coupled to the package interposer; a second integrated device, the second integrated device being coupled to the package interposer; a dummy silicon structure laterally located between the first integrated device and the second integrated device; and a second encapsulation layer coupled to the package interposer, where the encapsulation layer at least partially encapsulates the first integrated device, the second integrated device, and the dummy silicon structure. The package interposer includes a first metallization portion; a second metallization portion; a first passive device, wherein the first passive device is located between the first metallization part and the second metallization part; and a first encapsulation layer, wherein the first encapsulation layer is located between the first metallization part and the second metallization part.

Description

(19) State Intellectual Property Office (12) Invention Patent Application (10) Application Publication Number (43) Application Publication Date (21) Application Number 202580001454.7 (22) Application Date 2025.06.13 (30) Priority Data 18 / 748,011 2024.06.19 US (85) PCT International Application Entering National Phase Date 2025.08.14 (86) PCT International Application Application Data PCT / US2025 / 033541 2025.06.13 (87) PCT International Application Publication Data WO2025 / 264494 EN 2025.12.26 (71) Applicant Qualcomm Incorporated Address California, USA (72) Inventors Y. Song W. Stone (74) Patent Agency Shanghai Patent & Trademark Agency Co., Ltd. 31100 Patent Attorney Chen Wei (51) Int.Cl. H10W 44 / 00(2026.01) H10W 42 / 00(2026.01) H10W 74 / 10(2026.01) H10W 70 / 65(2026.01) H10D 80 / 30(2026.01) (54) Invention Title Includes Package with Dummy Silicon Structure Located Between Integrated Devices (57) Abstract A package includes: a package interposer; a first integrated device coupled to the package interposer; a second integrated device coupled to the package interposer; a dummy silicon structure laterally located between the first integrated device and the second integrated device; and a second encapsulation layer coupled to the package interposer, wherein the encapsulation layer at least partially encapsulates the first integrated device, the second integrated device and the dummy silicon structure. The packaged interposer includes a first metallized portion; a second metallized portion; a first passive device located between the first metallized portion and the second metallized portion; and a first encapsulation layer located between the first metallized portion and the second metallized portion.Claims 2 pages, Description 25 pages, Drawings 21 pages, CN 121605800 A 2026.03.03 CN 1 21 60 58 00 A 1. A package comprising: a package interposer, the package interposer comprising: a first metallized portion; a second metallized portion; a first passive device located between the first metallized portion and the second metallized portion; and a first encapsulation layer located between the first metallized portion and the second metallized portion; a first integrated device coupled to the package interposer; a second integrated device coupled to the package interposer; a dummy silicon structure laterally located between the first integrated device and the second integrated device; and a second encapsulation layer coupled to the package interposer, wherein the encapsulation layer at least partially encapsulates the first integrated device, the second integrated device and the dummy silicon structure. 2. The package of claim 1, wherein the dummy silicon structure is coupled to the package interposer via an adhesive. 3. The package of claim 1, wherein the dummy silicon structure is configured to have no electrical connection to the first integrated device and / or the second integrated device. 4. The package of claim 1, wherein the package interposer further comprises a second dummy silicon structure laterally located between the first integrated device and the second integrated device. 5. The package of claim 1, wherein the dummy silicon structure is positioned adjacent to (i) the edge of the first integrated device including a die-to-die portion and (ii) the edge of the second integrated device including a die-to-die portion. 6. The package of claim 1, wherein the first integrated device is coupled to the package interposer via a first plurality of columnar interconnects and / or a first plurality of solder interconnects, and wherein the second integrated device is coupled to the package interposer via a second plurality of columnar interconnects and / or a second plurality of solder interconnects. 7. The package of claim 1, wherein the first integrated device is coupled to the first metallized portion of the package interposer, and wherein the second integrated device is coupled to the first metallized portion of the package interposer. 8. The package of claim 1, wherein the first integrated device is coupled to the second metallized portion of the package interposer, and wherein the second integrated device is coupled to the second metallized portion of the package interposer. 9. The package of claim 1, wherein the first passive device comprises a trench capacitor device.10. The package of claim 1, wherein the package interposer further comprises a second passive device, wherein the first passive device is configured to be electrically coupled to the first integrated device, and wherein the second passive device is configured to be electrically coupled to the second integrated device. 11. The package of claim 1, wherein the package interposer further comprises a bridge located between the first metallized portion and the second metallized portion. 12. The package of claim 11, wherein the electrical path between the first integrated device and the second integrated device includes the bridge. 13. The package of claim 11, wherein the electrical path between the first integrated device and the second integrated device includes the bridge and the first metallized portion. 14. The package of claim 11, wherein the electrical path between the first integrated device and the second integrated device includes the bridge and the second metallized portion. 15. The package of claim 1, wherein the package is implemented in a device belonging to the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle. 16. A package comprising: a substrate; a first integrated device coupled to the substrate; a second integrated device coupled to the substrate; a dummy silicon structure laterally located between the first integrated device and the second integrated device; and an encapsulation layer coupled to the substrate, wherein the encapsulation layer at least partially encapsulates the first integrated device, the second integrated device, and the dummy silicon structure. 17. The package of claim 16, wherein the dummy silicon structure is coupled to the substrate by an adhesive. 18. The package of claim 16, wherein the first integrated device is coupled to the substrate via a first plurality of columnar interconnects and / or a first plurality of solder interconnects, and wherein the second integrated device is coupled to the substrate via a second plurality of columnar interconnects and / or a second plurality of solder interconnects.19. A package comprising: a metallized portion; a first integrated device coupled to the metallized portion; a second integrated device coupled to the metallized portion; a dummy silicon structure laterally located between the first integrated device and the second integrated device; and an encapsulation layer coupled to the metallized portion, wherein the encapsulation layer at least partially encapsulates the first integrated device, the second integrated device, and the dummy silicon structure. 20. The package of claim 19, wherein the dummy silicon structure contacts the metallized portion. Claims 2 / 2 Page 3 CN 121605800 A Package including a dummy silicon structure located between integrated devices

[0001] Cross-Reference to Related Applications

[0002] This application claims priority and benefit to U.S. Non-Provisional Application Serial No. 18 / 748,011, filed June 19, 2024, with the United States Patent and Trademark Office, the entire contents of which are incorporated herein by reference as fully set forth herein and for all applicable purposes. Technical Field

[0003] Various features relate to packages having trench capacitor devices. Background Art

[0004] Packages may include a substrate, an interposer, and / or an integrated device. These components are coupled together to provide a package capable of performing various electrical functions. There has always been a need to provide packages with better performance and / or more reliable and robust packages. Summary of the Invention

[0005] Various features relate to packages having trench capacitor devices.

[0006] One example provides a package comprising: a package interposer; a first integrated device coupled to the package interposer; a second integrated device coupled to the package interposer; a dummy silicon structure laterally located between the first integrated device and the second integrated device; and a second encapsulation layer coupled to the package interposer, wherein the encapsulation layer at least partially encapsulates the first integrated device, the second integrated device, and the dummy silicon structure. The package interposer includes a first metallized portion; a second metallized portion; a first passive device located between the first metallized portion and the second metallized portion; and a first encapsulation layer located between the first metallized portion and the second metallized portion.

[0007] Another example provides a package comprising: a substrate; a first integrated device coupled to the substrate; a second integrated device coupled to the substrate; a dummy silicon structure laterally located between the first integrated device and the second integrated device; and an encapsulation layer coupled to the substrate, wherein the encapsulation layer at least partially encapsulates the first integrated device, the second integrated device, and the dummy silicon structure.

[0008] Another example provides a package comprising: a metallized portion; a first integrated device coupled to the metallized portion; a second integrated device coupled to the metallized portion; a dummy silicon structure laterally located between the first integrated device and the second integrated device; and an encapsulation layer coupled to the metallized portion, wherein the encapsulation layer at least partially encapsulates the first integrated device, the second integrated device, and the dummy silicon structure. Brief Description of the Drawings

[0009] Various features, qualities, and advantages will become apparent when the detailed description set forth below is understood in conjunction with the accompanying drawings, in which similar reference characters are correspondingly identified throughout.

[0010] FIG1 illustrates an exemplary cross-sectional view of a package including a dummy silicon structure.

[0011] FIG2 illustrates an exemplary cross-sectional view of a package including a dummy silicon structure. Specification 1 / 25 Page 4 CN 121605800 A

[0012] FIG3 illustrates an exemplary cross-sectional view of a package including a dummy silicon structure.

[0013] FIG4 illustrates an exemplary cross-sectional view of a package including a dummy silicon structure.

[0014] FIG5 illustrates an exemplary plan view of a package including a dummy silicon structure.

[0015] FIGS. 6A to 6E illustrate exemplary steps for manufacturing a package including a dummy silicon structure.

[0016] FIG7 illustrates an exemplary flowchart of a method for manufacturing a package including a dummy silicon structure.

[0017] FIGS. 8A to 8E illustrate exemplary steps for manufacturing a package including a dummy silicon structure.

[0018] FIG9 illustrates an exemplary flowchart of a method for manufacturing a package including a dummy silicon structure.

[0019] FIGS. 10A to 10B illustrate exemplary steps for manufacturing a metallized portion.

[0020] FIG11 illustrates an exemplary flowchart of a method for manufacturing a metallized portion.

[0021] FIG12 illustrates various electronic devices in which the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein can be integrated. Detailed Description

[0022] In the following description, specific details are set forth to provide a thorough understanding of various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown as block diagrams to avoid complicating these aspects with unnecessary details. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid complicating these aspects of this disclosure.

[0023] This disclosure describes a package comprising: an interposer; a first integrated device coupled to the interposer; a second integrated device coupled to the interposer; a dummy silicon structure laterally located between the first and second integrated devices; and a second encapsulation layer coupled to the interposer, wherein the encapsulation layer at least partially encapsulates the first integrated device, the second integrated device, and the dummy silicon structure. The interposer includes a first metallized portion; a second metallized portion; a first passive device located between the first and second metallized portions; and a first encapsulation layer located between the first and second metallized portions. The use of the dummy silicon structure helps reduce warpage of the package and helps improve the reliability of the connectors and / or connections between the components of the package.

[0024] Exemplary Package Including Dummy Silicon Structure

[0025] FIG1 illustrates a cross-sectional view of a package 100 including a dummy silicon structure. The package 100 is coupled to a board 101 via a plurality of solder interconnects 114. The board 101 includes at least one board dielectric layer 110 and a plurality of board interconnects 112. The board 101 may include a printed circuit board (PCB). In some specific embodiments, the package 100 may be coupled to a substrate.

[0026] The package 100 includes a metallization portion 102, an integrated device 103, an integrated device 105, a dummy silicon structure 107, and an encapsulation layer 106. The metallization portion 102 includes at least one dielectric layer 120 and a plurality of metallization interconnects 122. A plurality of columnar interconnects 124 may be coupled to the plurality of metallization interconnects 122. The plurality of columnar interconnects 124 may be considered as part of the metallization portion 102. Multiple solder interconnects 114 may be coupled to multiple columnar interconnects 124 and multiple board interconnects 112.

[0027] Integration device 103 may be a first integration device. Integration device 105 may be a second integration device. Integration device 103 is coupled to metallization portion 102. Metallization portion 102 may be coupled to pad interconnects and / or columnar interconnects of integration device 103. For example, multiple metallization interconnects 122 may be coupled to and contact pad interconnects and / or columnar interconnects of integration device 103. Integration device 105 is coupled to metallization portion 102. Metallization portion 102 may be coupled to pad interconnects and / or columnar interconnects of integration device 105. For example, multiple metallization interconnects 122 may be coupled to and contact pad interconnects and / or columnar interconnects of integration device 105. Specification 2 / 25 pages 5 CN 121605800 A

[0028] Encapsulation layer 106 is coupled to the surface of metallization portion 102. Encapsulation layer 106 may at least partially encapsulate integrated device 103, integrated device 105 and dummy silicon structure 107.Therefore, integrated device 103, integrated device 105, and dummy silicon structure 107 may be at least partially located within encapsulation layer 106. Encapsulation layer 106 may include molding material, resin, epoxy resin, and / or filler.

[0029] Dummy silicon structure 107 may include dummy silicon components and / or dummy silicon blocks. Dummy silicon structure 107 may not contain transistors, passive devices, and / or logic units. Dummy silicon structure 107 may not contain any electrical connections to integrated device 103 and / or integrated device 105. For example, dummy silicon structure 107 may not contain any electrical connections to transistors and / or logic units of integrated device 103 and / or transistors and / or logic units of integrated device 105. Dummy silicon structure 107 may not contain any electrical connections to the circuitry of integrated device 103 and / or the circuitry of integrated device 105. Dummy silicon structure 107 may be laterally located between integrated device 103 and integrated device 105. The thickness and / or height of the dummy silicon structure 107 may vary depending on the specific implementation. In some implementations, the dummy silicon structure 107 may contact the metallization portion 102. In some implementations, the dummy silicon structure 107 may extend through a portion of the height and / or vertical thickness of the encapsulation layer 106, or extend through the entire height and / or vertical thickness of the encapsulation layer 106. In some implementations, the dummy silicon structure 107 may be positioned laterally to (i) the die substrate of the integrated device 103 and / or (ii) the die substrate of the integrated device 105. The dummy silicon structure 107 may be positioned adjacent to (i) the edge of the integrated device 103 including the die-to-die portion and (ii) the edge of the integrated device 105 including the die-to-die portion. The dummy silicon structure 107 may represent one or more dummy silicon structures located between the integrated device 103 and the integrated device 105. Therefore, in some embodiments, multiple dummy silicon structures may be located within the encapsulation layer 106 and between the integrated device 103 and the integrated device 105. In some embodiments, one or more dummy silicon structures may be located in other locations within the package 100.

[0030] The metallization portion 102 may include a redistribution portion. Multiple metallized interconnects 122 may include multiple redistribution interconnects. Redistribution interconnects may include portions having a U-shape or a V-shape. The terms “U-shape” and “V-shape” should be used interchangeably. The terms “U-shape” and “V-shape” may refer to the side profile shape of an interconnect, a metallized interconnect, and / or a redistribution interconnect. U-shaped interconnects (e.g., U-shaped side profile interconnects) and V-shaped interconnects (e.g., V-shaped side profile interconnects) may have a top and a bottom. The bottom of a U-shaped interconnect (or V-shaped interconnect) may be coupled to the top of another U-shaped interconnect (or V-shaped interconnect). In some specific embodiments, the process used to manufacture the redistributed interconnects may form U-shaped interconnects (or V-shaped interconnects). The above description of the metallized portions can be applied to other metallized portions described in this disclosure.

[0031] The use of at least one dummy silicon structure helps to provide a more reliable package that experiences less warping. The silicon material of the dummy silicon structure 107 may be the same as or closely matched to the material of the bare substrate of the integrated device 103 and / or the bare substrate of the integrated device 105, which helps to improve and / or minimize the warping of the package 100. Less warping of the package may mean a lower likelihood of connector breakage and / or may mean more reliable connectors and / or connections between different components of the package 100.

[0032] FIG2 illustrates a cross-sectional view of a package 200 including a dummy silicon structure. The package 200 is coupled to a board 101 via a plurality of solder interconnects 114. The board 101 includes at least one board dielectric layer 110 and a plurality of board interconnects 112. The board 101 may include a printed circuit board (PCB). In some specific embodiments, the package 200 may be coupled to a substrate.

[0033] The package 200 includes a substrate 202, an integrated device 203, an integrated device 205, a dummy silicon structure 107, and an encapsulation layer 106. The substrate 202 includes at least one dielectric layer 220 and a plurality of metallized interconnects 222. A plurality of columnar interconnects 224 may be coupled to the plurality of metallized interconnects 222. The plurality of columnar interconnects 224 may be considered as part of the metallized portion 202. A plurality of solder interconnects 114 may be coupled to the plurality of columnar interconnects 224 and a plurality of board interconnects 112.

[0034] The integrated device 203 may be a first integrated device. The integrated device 205 may be a second integrated device. The integrated device 203 is coupled to the substrate 202. For example, the integrated device 203 may be coupled to the substrate 202 via a plurality of columnar interconnects 230 and / or a plurality of solder interconnects 232. The integrated device 205 is coupled to the substrate 202. For example, integrated device 205 may be coupled to substrate 202 via multiple columnar interconnects 250 and / or multiple solder interconnects 252.

[0035] Encapsulation layer 106 is coupled to substrate 202. Encapsulation layer 106 may at least partially encapsulate integrated device 203, integrated device 205 and dummy silicon structure 107. Therefore, integrated device 203, integrated device 205 and dummy silicon structure 107 may be at least partially located in encapsulation layer 106. Encapsulation layer 106 may include molding material, resin, epoxy resin and / or filler.

[0036] Dummy silicon structure 107 may be laterally located between integrated device 203 and integrated device 205. Dummy silicon structure 107 may not contain transistors, passive devices and / or logic units. Dummy silicon structure 107 may not contain any electrical connection to integrated device 203 and / or integrated device 205. For example, the dummy silicon structure 107 may not contain any electrical connections to the transistors and / or logic units of the integrated device 203 and / or the transistors and / or logic units of the integrated device 205.The dummy silicon structure 107 may not contain any electrical connections to the circuitry of integrated device 203 and / or integrated device 205. The thickness and / or height of the dummy silicon structure 107 may vary depending on the specific implementation. In some implementations, the dummy silicon structure 107 may be coupled to the substrate 202 via adhesive 207. In some implementations, adhesive 207 may include a die attachment film (DAF). In some implementations, the dummy silicon structure 107 may extend through a portion of the height and / or vertical thickness of the encapsulation layer 106. In some implementations, the dummy silicon structure 107 may be positioned laterally to (i) the die substrate of integrated device 203 and / or (ii) the die substrate of integrated device 205. The dummy silicon structure 107 may be positioned adjacent to the edge of integrated device 203 including the die-to-die portion and the edge of integrated device 205 including the die-to-die portion. A dummy silicon structure 107 may represent one or more dummy silicon structures located between integrated device 203 and integrated device 205. Thus, in some embodiments, multiple dummy silicon structures may be located within encapsulation layer 106 and between integrated device 203 and integrated device 205. In some embodiments, one or more dummy silicon structures may be located in other locations of package 200.

[0037] The use of at least one dummy silicon structure helps to provide a more reliable package that experiences less warping. The silicon material of the dummy silicon structure 107 may be the same as or closely matched to the material of the die substrate of integrated device 203 and / or the die substrate of integrated device 205, which helps to improve and / or minimize warping of the package. Less warping of the package may mean a lower likelihood of connector breakage and / or may mean more reliable connectors and / or connections between different components of package 200.

[0038] FIG3 illustrates a cross-sectional view of package 300 including package interposers and dummy silicon structures. Package 300 is coupled to board 101 via a plurality of solder interconnects 114. Board 101 includes at least one board dielectric layer 110 and a plurality of board interconnects 112. Board 101 may include a printed circuit board (PCB). In some embodiments, instead of board 101, package 300 may be coupled to a substrate (e.g., a laminated substrate) via a plurality of solder interconnects 114.

[0039] Package 300 includes package interposer 302, integrated device 303a, integrated device 303b, dummy silicon structure 107, underfill 390, and encapsulation layer 309. In some embodiments, integrated device 303a may include a first system-on-a-chip (SoC). In some embodiments, integrated device 303b may include a second system-on-a-chip (SoC).

[0040] Package interposer 302 may be a package substrate. Package interposer 302 includes a metallization portion 320, an encapsulation portion 330, a metallization portion 340, and a plurality of columnar interconnects 325.In some embodiments, metallized portion 320 may be a first metallized portion, and metallized portion 340 may be a second metallized portion. Encapsulation portion 330 is coupled to metallized portion 320 and metallized portion 340. Encapsulation portion 330 is located between metallized portion 320 and metallized portion 340. Metallized portion 320 includes at least one dielectric layer 322 and a plurality of metallized interconnects 323. At least one dielectric layer 322 may include prepreg and / or polyimide. Metallized portion 340 includes at least one dielectric layer 342 and a plurality of metallized interconnects 343. At least one dielectric layer 342 may include prepreg and / or polyimide. A plurality of columnar interconnects 325 are coupled to the plurality of metallized interconnects 323 of metallized portion 320. The plurality of columnar interconnects 325 may be considered as part of metallized portion 320. The plurality of columnar interconnects 325 are coupled to a plurality of solder interconnects 114.

[0041] The encapsulation portion 330 includes an encapsulation layer 332 and a plurality of pillar interconnects 333. The plurality of pillar interconnects 333 may include a plurality of through-mold vias (TMVs). The encapsulation portion 330 also includes passive devices 304a, passive devices 304b, and bridges 306. Passive devices 304a, passive devices 304b, and / or bridges 306 may be at least partially located in the encapsulation layer 332. Therefore, the encapsulation layer 332 may at least partially encapsulate passive devices 304a, passive devices 304b, bridges 306, and / or the plurality of pillar interconnects 333. Passive devices 304a and / or passive devices 304b may include deep trench capacitor devices.

[0042] Bridges 306 may include silicon bridges. Bridges 306 may include bridge substrates (e.g., silicon substrates, silicon bridge substrates) and a plurality of bridge interconnects. Bridge 306 may also include at least one bridge dielectric layer. Bridge 306 may include a plurality of pillar interconnects 365.

[0043] Encapsulation layer 332 may include molding material, resin, epoxy resin and / or filler. Encapsulation layer 332 may be a component for encapsulation. Encapsulation layer 332 may be provided by using compression and transfer molding process, sheet molding process or liquid molding process. The back side of passive device 304a is coupled to metallized portion 320 via a plurality of solder interconnects 340a (e.g., multiple solder interconnects 340a coupled to multiple metallized interconnects 323 via multiple solder interconnects 340a). The back side of passive device 304b is coupled to metallized portion 320 via a plurality of solder interconnects 340b (e.g., multiple solder interconnects 340a coupled to multiple metallized interconnects 323 via multiple solder interconnects 340b). The back side of bridge 306 is coupled to metallized portion 320 via adhesive 360 ​​(e.g., die attach film (DAF)).

[0044] A plurality of post interconnects 333 extend through encapsulation layer 332.Multiple post interconnects 333 are coupled to metallized portions 320 and 340. For example, multiple post interconnects 333 may be coupled to (i) multiple metallized interconnects 323 of metallized portion 320 and (ii) multiple metallized interconnects 343 of metallized portion 340. Passive device 304a includes multiple post interconnects 345a. Multiple post interconnects 345a are coupled to and contact passive device 304a and multiple metallized interconnects 343 of metallized portion 340. Passive device 304b includes multiple post interconnects 345b. Multiple post interconnects 345b are coupled to and contact passive device 304b and multiple metallized interconnects 343 of metallized portion 340. Multiple post interconnects 365 are coupled to and contact bridge 306 and multiple metallized interconnects 343 of metallized portion 340.

[0045] Encapsulation layer 332, passive devices 304a and 304b, bridge 306, multiple pillar interconnects 333, multiple pillar interconnects 345a, multiple pillar interconnects 345b, and multiple pillar interconnects 365 are located between metallized portion 320 and metallized portion 340. Encapsulation layer 332 is coupled to metallized portion 320 and metallized portion 340. In some embodiments, some of the metallized interconnects from the multiple metallized interconnects 323 may be at least partially encapsulated by encapsulation layer 332.

[0046] Integration device 303a is coupled to a first surface of metallized portion 340 via multiple pillar interconnects 331a and multiple solder interconnects 334a. The multiple pillar interconnects 331a and / or multiple solder interconnects 334a may represent multiple bump interconnects. Integrated device 303b is coupled to a first surface of metallized portion 340 via a plurality of columnar interconnects 331b and a plurality of solder interconnects 334b. The plurality of columnar interconnects 331b and / or the plurality of solder interconnects 334b ​​may represent a plurality of bump interconnects.

[0047] Dummy silicon structure 107 may be laterally located between integrated device 303a and integrated device 303b. Dummy silicon structure 107 may not contain transistors, passive devices and / or logic units. Dummy silicon structure 107 may not contain any electrical connections to integrated device 303a and / or integrated device 303b. For example, dummy silicon structure 107 may not contain any electrical connections to transistors and / or logic units of integrated device 303a and / or transistors and / or logic units of integrated device 303b. Dummy silicon structure 107 may not contain any electrical connections to circuitry of integrated device 303a and / or circuitry of integrated device 303b. The thickness and / or height of the dummy silicon structure 107 may vary depending on the specific implementation. In some implementations, the dummy silicon structure 107 may be coupled to the package interposer 302 via adhesive 207. Adhesive 207 may include a die attachment film (DAF). In some implementations, the dummy silicon structure 107 may extend through a portion of the height and / or vertical thickness of the encapsulation layer 309.In some embodiments, the dummy silicon structure 107 may be positioned laterally to (i) the die substrate of the integrated device 303a and / or (ii) the die substrate of the integrated device 303b. The dummy silicon structure 107 may be positioned adjacent to the edge of (i) the integrated device 303a including the die-to-die portion and (ii) the edge of the integrated device 303b including the die-to-die portion. The dummy silicon structure 107 may be one or more dummy silicon structures located between the integrated device 303a and the integrated device 303b. Therefore, in some embodiments, multiple dummy silicon structures may be located in the encapsulation layer 309 and between the integrated device 303a and the integrated device 303b.

[0048] The underfill 390 is located between the integrated device 303a and the package interposer 302. The underfill 390 is located between the integrated device 303b and the package interposer 302. The underfill 390 may at least partially encapsulate and / or contact the dummy silicon structure 107. In some embodiments, the underfill 390 may comprise a composite material comprising an epoxy polymer and a filler. An encapsulation layer 309 may be located above the package insert 302. The package insert 302 may be coupled to the underfill 390, integrated devices 303a, 303b, 305a, and / or 305b. The encapsulation layer 309 may comprise a molding compound, resin, epoxy resin, and / or filler. The encapsulation layer 309 may be a component for encapsulation. The encapsulation layer 309 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes. The encapsulation layer 309 may differ from the underfill 390. For example, the encapsulation layer 309 may comprise a different material and / or a different material composition than the underfill 390. The underfill 399 may be located between the metallized portion 320 of the package insert 302 and the plate 101. The bottom filler 399 may be similar to the bottom filler 390.

[0049] The passive device 304a is configured to be electrically coupled to the integrated device 303a via the metallization portion 340. The electrical path between the integrated device 303a and the passive device 304a may include (i) columnar interconnects from a plurality of columnar interconnects 331a, (ii) solder interconnects from a plurality of solder interconnects 334a, (iii) at least one metallized interconnect from a plurality of metallized interconnects 343, and / or (iv) column interconnects from a plurality of column interconnects 345a.

[0050] The passive device 304b is configured to be electrically coupled to the integrated device 303b via the metallization portion 340.The electrical path between integrated device 303b and passive device 304b may include (i) columnar interconnects from a plurality of columnar interconnects 331b, (ii) solder interconnects from a plurality of solder interconnects 334b, (iii) at least one metallized interconnect from a plurality of metallized interconnects 343, and / or (iv) column interconnects from a plurality of column interconnects 345b.

[0051] In some embodiments, the electrical path between integrated device 303a and integrated device 303b may include a metallized portion 340. In some embodiments, the electrical path between integrated device 303a and integrated device 303b may include a metallized portion 340 and a bridge 306. For example, the electrical path between integrated device 303a and integrated device 303b may include (i) column interconnects from a plurality of column interconnects 331a, (ii) solder interconnects from a plurality of solder interconnects 334a, (iii) at least one metallized interconnect from a plurality of metallized interconnects 343, (iv) column interconnects from a plurality of column interconnects 365, (v) bridge 306, (vi) another column interconnect from a plurality of column interconnects 365, (vii) at least one other metallized interconnect from a plurality of metallized interconnects 343, (viii) solder interconnects from a plurality of solder interconnects 334b ​​and / or (ix) column interconnects from a plurality of column interconnects 331b.

[0052] In some specific embodiments, the electrical path between metallized portion 320 and metallized portion 340 may include at least one column interconnect from a plurality of column interconnects 333. In some embodiments, the electrical path between the metallized portion 320 and the metallized portion 340 may include a passive device 304a. Therefore, the electrical path between the metallized portion 320 and the metallized portion 340 may extend through a plurality of solder interconnects 340a, the passive device 304a, and a plurality of pillar interconnects 345a. The plurality of pillar interconnects 345a may be considered part of the passive device 304a. In some embodiments, the electrical path between the metallized portion 320 and the metallized portion 340 may include a passive device 304b. Therefore, the electrical path between the metallized portion 320 and the metallized portion 340 may extend through a plurality of solder interconnects 340b, the passive device 304b, and a plurality of pillar interconnects 345b. The plurality of pillar interconnects 345b may be considered part of the passive device 304b.

[0053] The integrated device 305a is coupled to the board 101 via a plurality of pillar interconnects 350a and / or a plurality of solder interconnects 352a. The integrated device 305a is coupled to the board 101 via a plurality of columnar interconnects 350b and / or a plurality of solder interconnects 352b. The integrated device 305a and / or the integrated device 305b may include memory (e.g., memory die, memory integrated device).In some embodiments, integrated device 305a may include a first memory integrated device (e.g., a first high-density memory die, a first high-bandwidth memory). In some embodiments, integrated device 305b may include a second memory integrated device (e.g., a second high-density memory die, a second high-bandwidth memory). Integrated device 305a is configured to be electrically coupled to integrated device 303a and / or integrated device 303b. Integrated device 305b is configured to be electrically coupled to integrated device 303a and / or integrated device 303b.

[0054] FIG4 illustrates a cross-sectional view of a package 400 including a package interposer and a dummy silicon structure. Package 400 is coupled to board 101 via a plurality of solder interconnects 114. In some embodiments, instead of board 101, package 400 may be coupled to a substrate (e.g., a laminated substrate) via a plurality of solder interconnects 114.

[0055] Package 400 is similar to package 300 of FIG3 and may include similar components arranged in a manner similar to that described for package 300. Package 400 includes package interposer 402, integrated device 303a, integrated device 303b, dummy silicon structure 107, and encapsulation layer 309. In some embodiments, integrated device 303a may include a first system-on-chip (SoC). In some embodiments, integrated device 303b may include a second system-on-chip (SoC).

[0056] Package interposer 402 may be a package substrate. Package interposer 402 includes a metallization portion 420, an encapsulation portion 430, a metallization portion 440, and a plurality of pillar interconnects 425. In some embodiments, metallization portion 420 may be a first metallization portion, and metallization portion 440 may be a second metallization portion. Encapsulation portion 430 is coupled to metallization portion 420 and metallization portion 440. Encapsulation portion 430 is located between metallization portion 420 and metallization portion 440. Metallization portion 420 includes at least one dielectric layer 422 and a plurality of metallized interconnects 423. At least one dielectric layer 422 may include prepreg and / or polyimide. Metallization portion 440 includes at least one dielectric layer 442 and a plurality of metallized interconnects 443. At least one dielectric layer 442 may include prepreg and / or polyimide. A plurality of columnar interconnects 425 are coupled to the plurality of metallized interconnects 423 of metallization portion 420. The plurality of columnar interconnects 425 may be considered as part of metallization portion 420. The plurality of columnar interconnects 425 are coupled to a plurality of solder interconnects 114.

[0057] Encapsulation portion 430 includes encapsulation layer 432 and a plurality of columnar interconnects 433. Encapsulation portion 430 also includes passive device 404a, passive device 404b and bridge 306.Passive devices 404a, 404b, and / or bridge 306 may be at least partially located within encapsulation layer 432. Therefore, encapsulation layer 432 may at least partially encapsulate passive devices 404a, 404b, bridge 306, and / or multiple pillar interconnects 433. Passive devices 404a and / or 404b may include deep trench capacitor devices.

[0058] Bridge 306 may include a silicon bridge. Bridge 306 may include a bridge substrate (e.g., a silicon substrate, a silicon bridge substrate) and multiple bridge interconnects. Bridge 306 may also include at least one bridge dielectric layer. Bridge 306 may include multiple pillar interconnects 365.

[0059] Encapsulation layer 432 may include molding materials, resin, epoxy resin, and / or fillers. Encapsulation layer 432 may be a component for encapsulation. Encapsulation layer 432 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes. The back side of passive device 404a is coupled to metallized portion 420 via multiple interconnects 448a. The back side of passive device 404b is coupled to metallized portion 420 via multiple interconnects 448b. The back side of bridge 306 is coupled to and contacts metallized portion 420.

[0060] Multiple pillar interconnects 433 extend through encapsulation layer 432. Multiple pillar interconnects 433 may include multiple through-mold vias (TMVs). Multiple pillar interconnects 433 are coupled to metallized portion 420 and metallized portion 440. For example, multiple pillar interconnects 433 may be coupled to (i) multiple metallized interconnects 423 of metallized portion 420 and (ii) multiple metallized interconnects 443 of metallized portion 440.

[0061] A plurality of solder interconnects 447a may be coupled to a passive device 404a (e.g., a plurality of pillar interconnects 445a coupled to the passive device 404a) and a plurality of metallized interconnects 443 of the metallized portion 440. A plurality of solder interconnects 447b may be coupled to a passive device 404b (e.g., a plurality of pillar interconnects 445b coupled to the passive device 404b) and a plurality of metallized interconnects 443 of the metallized portion 440. A plurality of interconnects 448a are coupled to and contact a plurality of metallized interconnects 423. A plurality of interconnects 448a may be considered as part of the passive device 404a. A plurality of interconnects 448a may be considered as part of the passive device 404a and / or coupled to the back side of the passive device. A plurality of interconnects 448b are coupled to and contact a plurality of metallized interconnects 423. Multiple interconnects, page 7 / 25, CN 121605800 A 448b, can be considered as part of passive device 404b. Multiple interconnects 448b can be considered as part of passive device 404b and / or coupled to the back side of the passive device.

[0062] The front side of passive device 404a faces the metallized portion 440. The front side of passive device 404a is coupled to the metallized portion 440 via multiple solder interconnects 447a.The front side of passive device 404b faces the metallization portion 440. The front side of passive device 404b is coupled to the metallization portion 440 via a plurality of solder interconnects 447b. In some embodiments, the front side of the passive device (e.g., 404a, 404b) may be the side of the passive device that includes a capacitor (e.g., a trench capacitor).

[0063] The front side of bridge 306 is coupled to a plurality of metallization interconnects 443 of metallization portion 440 via a plurality of pillar interconnects 365 and a plurality of solder interconnects 367. The back side of bridge 306 is coupled to and contacts metallization portion 420. In some embodiments, the back side of bridge 306 is the side that includes a bridge die substrate (e.g., a silicon bridge die substrate).

[0064] Encapsulation layer 432, passive device 404a, passive device 404b, bridge 306, multiple pillar interconnects 433, multiple pillar interconnects 445a, multiple pillar interconnects 445b, and multiple pillar interconnects 365 are located between metallized portion 420 and metallized portion 440. Encapsulation layer 432 is coupled to metallized portion 420 and metallized portion 440. In some embodiments, some of the metallized interconnects from the multiple metallized interconnects 423 may be at least partially encapsulated by encapsulation layer 432.

[0065] Integrated device 303a may be coupled to a first surface of metallized portion 440 via multiple pillar interconnects 331a and / or pad interconnects of integrated device 303a. Integrated device 303b may be coupled to a first surface of metallized portion 440 via multiple pillar interconnects 331b and / or pad interconnects of integrated device 303b.

[0066] Encapsulation layer 309 may be located above package inserter 402. Package inserter 402 may be coupled to integrated device 303a, integrated device 303b and encapsulation layer 309. Encapsulation layer 309 may include molding material, resin, epoxy resin and / or filler. Encapsulation layer 309 may be a component for encapsulation. Encapsulation layer 309 may be provided by using compression and transfer molding process, sheet molding process or liquid molding process.

[0067] Dummy silicon structure 107 may be laterally located between integrated device 303a and integrated device 303b. Dummy silicon structure 107 may not contain transistors, passive devices and / or logic units. Dummy silicon structure 107 may not contain any electrical connections to integrated device 303a and / or integrated device 303b. Dummy silicon structure 107 may not contain any electrical connections to the circuitry of integrated device 303a and / or integrated device 303b. The thickness and / or height of the dummy silicon structure 107 may vary depending on the specific implementation. In some implementations, the dummy silicon structure 107 may be coupled to the package interposer 302 via adhesive 207. In some implementations, the dummy silicon structure 107 may extend through a portion of the height and / or vertical thickness of the encapsulation layer 309 or through the entire height and / or vertical thickness of the encapsulation layer 309.In some embodiments, the dummy silicon structure 107 may be positioned laterally to (i) the die substrate of integrated device 303a and / or (ii) the die substrate of integrated device 303b. The dummy silicon structure 107 may be positioned adjacent to the edge of (i) the die-to-die portion of integrated device 303a and the edge of the die-to-die portion of integrated device 303b. The dummy silicon structure 107 may represent one or more dummy silicon structures located between integrated device 303a and integrated device 303b. Thus, in some embodiments, multiple dummy silicon structures may be located in encapsulation layer 309 and between integrated device 303a and integrated device 303b.

[0068] The passive device 404a is configured to be electrically coupled to integrated device 303a via metallization portion 440. The electrical path between the integrated device 303a and the passive device 404a may include (i) columnar interconnects from a plurality of columnar interconnects 331a, (ii) at least one metallized interconnect from a plurality of metallized interconnects 443, (iii) solder interconnects from a plurality of solder interconnects 447a and / or (iv) column interconnects from a plurality of column interconnects 445a.

[0069] The passive device 404b is configured to be electrically coupled to the integrated device 303b through the metallized portion 440. The electrical path between integrated device 303b and passive device 404b may include (i) columnar interconnects from a plurality of columnar interconnects 331b, (ii) at least one metallized interconnect from a plurality of metallized interconnects 443, (iii) solder interconnects from a plurality of solder interconnects 447b, and / or (iv) column interconnects from a plurality of pillar interconnects 445b.

[0070] In some embodiments, the electrical path between integrated device 303a and integrated device 303b may include a metallized portion 440. In some embodiments, the electrical path between integrated device 303a and integrated device 303b may include a metallized portion 440 and a bridge 306. For example, the electrical path between integrated device 303a and integrated device 303b may include (i) column interconnects from a plurality of column interconnects 331a, (ii) at least one metallized interconnect from a plurality of metallized interconnects 443, (iii) solder interconnects from a plurality of solder interconnects 367, (iv) column interconnects from a plurality of column interconnects 365, (v) bridge 306, (vi) another column interconnect from a plurality of column interconnects 365, (vii) another solder interconnect from a plurality of solder interconnects 367, (viii) at least one other metallized interconnect from a plurality of metallized interconnects 443 and / or (ix) column interconnects from a plurality of column interconnects 331b.

[0071] In some embodiments, the electrical path between the metallized portion 420 and the metallized portion 440 may include at least one pillar interconnect from a plurality of pillar interconnects 433. In some embodiments, the electrical path between the metallized portion 420 and the metallized portion 440 may include a passive device 404a. Thus, the electrical path between the metallized portion 420 and the metallized portion 440 may extend through a plurality of interconnects 448a, a passive device 404a, a plurality of pillar interconnects 445a, and a plurality of solder interconnects 447a. The plurality of pillar interconnects 445a and / or the plurality of interconnects 448a may be considered as part of the passive device 404a. In some embodiments, the electrical path between the metallized portion 420 and the metallized portion 440 may include a passive device 404b. Therefore, the electrical path between the metallized portion 420 and the metallized portion 440 may extend through multiple interconnects 448b, passive devices 404b, multiple pillar interconnects 445b, and multiple solder interconnects 447b. The multiple pillar interconnects 445b and / or multiple interconnects 448b may be considered part of the passive device 404b.

[0072] The integrated device 305a is coupled to the board 101 via multiple pillar interconnects 350a and / or multiple solder interconnects 352a. The integrated device 305a is coupled to the board 101 via multiple pillar interconnects 350b and / or multiple solder interconnects 352b. The integrated device 305a and / or integrated device 305b may include memory (e.g., memory die, memory integration device). In some specific embodiments, the integrated device 305a may include a first memory integration device (e.g., a first high-density memory die, a first high-bandwidth memory). In some specific implementations, integrated device 305b may include a second memory integrated device (e.g., a second high-density memory die, a second high-bandwidth memory). Integrated device 305a is configured to be electrically coupled to integrated device 303a and / or integrated device 303b. Integrated device 305b is configured to be electrically coupled to integrated device 303a and / or integrated device 303b.

[0073] FIG5 illustrates a plan view of a package 500 including a dummy silicon structure. Package 500 may be a representation of package 100, package 200, package 300 and / or package 400 of this disclosure. Package 500 includes integrated device 503, integrated device 505, a first dummy silicon structure 107a, a second dummy silicon structure 107b, a third dummy silicon structure 107c and an encapsulation layer 106. Encapsulation layer 106 may at least partially encapsulate integrated device 503, integrated device 505, first dummy silicon structure 107a, second dummy silicon structure 107b and / or third dummy silicon structure 107c. Encapsulation layer 106 may be coupled to package interposer, metallization portion and / or substrate.

[0074] Integrated device 503 includes die-to-die portion 530, first block portion 532 and second block portion 534.In some embodiments, the first block portion 532 may be configured as an input / output block for the integrated device 503. In some embodiments, the first block portion 532 may be configured as an IP block (e.g., a first functional block) for the integrated device 503. In some embodiments, the second block portion 534 may be configured as an input / output block for the integrated device 503. In some embodiments, the second block portion 534 may be configured as an IP block (e.g., a second functional block) for the integrated device 503.

[0075] The integrated device 505 includes a die-to-die portion 550, a first block portion 552, and a second block portion 554. In some embodiments, the first block portion 552 may be configured as an input / output block for the integrated device 505. In some embodiments, the first block portion 552 may be configured as an IP block (e.g., a first functional block) for the integrated device 505. In some embodiments, the second block portion 554 may be configured as an input / output block for integrated device 505. In some embodiments, the second block portion 554 may be configured as an IP block (e.g., a second functional block) for integrated device 505.

[0076] The die-to-die portion may be a portion of the integrated device including interconnects configured to provide electrical paths between two integrated devices. The input / output block may be a portion of the integrated device including interconnects configured to provide electrical paths for input / output signals. The IP block may be a portion of the integrated device including transistors and / or logic units for performing one or more functions.

[0077] The first dummy silicon structure 107a, the second dummy silicon structure 107b, and the third dummy silicon structure 107c are laterally located between integrated device 503 and integrated device 505. The first dummy silicon structure 107a, the second dummy silicon structure 107b, and the third dummy silicon structure 107c may be positioned adjacent to the edge of the die-to-die portion 530, the first block portion 532, and the second block portion 534 of the integrated device 503. The first dummy silicon structure 107a, the second dummy silicon structure 107b, and the third dummy silicon structure 107c may be positioned adjacent to the edge of the die-to-die portion 550, the first block portion 552, and the second block portion 554 of the integrated device 505.

[0078] It should be noted that different embodiments may have different numbers of dummy silicon structures with different shapes and / or sizes. In some embodiments, the dummy silicon structures may be located at different locations within the encapsulation layer. For example, one or more dummy silicon structures may be positioned along the periphery of the package. In some embodiments, multiple dummy silicon structures may laterally surround one or more integrated devices. In some embodiments, multiple dummy silicon structures may be positioned along the periphery of the package.In some specific implementations, other components and / or other materials may be used in place of the dummy silicon structure and / or in combination with the dummy silicon structure. Therefore, for example, another dummy structure comprising different materials and / or components may be used and implemented in the package of this disclosure.

[0079] Integrated devices (e.g., 303, 305) may include dies (e.g., semiconductor dies). Integrated devices may include power management integrated circuits (PMICs). Integrated devices may include application processors. Integrated devices may include modems. Integrated devices may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs) based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si) based integrated devices, silicon carbide (SiC) based integrated devices, memories, power management processors, and / or combinations thereof. Integrated devices may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). Integrated devices may include input / output (I / O) hubs. Integrated devices may include transistors. Integrated devices may be examples of electrical components and / or electrical equipment.

[0080] In some embodiments, integrated devices may be chiplets. Chipslets can be manufactured using processes that provide better yields compared to other processes used to manufacture other types of integrated devices, which can reduce the overall cost of manufacturing chiplets. Different chiplets may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different widths and / or pitches). In some embodiments, several chiplets may be used to perform the functionality of one or more chips (e.g., one or more integrated devices). As mentioned above, using several chiplets that perform several functions can reduce the overall cost of a package compared to using a single chip to perform all the functions of a package. In some embodiments, one or more chiplets and / or one or more integrated devices (e.g., 103) described in this disclosure may be manufactured using the same technology node or two or more different technology nodes. For example, an integrated device may be manufactured using a first technology node, and a chiplet may be manufactured using a second technology node that is less advanced than the first technology node. In such examples, the integrated device may include components (e.g., interconnects, transistors) having a first minimum size, and the chiplet may include components (e.g., interconnects, transistors) having a second minimum size, wherein the second minimum size is larger than the first minimum size. In some specific embodiments, the first and second integrated devices of the package may be manufactured using the same or different technology nodes as described on page 13 of this specification (CN 121605800 A).In some specific implementations, the same technology node or different technology nodes may be used to manufacture one chiplet and another chiplet of the package.

[0081] A technology node may refer to a specific manufacturing process and / or technology used to manufacture the integrated device and / or chiplet. A technology node may specify the minimum possible size (e.g., minimum size) that can be manufactured (e.g., transistor size, trace width, gap width between two transistors). Different technology nodes may have different yield losses. Different technology nodes may have different costs. Technology nodes that produce components with finer details (e.g., traces, transistors) are more expensive and may have higher yield losses compared to technology nodes that produce components with less fine details (e.g., traces, transistors). Therefore, more advanced technology nodes may be more expensive and may have higher yield losses compared to less advanced technology nodes. When all the functions of the package are implemented in a single integrated device, the same technology node is used to manufacture the entire integrated device, even if some functions of the integrated device do not need to be manufactured using that specific technology node. Therefore, the integrated device is locked into a technology node. To optimize package costs, some functions can be implemented in different integrated devices and / or chiplets, where different technology nodes can be used to manufacture different integrated devices and / or chiplets to reduce overall costs. For example, functions requiring state-of-the-art technology nodes can be implemented in an integrated device, while functions that can be implemented using less advanced technology nodes can be implemented in another integrated device and / or one or more chiplets. An example of manufacturing using a first technology node (e.g., a state-of-the-art technology node) configured to provide computing applications would be an integrated device, and an example of manufacturing using a second technology node configured to provide additional functionality would be at least one chiplet, where the second technology node is less expensive than the first technology node, and where the second technology node manufactures components with a minimum size greater than the minimum size of components manufactured using the first technology node. Examples of computing applications may include high-performance computing and / or high-performance processing, which can be achieved by manufacturing and packaging as many transistors as possible in an integrated device. This is why an integrated device configured for a computing application can be manufactured using the most advanced technology node available, while other chiplets can be manufactured using less advanced technology nodes, since these chiplets do not require as many transistors to be manufactured in a chiplet. Therefore, compared to using a single integrated device to perform all the functions of the package, using a combination of different technology nodes (which may have different associated yield losses) for different integrated devices and / or chiplets can reduce the overall cost of the package.

[0082] Another advantage of dividing the functions into several integrated devices and / or chiplets is that it allows for improvements in package performance without having to redesign each individual integrated device and / or chiplet.For example, if the package configuration uses a first integrated device and a first chiplet, the performance of the package may be improved by changing the design of the first integrated device while keeping the design of the first chiplet the same. Therefore, the first chiplet can be reused along with the improved and / or differently configured first integrated device. This saves costs when manufacturing a package with an improved integrated device by not having to redesign the first chiplet.

[0083] The package (e.g., 300) may be implemented in a radio frequency (RF) package. The RF package may be a radio frequency front-end (RFFE) package. The package (e.g., 300) may be configured to provide wireless fidelity (WiFi) communication and / or cellular communication (e.g., 2G, 3G, 4G, 5G). The package (e.g., 300) may be configured to support Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), and / or Long Term Evolution (LTE). The package (e.g., 100) may be configured to transmit and receive signals with different frequencies and / or communication protocols.

[0084] Exemplary Steps for Manufacturing a Package Including a Dummy Silicon Structure

[0085] In some embodiments, manufacturing a package includes several processes. Figures 6A to 6E illustrate exemplary steps for providing or manufacturing a package. In some embodiments, the steps of Figures 6A to 6E can be used to provide or manufacture a package (see specification page 11 / 25, 14 CN 121605800 A 300). However, the processes of Figures 6A to 6E can be used to manufacture any package described in this disclosure (e.g., 200).

[0086] It should be noted that the steps of Figures 6A to 6E may combine one or more stages to simplify and / or clarify the steps for providing or manufacturing a package. In some embodiments, the order of the processes may be changed or modified. In some embodiments, one or more of these processes may be substituted or replaced without departing from the scope of this disclosure.

[0087] Phase 1 of FIG6A illustrates the state on the carrier 600 and after the metallization portion 320 is formed on the carrier 600. The carrier 600 may include a glass carrier. The metallization portion 320 includes at least one dielectric layer 322 and a plurality of metallized interconnects 323. In some embodiments, the metallization portion 320 may be a first metallization portion. In some embodiments, the at least one dielectric layer 322 may be at least a first dielectric layer. In some embodiments, the plurality of metallized interconnects 323 may be a first plurality of metallized interconnects. In some embodiments, deposition processes, lamination processes, etching processes (e.g., photolithography), laser processes, exposure processes, development processes, photolithography processes, plating processes, and / or stripping processes may be used to form the metallization portion 320 including at least one dielectric layer 322 and a plurality of metallized interconnects 323.Examples of forming metallized portions are illustrated and described below in at least Figures 10A to 10B.

[0088] Stage 2 of Figure 6A illustrates the state after forming a plurality of pillar interconnects 333 and coupling the plurality of pillar interconnects to the metallized portion 320. The plurality of pillar interconnects 333 may be coupled to the plurality of metallized interconnects 323. The plurality of pillar interconnects 333 may be formed using photolithography, plating, lift-off and / or etching processes. In some specific embodiments, the metallized portion 320 may be optional. In such instances, the plurality of pillar interconnects 333 may be formed and coupled to the carrier 600.

[0089] Stage 3 of Figure 6A illustrates the state after coupling a bridge 306 to the metallized portion 320. The back side of the bridge 306 is coupled to the metallized portion 320 by an adhesive 360. The bridge 306 may include a plurality of pillar interconnects 365. The back side of the bridge (e.g., a silicon bridge) may be one side including a bridge substrate (e.g., a silicon bridge substrate). The front side of the bridge may be one side including bridge interconnects and / or a bridge dielectric layer.

[0090] Phase 3 of FIG6A also illustrates the state after passive devices 304a and 304b are coupled to the metallization portion 320. The back side of passive device 304a may be coupled to the metallization portion 320 via a plurality of solder interconnects 340a. The back side of passive device 304b may be coupled to the metallization portion 320 via a plurality of solder interconnects 340b. Passive device 304a may include a plurality of pillar interconnects 345a. Passive device 304b may include a plurality of pillar interconnects 345b. A solder reflow process may be used to couple passive devices 304a and / or passive devices 304b to the metallization portion 320.

[0091] Phase 4 of FIG6B illustrates the state after the encapsulation layer 332 is formed and coupled to the metallized portion 320. The encapsulation layer 332 may be a first encapsulation layer. The encapsulation layer 332 may include a molding compound, resin, epoxy resin and / or filler. The encapsulation layer 332 may be a component for encapsulation. The encapsulation layer 332 may be provided by using compression and transfer molding processes, sheet molding processes or liquid molding processes. The encapsulation layer 332 may at least partially encapsulate a plurality of pillar interconnects 333, bridges 306, passive devices 304a and / or passive devices 304b, a plurality of pillar interconnects 365, a plurality of pillar interconnects 345a and / or a plurality of pillar interconnects 345b. The encapsulation layer 332 may be overmolded.

[0092] Phase 5 of FIG6B illustrates the state after a portion of the encapsulation layer 332 is removed. The encapsulation layer 332 can be ground to form an encapsulation layer 332 with a flat surface. Portions of multiple pillar interconnects 333 and / or other pillar interconnects (e.g., 345a, 345b, 365) can also be removed. Stage 5 of Figure 6B illustrates the encapsulation portion 330 coupled to the metallized portion 320.

[0093] Phase 6 of FIG6B illustrates the state after a metallization portion 340 is formed on the encapsulation portion 330 and coupled to the encapsulation portion. The metallization portion 340 may be formed on the encapsulation layer 332. The metallization portion 340 includes at least one dielectric layer 342 and a plurality of metallized interconnects 343. In some embodiments, the metallization portion 340 may be a second metallization portion. In some embodiments, at least one dielectric layer 342 may be at least a second dielectric layer. In some embodiments, the plurality of metallized interconnects 343 may be a second plurality of metallized interconnects. The plurality of metallized interconnects 343 may be coupled to a plurality of pillar interconnects 333 and / or other pillar interconnects (e.g., 345a, 345b, 365) in the encapsulation layer 332. In some specific implementations, deposition processes, lamination processes, etching processes (e.g., photolithography), laser processes, exposure processes, development processes, photolithography processes, plating processes, and / or stripping processes can be used to form a metallized portion 340 including at least one dielectric layer 342 and a plurality of metallized interconnects 343. Examples of forming the metallized portion are illustrated and described below in at least Figures 10A to 10B. Stage 6 may illustrate a package interposer 302 including a metallized portion 320, an encapsulation portion 330, and a metallized portion 340. The encapsulation portion 330 may be located between the metallized portion 320 and the metallized portion 340.

[0094] Stage 7 of Figure 6C illustrates the state after the integrated device is coupled to the package interposer 302. The integrated device 303a is coupled to the metallized portion 340 via a plurality of columnar interconnects 331a and a plurality of solder interconnects 334a. The integrated device 303a can be coupled to the metallization portion 340 using a solder reflow process. The integrated device 303b is coupled to the metallization portion 340 via a plurality of columnar interconnects 331b and a plurality of solder interconnects 334b. The integrated device 303b can be coupled to the metallization portion 340 using a solder reflow process. A dummy silicon structure 107 can be coupled to the metallization portion 340 via adhesive 207. In some embodiments, more than one dummy silicon structure 107 may be provided. The dummy silicon structure 107 may be laterally located between the integrated device 303a and the integrated device 303b.

[0095] Stage 8 of FIG6C illustrates the state after the underfill 390 is provided. The underfill 390 may be disposed on the package insert 302. The underfill 390 may be located between (i) the metallization portion 340 and (ii) the integrated device 303a and / or the integrated device 303b. In some implementations, the underfill 390 may include a composite material comprising an epoxy polymer and a filler. The underfill 390 may at least partially encapsulate the dummy silicon structure 107.

[0096] Stage 9 of FIG6D illustrates the state after the encapsulation layer 309 is formed and coupled to the package interposer 302. The encapsulation layer 309 is coupled to the metallization portion 340. The encapsulation layer 309 may include molding material, resin, epoxy resin and / or filler. The encapsulation layer 309 may be a component for encapsulation. The encapsulation layer 309 may be provided by using compression and transfer molding processes, sheet molding processes or liquid molding processes. The encapsulation layer 309 may include a material and / or a different composition than the underlying filler 390. The encapsulation layer 309 may be overmolded and a portion of the encapsulation layer 309 may be removed using a polishing process. The encapsulation layer 309 may at least partially encapsulate the integrated device 303a, integrated device 303b and / or dummy silicon structure 107.

[0097] Stage 10 of FIG6D illustrates the state after the package interposer 302 is decoupled from the carrier 600. The package insert 302 can be detached from the carrier 600.

[0098] Stage 11 of FIG6E illustrates the state after forming a plurality of columnar interconnects 325 and coupling the plurality of columnar interconnects to the metallization portion 320. The plurality of columnar interconnects 325 may be coupled to a plurality of metallization interconnects 323. The plurality of columnar interconnects 325 may be formed using photolithography, plating, stripping and / or etching processes. The plurality of columnar interconnects 325 may be optional.

[0099] Stage 12 of FIG6E illustrates the state after coupling a plurality of solder interconnects 114 to the plurality of columnar interconnects 325. The plurality of columnar interconnects 325 may be coupled using a solder reflow process. In some embodiments, the plurality of solder interconnects 114 may be coupled to a plurality of metallization interconnects 323. Stage 12 of FIG6E may illustrate the package 300.

[0100] Different embodiments may use different processes to form the metal layers and / or interconnects. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form the metal layer.

[0101] Exemplary Flowchart of a Method for Manufacturing a Package Including a Dummy Silicon Structure

[0102] In some embodiments, manufacturing a package includes several processes. FIG7 illustrates an exemplary flowchart of a method 700 for providing or manufacturing a package. In some embodiments, method 700 of FIG7 may be used to provide or manufacture package 300 as described on pages 13 / 25 of this disclosure, CN 121605800 A. However, method 700 may be used to provide or manufacture any package (e.g., 200) described in this disclosure.

[0103] It should be noted that method 700 of FIG7 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a package. In some embodiments, the order of the processes may be changed or modified.

[0104] The method provides (at 705) a carrier and forms a first metallization portion on the carrier. Phase 1 of FIG6A illustrates and describes an example of the state of the carrier 600 and the state after the metallization portion 320 is formed on the carrier 600. The carrier 600 may include a glass carrier. The metallization portion 320 includes at least one dielectric layer 322 and a plurality of metallized interconnects 323. In some embodiments, the metallization portion 320 may be a first metallization portion. In some embodiments, the at least one dielectric layer 322 may be at least a first dielectric layer. In some embodiments, the plurality of metallized interconnects 323 may be a first plurality of metallized interconnects. In some embodiments, deposition processes, lamination processes, etching processes (e.g., photolithography), laser processes, exposure processes, development processes, photolithography processes, plating processes, and / or stripping processes may be used to form the metallization portion 320 including at least one dielectric layer 322 and a plurality of metallized interconnects 323. Examples of forming a metallized portion are illustrated and described below in at least Figures 10A to 10B.

[0105] The method forms (at 710) a plurality of pillar interconnects on the first metallized portion. Stage 2 of Figure 6A illustrates and describes an example of the state after forming the plurality of pillar interconnects 333 and coupling the plurality of pillar interconnects to the metallized portion 320. The plurality of pillar interconnects 333 may be coupled to the plurality of metallized interconnects 323. The plurality of pillar interconnects 333 may be formed using photolithography, plating, lift-off, and / or etching processes. In some specific embodiments, the metallized portion 320 may be optional. In such instances, the plurality of pillar interconnects 333 may be formed and coupled to the carrier 600.

[0106] The method couples at least one bridge and / or at least a passive device (at 715) to the first metallized portion. Stage 3 of Figure 6A illustrates and describes an example of the state after coupling the bridge 306 to the metallized portion 320. The back side of bridge 306 is coupled to metallization portion 320 via adhesive 360. Bridge 306 may include multiple pillar interconnects 365. The back side of the bridge (e.g., a silicon bridge) may be a side including a bridge substrate (e.g., a silicon bridge substrate). The front side of the bridge may be a side including bridge interconnects and / or a bridge dielectric layer. Phase 3 of FIG6A also illustrates and describes an example of the state after passive devices 304a and 304b are coupled to metallization portion 320. The back side of passive device 304a may be coupled to metallization portion 320 via multiple solder interconnects 340a. The back side of passive device 304b may be coupled to metallization portion 320 via multiple solder interconnects 340b. Passive device 304a may include multiple pillar interconnects 345a. Passive device 304b may include multiple pillar interconnects 345b. The passive device 304a and / or the passive device 304b can be coupled to the metallized portion 320 using a solder reflow process.

[0107] The method forms a first encapsulation layer (at 720) over the first metallized portion. Phase 4 of FIG6B illustrates and describes an example of the state after the encapsulation layer 332 is formed and coupled to the metallized portion 320. The encapsulation layer 332 may be the first encapsulation layer. The encapsulation layer 332 may include molding material, resin, epoxy resin and / or filler. The encapsulation layer 332 may be a component for encapsulation. The encapsulation layer 332 may be provided by using compression and transfer molding processes, sheet molding processes or liquid molding processes. The encapsulation layer 332 may at least partially encapsulate a plurality of pillar interconnects 333, bridges 306, passive devices 304a and / or passive devices 304b, a plurality of pillar interconnects 365, a plurality of pillar interconnects 345a and / or a plurality of pillar interconnects 345b. The encapsulation layer 332 may be overmolded. Forming the first encapsulation layer may include removing a portion of the first encapsulation layer. Phase 5 of Figure 6B illustrates and describes an example of a state where a portion of the encapsulation layer 332 has been removed. The encapsulation layer 332 may be ground to form an encapsulation layer 332 with a flat surface. Portions of multiple pillar interconnects 333 and / or other pillar interconnects may also be removed. Phase 5 of Figure 6B may illustrate an encapsulation portion 330 coupled to a metallization portion 320.

[0108] The method forms a second metallization (at 725) over the encapsulation portion. Phase 6 of Figure 6B illustrates and describes an example of a state after a metallization portion 340 has been formed over the encapsulation portion 330 and coupled to the encapsulation portion. (Pages 14 / 25, CN 121605800 A) The metallization portion 340 may be formed over the encapsulation layer 332. The metallization portion 340 includes at least one dielectric layer 342 and multiple metallized interconnects 343. In some specific embodiments, the metallization portion 340 may be a second metallization portion. In some embodiments, at least one dielectric layer 342 may be at least a second dielectric layer. In some embodiments, a plurality of metallized interconnects 343 may be a second plurality of metallized interconnects. The plurality of metallized interconnects 343 may be coupled to a plurality of pillar interconnects 333 and / or other pillar interconnects in the encapsulation layer 332. In some embodiments, deposition processes, lamination processes, etching processes (e.g., photolithography), laser processes, exposure processes, development processes, photolithography processes, plating processes, and / or lift-off processes may be used to form a metallized portion 340 including at least one dielectric layer 342 and a plurality of metallized interconnects 343. Examples of forming a metallized portion are illustrated and described below in at least Figures 10A to 10B. Stage 6 may illustrate a package insert 302 including a metallized portion 320, an encapsulation portion 330, and a metallized portion 340. The encapsulation portion 330 may be located between the metallized portion 320 and the metallized portion 340.

[0109] This method places and couples (at 730) an integrated device, memory die, and / or dummy silicon structure to a second metallization portion. Stage 7 of FIG6C illustrates and describes an example of the state after the integrated device is coupled to the package interposer 302. Integrated device 303a is coupled to metallization portion 340 via a plurality of pillar interconnects 331a and a plurality of solder interconnects 334a. Solder reflow process can be used to couple integrated device 303a to metallization portion 340. Integrated device 303b is coupled to metallization portion 340 via a plurality of pillar interconnects 331b and a plurality of solder interconnects 334b. Solder reflow process can be used to couple integrated device 303b to metallization portion 340. Dummy silicon structure 107 can be coupled to metallization portion 340 via adhesive 207. In some embodiments, more than one dummy silicon structure 107 may be provided. The dummy silicon structure 107 may be laterally located between integrated devices 303a and 303b.

[0110] The method provides and forms (at 735) an underfill. Stage 8 of FIG6C illustrates and describes an example of the state after the underfill 390 is provided. The underfill 390 may be disposed on the package interposer 302. The underfill 390 may be located between (i) the metallization portion 340 and (ii) the integrated devices 303a and / or 303b. In some specific embodiments, the underfill 390 may comprise a composite material comprising an epoxy polymer and a filler. The underfill 390 may at least partially encapsulate the dummy silicon structure 107.

[0111] The method forms (at 740) a second encapsulation layer. Stage 9 of FIG6D illustrates and describes an example of the state after the encapsulation layer 309 is formed and coupled to the package interposer 302. The encapsulation layer 309 is coupled to the metallization portion 340. Encapsulation layer 309 may include molding material, resin, epoxy resin, and / or filler. Encapsulation layer 309 may be a component for encapsulation. Encapsulation layer 309 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes. Encapsulation layer 309 may include a material and / or a different composition than the underlying filler 390. Encapsulation layer 309 may be overmolded, and a portion of encapsulation layer 309 may be removed using a polishing process. Encapsulation layer 309 may at least partially encapsulate integrated device 303a, integrated device 303b, and / or dummy silicon structure 107.

[0112] This method decouples (at 745) the carrier. Stage 10 of FIG6D illustrates and describes an example of the state after the package interposer 302 is decoupled from the carrier 600. Package interposer 302 may detach from the carrier 600.

[0113] This method forms (at 750) a plurality of columnar interconnects and solder interconnects. Phase 11 of FIG6E illustrates and describes an example of the state after the plurality of columnar interconnects 325 are formed and coupled to the metallization portion 320.Multiple columnar interconnects 325 may be coupled to multiple metallized interconnects 323. Multiple columnar interconnects 325 may be formed using photolithography, plating, stripping, and / or etching processes. Multiple columnar interconnects 325 may be optional.

[0114] Stage 12 of FIG6E illustrates and describes an example of the state after multiple solder interconnects 114 are coupled to multiple columnar interconnects 325. Solder reflow processes may be used to couple multiple columnar interconnects 325. In some embodiments, multiple solder interconnects 114 may be coupled to multiple metallized interconnects 323. Stage 12 of FIG6E may illustrate package 300. Specification 15 / 25 pages 18 CN 121605800 A

[0115] Different embodiments may use different processes to form the metal layers and / or interconnects. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form the metal layer.

[0116] Exemplary Steps for Manufacturing Packages Including Dummy Silicon Structures

[0117] In some embodiments, manufacturing a package includes several processes. Figures 8A through 8E illustrate exemplary steps for providing or manufacturing a package. In some embodiments, the steps of Figures 8A through 8E may be used to provide or manufacture package 400. However, the processes of Figures 8A through 8E may be used to manufacture any package (e.g., 100) described in this disclosure.

[0118] It should be noted that the steps of Figures 8A through 8E may be combined in one or more stages to simplify and / or clarify the steps for providing or manufacturing a package. In some embodiments, the order of the processes may be changed or modified. In some embodiments, one or more of these processes may be substituted or replaced without departing from the scope of this disclosure.

[0119] Phase 1 of FIG8A illustrates the state of the carrier 800 and the state after multiple integrated devices are placed on the carrier 800. Multiple integrated devices may be coupled to the carrier 800 via one or more adhesives. The back side of integrated device 303a is placed and / or coupled to the carrier 800. Integrated device 303a may include multiple columnar interconnects 331a. The back side of integrated device 303b is placed and / or coupled to the carrier 800. Integrated device 303b may include multiple columnar interconnects 331b. A dummy silicon structure 107 may be coupled to the carrier 800. An adhesive may be used to couple the dummy silicon structure 107 to the carrier 800. In some embodiments, more than one dummy silicon structure 107 may be provided. The dummy silicon structure 107 may be laterally located between integrated devices 303a and 303b.

[0120] Figure 8A, stage 2, illustrates the state after the encapsulation layer 309 is formed and coupled to the carrier 800, the integrated device 303a, the integrated device 303b and the dummy silicon structure 107.Encapsulation layer 309 may include molding material, resin, epoxy resin, and / or filler. Encapsulation layer 309 may be a component for encapsulation. Encapsulation layer 309 may be provided by using compression and transfer molding processes, sheet molding processes, or liquid molding processes. Encapsulation layer 309 may be overmolded. Encapsulation layer 309 may at least partially encapsulate dummy silicon structure 107, integrated device 303a, integrated device 303b, multiple columnar interconnects 331a and / or multiple columnar interconnects 331b.

[0121] Stage 3 of FIG8A illustrates the state after a portion of encapsulation layer 309 has been removed. A polishing process may be used to remove a portion of encapsulation layer 309. In some embodiments, portions of columnar interconnects (e.g., 331a, 331b) and / or portions of dummy silicon structure 107, integrated device 303a and / or integrated device 303b may also be removed.

[0122] Phase 4 of FIG8B illustrates the state after the metallization portion 440 is formed and coupled to the encapsulation layer 309. The metallization portion 440 includes at least one dielectric layer 442 and a plurality of metallized interconnects 443. In some embodiments, the metallization portion 440 may be a first metallization portion. In some embodiments, the at least one dielectric layer 442 may be at least a first dielectric layer. In some embodiments, the plurality of metallized interconnects 443 may be a first plurality of metallized interconnects. In some embodiments, deposition processes, lamination processes, etching processes (e.g., photolithography), laser processes, exposure processes, development processes, photolithography processes, plating processes, and / or lift-off processes may be used to form the metallization portion 440 including at least one dielectric layer 442 and a plurality of metallized interconnects 443. Examples of forming metallization portions are illustrated and described below in at least FIG10A to FIG10B.

[0123] Stage 5 of FIG8B illustrates the state after forming a plurality of pillar interconnects 433 and coupling the plurality of pillar interconnects to the metallization portion 440. The plurality of pillar interconnects 433 may be coupled to a plurality of metallization interconnects 443. The plurality of pillar interconnects 433 may be formed using photolithography, plating, lift-off and / or etching processes.

[0124] Stage 6 of FIG8B illustrates the state after coupling the bridge 306 to the metallization portion 440. The front side of the bridge 306 is coupled to the metallization portion 440 via a plurality of pillar interconnects 365 and / or a plurality of solder interconnects 367. The bridge may include a front side and a back side. The back side of the bridge (e.g., a silicon bridge) may be the side including the bridge substrate (e.g., a silicon bridge substrate). The front side of the bridge may be the side including the bridge interconnects and / or the bridge dielectric layer. The bridge 306 can be coupled to the metallized portion 440 using a solder reflow process.

[0125] Phase 6 of FIG8B also illustrates the state after passive devices 404a and 404b are coupled to the metallized portion 440. The front side of passive device 404a may be coupled to the metallized portion 440 via a plurality of pillar interconnects 445a and / or a plurality of solder interconnects 447a. The front side of passive device 404b may be coupled to the metallized portion 440 via a plurality of pillar interconnects 445b and / or a plurality of solder interconnects 447b. A solder reflow process may be used to couple passive devices 404a and / or passive devices 404b to the metallized portion 440.

[0126] Phase 7 of FIG8C illustrates the state after encapsulation layer 432 is formed and coupled to the metallized portion 440. Encapsulation layer 432 may be a second encapsulation layer. Encapsulation layer 432 may include molding material, resin, epoxy resin and / or filler. Encapsulation layer 432 may be a component for encapsulation. Encapsulation layer 432 may be provided by using compression and transfer molding processes, sheet molding processes, or liquid molding processes. Encapsulation layer 432 may at least partially encapsulate a plurality of post interconnects 433, bridges 306, passive devices 404a, and / or passive devices 404b. Encapsulation layer 432 may be overmolded. Encapsulation layer 432 may at least partially encapsulate a plurality of post interconnects 365, a plurality of interconnects 448a (e.g., post interconnects), a plurality of interconnects 448b (e.g., post interconnects), a plurality of solder interconnects 367, a plurality of solder interconnects 447a, and / or a plurality of solder interconnects 447b.

[0127] Stage 8 of FIG8C illustrates a state in which a portion of encapsulation layer 432 is removed. Encapsulation layer 432 may be ground to form encapsulation layer 432 having a flat surface. Portions of multiple post interconnects 433 and / or other post interconnects (e.g., 448a, 448b) may also be removed. Stage 8 may exemplify an encapsulation portion 430 including an encapsulation layer 432, multiple post interconnects 433, at least one bridge, and at least one passive device. Stage 8 of FIG8C illustrates an encapsulation portion 430 coupled to a metallization portion 440.

[0128] Stage 9 of FIG8D illustrates the state after a metallization portion 420 is formed over the encapsulation portion 430 and the metallization portion is coupled to the encapsulation portion. The metallization portion 420 may be formed over the encapsulation layer 432. The metallization portion 420 includes at least one dielectric layer 422 and multiple metallization interconnects 423. In some embodiments, the metallization portion 420 may be a second metallization portion. In some embodiments, at least one dielectric layer 422 may be at least a second dielectric layer. In some embodiments, multiple metallization interconnects 423 may be a second plurality of metallization interconnects. Multiple metallized interconnects 423 may be coupled to and contact multiple pillar interconnects 433 and / or other pillar interconnects (e.g., 448a, 448b) in the encapsulation layer 432.In some specific implementations, deposition processes, lamination processes, etching processes (e.g., photolithography), laser processes, exposure processes, development processes, photolithography processes, plating processes, and / or stripping processes can be used to form a metallized portion 420 including at least one dielectric layer 422 and a plurality of metallized interconnects 423. Stage 9 may illustrate a package insert 402 including a metallized portion 420, an encapsulation portion 430, and a metallized portion 440. The encapsulation portion 430 may be located between the metallized portion 420 and the metallized portion 440. Examples of forming metallized portions are illustrated and described below in at least Figures 10A to 10B.

[0129] Stage 10 of Figure 8D illustrates the state after a plurality of columnar interconnects 425 have been formed and coupled to the metallized portion 420. The plurality of columnar interconnects 425 may be coupled to a plurality of metallized interconnects 423. Multiple columnar interconnects 425 can be formed using photolithography, plating, stripping, and / or etching processes. The multiple columnar interconnects 425 can be optional. In some embodiments, the metallization portion 420 can be optional. In such instances, multiple columnar interconnects 425 can be formed and coupled to multiple columnar interconnects 433.

[0130] Stage 11 of FIG8E illustrates the state after multiple solder interconnects 114 are coupled to multiple columnar interconnects 425. Solder reflow processes can be used to couple the multiple columnar interconnects 425. In some embodiments, multiple solder interconnects 114 can be coupled to multiple metallized interconnects 423.

[0131] Stage 12 of FIG8E illustrates the state after the package insert 402 is decoupled from the carrier 800. The package insert 402 can be detached from the carrier 800. Stage 12 of FIG8E can illustrate the package 400. Specification 17 / 25 pages 20 CN 121605800 A

[0132] Different embodiments may use different processes to form metal layers and / or interconnects. In some embodiments, chemical vapor deposition (CVD) processes, physical vapor deposition (PVD) processes, sputtering processes, spraying processes, and / or plating processes may be used to form metal layers.

[0133] Exemplary flowchart of a method for manufacturing a package including a dummy silicon structure

[0134] In some embodiments, manufacturing a package includes several processes. FIG9 illustrates an exemplary flowchart of a method 900 for providing or manufacturing a package. In some embodiments, method 900 of FIG9 may be used to provide or manufacture package 400 described in this disclosure. However, method 900 may be used to provide or manufacture any package (e.g., 100) described in this disclosure.

[0135] It should be noted that method 900 of FIG9 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a package. In some specific implementations, the order of the processes can be changed or improved.

[0136] The method provides a carrier (at 905) and places an integrated device and a dummy silicon structure (at 905) on the carrier. Phase 1 of FIG8A illustrates and describes an example of the state of the carrier 800 and the state after multiple integrated devices are placed on the carrier 800. Multiple integrated devices may be coupled to the carrier 800 by one or more adhesives. The back side of integrated device 303a is placed and / or coupled to the carrier 800. Integrated device 303a may include multiple columnar interconnects 331a. The back side of integrated device 303b is placed and / or coupled to the carrier 800. Integrated device 303b may include multiple columnar interconnects 331b. Dummy silicon structure 107 may be coupled to the carrier 800. Adhesives may be used to couple dummy silicon structure 107 to the carrier 800. In some specific embodiments, more than one dummy silicon structure 107 may be provided. Dummy silicon structure 107 may be laterally located between integrated device 303a and integrated device 303b.

[0137] This method forms a first encapsulation layer (at 910) over an integrated device, a dummy silicon structure, and / or a memory die. Phase 2 of FIG8A illustrates and describes an example of the state after the encapsulation layer 309 is formed and coupled to the carrier 800, integrated device 303a, integrated device 303b, and dummy silicon structure 107. The encapsulation layer 309 may include molding material, resin, epoxy resin, and / or filler. The encapsulation layer 309 may be a component for encapsulation. The encapsulation layer 309 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes. The encapsulation layer 309 may be overmolded. The encapsulation layer 309 may at least partially encapsulate the dummy silicon structure 107, integrated device 303a, integrated device 303b, a plurality of columnar interconnects 331a, and / or a plurality of columnar interconnects 331b. Forming the encapsulation layer may include removing portions of the encapsulation layer. Phase 3 of Figure 8A illustrates and describes an example of the state after a portion of the encapsulation layer 309 has been removed. A polishing process can be used to remove a portion of the encapsulation layer 309. In some embodiments, portions of the columnar interconnects (e.g., 331a, 331b) and / or portions of the dummy silicon structure 107, integrated device 303a, and / or integrated device 303b may also be removed.

[0138] This method forms (at 915) a first metallization portion coupled to the encapsulation layer. Phase 4 of Figure 8B illustrates and describes an example of the state after the metallization portion 440 has been formed and coupled to the encapsulation layer 309. The metallization portion 440 includes at least one dielectric layer 442 and a plurality of metallized interconnects 443. In some embodiments, the metallization portion 440 may be a first metallization portion. In some embodiments, at least one dielectric layer 442 may be at least a first dielectric layer. In some embodiments, the plurality of metallized interconnects 443 may be a first plurality of metallized interconnects.In some specific implementations, deposition processes, lamination processes, etching processes (e.g., photolithography), laser processes, exposure processes, development processes, photolithography processes, plating processes, and / or stripping processes can be used to form a metallized portion 440 comprising at least one dielectric layer 442 and a plurality of metallized interconnects 443. Examples of forming the metallized portion are illustrated and described below in at least Figures 10A to 10B.

[0139] This method forms (at 920) a plurality of pillar interconnects coupled to the first metallized portion. Stage 5 of Figure 8B illustrates and describes an example of the state after the plurality of pillar interconnects 433 are formed and coupled to the plurality of pillar interconnects 440. The plurality of pillar interconnects 433 may be coupled to the plurality of metallized interconnects 443. Photolithography processes, plating processes, stripping processes, and / or etching processes can be used to form the plurality of pillar interconnects 433.

[0140] This method couples the bridge and passive device (at 925) to the first metallization portion. Stage 6 of FIG8B illustrates and describes an example of the state after the bridge 306 is coupled to the metallization portion 440. The front side of the bridge 306 is coupled to the metallization portion 440 via a plurality of pillar interconnects 365 and / or a plurality of solder interconnects 367. The bridge may include a front side and a back side. The back side of the bridge (e.g., a silicon bridge) may be a side including a bridge substrate (e.g., a silicon bridge substrate). The front side of the bridge may be a side including bridge interconnects and / or a bridge dielectric layer. A solder reflow process may be used to couple the bridge 306 to the metallization portion 440.

[0141] Stage 6 of FIG8B also illustrates and describes an example of the state after the passive devices 404a and 404b are coupled to the metallization portion 440. The front side of passive device 404a can be coupled to metallized portion 440 via multiple post interconnects 445a and / or multiple solder interconnects 447a. The front side of passive device 404b can be coupled to metallized portion 440 via multiple post interconnects 445b and / or multiple solder interconnects 447b. A solder reflow process can be used to couple passive device 404a and / or passive device 404b to metallized portion 440.

[0142] This method forms a second encapsulation layer (at 930) on top of the first metallized portion. Phase 7 of FIG8C illustrates and describes an example of the state after encapsulation layer 432 is formed and coupled to metallized portion 440. Encapsulation layer 432 may be a second encapsulation layer. Encapsulation layer 432 may include molding material, resin, epoxy resin and / or filler. Encapsulation layer 432 may be a component for encapsulation. Encapsulation layer 432 can be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes. Encapsulation layer 432 can at least partially encapsulate multiple post interconnects 433, bridges 306, passive devices 404a, and / or passive devices 404b.Encapsulation layer 432 may be overmolded. Encapsulation layer 432 may at least partially encapsulate a plurality of pillar interconnects 365, a plurality of interconnects 448a (e.g., pillar interconnects), a plurality of interconnects 448b (e.g., pillar interconnects), a plurality of solder interconnects 367, a plurality of solder interconnects 447a and / or a plurality of solder interconnects 447b. Forming the encapsulation layer may include removing portions of the encapsulation layer. Stage 8 of FIG8C illustrates and describes an example of a state in which a portion of the encapsulation layer 432 has been removed. Encapsulation layer 432 may be ground to form an encapsulation layer 432 having a flat surface. Portions of a plurality of pillar interconnects 433 and / or other pillar interconnects (e.g., 448a, 448b) may also be removed. Stage 8 may illustrate an encapsulation portion 430 including encapsulation layer 432, a plurality of pillar interconnects 433, at least one bridge and at least one passive device. Stage 8 of FIG8C illustrates an encapsulation portion 430 coupled to a metallized portion 440.

[0143] This method forms (at 935) a second metallization portion coupled to the encapsulation portion. Stage 9 of FIG8D illustrates and describes an example of the state after forming a metallization portion 420 over the encapsulation portion 430 and coupling the metallization portion to the encapsulation portion. The metallization portion 420 may be formed over the encapsulation layer 432. The metallization portion 420 includes at least one dielectric layer 422 and a plurality of metallized interconnects 423. In some embodiments, the metallization portion 420 may be a second metallization portion. In some embodiments, at least one dielectric layer 422 may be at least a second dielectric layer. In some embodiments, the plurality of metallized interconnects 423 may be a second plurality of metallized interconnects. The plurality of metallized interconnects 423 may be coupled to and contact a plurality of pillar interconnects 433 and / or other pillar interconnects (e.g., 448a, 448b) in the encapsulation layer 432. In some specific implementations, deposition processes, lamination processes, etching processes (e.g., photolithography), laser processes, exposure processes, development processes, photolithography processes, plating processes, and / or stripping processes can be used to form a metallized portion 420 including at least one dielectric layer 422 and a plurality of metallized interconnects 423. Stage 9 may illustrate a package insert 402 including a metallized portion 420, an encapsulation portion 430, and a metallized portion 440. The encapsulation portion 430 may be located between the metallized portion 420 and the metallized portion 440. Examples of forming metallized portions are illustrated and described below in at least Figures 10A to 10B.

[0144] This method forms (at 940) a plurality of columnar interconnects and / or a plurality of solder interconnects. Figure 8D, stage 10, illustrates and describes an example of the state after forming a plurality of columnar interconnects 425 and coupling the plurality of columnar interconnects to the metallized portion 420, as described on page 22 of the specification (CN 121605800 A, page 19 / 25). The plurality of columnar interconnects 425 may be coupled to a plurality of metallized interconnects 423.Multiple columnar interconnects 425 can be formed using photolithography, plating, stripping, and / or etching processes. The multiple columnar interconnects 425 may be optional. In some embodiments, the metallization portion 420 may be optional. In such instances, multiple columnar interconnects 425 may be formed and coupled to multiple columnar interconnects 433. Stage 11 of FIG8E illustrates and describes an example of the state after multiple solder interconnects 114 are coupled to multiple columnar interconnects 425. Solder reflow processes can be used to couple the multiple columnar interconnects 425. In some embodiments, multiple solder interconnects 114 may be coupled to multiple metallized interconnects 423.

[0145] This method decouples the package interposer (at 945) from the carrier. Stage 12 of FIG8E illustrates and describes an example of the state after the package interposer 402 is decoupled from the carrier 800. The package interposer 402 can be detached from the carrier 800. Phase 12 of FIG8E may exemplify package 400.

[0146] Exemplary Processes for Manufacturing Metallized Parts

[0147] In some embodiments, manufacturing a substrate includes several processes. FIG10A and FIG10B illustrate exemplary processes for providing or manufacturing metallized parts. In some embodiments, the processes of FIG10A and FIG10B may be used to provide or manufacture metallized part 102. However, the processes of FIG10A and FIG10B may be used to manufacture any metallized part described in this disclosure.

[0148] It should be noted that the processes of FIG10A and FIG10B may combine one or more phases to simplify and / or clarify the processes for providing or manufacturing metallized parts. In some embodiments, the order of the processes may be changed or modified. In some embodiments, one or more of these processes may be substituted or replaced without departing from the scope of this disclosure.

[0149] As shown in FIG10A, Phase 1 illustrates the state after the carrier 1000 is provided. A seed layer 1001 may be located on a carrier 1000. The carrier 1000 may be replaced by other components and / or materials.

[0150] Stage 2 illustrates the state after the formation of a plurality of interconnects 1012. The interconnects 1012 may be located on the seed layer 1001. The plurality of interconnects 1012 may be formed using photolithography, plating, lift-off, and / or etching processes. The interconnects 1012 may represent at least some of the interconnects from a plurality of metallized interconnects 123.

[0151] Stage 3 illustrates the state after the formation of a dielectric layer 1010 on the carrier 1000, the seed layer 1001, and the plurality of interconnects 1012. The dielectric layer 1010 may be formed using deposition and / or lamination processes. The dielectric layer 1010 may include a prepreg and / or polyimide. The dielectric layer 1010 may include a photoimageable dielectric. However, different materials may be used for the dielectric layer in different embodiments.

[0152] Stage 4 illustrates the state after forming a plurality of cavities 1013 in the dielectric layer 1010. The plurality of cavities 1013 can be formed using etching processes (e.g., photolithography), laser processes, exposure processes, and / or development processes.

[0153] Stage 5 illustrates the state after forming interconnects 1022 in and over the dielectric layer 1010 (including in and over the plurality of cavities 1013). For example, vias, pads, and / or traces can be formed. Interconnects can be formed using photolithography, plating, stripping, and / or etching processes.

[0154] As shown in FIG10B, Stage 6 illustrates the state after forming a dielectric layer 1020 over the dielectric layer 1010 and the plurality of interconnects 1022. The dielectric layer 1020 can be formed using deposition processes and / or lamination processes. The dielectric layer 1020 may include prepreg and / or polyimide. The dielectric layer 1020 may include a photoimageable dielectric. However, different materials may be used for the dielectric layer in different embodiments.

[0155] Stage 7 illustrates the state after a plurality of cavities 1023 have been formed in the dielectric layer 1040. The dielectric layer 1040 may represent dielectric layer 1010 and / or dielectric layer 1020. The plurality of cavities 1023 may be formed using etching processes (e.g., photolithography, page 20 / 25, CN 121605800 A), laser processes, exposure processes, and / or development processes.

[0156] Stage 8 illustrates the state after interconnects 1032 have been formed in and over the dielectric layer 1040 (including in and over the plurality of cavities 1023). For example, vias, pads, and / or traces may be formed. Interconnects may be formed using photolithography, plating, stripping, and / or etching processes.

[0157] Different processes may be used to form the metal layer and / or interconnects in different embodiments. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes can be used to form the metal layer.

[0158] Exemplary Flowchart of a Method for Manufacturing a Metallized Part

[0159] In some embodiments, manufacturing a substrate includes several processes. FIG11 illustrates an exemplary flowchart of a method 1100 for providing or manufacturing a metallized part. In some embodiments, the method 1100 of FIG11 can be used to provide or manufacture the metallized part of this disclosure. For example, the method 1100 of FIG11 can be used to manufacture the metallized part 102.

[0160] It should be noted that the method 1100 of FIG11 can combine one or more processes to simplify and / or clarify the method for providing or manufacturing a metallized part. In some embodiments, the order of the processes can be changed or modified.

[0161] The method provides (at 1105) a carrier having a seed layer.Phase 1 of Figure 10A illustrates and describes an example of the state after the carrier 1000 is provided. A seed layer 1001 may be located on the carrier 1000. The carrier 1000 may be replaced by other components and / or materials.

[0162] The method forms and patterns (at 1110) a plurality of interconnects. Phase 2 of Figure 10A illustrates and describes an example of the state after the formation of a plurality of interconnects 1012. Interconnects 1012 may be located on the seed layer 1001. A plurality of interconnects 1012 may be formed using photolithography, plating, lift-off and / or etching processes. Interconnects 1012 may represent at least some of the interconnects from a plurality of metallized interconnects 123.

[0163] The method forms (at 1110) a dielectric layer. Phase 3 of Figure 10A illustrates and describes an example of the state after the formation of the dielectric layer 1010 on the carrier 1000, the seed layer 1001 and the plurality of interconnects 1012. The dielectric layer 1010 can be formed using deposition and / or lamination processes. The dielectric layer 1010 may include prepreg and / or polyimide. The dielectric layer 1010 may include a photoimageable dielectric. However, different materials may be used for the dielectric layer in different embodiments.

[0164] This method forms (at 1120) a plurality of interconnects. Forming the plurality of interconnects may include forming a plurality of cavities in the dielectric layer and performing a plating process. Stage 4 of FIG10A illustrates and describes an example of the state after the plurality of cavities 1013 are formed in the dielectric layer 1010. The plurality of cavities 1013 may be formed using etching processes (e.g., photolithography), laser processes, exposure processes, and / or development processes.

[0165] Stage 5 of FIG10A illustrates and describes an example of the state after the interconnects 1022 are formed in and over the dielectric layer 1010 (including in and over the plurality of cavities 1013). For example, vias, pads, and / or traces may be formed. Interconnects can be formed using photolithography, plating, lift-off, and / or etching processes.

[0166] This method forms (at 1125) another dielectric layer. Stage 6 of FIG10B illustrates and describes an example of the state after the dielectric layer 1020 is formed over the dielectric layer 1010 and the plurality of interconnects 1022. The dielectric layer 1020 can be formed using deposition and / or lamination processes. The dielectric layer 1020 may include a prepreg and / or polyimide. The dielectric layer 1020 may include a photoimageable dielectric. However, different materials may be used for the dielectric layer in different embodiments.

[0167] This method forms (at 1130) a plurality of interconnects. Forming the plurality of interconnects may include forming a plurality of cavities in the dielectric layer and performing a plating process. Stage 7 of FIG10B illustrates and describes an example of the state after the plurality of cavities 1023 are formed in the dielectric layer 1040. Dielectric layer 1040 may represent dielectric layer 1010 and / or dielectric layer 1020.Multiple cavities 1023 can be formed using etching processes (e.g., photolithography), laser processes, exposure processes, and / or development processes. Specification 21 / 25 pages 24 CN 121605800 A

[0168] Phase 8 of FIG10B illustrates and describes an example of the state after interconnects 1032 are formed in and over the dielectric layer 1040 (including in and over the multiple cavities 1023). For example, vias, pads, and / or traces can be formed. Interconnects can be formed using photolithography, plating, stripping, and / or etching processes.

[0169] Different embodiments may use different processes to form metal layers and / or interconnects. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form metal layers.

[0170] Exemplary Electronic Devices

[0171] FIG12 illustrates various electronic devices that may integrate any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, stacked packages (PoP), system-in-packages (SiP), or system-on-a-chip (SoC). For example, mobile phone device 1202, laptop computer device 1204, fixed-location terminal device 1206, wearable device 1208, or motor vehicle 1210 may include device 1200 as described herein. For example, device 1200 may be any of the devices and / or integrated circuit (IC) packages described herein. Devices 1202, 1204, 1206, and 1208 and vehicle 1210 illustrated in FIG12 are merely exemplary. Other electronic devices may also be characterized as device 1200, including but not limited to a group of devices (e.g., electronic devices) including: mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device or any combination thereof that stores or retrieves data or computer instructions.

[0172] One or more of the components, processes, features and / or functions illustrated in Figures 1 to 5, Figures 6A to 6E, Figure 7, Figures 8A to 8E, Figure 9, Figures 10A to 10B and Figures 11 to 12 may be rearranged and / or combined into a single component, process, feature or function, or may be implemented in several components, processes or functions.Additional components, assemblies, processes, and / or functions may be added without departing from this disclosure. It should also be noted that Figures 1-5, 6A-6E, 7, 8A-8E, 9, 10A-10B, and 11-12, and their corresponding descriptions in this disclosure, are not limited to bare dies and / or ICs. In some embodiments, Figures 1-5, 6A-6E, 7, 8A-8E, 9, 10A-10B, and 11-12, and their corresponding descriptions, may be used to manufacture, create, provide, and / or produce equipment and / or integrated equipment. In some embodiments, equipment may include bare dies, integrated devices, integrated passive devices (IPDs), bare die packages, integrated circuit (IC) devices, device packages, integrated circuit (IC) packages, wafers, semiconductor devices, stacked package (PoP) devices, thermal devices, and / or interposers.

[0173] It should be noted that the accompanying drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all components and / or parts are shown for clarity. In some instances, the positioning, location, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some specific embodiments, the various components and / or parts in the drawings may be optional.

[0174] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any specific embodiment or aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupling” is used herein to refer to direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is physically in contact with object B, and object B is in contact with object C, then objects A and C can still be considered coupled to each other, even if they are not in direct physical contact. Object A coupled to object B may be coupled to at least a portion of object B. The term “electrical coupling” may mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can flow between the two objects. The two electrically coupled objects may or may not have current flowing between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything above the fourth) is arbitrary. Any component described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component may be a first component, a second component, a third component, or a fourth component.The terms “encapsulate,” “encapsulate,” and / or any derivative meaning that an object may partially or completely encapsulate another object. The terms “top” and “bottom” are arbitrary. A component located at the top may be located above a component located at the bottom. A top component may be considered a bottom component, and vice versa. As described in this disclosure, a first component located “above” a second component may mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component may be located above (e.g., above) a first surface of the second component, while a third component may be located above (e.g., below) a second surface of the second component, where the second surface is opposite the first surface. It should also be noted that the term “above,” as used in this application in the context of one component being above another, may be used to mean that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Therefore, for example, "above the second component" can mean: (1) the first component is above the second component but does not directly contact the second component; (2) the first component is above the second component (e.g., on the surface of the second component); and / or (3) the first component is within the second component (e.g., embedded in the second component). A first component located "in" the second component can be partially or completely located within the second component. Values ​​from about X to XX can mean values ​​between X and XX, including both X and XX. Values ​​between X and XX can be discrete or continuous. The terms "about 'value X'" or "approximately value X" as used in this disclosure mean within 10 percent of "value X". For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1. "A plurality of" components can include all possible components or only some components from all possible components. For example, if the device includes ten components, the use of the term "a plurality of components" can refer to all ten components or only some components from the ten components.

[0175] In some embodiments, an interconnect is an element or assembly in a device or package that allows or facilitates an electrical connection between two points, elements, and / or components. In some embodiments, an interconnect may include traces (e.g., trace interconnects), vias (e.g., via interconnects), pads (e.g., pad interconnects), pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some embodiments, an interconnect may include a conductive material configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or assembly. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. A seed layer may be considered part of an interconnect. An interconnect may be part of a circuit. Different embodiments may use different processes and / or steps to form interconnects.In some specific implementations, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes can be used to form interconnects.

[0176] It should also be noted that the various disclosures contained herein can be described as processes depicted as operation diagrams, flowcharts, structural diagrams, or block diagrams. Although flowcharts may describe operations as sequential processes, many operations within an operation can be performed in parallel or concurrently. Furthermore, the order of operations can be rearranged. A process terminates when its operations are completed.

[0177] Further examples are described below to facilitate understanding of the invention.

[0178] Aspect 1: A package comprising: an interposer; a first integrated device coupled to the interposer; a second integrated device coupled to the interposer; a dummy silicon structure laterally located between the first integrated device and the second integrated device; and a second encapsulation layer coupled to the interposer, wherein the encapsulation layer at least partially encapsulates the first integrated device, the second integrated device, and the dummy silicon structure. The interposer includes a first metallized portion; a second metallized portion; a first passive device located between the first metallized portion and the second metallized portion; and a first encapsulation layer located between the first metallized portion and the second metallized portion.

[0179] Aspect 2: The package according to Aspect 1, wherein the dummy silicon structure is coupled to the interposer by an adhesive.

[0180] Aspect 3: The package according to aspects 1 to 2, wherein the dummy silicon structure is configured to have no electrical connection to the first integrated device and / or the second integrated device.

[0181] Aspect 4: The package according to aspects 1 to 3, wherein the package interposer further includes a second dummy silicon structure laterally located between the first integrated device and the second integrated device.

[0182] Aspect 5: The package according to aspects 1 to 4, wherein the dummy silicon structure is positioned adjacent to (i) the edge of the first integrated device including a die-to-die portion and (ii) the edge of the second integrated device including a die-to-die portion.

[0183] Aspect 6: The package according to aspects 1 to 5, wherein the first integrated device is coupled to the package interposer via a first plurality of columnar interconnects and / or a first plurality of solder interconnects, and wherein the second integrated device is coupled to the package interposer via a second plurality of columnar interconnects and / or a second plurality of solder interconnects.

[0184] Aspect 7: The package according to aspects 1 to 6, wherein the first integrated device is coupled to the first metallized portion of the package interposer, and wherein the second integrated device is coupled to the first metallized portion of the package interposer.

[0185] Aspect 8: The package according to aspects 1 to 6, wherein the first integrated device is coupled to the second metallized portion of the package interposer, and wherein the second integrated device is coupled to the second metallized portion of the package interposer.

[0186] Aspect 9: The package according to aspects 1 to 8, wherein the first passive device includes a trench capacitor device.

[0187] Aspect 10: The package according to aspects 1 to 9, wherein the package interposer further includes a second passive device, wherein the first passive device is configured to be electrically coupled to the first integrated device, and wherein the second passive device is configured to be electrically coupled to the second integrated device.

[0188] Aspect 11: The package according to aspects 1 to 10, wherein the package interposer further includes a bridge located between the first metallized portion and the second metallized portion.

[0189] Aspect 12: The package according to aspect 11, wherein the electrical path between the first integrated device and the second integrated device includes the bridge.

[0190] Aspect 13: The package according to aspect 11, wherein the electrical path between the first integrated device and the second integrated device includes the bridge and the first metallized portion.

[0191] Aspect 14: The package according to aspect 11, wherein the electrical path between the first integrated device and the second integrated device includes the bridge and the second metallized portion.

[0192] Aspect 15: The package according to aspects 1 to 14, wherein the package is implemented in a device from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in motor vehicles. Specification page 24 / 25 27 CN 121605800 A

[0193] Aspect 16: A package comprising: a substrate; a first integrated device coupled to the substrate; a second integrated device coupled to the substrate; a dummy silicon structure laterally located between the first integrated device and the second integrated device; and an encapsulation layer coupled to the substrate, wherein the encapsulation layer at least partially encapsulates the first integrated device, the second integrated device and the dummy silicon structure.

[0194] Aspect 17: The package according to aspect 16, wherein the dummy silicon structure is coupled to the substrate by an adhesive.

[0195] Aspect 18: The package according to aspects 16 to 17, wherein the first integrated device is coupled to the substrate by a first plurality of columnar interconnects and / or a first plurality of solder interconnects, and wherein the second integrated device is coupled to the substrate by a second plurality of columnar interconnects and / or a second plurality of solder interconnects.

[0196] Aspect 19: A package comprising: a metallized portion; a first integrated device coupled to the metallized portion; a second integrated device coupled to the metallized portion; a dummy silicon structure laterally located between the first integrated device and the second integrated device; and an encapsulation layer coupled to the metallized portion, wherein the encapsulation layer at least partially encapsulates the first integrated device, the second integrated device, and the dummy silicon structure.

[0197] Aspect 20: The package according to aspect 19, wherein the dummy silicon structure contacts the metallized portion.

[0198] Aspect 21: An apparatus comprising aspects 1 to 20, wherein the apparatus is one of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and an apparatus in a motor vehicle.

[0199] Various features of the present disclosure described herein may be implemented in different systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of aspects of the present disclosure is intended to be illustrative and not to limit the scope of the appended claims. Thus, the teachings herein are readily applicable to other types of apparatuses, and many substitutions, modifications, and variations will be apparent to those skilled in the art.Instruction manual page 25 / 25 28 CN 121605800 A Figure 1 Instruction manual Figure 1 / 21 page 29 CN 121605800 A Figure 2 Instruction manual Figure 2 / 21 page 30 CN 121605800 A Figure 3 Instruction manual Figure 3 / 21 page 31 CN 121605800 A Figure 4 Instruction manual Figure 4 / 21 page 32 CN 121605800 A Figure 5 Instruction manual Figure 5 / 21 page 33 CN 121605800 A Figure 6A Instruction manual Figure 6 / 21 page 34 CN 121605800 A Figure 6B Instruction manual Figure 7 / 21 page 35 CN 121605800 A Figure 6C Instruction manual Figure 8 / 21 page 36 CN 121605800 A Figure 6D Instruction manual Figure 9 / 21 page 37 CN 121605800 A Figure 6E Figure 7 of the instruction manual, page 38, CN 121605800 A, page 39, CN 121605800 A, page 40, CN 121605800 A, page 41, CN 121605800 A, page 42, CN 121605800 A, page 43, CN 121605800 A, page 44, CN 121605800 A, page 45, CN 121605800 A, page 46, CN 121605800 A, page 47 ...8, page 46, CN 121605800 A, page 47, page 19, page 45, CN 121605800 A, page 46, CN 121605800 A, page 47, page 19, page 45, CN 121605800 A, page 46, CN 121605800 A, page 47, page 19, page 45, CN 121605800 A, page 46, CN 121605800 A, page 47, page 19, page 47, CN 121605800 A, page 48, page 46, CN 121605800 A, page 47, page 19, page 47, CN 121605800 A, page 48, page 49, page 47, page 48, page 49, page 47 121605800 A Figure 11 Appendix to the Instruction Manual, Page 48, 20 / 21 CN 121605800 A Figure 12 Appendix to the Instruction Manual, Page 49, 21 / 21 CN 121605800 A.

Claims

1. A package, the package comprising: Package interposer, the package interposer comprising: First metallization section; Second metallization section; A first passive device, located between the first metallized portion and the second metallized portion; and A first encapsulation layer is located between the first metallized portion and the second metallized portion; A first integrated device, the first integrated device being coupled to the package interposer; A second integrated device, the second integrated device being coupled to the package interposer; A dummy silicon structure, the dummy silicon structure being laterally located between the first integrated device and the second integrated device; and A second encapsulation layer is coupled to the package interposer, wherein the encapsulation layer at least partially encapsulates the first integrated device, the second integrated device, and the dummy silicon structure.

2. The package of claim 1, wherein the dummy silicon structure is coupled to the package interposer via an adhesive.

3. The package of claim 1, wherein the dummy silicon structure is configured to have no electrical connection to the first integrated device and / or the second integrated device.

4. The package according to claim 1, wherein the package interposer further comprises a second dummy silicon structure, the second dummy silicon structure being laterally located between the first integrated device and the second integrated device.

5. The package of claim 1, wherein the dummy silicon structure is positioned adjacent to (i) the edge of the first integrated device including the die-to-die portion and (ii) the edge of the second integrated device including the die-to-die portion.

6. The packaging component according to claim 1, The first integrated device is coupled to the package interposer via a first plurality of columnar interconnects and / or a first plurality of solder interconnects, and The second integrated device is coupled to the package interposer via a second plurality of columnar interconnects and / or a second plurality of solder interconnects.

7. The packaging component according to claim 1, The first integrated device is coupled to the first metallized portion of the package interposer, and The second integrated device is coupled to the first metallized portion of the package interposer.

8. The package according to claim 1, The first integrated device is coupled to the second metallized portion of the package interposer, and The second integrated device is coupled to the second metallized portion of the package interposer.

9. The package of claim 1, wherein the first passive device comprises a trench capacitor device.

10. The package according to claim 1, The packaged interposer also includes a second passive device. The first passive device is configured to be electrically coupled to the first integrated device, and The second passive device is configured to be electrically coupled to the second integrated device.

11. The package of claim 1, wherein the package inserter further comprises a bridge located between the first metallized portion and the second metallized portion.

12. The package of claim 11, wherein the electrical path between the first integrated device and the second integrated device includes the bridge.

13. The package of claim 11, wherein the electrical path between the first integrated device and the second integrated device includes the bridge and the first metallized portion.

14. The package of claim 11, wherein the electrical path between the first integrated device and the second integrated device includes the bridge and the second metallized portion.

15. The package of claim 1, wherein the package is implemented in a device from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

16. A package comprising: substrate; A first integrated device, the first integrated device being coupled to the substrate; A second integrated device, the second integrated device being coupled to the substrate; A dummy silicon structure is laterally located between the first integrated device and the second integrated device; as well as An encapsulation layer coupled to the substrate, wherein the encapsulation layer at least partially encapsulates the first integrated device, the second integrated device, and the dummy silicon structure.

17. The package of claim 16, wherein the dummy silicon structure is coupled to the substrate by an adhesive.

18. The package according to claim 16, The first integrated device is coupled to the substrate via a first plurality of columnar interconnects and / or a first plurality of solder interconnects, and The second integrated device is coupled to the substrate via a second plurality of columnar interconnects and / or a second plurality of solder interconnects.

19. A package comprising: Metallized portion; A first integrated device, the first integrated device being coupled to the metallized portion; A second integrated device, the second integrated device being coupled to the metallized portion; A dummy silicon structure is laterally located between the first integrated device and the second integrated device; as well as An encapsulation layer coupled to the metallization portion, wherein the encapsulation layer at least partially encapsulates the first integrated device, the second integrated device, and the dummy silicon structure.

20. The package of claim 19, wherein the dummy silicon structure contacts the metallized portion.

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