Broadband doherty power amplifier

Abstract

The invention discloses a broadband Doherty power amplifier. The Doherty power amplifier comprises a main power amplifier and a peak amplifier. The Doherty power amplifier combines the outputs after the impedance conversion circuit in the peaking amplifier output path compared to a conventional approach of combining the outputs from the main amplifier and the peaking amplifier prior to the impedance conversion circuit. This eliminates or at least reduces possible impedance levels and corresponding impedance levels for the main output path. The reduction or elimination of this step down and step up reduces insertion loss, and allows efficiency at the first efficiency peak to be improved and improves the fractional bandwidth of the Doherty power amplifier.

Description

(19) State Intellectual Property Office (12) Invention Patent Application (10) Application Publication Number (43) Application Publication Date (21) Application Number 202480075002.9 (22) Application Date 2024.11.19 (30) Priority Data 63 / 602,791 2023.11.27 US (85) PCT International Application Entering National Phase Date 2026.05.27 (86) PCT International Application Application Data PCT / US2024 / 056463 ​​2024.11.19 (87) PCT International Application Publication Data WO2025 / 117239 EN 2025.06.05 (71) Applicant QORVO US Company Address USA (72) Inventors B. Scott M.F. Zbulahuzhuangli G. Maxim M. Cao (74) Patent Agency China Council for the Promotion of International Trade Patent & Trademark Agency Co., Ltd. 11038 Patent Attorney Zhang Dan (51) Int.Cl. H03F 1 / 02 (2006.01) H03F 1 / 42 (2006.01) (54) Invention Title: Broadband Doherty Power Amplifier (57) Abstract: A broadband Doherty power amplifier is disclosed. The Doherty power amplifier includes a main power amplifier and a peak amplifier. Compared with the conventional method of combining the outputs of the main amplifier and the peak amplifier before the impedance transformation circuit, this Doherty power amplifier combines the outputs after the impedance transformation circuit in the output path of the peak amplifier. This eliminates or at least reduces the possible impedance step drop and corresponding impedance step rise for the main output path. This reduction or elimination of the step drop and step rise reduces the insertion loss and allows for increased efficiency at the first efficiency peak and improves the fractional bandwidth of the Doherty power amplifier. Claims 2 pages, Description 8 pages, Drawings 8 pages, Claims amended according to Article 19 of the Treaty 2 pages CN 122295846 A 2026.06.26 CN 1 22 29 58 46 A 1. A Doherty power amplifier comprising: a main power amplifier having a main output terminal; a phase shifter coupled to the main output terminal and a combination node; a peak power amplifier having a peak output terminal; and an impedance transfer converter circuit coupled to the peak output terminal at the input side and coupled to the combination node at the output side. 2. The Doherty power amplifier of claim 1, wherein the phase shifter comprises a transmission line sized to provide a 90-degree phase shift.3. The Doherty power amplifier of claim 1, wherein the phase shifter includes an LC circuit providing a 90-degree phase shift. 4. The Doherty power amplifier of claim 1, wherein the phase shifter has an output impedance of approximately fifty ohms (50 Ω). 5. The Doherty power amplifier of claim 1, wherein the phase shifter has an output impedance between twenty ohms and forty ohms (20 Ω to 40 Ω). 6. The Doherty power amplifier of claim 5, further comprising a second impedance transfer circuit coupled to the combination node and configured to step the impedance to approximately fifty ohms (50 Ω). 7. The Doherty power amplifier of claim 1, wherein the peak power amplifier includes a differential output. 8. The Doherty power amplifier of claim 1, further comprising a DC bias coupled to the primary coil of the impedance transfer converter circuit. 9. The Doherty power amplifier of claim 1, further comprising an inverter circuit coupled to the input of the peak power amplifier. 10. The Doherty power amplifier of claim 9, further comprising a tuning circuit coupled to the impedance transfer converter circuitry, the tuning circuitry adding a delay of up to 180 degrees to the peak path of the peak power amplifier. 11. A Doherty power amplifier comprising: a main path through a main power amplifier, the main path including a 90-degree phase shift after the main power amplifier; and a peak path through a peak power amplifier having an inverting input path for a differential signal to form a negative 180-degree phase shift, the peak path including an initial 90-degree phase shift before the peak power amplifier and at least one tunable element to add a delay to the peak path such that the negative 180-degree phase shift is canceled out. 12. The Doherty power amplifier of claim 11, wherein the at least one tunable element comprises a tunable capacitor. 13. The Doherty power amplifier of claim 12, further comprising an impedance transfer converter circuitry, and the tunable capacitor being associated with the impedance transfer converter circuitry. 14. The Doherty power amplifier of claim 11, further comprising a combination node, wherein the peak path includes impedance transfer converter circuitry positioned prior to the combination node.Claims 1 / 2 Page 2 CN 122295846 A 15. The Doherty power amplifier of claim 14, further comprising a second impedance transfer circuit located after the combined node. 16. A method of operating a Doherty power amplifier, the method comprising: providing a first signal through a main path having a main power amplifier; phase-shifting the first signal by ninety degrees using a phase shifter; providing a second signal through a peak path having a peak power amplifier; using an impedance transfer transformer circuit to step the impedance of the peak path; and combining the main path and the peak path after stepping the impedance of the peak path. 17. The method of claim 16, further comprising providing an additional impedance step of up to about fifty ohms (50 Ω) after combination. 18. The method of claim 16, further comprising providing a DC bias in the peak path through the impedance transfer transformer circuit. 19. The method of claim 16, further comprising providing a DC bias in the main path through the impedance transfer transformer circuit. 20. A mobile terminal including a transceiver, the transceiver including a power amplifier stage, the power amplifier stage including: a Doherty power amplifier, the Doherty power amplifier including: a main power amplifier having a main output; a phase shifter coupled to the main output and a combination node; a peak power amplifier having a peak output; and an impedance transfer converter circuit coupled to the peak output at an input side and coupled to the combination node at an output side. Claims 2 / 2 Page 3 CN 122295846 A Broadband Doherty Power Amplifier

[0001] Cross-Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 602,791, filed November 27, 2023, entitled “BROADBAND DOHERTY POWER AMPLIFIER”, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to power amplifiers, and more specifically, to broadband Doherty power amplifiers that can be used, for example, in wireless transmission circuits. Background Art

[0004] Computing devices are ubiquitous in modern society, and more specifically, mobile communication devices have become increasingly common. The widespread use of these mobile communication devices is partly due to the many functions that can now be performed on such devices.The increased processing power in such devices means that mobile communication devices have evolved from simple communication tools into sophisticated mobile multimedia centers, thus enhancing the user experience. With the emergence of numerous functions available for such devices, the pressure to find ways to increase the amount of data that can be transmitted to and received from such devices has increased. This pressure has led to, for example, evolved cellular standards, which place stringent requirements on transmitters within mobile communication devices. These requirements include the ability to handle signals within a relatively large bandwidth compared to historical requirements. Simultaneously, there is pressure to reduce the overall size of the circuitry used in the transmitter. Balancing these design principles provides room for innovation.

[0005] The aspects disclosed in the detailed description include systems and methods for providing broadband Doherty power amplifiers. In particular, the Doherty power amplifier includes a main power amplifier and a peak amplifier. Compared to conventional methods that combine the outputs of the main amplifier and the peak amplifier before impedance transformation circuitry, the aspects of this disclosure combine the outputs after impedance transformation circuitry in the peak amplifier output path. This eliminates or at least reduces possible impedance descent and corresponding impedance rise for the main output path. This reduction or elimination of step descent and step rise reduces insertion loss and allows for increased efficiency at the first efficiency peak and improves the fractional bandwidth of the Doherty power amplifier.

[0006] In this regard, in one aspect, a Doherty power amplifier is disclosed. The Doherty power amplifier includes a main power amplifier having a main output, a phase shifter coupled to the main output and a combination node, and a peak power amplifier having a peak output. The Doherty power amplifier also includes an impedance transfer converter circuit coupled to the peak output at the input side and to the combination node at the output side.

[0007] In another aspect, a Doherty power amplifier is disclosed. The Doherty power amplifier includes: a main path through a main power amplifier, the main path including a 90-degree phase shift after the main power amplifier; and a peak path through a peak power amplifier having an inverting input path for a differential signal to form a negative 180-degree phase shift, the peak path including an initial 90-degree phase shift before the peak power amplifier and at least one tunable element to add a delay to the peak path such that the negative 180-degree phase shift is canceled out.

[0008] In another aspect, a method of operating a Doherty power amplifier is disclosed. The method includes providing a first signal through the main path of a power amplifier having a main specification page 1 / 8 4 CN 122295846 A, and using a phase shifter to phase-shift the first signal by 90 degrees.The method also includes providing a second signal via a peak path having a peak power amplifier, using an impedance transfer converter circuit to step the impedance of the peak path, and combining the main path and the peak path after stepping the impedance of the peak path.

[0009] In another aspect, a mobile terminal including a transceiver is disclosed, the transceiver including a power amplifier stage. The mobile terminal includes a Doherty power amplifier, the Doherty power amplifier including a main power amplifier having a main output, a phase shifter coupled to the main output and a combination node, and a peak power amplifier having a peak output. The mobile terminal also includes an impedance transfer converter circuit coupled to the peak output at the input side and coupled to the combination node at the output side.

[0010] FIG1A is a block diagram of a conventional Doherty power amplifier used in a wireless communication device;

[0011] FIG1B to FIG1D are block diagrams of variations of the Doherty power amplifier of FIG1A with various transformations between single-ended and differential signals;

[0012] FIG1E is a block diagram of a conventional Doherty power amplifier highlighting the shortcomings of the basic Doherty design;

[0013] FIG2 is a block diagram of a first exemplary aspect of a Doherty power amplifier having an output path combined after impedance transformation for a peak amplifier;

[0014] FIG3 is a block diagram of a second exemplary aspect of a Doherty power amplifier having an output path combined after impedance transformation for a peak amplifier, but maintaining a small impedance step in the output path of the main power amplifier;

[0015] FIG4 is a block diagram of another exemplary aspect of a Doherty power amplifier in which a DC bias is provided to the peak power amplifier via an impedance transfer converter circuit, thereby reducing the need for an additional radio frequency (RF) choke;

[0016] Figure 5 is a block diagram of another exemplary aspect of a Doherty power amplifier, wherein DC bias is provided for both the peak power amplifier and the main power amplifier via an impedance transfer converter circuit, thereby reducing the need for an additional RF choke;

[0017] Figure 6 is a block diagram of a Doherty power amplifier according to the present disclosure having an output path combination point, the Doherty power amplifier having a delay compensation circuit for maintaining Doherty action;

[0018] Figure 7 is a block diagram of a Doherty power amplifier according to aspects of the present disclosure having additional analog predistortion to assist linearization;

[0019] Figures 8 and 9 are block diagrams reflecting two possible design choices where some circuitry can be digital or analog;

[0020] Figure 10 is a flowchart illustrating an exemplary process for operating a Doherty power amplifier according to aspects of the present disclosure; and

[0021] Figure 11 is a block diagram of a mobile terminal according to the present disclosure that may include the Doherty power amplifiers of Figures 2 through 9 in a transceiver. Detailed Description

[0022] The embodiments described below represent the information necessary to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and will understand the application of these concepts not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0023] It will be understood that while the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element without departing from the scope of this disclosure, and similarly, a second element may be referred to as a first element. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0024] It should be understood that when an element, such as a layer, region, or substrate, is referred to as “on another element” or “extends to another element,” it may be directly on or directly extend to the other element, or there may be intermediate elements present. In contrast, when an element is referred to as “directly on” or “directly” extending “to” another element, there are no intermediate elements present. Similarly, it should be understood that when an element, such as a layer, region, or substrate, is referred to as “over another element” or “extends over another element,” it may be directly over or directly extend over the other element, or there may be intermediate elements present. Conversely, when an element is referred to as “directly above another element” or “extends directly above another element,” there is no intermediate element. It will also be understood that when an element is referred to as “connected” or “coupled” to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element. Conversely, when an element is referred to as “directly connected” or “directly coupled” to another element, there is no intermediate element.

[0025] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe the relationship of an element, layer, or area to another element, layer, or area as shown in the figures. It should be understood that these terms and those discussed above are intended to include different orientations of the device other than those depicted in the figures.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” are intended to also include the plural forms. It should also be understood that, when used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0027] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.It will be further understood that, unless explicitly defined herein, the terms used herein should be interpreted as having the meaning consistent with their meaning in the context of this specification and related art, and will not be interpreted in an idealized or overly formal sense.

[0028] Consistent with the foregoing admonition regarding definitions, this disclosure uses the term "transceiver" in a broad sense. Current industry literature uses "transceiver" broadly to refer to multiple circuits that transmit and receive signals. Exemplary circuits may include a baseband processor, up / down conversion circuitry, filters, amplifiers, couplers, etc., coupled to one or more antennas. Similarly, some authors in industry literature refer to the circuitry positioned between the baseband processor and the power amplifier circuitry as a transceiver. This intermediate circuitry may include up / down conversion circuitry, mixers, oscillators, filters, etc., but typically does not include a power amplifier. As used herein, the term transceiver is used in its first sense. In cases relating to the distinction between the two definitions, the terms "transceiver chain" and "transceiver circuitry" are used respectively.

[0029] The aspects disclosed in the detailed description include systems and methods for providing broadband Doherty power amplifiers. Specifically, the Doherty power amplifier includes a main power amplifier and a peak amplifier. Compared to the conventional method of combining the outputs of the main amplifier and the peak amplifier before the impedance transformation circuit, aspects of this disclosure combine the outputs after the impedance transformation circuit in the peak amplifier output path. This eliminates or at least reduces the possible impedance step drop and corresponding impedance rise for the main output path. This reduction or elimination of the step drop and rise reduces insertion loss and allows for increased efficiency at the first efficiency peak and improves the fractional bandwidth of the Doherty power amplifier.

[0030] Before explaining aspects of this disclosure, an overview of a conventional Doherty power amplifier is provided with reference to Figures 1A through 1D. Specific problems that pose challenges to designers are discussed with reference to Figure 1E, and solutions to these challenges are discussed starting with reference to Figure 2.

[0031] In this regard, Figure 1A is a simplified block diagram of a conventional Doherty amplifier 100. The Doherty amplifier 100 has an input node 102 and an output node 104. At input node 102, the incoming signal is branched. The first signal path 106 leads to the primary or main power amplifier 108. The secondary signal path 110 is active when switches 112A and 112B are on (i.e., closed, allowing signals to pass through these switches), and inactive when switches 112A and 112B are off (i.e., open or unconnected, preventing signals from passing through these switches). When the secondary signal path 110 is active, the signal on this path passes through phase shifter 114, which applies a 90-degree phase shift to the signal. The peak power amplifier 116 amplifies the shifted signal.Combiner 118 combines signal paths 106 and 110 and provides the summed signal to output node 104.

[0032] Therefore, in operation, during low power level boosts, switches 112A and 112B are open, and only the main power amplifier 108 is used to amplify the signal. When a gain exceeding the possible gain of the main power amplifier 108 is required, switches 112A and 112B are closed, and peak power amplifier 116 is used to form an additional boost to the signal, such that when the signals on paths 106 and 110 are summed, a sufficiently amplified signal appears at output node 104. To ensure that signal paths 106 and 110 are in phase, a phase shifter 120 can be provided in the first signal path 106. It should be noted that combiner 118 at output node 104 can be a simple shared conduction node and does not require explicit circuitry.

[0033] By design, the Doherty amplifier has a single-ended output. However, there may be situations where differential signals are required for various reasons. Figures 1B to 1D illustrate several possible configurations and possible variations in signal path conditioning. It should be understood that, without explicit indication to the contrary, aspects of this disclosure can work with any of these basic structures, regardless of which specific elements are located within which signal paths, and regardless of whether a particular portion of the path is single-ended or differential.

[0034] Figure 1B illustrates a Doherty power amplifier 100B having a differential portion in the peak path and drive amplifier stages in each path. More specifically, the Doherty power amplifier 100B has an input node 102 and an output node 104 having a main path 126 and a peak path 128. The main path 126 has a main drive amplifier 130 and a main amplifier 132, and a phase shifter 134. The peak path 128 has a phase shifter 136, a single-ended to differential drive amplifier 138, a differential peak amplifier 140, and a differential to single-ended filter 142. Paths 126 and 128 are combined at output node 104.

[0035] FIG1C illustrates a Doherty power amplifier 100C having a differential main portion located in the main path. More specifically, the Doherty power amplifier 100C has an input node 102 and an output node 104, the output node having a main path 146 and a peak path 148. The main path 146 has a single-ended to differential drive amplifier 150, a differential main power amplifier 152, a differential to single-ended filter 154, and a phase shifter 156. The peak path 148 has a phase shifter 114, a single-ended drive amplifier 160, and a single-ended peak power amplifier 162. Paths 146 and 148 are combined at output node 104.

[0036] FIG1D illustrates a Doherty power amplifier 100D having a differential main path 166 and a differential peak path 168. More specifically, the Doherty power amplifier 100D has an input node 102 and an output node 104. The main path 166 has a single-ended drive amplifier 170, a single-ended to differential interstage matching circuit 172, a differential main power amplifier 174, and a phase shifter 175. The peak path 168 has a phase shifter 114, a single-ended drive amplifier 178, a single-ended to differential interstage matching circuit 180, and a differential peak power amplifier 182. Paths 166 and 168 are combined at a combination node 184, and a differential-to-single-ended filter 186 couples the combination node 184 to the output node 104.

[0037] Whether only single-ended components are present or some mixture of differential components are present, and regardless of the presence of a drive amplifier or interstage matching circuit, conventional Doherty amplifiers use phase shifters in the main path (e.g., phase shifters 120, 134, 156, and 175 for main paths 106, 126, 146, and 166, respectively).

[0038] A general representation of this structure is provided in Figure 1E, where the Doherty amplifier 100E has a main path 190 and a peak path 192. The main path has a main power amplifier 193 and a phase shifter 194, while the peak path 192 has a peak amplifier 195, and these paths are combined at node 196. For reasons explained below, an impedance transfer converter circuit 198 is provided at node 196.

[0039] Phase shifter 194 (and its associated phase shifters 120, 134, 156, 175) is used for load modulation, specifically to place the signal in the main path 190 in the same phase as the signal in the peak path 192. In most cases, phase shifter 194 can be a transmission line of a certain length that shifts the phase of the main path 190 by its length. It is also possible to combine the transmission line with an LC circuit that applies the same phase shift.

[0040] The output of peak amplifier 195 is typically low impedance. This low impedance is used because it is easier to drive power out of the power amplifier at low impedance than at higher impedance. Therefore, node 196 can be, for example, about ten ohms (10 Ω). In order to obtain proper impedance matching between paths 190, 192 at node 196, phase shifter 194 (i.e., transmission line) can step down the impedance from a relatively high impedance (e.g., 40 Ω) to the low impedance of node 196. Although it is envisioned that there may be low impedance at the output of the main amplifier 193, the requirements of the phase shifter 194 make this approach impractical.

[0041] To bring the output of the Doherty amplifier 100E back to a level suitable for use by other components in the amplifier chain, the impedance transfer transformer circuit 198 typically brings the impedance step back to (indicated by the Z↑ symbol) fifty ohms.

[0042] This arrangement introduces two drawbacks. First, bandwidth is a function of the square root of the total impedance transfer, so having two impedance transfers after the main amplifier 193 limits the bandwidth. This bandwidth loss is not too problematic when the operating frequency is in a relatively low frequency band. However, as the frequencies of emerging cellular and other wireless standards increase, this bandwidth loss becomes commercially impractical. Second, having both functions after the main amplifier 193 introduces two insertion losses, which reduces efficiency.

[0043] By design, the Doherty amplifier has optimal efficiency when both the main amplifier 193 and the peak amplifier 195 are operating, but the Doherty amplifier operates at average power most of the time, meaning the peak amplifier 195 is off. Therefore, most of the time, when only the main amplifier 193 is used, efficiency is reduced due to the two insertion losses. When the peak amplifier 195 and its individual insertion loss operate, efficiency is improved, but again, this benefit is only available for a small fraction of the total time.

[0044] An exemplary aspect of this disclosure repositions the combining node after the impedance transfer transformer, so that the main path no longer suffers the losses associated with two large impedance transfers, thereby improving the main path bandwidth and efficiency.

[0045] In the first exemplary aspect illustrated in FIG2, the impedance step for the combining node is eliminated. Specifically, the Doherty amplifier 200 has a main path 202 and a peak path 204. The main path 202 includes a main power amplifier 206 and a phase shifter 208, which, as discussed above, can be a transmission line or a combiner line. The peak path 204 has a peak power amplifier 210 and an impedance transfer transformer circuit 212, which can also perform differential-to-single-ended transfer functionality. After the impedance transfer transformer circuit 212, paths 202 and 204 are combined at the combining node 214. Relatedly, the phase shifter 208 can have a uniform impedance along the length of the transmission line and can match the stepped impedance (e.g., 50 Ω) generated by the impedance transfer converter circuit 212. Now, the main path 202 has no loss from impedance transfer and only the insertion loss of the phase shifter 208, thereby improving both bandwidth and efficiency.

[0046] It should be understood that although shown as a single-ended main path 202 and a differential peak path 204, any arrangement and other variations shown in Figures 1A through 1D can still benefit from the arrangement of Figure 2.

[0047] It should be noted that for the main power amplifier 206 to have an output impedance of fifty ohms (50 Ω), the main power amplifier 206 may require a supply voltage of up to six (or higher) volts (6+V). Not every mobile computing device can provide this level of supply voltage. Therefore, the Doherty amplifier 300 illustrated in FIG3 can be used instead. In particular, the Doherty amplifier 300 has a main path 302 and a peak path 304. The main path 302 includes the main power amplifier 306 and a phase shifter 308, which, as discussed above, can be a transmission line or a combiner line. The peak path 304 has a peak amplifier 310 and an impedance transfer converter circuit 312, which can also perform differential-to-single-ended transfer functionality. After the impedance transfer converter circuit 312, paths 302 and 304 are combined at a combination node 314.

[0048] Compared to phase shifter 208 of FIG. 2, phase shifter 308 may also include a small impedance step. For example, combination node 314 may have an intermediate impedance of thirty-five ohms (35 Ω). Phase shifter 308 can step up a low initial impedance (e.g., 10 Ω) to this intermediate impedance. Subsequently, another small impedance transfer circuit 316 may be present to step up the impedance to fifty ohms. By having two small impedance steps, the bandwidth is less affected than the step-down-step arrangement of FIG. 1E. Similarly, the overall efficiency remains relatively high compared to the arrangement of FIG. 1E by placing only a relatively small impedance transfer. Alternatively, phase shifter 308 does not have an impedance function, and the main power amplifier 306 outputs to the intermediate impedance.

[0049] FIG. 4 provides additional details regarding impedance transfer converter circuit 212 and provides auxiliary benefits that can be provided to differential peak power amplifier 210. Specifically, a DC bias signal is generally provided to peak power amplifier 210 through a large radio frequency (RF) choke. This RF choke is typically represented by an inductor. Inductors generally occupy a relatively large amount of space. However, by having a converter in the impedance transfer converter circuit 212, the opportunity is created to reduce or eliminate additional inductors. Specifically, the impedance transfer converter circuit 212 may include a primary coil (i.e., inductor) 400 and a secondary coil (i.e., also an inductor) 402. A DC bias signal can be supplied to the peak power amplifier 210 through the center tap 404 on the primary coil 400. Similarly, a DC bias signal can be supplied to the main power amplifier through the bottom 406 of the secondary coil 402. Although not shown, the bottom 406 may need to be at AC ground. This ground can be provided by a suitable capacitor, as better explained below.

[0050] When both the peak power amplifier and the main power amplifier are differential, two center taps can be provided, as illustrated by the Doherty amplifier 500 in FIG5. The Doherty amplifier 500 may include a main path 502 and a peak path 504. The main path 502 has a differential main power amplifier 506 and phase shifters 508A, 508B. The peak path 504 has a differential peak power amplifier 510 and an impedance transfer converter circuit 512. Paths 502, 504 are combined at a differential node 514. A differential-to-single-ended filter 516 is coupled to node 514 and provides a single-ended output at output node 518.

[0051] Continuing to refer to FIG5, the impedance transfer converter circuit 512 (similar to impedance transfer converter circuit 212) has a primary coil 520 and a secondary coil 522. A center tap 524 on the primary coil 520 provides a DC bias signal to the peak power amplifier 510. The center tap 526 on the secondary coil 522 provides a DC bias signal to the main power amplifier 506.

[0052] It should be noted that, according to various aspects of this disclosure, the active elements of a Doherty amplifier can impose a certain phase delay relative to the main path in the signal in the peak path. When the conversion frequency (FT) is large compared to the operating frequency (OF), such delay can be considered negligible. However, modern operating frequencies are increasing and are therefore more likely to be a significant part of the FT. Therefore, these delays may be large enough to negatively affect the Doherty effect (because the signals are no longer in phase at the combination node).

[0053] Figure 6 provides a solution to this unwanted phase shift. It should be noted that, according to various aspects of this disclosure, this complexity is not necessary for every Doherty amplifier, but this solution may be helpful to designers in certain situations. Specifically, the Doherty amplifier 600 has a main path 602 and a peak path 604. The main path 602 includes a drive amplifier 608A and a main power amplifier 608B, as well as a phase shifter 610 that provides a 90-degree phase shift as previously discussed. Specification 6 / 8 pages 9 CN 122295846 A

[0054] The peak path 604 includes an initial phase shifter 612 (similar to phase shifters 114 and 136 of Figures 1A to 1D) that provides a 90-degree phase shift. The peak path 604 also includes a drive amplifier 614A and a peak power amplifier 614B. However, instead of a direct connection between the drive amplifier 614A and the peak power amplifier 614B, the input of the peak power amplifier 614B is inverted, which effectively provides a negative 180-degree phase shift.Subsequently, tunable elements 618A and 618B are added to the impedance transfer converter circuit 616, which allows the peak path delay to be extended to 180 degrees (a portion of which comes from the inherent delay of the active elements, and the remainder is tuned by the tunable elements 618A and 618B). By forcing the delay to 180 degrees and providing an effective negative 180 degrees, the phase is aligned at the combined node 620. It should be noted that capacitor 622 is added as AC ground as discussed above.

[0055] As illustrated in FIG7, the assignee of this disclosure also has various disclosures related to analog predistortion (APD), and any of those techniques can be added to the front-end module (FEM) 700. Specifically, baseband circuit 702 can provide information to transceiver circuit 704 and / or FEM 700 (and in particular APD linearization circuit 706). Additionally, sensor 708 can provide information to APD linearization circuit 706. APD linearization circuit 706 can force peak amplifier 710 to turn on or off, or control the bias used for peak amplifier 710 or main amplifier 712. Similarly, other tunable elements that can be adjusted to assist APD linearization may be present in FEM 700.

[0056] Figures 8 and 9 provide options for comparing a fully analog (e.g., gallium arsenide) Doherty method (Figure 8) with a hybrid method (where a portion of the Doherty method is implemented in a complementary metal-oxide-semiconductor (CMOS) chip). Thus, the APD signal can be transmitted from the CMOS controller 800 in Figure 8 to the GaAs Doherty amplifier 802, whereas, in contrast, the APD signal can be transmitted to pre-drive amplifiers 900A, 900B in the CMOS controller 902. The remainder of the Doherty amplifier may be located in the GaAs chip 904.

[0057] As illustrated in Figure 10, a method of operating a Doherty amplifier according to aspects of this disclosure is provided in process 1000. Process 1000 begins by splitting the signal into a main path and a peak path (box 1002). The peak signal is phase-shifted (box 1004), amplified (box 1006), and then impedance-transformed using an impedance transfer transformer circuit (box 1008).

[0058] Simultaneously, the main signal is amplified (box 1010) and phase-shifted (box 1012). After boxes 1008 and 1012, the signals are combined (box 1014). Optionally, and not shown, additional impedance transfer may be applied. Accordingly, the impedance transformation at box 1008 occurs only on the peak signal and only when the peak path is active.

[0059] Referring to FIG11, the concepts described above can be implemented in various types of user element 1100, such as mobile terminals, smartwatches, tablet computers, computers, navigation devices, access points, and similar wireless communication devices supporting wireless communications such as cellular, wireless local area networks (WLAN), Bluetooth, and near-field communication. User element 1100 will generally include a control system 1102, a baseband processor 1104, a transmitting circuit 1106, a receiving circuit 1108, an antenna switching circuit 1110, multiple antennas 1112, and user interface circuitry 1114. In a non-limiting example, as an example, the control system 1102 may be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). In this regard, the control system 1102 may include at least a microprocessor, embedded memory circuitry, and a communication bus interface. The receiving circuit 1108 receives radio frequency signals from one or more base stations via antenna 1112 and through antenna switching circuit 1110. Low-noise amplifiers and filters in the receiving circuit 1108 cooperate to amplify and remove broadband interference from the received signals for processing. Then, a down-conversion and digitization circuit (not shown) down-converts the filtered received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter (ADC).

[0060] The baseband processor 1104 processes the digitized received signal to extract the information or data bits transmitted in the received signal. This processing typically includes demodulation, decoding, and error correction operations. The baseband processor 1104 is typically implemented in one or more digital signal processors (DSPs) and ASICs. Specification 7 / 8 pages 10 CN 122295846 A

[0061] For transmission, the baseband processor 1104 receives digitized data representing voice, data, or control information encoded by the control system 1102 for transmission. The encoded data is output to the transmission circuit 1106, where a digital-to-analog converter (DAC) converts the digitally encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal at the desired transmission frequency or multiple frequencies. The power amplifier amplifies the modulated carrier signal to a level suitable for transmission and transmits the modulated carrier signal to antenna 1112 via antenna switching circuit 1110. Multiple antennas 1112, along with replicated transmit circuitry 1106 and receive circuitry 1108, can provide spatial diversity. Those skilled in the art will understand the modulation and processing details.

[0062] It should also be noted that the operational steps described in any exemplary aspect herein are described to provide examples and discussion. The described operations may be performed in several different orders other than the order shown. Furthermore, the operations described in a single operational step may actually be performed in several different steps.Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that the operational steps shown in the flowcharts may undergo many different modifications, as will be apparent to those skilled in the art. Those skilled in the art will also understand that information and signals may be represented using any of a variety of different techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced in the above embodiments may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0063] The prior description of this disclosure is provided so that any person skilled in the art may make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein. Instruction Manual Page 8 / 8, 11 CN 122295846 A, Figure 1A, Figure 1B, Figure 1C; Instruction Manual Drawings Page 1 / 8, 12 CN 122295846 A, Figure 1D, Figure 1E, Figure 2; Instruction Manual Drawings Page 2 / 8, 13 CN 122295846 A, Figure 3, Figure 4; Instruction Manual Drawings Page 3 / 8, 14 CN 122295846 A, Figure 5; Instruction Manual Drawings Page 4 / 8, 15 CN 122295846 A, Figure 6, Figure 7; Instruction Manual Drawings Page 5 / 8, 16 CN 122295846 A, Figure 8, Figure 9; Instruction Manual Drawings Page 6 / 8, 17 CN 122295846 A, Figure 10; Instruction Manual Drawings Page 7 / 8, 18 CN 122295846 A, Figure 11; Instruction Manual Drawings Page 8 / 8, 19 CN 122295846 A 1. A Doherty power amplifier, the Doherty power amplifier comprising: A main power amplifier having a main output terminal; a phase shifter coupled to the main output terminal and a combination node; a peak power amplifier having a peak output terminal; an inverter coupled to the input terminal of the peak power amplifier; an impedance transfer converter circuit coupled to the peak output terminal at the input terminal side and coupled to the combination node at the output terminal side; and a tuning circuit coupled to the impedance transfer converter circuit, the tuning circuit adding a delay of up to 180 degrees to the peak path of the peak power amplifier. 2. The Doherty power amplifier of claim 1, wherein the phase shifter includes a transmission line sized to provide a 90-degree phase shift.3. The Doherty power amplifier of claim 1, wherein the phase shifter includes an LC circuit providing a 90-degree phase shift. 4. The Doherty power amplifier of claim 1, wherein the phase shifter has an output impedance of approximately fifty ohms (50 Ω). 5. The Doherty power amplifier of claim 1, wherein the phase shifter has an output impedance between twenty ohms and forty ohms (20 Ω to 40 Ω). 6. The Doherty power amplifier of claim 5, further comprising a second impedance transfer circuit coupled to the combination node and configured to step the impedance to approximately fifty ohms (50 Ω). 7. The Doherty power amplifier of claim 1, wherein the peak power amplifier includes a differential output. 8. The Doherty power amplifier of claim 1, further comprising a DC bias coupled to the primary coil of the impedance transfer converter circuit. 9. A Doherty power amplifier comprising: a main path through a main power amplifier, the main path including a 90-degree phase shift after the main power amplifier; and a peak path through a peak power amplifier having an inverting input path for a differential signal to form a negative 180-degree phase shift, the peak path including an initial 90-degree phase shift before the peak power amplifier and at least one tunable element to add a delay to the peak path such that the negative 180-degree phase shift is canceled out. 10. The Doherty power amplifier of claim 9, wherein the at least one tunable element comprises a tunable capacitor. 11. The Doherty power amplifier of claim 10, further comprising an impedance transfer converter circuit, and the tunable capacitor being associated with the impedance transfer converter circuit. 12. The Doherty power amplifier of claim 9, further comprising a combination node, wherein the peak path includes an impedance transfer converter circuit positioned before the combination node. 13. The Doherty power amplifier of claim 12, further comprising a second impedance transfer circuit located after the combination node.Claims amended under Article 19 of the Treaty, page 1 / 2, 20 CN 122295846 A 14. A method of operating a Doherty power amplifier, the method comprising: providing a first signal via a main path having a main power amplifier; phase-shifting the first signal by 90 degrees using a phase shifter positioned after the main power amplifier; providing a second signal via a peak path having a peak power amplifier, wherein the second signal is a differential signal; shifting the second signal by an initial 90-degree phase shift before the peak power amplifier; inverting the second signal to form a negative 180-degree phase shift; shifting the second signal with a tunable element to add a delay to the peak path such that the negative 180-degree phase shift is canceled out; using an impedance transfer converter circuit to step the impedance of the peak path; and combining the main path and the peak path after stepping the impedance of the peak path. 15. The method of claim 14, further comprising providing an additional impedance step of up to about fifty ohms (50 Ω) after combination. 16. The method of claim 14, further comprising providing a DC bias in the peak path via the impedance transfer converter circuit. 17. The method of claim 14, further comprising providing a DC bias in the main path via the impedance transfer converter circuit. 18. A mobile terminal including a transceiver, the transceiver including a power amplifier stage, the power amplifier stage including: the Doherty power amplifier of claim 1. Claims amended under Article 19 of the Treaty, 2 / 2 pages, 21 CN 122295846 A.

Claims

1. A Doherty power amplifier, the Doherty power amplifier comprising: A main power amplifier having a main output terminal; A phase shifter, the phase shifter being coupled to the main output terminal and the combination node; A peak power amplifier having a peak output terminal; and An impedance transfer converter circuit, wherein the impedance transfer converter circuit is coupled to the peak output terminal at the input terminal side and coupled to the combined node at the output terminal side.

2. The Doherty power amplifier of claim 1, wherein the phase shifter includes a transmission line sized to provide a 90-degree phase shift.

3. The Doherty power amplifier of claim 1, wherein the phase shifter includes an LC circuit that provides a 90-degree phase shift.

4. The Doherty power amplifier of claim 1, wherein the phase shifter has an output impedance of approximately fifty ohms (50Ω).

5. The Doherty power amplifier of claim 1, wherein the phase shifter has an output impedance between 20 ohms and 40 ohms (20 Ω to 40 Ω).

6. The Doherty power amplifier of claim 5, further comprising a second impedance transfer circuit coupled to the combined node and configured to step up the impedance to approximately fifty ohms (50 Ω).

7. The Doherty power amplifier of claim 1, wherein the peak power amplifier includes a differential output terminal.

8. The Doherty power amplifier of claim 1, further comprising a DC bias of the primary coil coupled to the impedance transfer converter circuit.

9. The Doherty power amplifier of claim 1, wherein the Doherty power amplifier further comprises an inverter circuit coupled to the input terminal of the peak power amplifier.

10. The Doherty power amplifier of claim 9, further comprising a tuning circuit coupled to the impedance transfer converter circuitry, the tuning circuitry adding a delay of up to 180 degrees to the peak path of the peak power amplifier.

11. A Doherty power amplifier, the Doherty power amplifier comprising: The main path through the main power amplifier includes a 90-degree phase shift after the main power amplifier; The peak path of the peak power amplifier has an inverting input path for the differential signal to form a negative 180-degree phase shift. The peak path includes an initial 90-degree phase shift before the peak power amplifier and at least one tunable element to add a delay to the peak path such that the negative 180-degree phase shift is canceled out.

12. The Doherty power amplifier of claim 11, wherein the at least one tunable element comprises a tunable capacitor.

13. The Doherty power amplifier of claim 12, further comprising an impedance transfer converter circuit, and the tunable capacitor being associated with the impedance transfer converter circuit.

14. The Doherty power amplifier of claim 11, further comprising a combination node, wherein the peak path includes impedance transfer converter circuitry positioned prior to the combination node.

15. The Doherty power amplifier of claim 14, further comprising a second impedance transfer circuit located after the combination node.

16. A method of operating a Doherty power amplifier, the method comprising: The first signal is provided through the main path, which has a main power amplifier; The first signal is phase-shifted by ninety degrees using a phase shifter; The second signal is provided through a peak path with a peak power amplifier; An impedance transfer converter circuit is used to step up the impedance of the peak path. as well as After stepping the impedance of the peak path, the main path and the peak path are combined.

17. The method of claim 16, further comprising, after combination, providing an additional impedance step of up to approximately fifty ohms (50 Ω).

18. The method of claim 16, further comprising providing a DC bias in the peak path via the impedance transfer converter circuit.

19. The method of claim 16, further comprising DC biasing in the main path via the impedance transfer converter circuit.

20. A mobile terminal including a transceiver, the transceiver including a power amplifier stage, the power amplifier stage comprising: Doherty power amplifier, the Doherty power amplifier comprising: A main power amplifier having a main output terminal; A phase shifter, the phase shifter being coupled to the main output terminal and the combination node; A peak power amplifier having a peak output terminal; and An impedance transfer converter circuit, wherein the impedance transfer converter circuit is coupled to the peak output terminal at the input terminal side and coupled to the combined node at the output terminal side.

Images