POWER SAVING TECHNIQUES IN COMPUTER DEVICES THROUGH COMMUNICATION BUS CONTROL

Abstract

A power-saving technique in computing devices through communication bus control starts a timer when data is ready to be sent across the communication bus from the first terminal to the second terminal. While the timer is running, any data from any channel ready to be sent across the communication bus from the first terminal to the second terminal is accumulated. When the timer expires, all data is sent over the communication bus. By holding or accumulating data in this manner, unnecessary transitions between low-power and active states on the communication bus are reduced and power is saved. The timer can be set based on the latency requirements of the data ready to be sent.

Description

Description POWER SAVING TECHNIQUES IN COMPUTER DEVICES VIA COMMUNICATION BUS CONTROL Invention Engineering Field The technology of the disclosure generally relates to power saving techniques in computing devices through control of communication buses. Background of the Invention Computing devices abound in modern society. From small mobile computing devices, such as smartphones or tablets, to large server farms with numerous blades and memory banks, these devices are expected to communicate across multiple networks while providing a variety of other basic functions. While desktop and server devices are generally immune to power consumption concerns, mobile devices continually struggle to find the right balance between available functionality and battery life. This means that as more functions are provided, power consumption increases, and battery life is shortened. Servers may also face power consumption issues when assembled in large server farms. Therefore, there is always room for securing power savings. Brief Description of the Invention The aspects disclosed in the detailed description include power-saving techniques in computing devices through communication bus control. Specifically, when data is ready to be transmitted over the communication bus from the first terminal to the second terminal, a timer is started. While the timer is running, any data from any channel that is ready to be transmitted across the communication bus from the first terminal to the second terminal is accumulated. When the timer expires, all data is transmitted over the communication bus. By holding or accumulating data in this manner, unnecessary transitions between low-power and active states on the communication bus are reduced and power is saved. The timer can be set based on the latency requirements of the data ready to be transmitted. In this case, in one aspect, an integrated circuit (IC) is disclosed. The IC includes a timer. The IC also includes at least one data source circuit. The IC also includes an interconnectivity bus interface. The IC also includes control circuitry. The control circuitry is configured to receive an indication that at least one data source circuit has data or a command to send to a second IC. The control circuitry is also configured to initiate a timer upon receiving the indication. The control circuitry is also configured to accumulate data across multiple channels until the timer expires. The control circuitry is also configured to send the accumulated data at the timer expiration time through the interconnectivity bus interface to the second IC. In another aspect, a communication system is disclosed. The communication system includes an interconnectivity bus. The communication system also includes a first IC. The first IC includes a first timer. The first IC also includes at least one first data source circuit. The first IC also includes a first interconnectivity bus interface coupled to the interconnectivity bus. The first IC also includes a first control circuit. The first control circuit is configured to receive an indication that at least one first data source circuit has first data to transmit to a second IC. The first control circuit is also configured to initiate a first timer upon receiving the indication. The first control circuit is also configured to accumulate data across the plurality of channels until the expiration of the first timer.The first control circuit is also configured to send data accumulated upon the expiration of the first timer through the first interconnectivity bus interface to the second IC. The communication system also includes a second IC. The second IC includes a second interconnectivity bus interface coupled to the interconnectivity bus. The second IC also includes a second control circuit. The second control circuit is configured to receive the accumulated data. The second control circuit is also configured, responsive to receiving the initially accumulated data, to begin sending the second data to the first IC. In another aspect, a method for controlling an interconnectivity bus is disclosed. The method includes receiving an indication that at least one first data source circuit has first data to be sent to a remote IC via the interconnectivity bus. The method also includes starting a first timer upon receiving the indication. The method also includes accumulating data across multiple channels until the expiration of the first timer. The method also includes sending data accumulated at the expiration of the first timer via the interconnectivity bus interface to the remote IC. Short Description of Image Figure 1A is a simplified view of a computing device operating over a remote network; Figure 1B is a simplified view of a mobile terminal operating over a long-distance network; Figure 1C is an expanded block diagram view of the mobile terminal of Figure 1B with an illustration of the internal interconnection buses; Figure 1D is a block diagram of a cellular terminal. 1B; Figure 2 is a diagram of the protocol stack that can be sent from the internal interconnect bus and where channels can emerge from within the protocol stack; Figure 3A is an example of a time versus link power graph in a conventional computing device for a single channel; Figure 3B is an example of a time versus link power graph in a conventional computing device for a number of channels; Figure 4 is a block diagram of a Peripheral Component Interconnect (PCI) Express (PCIE) system in a computing device that may benefit from the power saving techniques of the present disclosure; Figure 5 is a block diagram of an application processor that has a complex PCIE root circuit inside it; Figure 6 is a block diagram of a modem that has PCIE Endpoint circuitry inside it; Figure 7A is a flowchart illustrating an example process for reducing power consumption through communication bus control; Figure 7B is a second flowchart illustrating a more explicit decision point in the process of Figure 7A; Figure 8 is a graph of time versus link power for a PCIE system operating according to an exemplary aspect of the present disclosure; and Figure 9 is a block diagram of an example processor-based system that may include a PCIE system such as the PCIE system in Figure 4 that includes the power reduction processes in Figures 7A and 7B. Complete Description of the Invention With reference now to the drawings, some exemplary aspects of the present disclosure are described. The word exemplary is used herein to mean serving as an example, instance, or illustration. Any aspect described herein as an example should not be construed as being preferable or more advantageous than any other aspect. The aspects disclosed in the detailed description include power-saving techniques in computing devices through communication bus control. Specifically, when data is ready to be transmitted over the communication bus from the first terminal to the second terminal, a timer is started. While the timer is running, any data from any channel that is ready to be transmitted across the communication bus from the first terminal to the second terminal is accumulated. When the timer expires, all data is transmitted over the communication bus. By holding or accumulating data in this manner, unnecessary transitions between low-power and active states on the communication bus are reduced and power is saved. The timer can be set based on the latency requirements of the data ready to be transmitted. In a particularly considered aspect, the present disclosure is suitable for use by a Peripheral Component Interconnect (PCI) Express (PCIE) system in a mobile terminal. By combining or consolidating all channels on a PCIE link, the link terminal may remain in a low-power mode for a longer period of time, and less power is consumed in entering and exiting the low-power mode. While it is intended that the power-saving techniques of the present disclosure be used in a PCIE link in a mobile terminal, such as a smartphone or tablet, the disclosure is not so limited. Therefore, Figures 1A and 1B illustrate a computing device coupled to a remote network via a modem that may implement exemplary aspects of the power-saving techniques of the present disclosure, while Figures 1C and 1D provide additional details about the internal communication link for the modem to another processor within the computing device. In this case, Figure 1A illustrates a computing device 100 coupled to a network 102, which, in an exemplary aspect, is the internet. The computing device 100 may include a housing 104 with a central processing unit (CPU) (not illustrated) therein.Users can interact with computing device 100 through a user interface formed from input / output elements such as a monitor 106 (sometimes referred to as a display), a keyboard 108, and / or a mouse 110. In some aspects, the monitor 106 can be incorporated into a housing 104. While the keyboard 108 and mouse 110 are illustrated as input devices, the monitor 106 can be a touchscreen display, which can supplement or replace the keyboard 108 and mouse 110 as input devices. Other input / output devices may also be present as is well understood in connection with desktop or laptop style computing devices. Although not illustrated in Figure 1A, the housing 104 may also include a modem within it. The modem may be positioned on a network interface card (NIC), as is well understood. Similarly, additional routers and / or modems may be located outside the housing 104.For example, a computing device 100 may be connected to a network 102 via a router and a cable modem, as is well understood. However, even where such an external router and modem are present, the computing device 100 may have an internal modem for communicating with the external router and modem. In addition to the computing device 100, exemplary aspects of the present disclosure may also be applied to mobile terminals, which are a form of computing device as that term is used herein. In this regard, exemplary aspects of the mobile terminal 120 are illustrated in Figure 1B. Instead of a smartphone, the mobile terminal 120 may be a cellular telephone, tablet, laptop, or other mobile computing device. The mobile terminal 120 may communicate with a remote antenna 122 associated with a base station (BS) 124. The BS 124 may communicate with the public land mobile network (PLMN) 126, the public switched telephone network (PSTN, not shown), or the network 102 (e.g., the internet). It is also possible that the PLMN 126 communicates with the internet (e.g., network 102) either directly or through an intervening network (e.g., the PSTN).It should be understood that most contemporary mobile terminals 120 enable various types of communication with network elements 102. For example, audio streaming, video streaming, and / or web browsing are all common functions on most contemporary mobile terminals 120. These functions are enabled through applications stored in the memory of the mobile terminal 120 and using the wireless transceiver of the mobile terminal 120. To perform a function, such as video streaming, data arrives from a remote antenna 122 on antenna 130 of the mobile terminal 120, as illustrated in Figure 1C. The data is initially processed on the mobile device modem (MDM) 132 of the mobile terminal 120 and forwarded to the application processor 134 by the interconnectivity bus 136. In this context, the application processor 134 is generally an integrated circuit (IC) and may be a host, and the MDM 132 is also an IC and may be a device as that term is used in the PCIE standard. While the exemplary aspects consider operation over a PCIE-compliant interconnectivity bus 136, it is possible that the interconnectivity bus 136 may be High Speed ​​Interconnect (HSIC), Universal Asynchronous Receiver / Transmitter (UART), universal serial bus (USB), or the like. A more detailed depiction of some of the components of the mobile terminal 120 is provided with reference to Figure 1D. The mobile terminal 120 may include a receive path 138, a transmit path 140, an antenna 130 (mentioned above with reference to FIG. 1C), a switch 142, a modem processor 144, and an application processor 134 (also introduced above with reference to FIG. 1C). Optionally, a separate control circuit (not shown) may also be present with the CPU as is well understood. The application processor 134 and the modem processor 144 are connected by an interconnectivity bus 136. The application processor 134 and / or the control circuit (if any) may operate with a user interface 146 and a memory 148 with software 150 stored therein. The receiving path 138 receives information containing radio frequency (RF) signals from one or more remote transmitters provided by a base station (e.g., BS 124 of Figure 1B). A low-noise amplifier (not shown) amplifies the signal. A filter (not shown) minimizes broadband interference in the received signal. Down-conversion and digitization circuitry (not shown) down-converts the filtered and received signal into an intermediate or baseband frequency signal. The baseband frequency signal is then digitized into one or more digital streams. The receiving path 138 typically uses one or more mixing frequencies generated by a frequency synthesizer. The modem processor 144 may include a baseband processor (BBP) (not shown) that processes the digital receive signal to extract information or data bits conveyed in the signal.Thus, BBP is typically implemented in one or more digital signal processors (DSPs) within the modem processor 144 or as a separate IC as needed or desired. In an exemplary aspect, the receive path 138 may include data source circuitry responsible for incoming data from a remote network. In addition, there may be circuitry (not shown) within the modem processor 144 that acts as data source circuitry. For example, the control circuitry may generate control data, BIOS data, or the like for transmission to the application processor 134. With continued reference to Figure 1D, on the transmit side, modem processor 144 receives digital data, which may represent voice, data, or control information, from application processor 134, which is encoded for transmission. The encoded data is output to transmit path 140, where it is used by a modulator (not shown) to modulate a carrier signal at the desired transmission frequency. An RF power amplifier (not shown) amplifies the modulated carrier signal to a level suitable for transmission, and sends the amplified and modulated carrier signal to antenna 130 via switch 142. Collectively, modem processor 144, receive path 138, and transmit path 140 constitute the MDM 132 of Figure 1C (sometimes also referred to as a wireless modem). While MDM 132 is described specifically with respect to RF signals associated with cellular signals as provided under 5G, the present disclosure is not so limited.For example, wireless modems that use other wireless protocols may also benefit from the inclusion of aspects of the present disclosure. Thus, modems operating under standards such as BLUETOOTH®, various IEEE 802.11 standards, Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Long Term Evolution (LTE), and other wireless protocols may all benefit from the inclusion of aspects of the present disclosure. With continued reference to Figure 1D, a user may interact with the mobile terminal 120 through a user interface 146, such as a microphone, speaker, keypad, and display. The audio information encoded in the received signal is recovered by the BBP, and converted into an analog signal suitable for driving the speaker. The keypad and display enable the user to interact with the mobile terminal 120. For example, the keypad and display enable the user to enter a number to call, access address book information, or the like, and monitor call progress information. The memory 148 may have software 150 contained therein as noted above, which may affect exemplary aspects of the present disclosure. On conventional mobile terminals that have a PCIE interconnectivity bus (i.e., interconnectivity bus 136), the PCIE standard allows the interconnectivity bus 136 to be placed in a sleep or low-power mode. While placing the interconnectivity bus 136 in a sleep or low-power mode generally saves power, such sleep modes have the disadvantage of consuming relatively large amounts of power when resuming sleep mode. This power consumption is exacerbated by the asynchronous nature of the PCIE interconnectivity bus 136. That is, the first data may arrive at the modem processor 144 for transmission to the application processor 134 at a different time than the second data may be ready to be passed from the application processor 134 to the modem processor 144. This problem is not unique to the PCIE interconnectivity bus 136. Furthermore, these data may exist on different channels within the interconnectivity bus 136. Figure 2 illustrates the protocol stacks that may exist within the application processor 134 and modem processor 144 to provide an overview of the various types of channels and data source circuits that may exist. Specifically, there may be a top layer protocol 200 over which application-specific software 202A and 202B operate, respectively. Below the protocol stack is a modem host interface (MHI) protocol layer 204 over which drivers 206A and 206B operate. Below the protocol stack is a PCIE-specific protocol layer 208 with complex originating drivers 210 and endpoint drivers 212 that send and receive signals over bus interfaces 214 and 216, respectively, via bus 136. Circuits may exist at each level of the protocol stack that act as data source circuits that generate data to be sent to other terminals (e.g., application processor 134 to modem processor 144 or vice versa). Figure 3A illustrates a time versus link (e.g., PCIE link) power graph 300A that highlights how downlink data 302 may have a different transmission time than uplink data 304 for a particular channel in a particular time slot 306. Specifically, the interconnectivity bus 136 (FIG. 1C or 1D) starts in a sleep or low power state and transitions to an active power state with a transition 308 so that the downlink data 302 can be transmitted to the application processor 134. However, the downlink data 302 may not occupy the entire time slot 306, and the interconnectivity bus 136 may return to a low power state. However, subsequently, but still in the same time slot 306, uplink data 304 from the application processor 134 is sent to the modem processor 144. Thus, the interconnectivity bus 136 is transitioned again from a low power state to an active power state by the second transition 310. In the example aspect, the time slot 306 is approximately one millisecond (1 ms) in length.So, if two transitions (i.e., 308, 310) from low power to active power occur every 306 time slots, then thousands of 308, 310 transitions occur every second. Thousands of transitions. 308, 310 consumes a lot of power and reduces the battery life of the mobile terminal 120. The number of transitions in one second may be even worse than projected by graph 300A because graph 300A represents only one channel through the interconnectivity bus 136. If the interconnectivity bus 136 is a PCIE bus, there may be multiple channels as illustrated by the time versus link power graph 300B in Figure 3B. For example, there may be a BIOS channel 350, an MHI channel 352, a network traffic channel 354, and / or a control channel 356. Each of the channels 350, 352, 354, and 356 may have 358 up-transitions each for the uplink and downlink data with an intermediate low-power window. The cumulative number of 358 transitions results in a further drain on the battery life of the mobile terminal 120. Exemplary aspects of the present disclosure help reduce the number of transitions on an interconnectivity bus by combining or aggregating data across all channels from multiple data source circuits and transmitting the aggregated data within a single active window, thereby allowing the bus end to remain in a low-power state longer and with fewer interruptions. Before providing details of this consolidation, a more detailed overview of the PCIE system is provided with reference to FIGS. 4-6. In this case, Figure 4 illustrates a computing environment 400 with a host 402 coupled to a plurality of devices 404(1)-404(N) directly and to a plurality of second devices 406(1)-406(M) via a switch 408. The host 402 may include a PCIE origin complex (RC) 410 that includes bus interfaces (not illustrated directly) configured to couple to multiple PCIE buses 412(1)-412(N+1). The switch 408 communicates with the devices 406(1)-406(M) via the PCIE buses 414(1)-414(M). The devices 404(1)-404(N) and 406(1)-406(M) may or may not include PCIE endpoints. In the first example aspect, the computing environment 400 may be a single computing device such as a computer with the host 402 being the CPU and the devices 404(1)-404(N) and 406(1)-406(M) being internal components such as hard drives, disk drives, or the like.In a second example aspect, the computing environment 400 may be a computing device where the host 402 is an IC on the board and devices 404(1)-404(N) and 406(1)-406(M) are other ICs in the computing device. In a third example aspect, the computing environment 400 may be a computing device having an internal host 402 coupled to external devices 404(1)-404(N) and 406(1)-406(M) such as a server coupled to one or more external memory drives. Note that these aspects are not necessarily mutually exclusive as different devices may be IC, internal, or external relative to a single host 402. Figure 5 provides a block diagram of device 500 which may be one of devices 404(1)-404(N) or devices 406(1)-406(M). Specifically, device 500 acts as an endpoint in a PCIE system, and may, for example, be a memory device that includes a memory element 502 and a control circuit 504. Further, device 500 includes a PCIE hardware element 506 that includes a bus interface configured to couple to the PCIE bus. The PCIE hardware element 506 may include a physical layer (PHY) 508 that is, or works with, the bus interface to communicate over the PCIE bus. The control circuit 504 communicates with the PCIE hardware element 506 over the system bus 510. The PCIE hardware element 506 may further include a plurality of registers 512. The registers 512 may be conceptually separated into configuration registers and capability registers. Additionally, control circuitry 504 may work with timer 514 to carry out aspects of the present disclosure. Similarly, Figure 6 illustrates a host 600 that may be the host 402 of Figure 4. The host 600 may include an application processor 602 or another processor core that communicates with a memory element 604 that has an operating system 606 operating therewith. A system bus 608 connects the application processor 602 with the memory element 604 and the PCIE hardware (HW) or PCIE RC 610. The PCIE RC 610 may include a PHY 612 that operates with or is a bus interface configured to be coupled to the PCIE bus. The PCIE RC 610 further includes a plurality of registers 614 that track the configuration and capabilities of the connected endpoints. The application processor 602 or PCIE RC 610 may operate with a timer 616 according to exemplary aspects of the present disclosure. It should be appreciated that both device 500 and host 600 may have multiple data source circuits within them. For example, a transmit path (not illustrated) may be a data source circuit within device 500 and may be a control circuit 504 or an actual PHY 508. Similarly, host 600 may have multiple data source circuits within it. For example, a transmit path (not illustrated) that sends data to a modem for transmission to a remote network may be a data source circuit and may be a control circuit, an actual PHY 612, or the like. Each of these data source circuits may have a dedicated channel within the PCIE link or may share a channel with other data source circuits (e.g., all data source circuits in the MHI layer of the protocol stack may share a channel). A high-level flow diagram of the signal accumulation process is provided in Figure 7A with reference to process 700. Specifically, process 700 begins by receiving an indication that at least one first data source circuit has first data to send to a remote IC over the interconnectivity bus (block 702). For example, if a modem processor receives data from a remote network, the transmit line may indicate that there is data to send to the application processor over the PCIE bus. Process 700 proceeds by starting a first timer upon receipt of the signal (block 704). Continuing this example, the first timer is in the modem processor and is started upon receipt of data from the remote network. Process 700 continues by accumulating data across the multiple channels until the expiration of the first timer (block 706).This means that any additional data or commands generated in the modem are accumulated with data from the remote network while the timer is running. Process 700 continues by sending the data accumulated at the expiration of the first timer through the interconnectivity bus interface to the remote IC (block 708). All data on all channels that have accumulated while the timer is running is sent to the application processor. Because the data is sent as an accumulation burst, there are fewer low-power transitions on the PCIE bus, and the terminal is allowed to remain in a low-power state for a longer period. The reduced transitions reduce power consumption. Note that once data begins flowing from the modem to the application processor, the application processor can respond with data stored or accumulated on the application processor. In the first aspect, the application processor sends data to the initiating modem processor.In a second aspect, upon exiting the low power state, the application processor sends any pending data to any possible endpoints (e.g., all 404(1)-404(N) devices and 406(1)406(M) devices). By sending all pending data, the application processor maximizes the productivity of the active state and can prevent subsequent exits and entries from the low power state. The data may be interleaved with data from the modem or sent after the modem has finished transmitting but before transitioning to the low power state. A more detailed explanation of power savings through the communication bus control process is provided by process 750, defined in Figure 7B. Specifically, there are several service data transfer requests (block 752). This means that the data source circuit has indicated that there are data or commands to be transferred. The control circuit that has received the data transfer request determines whether the PCIE link is active (i.e., in state D0) (block 753). If the answer to block 753 is yes, the PCIE link is active, then data is sent by writing pending data (e.g., dequeue) to the target (block 754). This means that data or commands are sent over the PCIE link to the remote IC. However, if the answer to block 753 is no, the PCIE link is inactive (e.g., the PCIE link is in low-power or sleep mode), then the control circuit determines whether a buffer is unavailable or the data is time-critical (block 756).If the answer to any of the questions in block 756 is yes, then the control circuit wakes up the PCIE link to D0 (block 758) and data is written (block 754). However, if the answer to block 756 is no (that is, there is buffer space and the data is not time-critical), the control circuit queues the data if it is not already queued (block 760). Next, the control circuit determines whether any active PCIE timers are scheduled (that is, running) (block 762). If the answer to block 762 is yes, then the control circuit compares the timeout value associated with the current data with the buffer tolerance value (block 764). That is, whether the new data has a latency requirement shorter than the amount of time remaining on the running timer. If the answer is no, then the data is simply accumulated with the previous data and sent along with it. However, if the new data has a shorter latency (or there is no previous data from block 762), then the control circuit schedules (or adjusts / reschedules) the timer to wake up the PCIE link (block 766). With further reference to Figure 7B, at timeout, PCIE link wakeup is initiated (block 768), PCIE link wakeup (block 758), and data is sent (block 754). The net result of data accumulation according to exemplary aspects of the present disclosure is presented as a time versus link power graph 800 in Figure 8, wherein initially, data is accumulated (e.g., reserved) while the PCIE link remains in a low-power state (e.g., L1.2) (generally a time window 802). At time 804, the timer has expired, and the PCIE link wakes up to an active state beginning at time 806. While in the active state, all pending data is transferred. At time 808, the data has completed transfer and after a period of inactivity, the PCIE link transitions to a low-power state (e.g., L0s). After being idle until time 810, the PCIE link returns to the L1.2 low-power state. A latency tolerance report (LTR) is reported and updated. The LTR is defined in section 6.18 of the PCIE specification which specifically states: The LTR mechanism “enables Endpoints to report their service latency requirements for Memory Reads and Writes to the Root Complex, so that power management policies for central platform resources (such as main memory, RC internal interconnects, and snooping resources) can be implemented to take into account the Endpoint service requirements.” An exemplary aspect of the present disclosure allows a PCIE endpoint (e.g., device 500) to send an LTR message to a parent or root complex (e.g., parent 600) according to some guidelines. Specifically, the acceptable latency indicated by the LTR message from the PCIE endpoint is the lowest tolerable latency value associated with all PCIE MHI channels or services. The latency value, in an exemplary aspect, may generally range from tens of milliseconds to hundreds of milliseconds per MHI channel. Conversely, a low power threshold (e.g., L1.2 threshold) may be hundreds of microseconds. Therefore, it is sufficient for the PCIE link to enter L1.2 low power mode when CLKREQ# is released. In an exemplary aspect, the LTR message may be sent after all data transfers to the root complex have been completed. Alternatively, the LTR message may be sent during power-up initialization.Sending after data transfer may be appropriate if there is a change in the lowest tolerable latency value for the MHI channel. Responding to LTR reports, the host 600 can schedule an appropriate wake-up timer for MHI transfers. Specifically, the timeout setting must not exceed the endpoint's reported LTR value to help ensure all endpoint service latency constraints are met. Power saving techniques in computing devices through communication bus control according to the aspects disclosed herein may be provided or integrated into any processor-based device. Examples, without limitation, include set top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smart phones, session initiation protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, glasses, etc.).), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multicopters. More generally, Figure 9 is a system-level block diagram of an exemplary mobile terminal 900 such as a smart phone, a mobile computing device tablet, or the like. While mobile terminals having a PCIE bus are specifically considered to be capable of benefiting from the exemplary aspects of the present disclosure, it should be understood that the present disclosure is not so limited and may be useful in any system having an interconnectivity bus. With continued reference to Figure 9, the mobile terminal 900 includes an application processor 904 (sometimes referred to as a host) that communicates with a mass storage element 906 via a universal flash storage (UFS) bus 908. The application processor 904 may further be connected to a display 910 via a display serial interface (DSI) bus 912 and a camera 914 via a camera serial interface (CSI) bus 916. Various audio elements such as a microphone 918, a speaker 920, and an audio codec 922 may be coupled to the application processor 904 via a low-power multimedia interchip serial bus (SLIMbus) 924. In addition, the audio elements may communicate with each other via a SOUNDWIRE bus 926. A modem 928 may also be coupled to the SLIMbus 924 and / or the SOUNDWIRE bus 926. The modem 928 may further be connected to the application processor 904 via a PCI or PCIE bus 930 and / or a system power management interface (SPMI). bus 932. With continued reference to Figure 9, the SPMI bus 932 may also be coupled to a local area network (LAN or WLAN) IC (LAN IC or WLAN IC) 934, a power management integrated circuit (PMIC) 936, a companion IC (sometimes referred to as a bridge chip) 938, and a radio frequency IC (RFIC) 940. It should be understood that separate PCI buses 942 and 944 may also couple the application processor 904 to the companion IC 938 and the WLAN IC 934. The application processor 904 may then be connected to the sensor 946 via the sensor bus 948. The modem 928 and the RFIC 940 may communicate using the bus 950. With continued reference to Figure 9, RFIC 940 may be coupled to one or more RFFE elements, such as antenna tuner 952, switch 954, and power amplifier 956 via radio frequency front end (RFFE) bus 958. In addition, RFIC 940 may be coupled to envelope tracking power supply (ETPS) 960 via bus 962, and ETPS 960 may communicate with power amplifier 956. Collectively, the RFFE elements, including RFIC 940, may be considered as RFFE system 964. It should be understood that RFFE bus 958 may be formed from clock lines and data lines (not illustrated). Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in other computer-readable media and executed by a processor or other processing device, or a combination thereof. The devices described herein may be used in any circuit, hardware component, integrated circuit, or IC chip, for example. The memory disclosed herein may be of any type and size and may be configured to store any type of information desired. To clearly illustrate this interchangeability, the various illustrative components, blocks, modules, circuits, and steps have been described above in general terms in terms of their functionality.How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Experts may implement the described functionality in a variety of ways for any particular application, but such implementation decisions should not be construed as causing a departure from the scope of this disclosure. The various illustrative logic blocks, modules and circuits described in connection with the aspects disclosed herein may be implemented or performed with processors, Digital Signal Processors (DSPs), Integrated Circuits Application Specific Integer (ASIC), Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or a combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but alternatively, it may be a conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a number of microprocessors, one or more microprocessors in conjunction with a DSP core, or other configuration). The aspects disclosed herein may be embodied in hardware and in instructions stored in the hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Erasable Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, hard disks, removable disks, CDROMs, or other forms of computer-readable media known in the art. Example storage media are coupled to the processor so that the processor can read information from, and write information to, the storage media. Alternatively, the storage media may be an integral part of the processor. The processor and storage media may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage media may be located as discrete components in a remote station, base station, or server. It should also be noted that the operational steps described in one aspect of the example herein are described for illustrative purposes only. The operations described may be performed in many different sequences other than the sequence illustrated. Furthermore, the operations described in one operational step may actually be performed in several different steps. Furthermore, one or more of the operational steps discussed in the example aspects may be combined. It should be understood that the operational steps illustrated in the flowchart diagram are subject to many different modifications, as will be readily apparent to someone skilled in the art. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different technologies and techniques.For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the foregoing description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or combinations thereof. The description of the foregoing disclosure is provided to enable those skilled in the art to develop or use it. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applicable to other variations. Accordingly, the disclosure is not intended to be limited to the examples and designs described herein, but should be adapted to the broadest scope consistent with the principles and new features disclosed herein.

Claims

Claim:

1. An integrated circuit (IC) comprising: a timer; at least one data source circuit; an interconnectivity bus interface; and control circuitry configured to: receive an indication that the at least one data source circuit has data or a command to send to a second IC; start the timer upon receiving the indication; collect data across multiple channels until a timer expires; and send the collected data upon expiration of the timer via the interconnectivity bus interface to the second IC.

2. The IC according to claim 1, wherein the IC comprises a modem and the second IC comprises an application processor.

3. The IC according to claim 2, wherein the at least one data source circuitry comprises a wireless transceiver.

4. The IC according to claim 1, wherein the IC comprises an application processor and the second IC comprises a modem.

5. The IC according to claim 1, wherein the interconnectivity bus interface comprises a Peripheral Component Interconnect (PCI) Express (PCIE) bus interface.

6. The IC according to claim 1, wherein the at least one data source circuit comprises one of: a BIOS circuit, a modem hardware interface (MHI) circuit, or a packet generation circuit.

7. The IC according to claim 1, wherein the multiple channels comprise at least two of: a control channel, an MHI control channel, a BIOS channel, and a network traffic channel.

8. The IC according to claim 1, further comprising a buffer and wherein the control circuitry is configured to transmit accumulated data responsive to the buffer being full.

9. The IC according to claim 1, wherein the control circuit is configured to turn off the timer after transmitting the accumulated data.

10. The IC according to claim 1, wherein the control circuit is further configured to select an amount of time for the timer based on a first latency requirement associated with a channel associated with the at least one data source circuit.

11. The IC according to claim 10, wherein the control circuit is further configured to: receive a second indication that the second data source circuit has second data to transmit to the second IC, wherein the second data has a second latency requirement shorter than the first latency requirement; and adjust the timer based on the second latency requirement.

12. The IC according to claim 1, wherein the control circuit is configured to initiate a timer with a timer duration exceeding a single time slot of one of the multiple channels.

13. The IC according to claim 1, wherein the control circuitry is configured to: calculate a latency tolerance report (LTR) based on the lowest tolerable latency value; and send the LTR update to the second IC.

14. The IC according to claim 1, wherein the control circuit is further configured to receive second data from the second IC during or after transmitting the accumulated data.

15. The IC according to claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular telephone; a smartphone; a session initiation protocol (SIP) telephone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multicopter.

16. A communication system comprising: an interconnectivity bus; a first integrated circuit (IC) comprising: a first timer; at least one first data source circuit; a first interconnectivity bus interface coupled to the interconnectivity bus; and a first control circuit configured to: receive an indication that the at least one data source circuit sends to a second first IC; have first data to start the first timer upon receiving the indication; accumulate data across multiple channels until the first timer expires; and send the accumulated data upon expiration of the first timer through the first interconnectivity bus interface to a second IC; and a second IC comprising: a second interconnectivity bus interface coupled to the interconnectivity bus; and a second control circuit configured to: receive the accumulated data; and responsive to initially receiving the accumulated data, start sending second data to the first IC.

17. The communication system according to claim 16, wherein the interconnectivity bus comprises a Peripheral Component Interconnect (PCI) Express (PCIE) bus.

18. The communication system according to claim 16, wherein the first IC comprises a modem.

19. The communication system according to claim 18, wherein the second IC comprises an application processor.

20. The communication system according to claim 16, wherein the first IC further comprises a buffer and a first control circuit configured to transmit accumulated data responsive to the buffer being full.

21. A communication system according to claim 16, wherein the second IC 22.

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27. further comprises a second timer. The communication system according to claim 21, wherein the second control circuit is further configured to: receive a second indication that there is second data to be sent to the first IC; start the second timer upon receiving the second indication; and send the second data upon expiration of the second timer via a second interconnectivity bus interface to the first IC. The communication system according to claim 16, wherein the second control circuit is further configured to, responsive to initially receiving the accumulated data, begin sending additional data to the plurality of other ICs. The communication system according to claim 16, wherein the first control circuit is further configured to: calculate a latency tolerance report (LTR) based on the lowest tolerable latency value; and send the LTR update to the second IC.A communication system according to claim 24, wherein the first control circuit is configured to transmit an LTR update after transmitting accumulated data. A communication system according to claim 24, wherein the second control circuit is configured to set a first timer based on the LTR update. A method of controlling an interconnectivity bus, comprising: receiving an indication that at least one first data source circuit has first data to transmit to a remote integrated circuit (IC) via an interconnectivity bus; 5 starting the first timer after receiving the indication; accumulating data across the plurality of channels until the expiration of the first timer; and transmitting the accumulated data at the expiration of the first timer via an interconnectivity bus interface to the remote IC.

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