Voltage scaling method and electronic device

Abstract

The present application relates to the technical field of electronics, and provides a voltage adjustment method and an electronic device, for use in ensuing that power consumption of a processor can be reduced and performance thereof can be improved under both light load and heavy load. The method is applied to an electronic device comprising a processor and a power source supplying power to the processor. The method comprises: the processor sends power supply adjustment information to the power source according to a clock speed in a next time period; the power source determines, according to the power supply adjustment information, a power supply voltage V out used for supplying power to the processor. The power supply voltage V out decreases as the load current of the power source increases. V min≤V out≤V, V min is a minimum power supply voltage for the processor at the clock speed in the next time period, and V is a set power supply voltage for the processor at the clock speed in the next time period.

Description

A voltage regulation method and electronic device

[0001] This application claims priority to Chinese Patent Application No. 201911252945.1, filed with the State Intellectual Property Office of China on December 9, 2019, entitled "A Voltage Regulation Method and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of electronic technology, and in particular to a voltage regulation method and an electronic device. Background Technology

[0003] Moore's Law, or Circuit Law, is a law that reveals the speed of progress in information technology. It states that, with a constant price, the number of components that can be placed on an integrated circuit roughly doubles every 18-24 months, and performance also doubles. In other words, the computer performance that can be bought for one dollar more than doubles every 18-24 months.

[0004] In recent years, with the continuous increase in the operating frequency and integration level of integrated circuits, the power consumption of integrated circuits has increased rapidly, making it difficult for integrated circuits to continue to apply Moore's Law. This has led to problems such as the inability to improve processor performance and integration level, and increased cooling costs.

[0005] To address the aforementioned issues, Dynamic Voltage and Frequency Scaling (DVFS) technology is typically used to adjust the power supply voltage to the processor. This involves reducing the processor's clock speed and supply voltage under light loads, and increasing these voltages under heavy loads, thereby reducing processor power consumption. However, under heavy processor loads, DVFS cannot reduce the processor's supply voltage; therefore, its effectiveness in reducing power consumption is not significant.

[0006] Summary of the Invention

[0007] This application provides a voltage regulation method and an electronic device to ensure that the processor can achieve reduced power consumption and improved performance under both light and heavy load conditions.

[0008] To address the aforementioned technical problems, the embodiments of this application provide the following technical solutions:

[0009] In a first aspect, embodiments of this application provide a voltage regulation method applied to an electronic device having a processor and a power supply supplying power to the processor. The method includes: the processor sending power supply regulation information to the power supply according to the next time period's clock frequency, the power supply regulation information including a set power supply voltage V for the next time period's clock frequency, where the next time period's clock frequency refers to a clock frequency predicted based on the current clock frequency; and the power supply supplying the processor with the set power supply voltage V based on the set power supply voltage V for the next time period's clock frequency and a set voltage slope R for the next time period's clock frequency. out Voltage slope refers to the rate at which the supply voltage V increases as the load current of the power supply increases. out The rate of descent. The supply voltage V. out It decreases as the load current increases. V min ≤V out ≤V, V min This is the minimum supply voltage required for the processor to operate normally under increased load current during the next period of clock frequency operation.

[0010] In the method provided in this application, the next time period clock frequency refers to the clock frequency predicted based on the current clock frequency, and the power supply provides the processor with a power supply voltage V based on the set supply voltage V of the next time period clock frequency and the set voltage slope R of the next time period clock frequency. out This adapts to the processor's next clock frequency. Furthermore, because the load current periodically increases from its minimum to its maximum, in existing technologies where the power supply outputs a constant voltage to the load terminal, the load terminal voltage passively decreases as the load current increases. The method provided in this application, however, actively controls the power supply output voltage V. out The voltage decreases as the load current increases, resulting in a decrease in the supply voltage V output by the power supply when the load current begins to rise. out The active voltage decreases as the load current increases. At this time, the supply voltage V... out The supply voltage V is less than the processor's set supply voltage V at the next clock frequency and greater than or equal to the minimum supply voltage V required for normal operation under increased load current at the processor's clock frequency in the next clock frequency period. min Therefore, compared with the prior art, the power supply voltage V provided by the power source in the method provided in this application is significantly higher. ou This method reduces processor power consumption while ensuring normal processor operation, thereby improving processor performance. Furthermore, since a higher processor clock speed results in a higher processor load, the method provided in this application ensures that regardless of the processor load, the power supply can provide power to the processor at a voltage lower than the current clock speed setting when the load current increases, thus enabling the processor to operate normally with low power consumption.

[0011] In some possible implementations, before the processor sends power supply adjustment information to the power supply based on the clock speed for the next time period, the method further includes: the processor predicting the load for the next time period based on the current load, and determining the clock speed for the next time period based on the load for the next time period. For example, a table mapping load to clock speed is stored in the motherboard or the processor's built-in memory, and the clock speed for the next time period is looked up in the table based on the predicted load for the next time period.

[0012] In some possible implementations, the above method further includes: if the processor determines that the clock frequency for the next time period is not equal to the current clock frequency, setting the current clock frequency equal to the clock frequency for the next time period. Given that power supply voltage regulation and clock frequency regulation are interdependent, setting the current clock frequency equal to the clock frequency for the next time period when the processor determines that the clock frequency for the next time period is not equal to the current clock frequency includes: if the processor determines that the clock frequency for the next time period is less than the current clock frequency, before sending power supply regulation information to the power supply based on the clock frequency for the next time period, setting the current clock frequency equal to the clock frequency for the next time period; if the processor determines that the clock frequency for the next time period is greater than the current clock frequency, the power supply provides a power supply voltage V to the processor based on the set power supply voltage V and the set voltage slope R of the clock frequency for the next time period. out Then, the processor sets the current clock speed to be equal to the clock speed for the next time period.

[0013] In some possible implementations, the aforementioned supply voltage V out =VI*R, where I is the load current of the power supply, determined by the supply voltage V. out The calculation formula shows that the supply voltage V out The voltage slope R of the processor in the next time period, the set supply voltage V in the next time period, and the load current I are determined. Since the voltage slope refers to the rate at which the supply voltage decreases as the load current of the power supply increases, the product of the set voltage slope R and the load current I in the next time period essentially represents the active decrease in supply voltage when the load current of the power supply increases. As long as this active decrease is greater than or equal to the maximum passive decrease in load-side voltage under increased load current conditions in the prior art, the supply voltage V can be kept within acceptable limits. out It is always greater than or equal to the minimum supply voltage V that the processor operates normally under increased load current during the next operating period. min .

[0014] In some possible implementations, the set supply voltage V for the next time period's main frequency can be provided by the processor, while the set voltage slope R for the next time period's main frequency can exist in the power supply or be provided by the processor. When the processor only provides the set supply voltage V for the next time period's main frequency to the power supply, the processor does not need to dynamically set the set voltage slope R for the next time period's main frequency within the power supply using the processor-power supply communication interface, thereby effectively reducing communication latency and voltage regulation latency, and improving voltage regulation speed.

[0015] In some possible implementations, the processor sending power supply adjustment information to the power supply based on the next time period's clock frequency includes: the processor looking up the set supply voltage V for the next time period's clock frequency from a target correspondence, and then sending the set supply voltage V for the next time period's clock frequency to the power supply. Here, the target correspondence is the correspondence between the processor's clock frequency, the set supply voltage, and the set voltage slope. Of course, the target correspondence can also be the correspondence between the processor's clock frequency and the set supply voltage. In this case, the processor only needs to look up the set supply voltage for the next time period's clock frequency from the target correspondence and send it to the power supply, thus reducing communication latency and voltage regulation latency, and shortening the voltage regulation time.

[0016] In some possible implementations, when the processor only supplies the power supply with the set voltage V for the next clock frequency, the aforementioned set voltage slope R for the next clock frequency can exist in the power supply as a constant voltage slope. This can be stored in a saved manner. The constant voltage slope is the minimum voltage slope R allowed by the set power supply voltage at each clock frequency. min R min >0. Because R min A value greater than 0 ensures that the power supply always provides the processor with a voltage less than or equal to the set supply voltage, regardless of the processor's load or clock frequency, resulting in lower power consumption. Furthermore, since the constant voltage slope is the minimum value R of the measured voltage slope at each clock frequency... min Therefore, by using a constant voltage slope as the set voltage slope R for the next period's main frequency, the product of the set voltage slope and the load current for the next period's main frequency can be controlled, ensuring normal processor operation and preventing issues caused by a large constant voltage slope leading to increased load current and excessive processor voltage V. out An error occurred that prevented the system from functioning properly.

[0017] In some possible implementations, when the set voltage slope R of the next time period main frequency is provided by the processor, the power supply adjustment information includes not only the set power supply voltage V of the next time period main frequency, but also the set voltage slope R of the next time period main frequency.

[0018] In some possible implementations, when the set voltage slope R of the next time period's main frequency is provided by the processor, the processor sending power supply adjustment information to the power supply based on the next time period's main frequency includes: the processor looking up the set power supply voltage V and the set voltage slope R of the next time period's main frequency from a target correspondence based on the next time period's main frequency, and sending the set power supply voltage V and the set voltage slope R of the next time period's main frequency to the power supply. The target correspondence is the correspondence between the processor's main frequency, the set power supply voltage, and the set voltage slope.

[0019] In one possible implementation, the set voltage slope of the processor at each clock frequency is the voltage slope allowed by the set supply voltage of the processor at each clock frequency. In other words, the set voltage slope of each clock frequency in the above target correspondence is the voltage slope allowed by the set supply voltage of the processor at each clock frequency. At this time, the set supply voltage V in the next time period has a good match with the set voltage slope R in the next time period, ensuring that the supply voltage V supplied by the power supply to the processor... out While ensuring the processor operates normally, optimize the processor's power consumption.

[0020] In one possible implementation, the voltage slope of the processor at all clock frequencies is equal to a constant voltage slope. The constant voltage slope is the minimum value R of the voltage slope allowed by the processor's set supply voltage at each clock frequency. min R min >0. In other words, the set voltage slope for all frequencies in the above target correspondence is equal to a constant voltage slope. When the processor first sends the set supply voltage V and the set voltage slope R for the next frequency period to the power supply, the power supply can save the set voltage slope R for the next frequency period in the form of a constant voltage slope. Since the set voltage slope for all frequencies in the target correspondence is equal to a constant voltage slope, the power supply essentially saves the set voltage slope for all frequencies in the target correspondence in the form of a constant voltage slope. When the power supply needs to adjust the supply voltage V supplied to the processor again... out At this time, the processor only needs to query the set supply voltage R of the next time period's main frequency from the target mapping relationship, and send the set supply voltage V of the next time period's main frequency to the power supply, so that the power supply adjusts the reference voltage according to the set supply voltage V of the next time period's main frequency. In this process, the processor only needs to dynamically set the reference voltage in the power supply according to the next time period's main frequency through the bus interface to reduce communication latency and voltage adjustment latency, thereby shortening the voltage adjustment time. In addition, since the constant voltage slope is the minimum value R of the voltage slope allowed by the processor at each main frequency's set supply voltage. min R min A value greater than 0 ensures that the power supply voltage V to the processor remains constant regardless of the load or clock speed.out Always satisfy V min ≤V out ≤V, thus enabling the processor to have low power consumption while operating normally.

[0021] In some possible implementations, the voltage slope R allowed by the set supply voltage of the processor at each clock frequency is... (i) =R max(i) -ΔR (i) R max(i) ΔR is the maximum voltage slope of the set supply voltage for the processor at each clock frequency. (i) This represents the voltage slope margin for the processor at each clock frequency. At this point, due to R... max(i) This refers to the maximum voltage slope of the power supply voltage for the processor at each clock frequency. Therefore, when the load current increases, the power supply voltage V supplied to the processor... out To get as close to V as possible min This ensures the processor operates at lower power consumption. Furthermore, when R... (i) =R max(i) At this time, when the load current increases, it can easily lead to an increase in the supply voltage V. out Slightly lower than V min This causes the processor to malfunction. Based on this, it is possible to... (The sentence is incomplete and requires more context to translate accurately.) max(i) This is achieved by subtracting the voltage slope margin from the base voltage, thereby ensuring that the processor operates normally with lower power consumption.

[0022] In one possible implementation, the set supply voltage for each clock frequency in the aforementioned processor is V. (i) That is, the set supply voltage for each main frequency in the above target correspondence is V. (i) V (i) =V min(i) +ΔV (i) V min(i) ΔV represents the minimum supply voltage required for the processor to operate normally at each clock frequency under increased load current. (i) This represents the power supply voltage margin for the processor at each clock frequency. At this point, the set power supply voltage V for the next clock frequency that the processor is looking for is greater than the minimum power supply voltage Vmin that the processor will operate normally under increased load current conditions at the next clock frequency. min Slightly larger, causing the power supply voltage V to the processor to be supplied by the power supply. out It can ensure that the processor operates normally at low power consumption.

[0023] In one possible implementation, before the processor sends power supply adjustment information to the power supply according to the next time period's clock frequency, the method further includes: the processor calibrating the target correspondence based on performance difference information, so that the calibrated target correspondence matches the processor included in the electronic device, thereby improving the reliability and accuracy of voltage adjustment. This performance difference information can be detected by a critical path monitor (CPM) circuit built into the processor. The CPM circuit is used to simulate the timing critical path of the reference processor. The delay level (such as delay time) or oscillation frequency determined by the CPM circuit is the performance difference information. When the processor's delay level or oscillation frequency varies under different environments, the minimum supply voltage of the processor at a given clock frequency will also vary.

[0024] In one possible implementation, to facilitate the processor's calibration of the target correspondence based on performance difference information, a pre-stored correspondence between the performance differences of multiple processors and their minimum supply voltage differences should be established, either without considering temperature effects or considering temperature effects and establishing a correspondence between the performance differences of multiple processors at multiple temperature levels and their minimum supply voltage differences. For example, when the target correspondence is the target correspondence of a benchmark processor, the performance difference of each processor can be represented by its latency level (e.g., latency time) or oscillation frequency, or indirectly by the latency difference or oscillation frequency difference between the processor and the benchmark processor at the same voltage. The minimum supply voltage difference corresponding to each processor's performance difference refers to the minimum supply voltage difference between the processor and the benchmark processor at the same clock frequency. The benchmark processor is the processor with the worst performance among the multiple processors. That is, the benchmark processor is the processor with the highest minimum supply voltage among the multiple processors at the same clock frequency.

[0025] When the influence of temperature is not considered, the performance difference information detected by the CPM circuit, and the processor calibrating the target correspondence based on the performance difference information to match the target correspondence with the processors included in the electronic device, includes: the processor searching for the lowest power supply voltage difference from the correspondence between various processor performance differences and the lowest power supply voltage difference based on the performance difference information, and calibrating the set power supply voltage corresponding to each main frequency in the target correspondence based on the lowest power supply voltage difference, so that the calibrated target correspondence matches the processors included in the electronic device.

[0026] When considering the influence of temperature, the CPM circuit detects performance difference information. The processor then calibrates the target correspondence based on this performance difference information to match the processors included in the electronic device. This process includes: the processor searching for the correspondence between the performance differences and minimum supply voltage differences of multiple processors at multiple temperature levels based on the current temperature; searching for the minimum supply voltage difference that matches the current performance difference information based on the corresponding correspondence between the performance differences and minimum supply voltage differences of multiple processors at the current temperature level based on the performance difference information; and calibrating the set supply voltage corresponding to each main frequency in the target correspondence based on the minimum supply voltage difference that matches the performance difference information, so that the calibrated target correspondence matches the processors included in the electronic device.

[0027] In one possible implementation, the aforementioned electronic device includes a storage medium. This storage medium can exist independently of the processor or be integrated within the processor. The aforementioned target-to-target correspondence can be stored directly or indirectly in this storage medium in various forms. Of course, the storage medium can also store correspondences between various processor performance differences and minimum supply voltage differences, or correspondences between various processor performance differences at multiple temperature levels and minimum supply voltage differences. For example, the correspondences between various processor performance differences and minimum supply voltage differences can be stored in the storage medium in the form of a relational table or a functional expression. Similarly, the correspondences between various processor performance differences at multiple temperature levels and minimum supply voltage differences can also be stored in the storage medium in the form of a relational table or a functional expression.

[0028] In one possible implementation, the aforementioned target correspondence is stored in the aforementioned storage medium. This target correspondence is the target correspondence of a reference processor. The reference processor is the processor with the highest minimum supply voltage among multiple processors at the same clock frequency; that is, the reference processor is the worst-performing processor among the multiple processors. In this case, the set supply voltage and set voltage slope corresponding to each clock frequency in the target correspondence can satisfy the voltage adjustment of multiple processors. Therefore, the target correspondence of the reference processor has broad applicability. It should be understood that multiple processors can be distinguished according to manufacturing processes, aging levels, etc. Regardless of the difference in manufacturing processes or aging levels, it will ultimately be reflected in performance difference information. For example, for processors of the same model, slight differences in manufacturing processes between different batches of processors result in different batches of the same model of processors belonging to different categories.

[0029] In one possible implementation, the aforementioned target mapping relationship is stored in a storage medium. This target mapping relationship refers to the target mapping relationship of the processor included in the electronic device where the storage medium is located. This target mapping relationship can be determined through debugging after the electronic device leaves the factory and then stored in the storage medium.

[0030] In one possible implementation, the aforementioned electronic device further includes a storage medium. This storage medium stores the target correspondence of the reference processor across multiple temperature ranges. The definition of the reference processor is as described above and will not be detailed here. Before the processor sends power supply adjustment information to the power supply based on the next time period's clock frequency, the method further includes: the processor searching for the target correspondence of the reference processor across multiple temperature ranges based on the current temperature. This target correspondence is the target correspondence of the reference processor at the temperature range where the current temperature is located. At this point, calibrating the searched target correspondence can improve the matching between the calibrated target correspondence and the processor.

[0031] In one possible implementation, without considering the influence of temperature, before the electronic device is powered on, the CPM circuit detects performance difference information, and the processor sends power supply adjustment information to the power supply according to the main frequency of the next time period, the method further includes: the processor searching for a target correspondence that matches the processors included in the electronic device from a target correspondence of multiple processors based on the performance difference information. The difference information of the processor corresponding to this target correspondence has a good match with the difference information tested by the CPM circuit.

[0032] When considering the influence of temperature, when the electronic device is powered on, the CPM circuit detects performance difference information. Before the processor sends power supply adjustment information to the power supply according to the main frequency of the next period, the method further includes: the processor searching for the target correspondence of multiple processors at multiple temperature levels based on the current temperature from the target correspondence of multiple processors at multiple temperature levels; and searching for the target correspondence of the processor included in the electronic device from the target correspondence of multiple processors at the current temperature level based on the performance difference information.

[0033] In one possible implementation, to facilitate the processor's search for a target correspondence matching the processors included in the electronic device, the electronic device includes a storage medium. Without considering the influence of temperature, the electronic device further includes a storage medium that can, before leaving the factory, utilize a CPM circuit to determine the performance differences between multiple processors and the target correspondence between them, establish the relationship between the two, and store the performance differences and target correspondences of the multiple processors in the storage medium. Considering the influence of temperature, before leaving the factory, a CPM circuit can be used to determine the performance differences between multiple processors at multiple temperature levels and the target correspondences of the multiple processors at multiple temperature levels, establish the interdependence between the performance differences and target correspondences of the multiple processors at multiple temperature levels, and then store the performance differences and target correspondences of the multiple processors at multiple temperature levels in the storage medium.

[0034] Secondly, this application provides an electronic device. The electronic device includes: a processor, configured to send power supply adjustment information to a power supply according to the main frequency of the next time period; the power supply adjustment information includes a set power supply voltage V for the main frequency of the next time period, wherein the main frequency of the next time period refers to a main frequency predicted based on the current main frequency; and a power supply, configured to provide a power supply voltage V to the processor according to the set power supply voltage V for the main frequency of the next time period and a set voltage slope R for the main frequency of the next time period. out Voltage slope refers to the rate at which the supply voltage V increases as the load current of the power supply increases. out The rate of descent; the supply voltage V out V decreases as the load current of the power supply increases; min ≤V out ≤V, V min This is the minimum supply voltage required for the processor to operate normally under increased load current during the next period of clock frequency operation.

[0035] In one possible implementation, the processor is further configured to predict the load for the next period based on the current load before sending power supply adjustment information to the power supply according to the next period's main frequency, and determine the main frequency for the next period based on the load for the next period.

[0036] In some possible implementations, the processor is further configured to set the current clock frequency equal to the clock frequency of the next time period if the processor determines that the clock frequency of the next time period is not equal to the current clock frequency. For example, the processor is further configured to set the current clock frequency equal to the clock frequency of the next time period before sending power supply adjustment information to the power supply based on the clock frequency of the next time period if it determines that the clock frequency of the next time period is less than the current clock frequency. The power supply is configured to provide a power supply voltage V to the processor based on the set power supply voltage V of the clock frequency of the next time period and the set voltage slope R of the clock frequency of the next time period. outThen, the processor is specifically used to determine that the clock frequency in the next time period is greater than the current clock frequency, and to set the current clock frequency to be equal to the clock frequency in the next time period.

[0037] In one possible implementation, the aforementioned supply voltage V out =VI*R, where I is the load current of the power supply.

[0038] In one possible implementation, the processor is specifically used to look up the set supply voltage V of the next time period's main frequency from the target correspondence based on the main frequency of the next time period, and send the set supply voltage V of the next time period's main frequency to the power supply. The target correspondence is either a correspondence between the processor's main frequency, the set supply voltage, and the set voltage slope, or a correspondence between the processor's main frequency and the set supply voltage.

[0039] In one possible implementation, the voltage slope for the next clock frequency mentioned above exists in the power supply as a constant voltage slope. This constant voltage slope is the minimum value R of the voltage slope allowed by the processor's set supply voltage at each clock frequency. min R min >0.

[0040] In one possible implementation, the aforementioned power supply regulation information also includes the set voltage slope R of the main frequency for the next time period.

[0041] In one possible implementation, the processor is specifically used to look up the set supply voltage V and the set voltage slope R of the next time period's main frequency from the target correspondence based on the main frequency of the next time period, and then send the set supply voltage V and the set voltage slope R of the next time period's main frequency to the power supply. The target correspondence is the correspondence between the processor's main frequency, the set supply voltage, and the set voltage slope.

[0042] In one possible implementation, the set voltage slope of the processor at each clock frequency is the voltage slope allowed by the set supply voltage of the processor at each clock frequency.

[0043] In one possible implementation, the voltage slope of the processor at all clock frequencies is equal to a constant voltage slope. This constant voltage slope is the minimum value R of the voltage slope allowed by the processor's set supply voltage at each clock frequency. min R min >0.

[0044] In one possible implementation, the voltage slope allowed by the set supply voltage of the processor at each clock frequency is R. (i) R (i) =R max(i) -ΔR (i) R max(i)ΔR is the maximum voltage slope of the set supply voltage for the processor at each clock frequency. (i) This is the voltage slope margin for the processor at each clock frequency.

[0045] In one possible implementation, the processor described above has a set supply voltage V at each clock frequency. (i) =V min(i) +ΔV (i) V min(i) ΔV represents the minimum supply voltage required for the processor to operate normally at each clock frequency under increased load current. (i) This refers to the power supply voltage margin for the processor at each clock frequency.

[0046] In one possible implementation, the processor is further configured to calibrate the target correspondence based on performance difference information before sending power supply adjustment information to the power supply according to the main frequency of the next time period, so that the calibrated target correspondence matches the processor included in the electronic device.

[0047] In one possible implementation, without considering the effect of temperature, the processor is specifically used to find the minimum power supply voltage difference from the correspondence between multiple processor performance differences and minimum power supply voltage differences based on performance difference information, and to calibrate the set power supply voltage corresponding to each main frequency in the target correspondence based on the minimum power supply voltage difference, so that the calibrated target correspondence matches the processor included in the electronic device.

[0048] Taking temperature into account, the processor is specifically used to find the correspondence between the performance differences of multiple processors and the minimum supply voltage differences at the current temperature from the correspondence between the performance differences of multiple processors at multiple temperature levels. Based on the performance difference information, it finds the minimum supply voltage difference that matches the current performance difference information from the correspondence between the performance differences of multiple processors and the minimum supply voltage differences at the current temperature level. Based on the minimum supply voltage difference that matches the performance difference information, it calibrates the set supply voltage corresponding to each main frequency in the target correspondence, so that the calibrated target correspondence matches the processors included in the electronic device.

[0049] In one possible implementation, the aforementioned electronic device includes a storage medium. This storage medium can exist independently of the processor or be integrated within the processor. The aforementioned target-to-target correspondence can be stored directly or indirectly in this storage medium in various forms. Of course, the storage medium can also store correspondences between various processor performance differences and minimum supply voltage differences, or correspondences between various processor performance differences at multiple temperature levels and minimum supply voltage differences. For example, the correspondences between various processor performance differences and minimum supply voltage differences can be stored in the storage medium in the form of a relational table or a functional expression. Similarly, the correspondences between various processor performance differences at multiple temperature levels and minimum supply voltage differences can also be stored in the storage medium in the form of a relational table or a functional expression.

[0050] In one possible implementation, the aforementioned target mapping is stored in a storage medium, and the target mapping is the target mapping of a reference processor. This reference processor is the processor with the highest minimum supply voltage among multiple processors operating at the same clock frequency.

[0051] In one possible implementation, the aforementioned target mapping relationship is stored in a storage medium. This target mapping relationship refers to the target mapping relationship of the processor included in the electronic device where the storage medium is located. This target mapping relationship can be determined through debugging after the electronic device leaves the factory and then stored in the storage medium.

[0052] In one possible implementation, the aforementioned electronic device further includes a storage medium. This storage medium stores a target mapping relationship of a reference processor across multiple temperature ranges. The reference processor is the processor with the highest minimum supply voltage among multiple processors operating at the same clock frequency. The processor is also used to look up the target mapping relationship from the reference processor's target mapping relationship across multiple temperature ranges based on the current temperature before sending power adjustment information to the power supply according to the clock frequency for the next time period. This target mapping relationship is the target mapping relationship of the reference processor at the temperature range where the current temperature is located.

[0053] In one possible implementation, without considering the effect of temperature, the processor is further configured to, before sending power supply adjustment information to the power supply according to the clock frequency of the next time period, search for a target correspondence that matches the processor included in the electronic device from a target correspondence of multiple processors based on performance difference information. Considering the effect of temperature, the processor is further configured to, before sending power supply adjustment information to the power supply according to the clock frequency of the next time period, search for a target correspondence of multiple processors at the current temperature level from a target correspondence of multiple processors at multiple temperature levels; and search for a target correspondence that matches the processor included in the electronic device from a target correspondence of multiple processors at the current temperature level based on performance difference information.

[0054] In one possible implementation, the aforementioned electronic device includes a storage medium. Without considering the effects of temperature, the storage medium stores performance difference information for multiple processors and target correspondences for these processors, wherein the performance difference information and target correspondences are interdependent. Considering the effects of temperature, performance difference information for multiple processors at multiple temperature levels and target correspondences for these processors at multiple temperature levels are stored in the storage medium, and these performance difference information and target correspondences for these processors at multiple temperature levels are interdependent.

[0055] Thirdly, this application also provides a processor. The processor includes one or more modules for implementing the steps of the first aspect described above, which may correspond to the respective steps executed by the processor in the method of the first aspect described above.

[0056] Fourthly, this application provides a power supply. The power supply includes one or more modules for implementing the steps performed by the power supply in the first aspect described above, wherein the one or more modules may correspond to the respective steps performed by the power supply in the method of the first aspect described above.

[0057] Fifthly, this application provides a terminal device. The terminal device includes a processor and a power supply. The processor is configured to perform steps executed by the processor as described in the first aspect or any possible implementation of the first aspect, and the power supply is configured to perform steps executed by the power supply as described in the first aspect or any possible implementation of the first aspect.

[0058] In some possible implementations, the aforementioned terminal device also includes a storage medium for storing the correspondence between computer programs and targets.

[0059] In a sixth aspect, this application provides a communication device including a processor and a power supply, the processor being configured to perform steps performed by the processor as described in the first aspect or any possible implementation of the first aspect, and the power supply being configured to perform steps performed by the power supply as described in the first aspect or any possible implementation of the first aspect.

[0060] In some possible implementations, the aforementioned communication device also includes a storage medium for storing the correspondence between computer programs and targets.

[0061] In a seventh aspect, this application also provides a chip. The chip includes a processor and a communication interface coupled to a communication interface. The processor is used to run computer programs or instructions to implement the steps performed by the processor as described in the first aspect or any possible implementation of the first aspect.

[0062] In one possible implementation, the chip also includes a memory for storing computer programs or instructions and target mappings.

[0063] Eighthly, this application also provides a chip. The chip includes a processor and a communication interface coupled to a communication interface. The processor is used to run computer programs or instructions to implement the steps performed by a power source as described in the first aspect or any possible implementation of the first aspect.

[0064] In one possible implementation, the chip also includes a memory for storing computer programs.

[0065] Any of the devices, computer storage media, computer program products, chips, or communication systems provided above are used to execute the corresponding methods provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects of the corresponding solutions in the corresponding methods provided above, and will not be repeated here. Attached Figure Description

[0066] Figure 1 is a schematic diagram of the structure of the electronic device provided in an embodiment of this application;

[0067] Figure 2 is a schematic diagram of the connection structure between the processor and the power supply in an embodiment of this application;

[0068] Figure 3 is a system architecture diagram of a vehicle communication system provided in an embodiment of this application;

[0069] Figure 4 is a schematic flowchart of the voltage regulation method provided in the embodiment of this application;

[0070] Figure 5 is a schematic flowchart of the voltage regulation method provided in the embodiment of this application (II).

[0071] Figure 6 is a schematic diagram of the transient process of the power supply load;

[0072] Figure 7 is a schematic diagram of the power supply loadline characteristics;

[0073] Figure 8 is a schematic diagram illustrating the mechanism by which DVFS technology reduces power consumption;

[0074] Figure 9 is a comparison diagram of the method of this application, DVFS technology, and fixed voltage power supply;

[0075] Figure 10 shows the processor's clock speed and voltage slope curves;

[0076] Figure 11 is a schematic flowchart of the voltage regulation method provided in the embodiment of this application;

[0077] Figure 12 is a schematic flowchart of the voltage regulation method provided in the embodiment of this application;

[0078] Figure 13 is a schematic flowchart of the voltage regulation method provided in the embodiment of this application;

[0079] Figure 14 shows the voltage slope of the supply voltage under rated mode;

[0080] Figure 15 shows the voltage slope under different power consumption modes;

[0081] Figure 16 is a schematic diagram of the structure of a device provided in an embodiment of this application;

[0082] Figure 17 is a schematic diagram of a voltage regulation device provided in an embodiment of this application;

[0083] Figure 18 is a schematic diagram of another voltage regulation device provided in an embodiment of this application;

[0084] Figure 19 is a schematic diagram of another voltage regulation device provided in an embodiment of this application;

[0085] Figure 20 is a schematic diagram of the chip structure provided in an embodiment of this application. Detailed Implementation

[0086] Before introducing the embodiments of this application, the relevant terms involved in the embodiments of this application are first explained as follows:

[0087] Dynamic Voltage and Frequency Scaling (DVFS) technology refers to dynamically adjusting the chip's operating frequency and voltage based on the computing power requirements of the applications running on the chip (for the same chip, the higher the frequency, the higher the required voltage), thereby achieving energy saving. Specifically, it reduces the processor's clock speed and supply voltage when the processor load is light, and increases the processor's clock speed and supply voltage when the processor load is heavy, thus reducing processor power consumption.

[0088] Intel Turbo Boost Technology, also known as Turbo Boost, is a multi-core CPU overclocking (OC) technology. When a CPU core fails to reach its temperature, current, and power consumption limits, Turbo Boost automatically allows certain active cores to run above their rated clock speed, improving processor performance and handling peak loads.

[0089] The Basic Input Output System (BIOS) is a set of programs embedded in a read-only memory image chip on the computer's motherboard. It contains the computer's most important basic input / output programs, power-on self-test programs, and system startup programs.

[0090] Adaptive voltage scaling (AVS) is a closed-loop power management technology that allows for real-time, continuously adjustable supply voltage. AVS can be implemented using a critical path monitor (CPM) circuit. The CPM circuit simulates the timing critical path of a reference processor to determine performance differences such as delay levels or oscillation frequencies. Based on these performance differences, the circuit's supply voltage is adaptively adjusted to ensure that the delay level or oscillation frequency meets system requirements while minimizing voltage.

[0091] Voltage Identification (VID), also known as VID encoding, is an encoding that represents a voltage value; in essence, it is a digitized voltage value.

[0092] A voltage regulator module (VRM) is a device that provides a suitable supply voltage to a microprocessor; it is also called a VRM power supply. The VRM power supply can identify VID codes and adjust the output constant voltage supply voltage to ensure that the output constant voltage supply voltage matches the voltage value represented by the VID code. Specifically, the VRM power supply integrates an 8-bit VID code, representing 256 different voltage values. The processor sends an 8-bit VID code to the VRM power supply, which can then use its integrated 8-bit VID code to identify the VID code sent by the processor and thus determine the supply voltage.

[0093] The load line, also known as the load line, refers to the characteristic curve of the supply voltage output by the VRM power supply decreasing linearly as the load current increases.

[0094] The voltage drop slope, also known as the loadline value, represents the rate at which the supply voltage decreases linearly as the load current of a power supply such as a VRM increases. A larger loadline value indicates a faster rate at which the supply voltage from the VRM decreases linearly with increasing load current. Conversely, a smaller loadline value indicates a slower rate at which the supply voltage from the VRM decreases linearly with increasing load current.

[0095] A phase-locked loop (PLL) is a typical feedback control circuit that uses an externally input reference signal to control the frequency and phase of an internal oscillation signal, achieving automatic tracking of the output signal frequency to the input signal frequency. It is generally used in closed-loop tracking circuits.

[0096] A digital-to-analog converter (DAC) is a device that converts digital signals into analog signals (in the form of current, voltage, or charge).

[0097] The Power Management Bus (PMBus) is a bus that supports open standard digital power management protocols. These open standard protocols facilitate communication with power converters or other devices by defining transport and physical interfaces as well as command languages.

[0098] To facilitate a clear description of the technical solutions in the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are only used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and the terms "first" and "second" are not necessarily different.

[0099] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0100] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0101] The method provided in this application is applied to an electronic device. This electronic device can be used in a terminal or a communication device. The terminal can be a vehicle-mounted terminal, mobile phone, computer, server, or other various terminal devices. The communication device can be a base station, satellite, or other various communication devices.

[0102] Figure 1 shows a schematic diagram of the structure of an electronic device provided in an embodiment of this application. As shown in Figure 1, the electronic device 100 includes a processor 101, a power supply 102, and a storage medium 103. The processor 101 and the power supply 102 can be integrated together or exist independently. The processor 101 can cover various general-purpose processors for terminals and data center equipment, and can also be an in-vehicle processor, but is not limited to those listed here. The processor 101 may include one or more CPUs. The storage medium 103 is coupled to the processor and can store computer execution instructions and data for executing the scheme of this application, and is controlled by the processor 101. The processor 101 is used to execute the computer execution instructions stored in the storage medium, thereby implementing the method provided in the following embodiments of this application. Optionally, the computer execution instructions in the embodiments of this application may also be referred to as application code, and the embodiments of this application do not specifically limit this.

[0103] As shown in Figure 1, the storage medium 103 can exist independently of the processor 101 or be built into the processor 101. For example, the storage medium 103 can be the built-in memory within the processor 101 or the BIOS memory on the motherboard.

[0104] As shown in Figure 1, the processor 101 can be a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an ASIC, a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The memory can be random access memory (RAM), or it can include non-volatile memory, such as disk storage, flash memory, etc., which will not be listed exhaustively. Specifically, the memory can be external memory such as memory on the motherboard (e.g., BIOS memory), or it can be the processor's internal memory. For example, when the processor 101 is a CPU, the storage medium 103 can be the CPU's internal memory.

[0105] As shown in Figure 1, the storage medium 103 can be a random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), register, hard disk, portable hard disk, read-only optical disc (CD-ROM), or any other form of storage medium known in the art.

[0106] Figure 2 shows a schematic diagram of the connection structure between the processor and the power supply in an embodiment of this application. As shown in Figure 2, the processor 101 includes a processor core 1011 and a phase-locked loop 1013. The phase-locked loop 1013 adjusts or sets the processor's clock frequency under the control of the processor core 1011. Furthermore, when the processor 101 also includes a built-in memory 1012, the built-in memory 1012 can implement the functions of the aforementioned storage medium 103, thereby reducing unnecessary hardware in the electronic device and resulting in a higher degree of integration.

[0107] In one example, as shown in FIG2, the processor 101 further includes a CPM circuit 1015, which is electrically connected to the processor core 1011.

[0108] The power supply 102 shown in Figure 1 can be any power supply with voltage regulation function, providing power supply voltage to the processor 101. Figure 2 shows a schematic diagram of the power supply 102 using a VRM power supply as an example. As shown in Figure 2, the power supply 102 includes a VRM chip 1021, a logic control circuit 1022, and a buck converter 1023. The VRM chip 1021 is connected to the signal input terminal of the logic control circuit 1022, and the signal output terminal of the logic control circuit 1022 is electrically connected to the buck converter 1023, so that the VRM chip 1021 provides a signal carrying information to the logic control circuit 1022. Of course, the power supply 102 may also include a register 1024 or other devices with storage functions, which can store information that can be retrieved by the VRM chip 1021. In some cases, the buck converter 1023 may also be independent of the power supply 102, located between the power supply 102 and the processor 101.

[0109] For example, as shown in Figure 2, the Buck converter 1023 includes a grounding capacitor C and multiple inductors L connected in parallel. The first end of each inductor L is connected to the signal output terminal of the logic control circuit 1022, and the second end of each inductor L is grounded through the grounding capacitor C. Therefore, the Buck converter 1023 is connected in a multi-channel interleaved parallel quasi-square-wave (QSW) topology, which has good ripple cancellation. The more inductors connected in parallel, the better the ripple cancellation. The number of inductors L connected in parallel is set according to actual needs, but there must be at least two inductors L. For example, when there are four inductors connected in parallel in the Buck converter 1023, the ripple of the supply voltage output by the power supply 102 can be completely cancelled when the duty cycle of the multi-channel interleaved parallel QSW topology is 0.25, 0.5, or 0.75. If the duty cycle is not equal to the above values, only partial ripple cancellation can be achieved.

[0110] As shown in Figure 2, the processor 101 and the power supply 102 can communicate. In practical applications, the processor 101 includes a communication interface 1014. The power supply 102 includes a communication interface 1025 to enable communication between the processor 101 and the power supply 102. For example, the processor 101 and the power supply 102 are connected via a bus or power line. The bus can be a Power Management Bus (PMBus) or an I2C (Inter-Integrated Circuit) bus. For example, the processor 101 and the power supply 102 communicate via a PMBus bus. In this case, both the communication interface of the processor 101 and the communication interface of the power supply 102 are PMBus interfaces.

[0111] The method provided in this application can be implemented using any general-purpose processor or application-specific integrated circuit (ASIC). The following description uses an in-vehicle processor applied to a vehicle as an example. This description is for comprehension purposes only and is not intended to limit the scope of the application.

[0112] Figure 3 is a system architecture diagram of a vehicle communication system provided in an embodiment of this application. In Figure 3, similar symbols identify similar components unless the context otherwise indicates. The illustrative system and method embodiments described herein are not intended to be limiting. It will be readily understood that certain aspects of the disclosed systems and methods can be arranged and combined in a variety of different configurations, all of which are contemplated herein.

[0113] As shown in Figure 3, the vehicle communication system 10 includes a vehicle 12, one or more wireless carrier systems 14, a terrestrial communication network 16, a computer 18, and a call center 20. It should be understood that the disclosed methods can be used with any number of different systems and are not specifically limited to the operating environment shown herein. Similarly, the architecture, construction, setup, and operation of the communication system 10, as well as its individual components, are generally known in the prior art. Therefore, the following paragraphs merely provide a brief overview of an example communication system 10, and other systems not shown herein can also use the disclosed methods.

[0114] The aforementioned vehicle 12 can be an unmanned vehicle or a manned vehicle. Vehicle 12 can be implemented on or in the form of a car. However, the example system can also be implemented on or in the form of other vehicles, such as cars, trucks, motorcycles, buses, boats, airplanes, helicopters, lawnmowers, snowplows, SUVs, amusement park vehicles, agricultural equipment, construction equipment, trams, golf carts, trains, and trams. Furthermore, robotic devices can also be used to perform the methods and systems described herein.

[0115] Figure 3 illustrates some vehicle hardware 28. This vehicle hardware 28 includes an information communication unit 30, a microphone 32, one or more buttons or other control inputs 34, an audio system 36, a visual display 38, a GPS (Global Positioning System) module 40, and multiple VM modules 42 (Vehicle Security Module, abbreviated as VM here to distinguish it from the VSM power supply mentioned earlier). Some of these devices can be directly connected to the information communication unit, such as the microphone 32 and the buttons 34, while others are indirectly connected using one or more network connections, such as a communication bus 44 or an entertainment bus 46. Examples of suitable network connections include CAN (Controller Area Network), MOST (Media Oriented Systems Transport), LIN (Local Interconnect Network), LAN (Local Area Network), and other suitable connections such as Ethernet or others conforming to known ISO (International Organization for Standardization), SAE (Society of Automotive Engineers), and IEEE (Institute of Electrical and Electronics Engineers) standards and specifications, to name just a few.

[0116] As shown in Figure 3, the information communication unit 30 can be an OEM (Original Equipment Manufacturer) installed (embedded) or aftermarket device installed in the vehicle and capable of wireless voice and / or data communication over the wireless carrier system 14 and via wireless networking. This enables the vehicle to communicate with call center 20, other information communication-enabled vehicles, or other entities or devices. The information communication unit preferably uses radio broadcasting to establish a communication channel (voice channel and / or data channel) with the wireless carrier system 14, allowing voice and / or data transmission to be sent and received on the channel. By providing voice and data communication, the information communication unit 30 enables the vehicle to offer a variety of different services, including those associated with navigation, telephone, emergency assistance, diagnostics, infotainment, etc. Data can be transmitted via data connections (e.g., via packet data transmission over a data channel, or via a voice channel using techniques known in the prior art). For combined services that include both voice communication (e.g., a live advisor or voice response unit at call center 20) and data communication (e.g., providing GPS location data or vehicle diagnostic data to call center 20), the system can utilize a single call on the voice channel and switch between voice and data transmission on the voice channel as needed, which can be accomplished using techniques known to those skilled in the art. Furthermore, data can be sent and received using Short Message Service (SMS) (e.g., PDP (Packet Data Protocol)); the messaging unit can be configured to terminate and / or initiate mobile communication, or to terminate and / or initiate application communication.

[0117] The aforementioned information communication unit 30 utilizes cellular communication according to the GSM (Global System for Mobile Communication) or CDMA (Code Division Multiple Access) standard, and therefore includes a cellular chipset 50 (standard cellular chipset) for voice communication (e.g., hands-free calling), a wireless modem for data transmission, a processing device 52, one or more digital memories 54, and dual antennas 56. It should be understood that the modem can be implemented by software stored within the information communication unit and executed by the processing device 52, or it can be a separate hardware component located inside or outside the information communication unit 30. The modem can operate using any number of different standards or protocols (e.g., EVDO (CDMA2000 1xEV-DO), CDMA, GPRS (General Packet Radio Service), and EDGE (Enhanced Data Rate for GSM Evolution)). Wireless networking between vehicles and other networked devices can also be performed using the information communication unit 30. For this purpose, the information communication unit 30 can be configured to communicate wirelessly according to one or more wireless protocols (e.g., IEEE 802.11, WiMAX (Worldwide Interoperability for Microwave Access), or Bluetooth). When used for packet-switched data communication such as TCP / IP (Transmission Control Protocol / Internet Protocol), the information communication unit can be configured to have a static IP address, or can be set to automatically receive an assigned IP address from another device on the network (e.g., a router) or from a network address server.

[0118] The aforementioned processing device 52 is an on-board processor. This processing device 52 can be any type of device capable of processing electronic instructions, including microprocessors, microcontrollers, main processors, controllers, vehicle communication processors, and ASICs (Application Specific Integrated Circuits). It can be a dedicated processor solely for the information communication unit 30 or can be shared with other vehicle systems. The processing device 52 executes various types of digital storage instructions, such as software or firmware programs stored in the memory 54, enabling the information communication unit to provide a wide range of services. Specifically, the processing device 52 can execute programs or process data to perform at least a portion of the methods discussed herein. The processing device 52 can be an electronic device applying the methods of this application.

[0119] The aforementioned information communication unit 30 can be used to provide a variety of vehicle services, including wireless communication with other parts of the vehicle. Such services include: turn-by-turn direct 1ns and other navigation-related services provided in conjunction with the GPS-based vehicle navigation module 40; airbag deployment notifications and other emergency or roadside assistance-related services provided in conjunction with one or more collision sensor interface modules (e.g., the main control module (not shown)); diagnostic reports using one or more diagnostic modules; and infotainment-related services, where music, web pages, movies, television programs, video games, and / or other information are downloaded by the infotainment module and stored for current or later playback. The services listed above are by no means an exhaustive list of all the capabilities of the information communication unit 30, but merely an enumeration of some of the services that the information communication unit can provide. Furthermore, it should be understood that at least some of the aforementioned modules can be implemented in the form of software instructions stored internally or externally to the information communication unit 30. These can be hardware components located internally or externally to the information communication unit 30, or they can be integrated and / or shared with each other, or integrated and / or shared with other systems located throughout the vehicle; these are just a few possibilities. When the VM modules 42 located outside the information communication unit 30 are in operation, they can exchange data and commands with the information communication unit 30 via the vehicle bus 44.

[0120] GPS module 40 receives radio signals from GPS satellites 60. From these signals, GPS module 40 can determine the location of the vehicle, which is used to provide navigation and other location-related services to the driver. Navigation information can be displayed on display 38 (or other displays within the vehicle) or presented verbally, for example, when providing turn-by-turn navigation. Navigation services can be provided using a dedicated navigation module within the vehicle (which may be part of GPS module 40), or some or all of the navigation services can be provided via information communication unit 30, where location information is sent to a remote location to provide navigation maps, map markers (points of interest, restaurants, etc.), route calculations, etc., for the vehicle. Location information can be provided to call center 20 or other remote computer systems, such as computer 18, for other purposes, such as fleet management. Furthermore, new or updated map data can be downloaded from call center 20 to GPS module 40 via information communication unit 30.

[0121] In addition to the audio system 36 and GPS module 40, the vehicle 12 may include other vehicle safety modules in the form of electronic hardware components, namely VM modules 42. VM modules 42 are located throughout the vehicle and typically receive input from one or more sensors, using the sensed input to perform diagnostic, monitoring, control, reporting, and / or other functions. Each of the VM modules 42 is preferably connected to the VM module 42 via a communication bus 44, also connected to the information communication unit 30, and can be programmed to run vehicle system and subsystem diagnostic tests. For example, one VM module 42 may be an ECM (Engine Control Module) controlling various aspects of engine operation (e.g., fuel ignition and ignition timing), another VM module 42 may be a powertrain control module regulating the operation of one or more components of the vehicle's powertrain, and yet another VM module 42 may be a main control module managing various electrical components located throughout the vehicle (such as the vehicle's electric door locks and headlights). According to one embodiment, the engine control module is equipped with OBD (On-Board Diagnostics) features. These features provide a large amount of real-time data, such as data received from various sensors (including vehicle emission sensors), and provide a standardized series of diagnostic fault codes. These fault codes allow technicians to quickly identify and repair faults within the vehicle. As those skilled in the art will understand, the VM module mentioned above is merely an example of some modules that can be used within the vehicle 12, and many other modules are possible.

[0122] The vehicle electronics 28 also includes multiple vehicle user interfaces, providing means for vehicle occupants to provide and / or receive information, including a microphone 32, buttons 34, an audio system 36, and a visual display 38. As used herein, the term "vehicle user interface" broadly includes any suitable form of electronic equipment, including hardware and software components, located on the vehicle and enabling the vehicle user to communicate with or through components of the vehicle. The microphone 32 provides audio input to the information communication unit, enabling the driver or other occupants to provide voice commands and execute hands-free calls via the wireless carrier system 14. For this purpose, it can connect to an onboard automated voice processing unit utilizing HMI (Human Machine Interface) technology known in the art. Button 34 allows manual user input to the information communication unit 30 to initiate wireless telephone calls and provide other data, response, or control inputs. Separate buttons can be used to initiate emergency calls and routine service assistance calls to the call center 20. Audio system 36 provides audio output to the vehicle's driver and passengers and can be a dedicated standalone system or part of the main vehicle audio system. According to the specific embodiment shown here, audio system 36 is operatively connected to vehicle bus 44 and entertainment bus 46, and can provide AM (Amplitude Modulation), FM (Frequency Modulation), and satellite radio, DVD (Digital Versatile Disc), and other multimedia functions. This functionality can be provided in conjunction with the infotainment modules described above or independently. Visual display 38 is preferably a graphic display, such as a touchscreen on the dashboard or a head-up display reflected from the windshield, and can be used to provide various input and output functions. Various other vehicle user interfaces can also be utilized, as the interface in Figure 3 is merely an example of one specific implementation.

[0123] The wireless carrier system 14 is preferably a cellular telephone system, comprising a plurality of cell towers 70 (only one shown), one or more MSCs (Mobile Switching Centers) 72, and any other networking components required to connect the wireless carrier system 14 to the terrestrial network 16. Each cell tower 70 includes transmit and receive antennas and a base station, with base stations from different cell towers directly connected to the MSC 72 or connected to the MSC 72 via an intermediate device (e.g., a base station controller). The wireless carrier system 14 can implement any suitable communication technology, including, for example, analog technology (e.g., AMPS (Advanced Mobile Phone System)) or newer digital technology (e.g., CDMA (e.g., CDMA2000) or GSM / GPRS). As those skilled in the art will appreciate, various cell tower / base station / MSC configurations are possible and can be used with the wireless carrier system 14. For example, base stations and cell towers can coexist in the same location, or they can be located far apart from each other; each base station can respond to a single cell tower or a single base station can serve multiple cell towers; each base station can be connected to a single MSC; this is only a small subset of possible configurations.

[0124] In addition to using wireless carrier system 14, different forms of satellite communication wireless carrier systems can be used to provide one-way or two-way communication with vehicles. This can be accomplished using one or more communication satellites 62 and uplink transmitting station 64. One-way communication can be, for example, a satellite broadcasting service, in which program content (news, music, etc.) is received by transmitting station 64, packaged for uploading, and then sent to satellite 62, which broadcasts the program to the user. Two-way communication can be, for example, a satellite telephone service that uses satellite 62 to relay telephone communication between vehicle 12 and station 64. If used, such a satellite telephone can be attached to or used in place of wireless carrier system 14.

[0125] Terrestrial network 16 may be a conventional terrestrial radio communication network that connects to one or more landline telephones and connects wireless carrier system 14 to call center 20. For example, terrestrial network 16 may include a PSTN (Public Switched Telephone Network), such as the PSTN used to provide wired telephone, packet-switched data communications, and Internet infrastructure. One or more portions of terrestrial network 16 can be implemented using standard wired networks, fiber optic or other optical networks, cable networks, power lines, other wireless networks (e.g., WLANs), or networks providing BWA (Broadband Wireless Access), and any combination thereof. Terrestrial network 16 may also include one or more SMSCs (Short Message Service Centers) for storing, uploading, converting, and / or transmitting SMS (Short Message Service) messages between senders and receivers. For example, an SMSC may receive SMS messages from call center 20 or a content provider (e.g., an external short message entity or ESME), and the SMSC may transmit SMS messages to vehicle 12 (e.g., a mobile terminal device). SMSCs and their functions are known to technicians. Furthermore, call center 20 does not necessarily need to be connected to terrestrial network 16, but may include wireless telephone equipment, enabling it to communicate directly with wireless networks (such as wireless carrier system 14).

[0126] Computer 18 can be one of multiple computers accessible via private or public networks (e.g., the Internet). Each such computer 18 can be used for one or more purposes, such as a vehicle accessing a web server via information communication unit 30 and wireless carrier system 14. Other such accessible computers 18 can be, for example: a service center computer where diagnostic information and other vehicle data can be uploaded from the vehicle via information communication unit 30; a client computer used by the vehicle owner or other user for purposes such as: accessing or receiving vehicle data, setting or configuring user parameters, or controlling vehicle functions; or a third-party library, to which vehicle data or other information is provided or received, whether through communication with vehicle 12 or call center 20, or both. Computer 18 can also be used to provide Internet connectivity, such as DNS (Domain Name Server) services, or as a network address server using DHCP (Dynamic Host Configuration Protocol) or other suitable protocols to assign IP addresses to vehicle 12.

[0127] Call center 20 is designed to provide a variety of different system back-end functions to vehicle electronics 28, and according to the exemplary embodiment shown herein, call center 20 typically includes one or more switches 80, a server 82, a database 84, field consultants 86, and a VRS (Automatic Voice Response System) 88, all of which are known in the prior art. These various call center components are preferably interconnected via a wired or wireless local area network 90. ​​Switch 80 can be a PBX (Private Branch Exchange), routing incoming signals so that voice transmissions are typically sent to the field consultant 86 via ordinary telephone or to the Automatic Voice Response System 88 using VoIP. Field consultant calls can also use VoIP (Voice over Internet Phone), as indicated by the dashed line in Figure 3. VoIP and other data communications via switch 80 are implemented via a modem (not shown) connected between switch 80 and network 90. ​​Data transmission is delivered via the modem to server 82 and / or database 84. Database 84 can store account information, such as user authentication information, vehicle identifiers, profile records, behavioral patterns, and other relevant user information. Data transmission can also be performed by wireless systems, such as 802.1lx, GPRS, etc. Furthermore, short message service (SMS) can be used to send and / or receive data (e.g., PDP); and call center 20 can be configured for mobile termination and / or initiation, or for application termination and / or initiation. Although the illustrated embodiment has been described as being used with a manned call center 20 using field advisor 86, it will be understood that the call center can use VRS 88 instead of an automated advisor, or a combination of VRS 88 and field advisor 86 can be used.

[0128] Currently, autonomous vehicles require processing equipment with high computing power and high reliability. The high ambient temperature inside autonomous vehicles (e.g., the interior temperature of a car's center console can reach 85 degrees Celsius), coupled with the high computing power and high power consumption of the autonomous driving processor itself, causes a sharp rise in processor core temperature, limiting further improvements in processor computing power. To ensure that the processor core temperature does not become too high under high computing power, in addition to improving the cooling system's capabilities, it is crucial to effectively reduce processor power consumption through power reduction technologies. However, current technologies can only reduce power consumption under low processor loads. When the processor load is high, power consumption remains difficult to reduce in order to maintain processing speed. Therefore, the chip integration density of the processor in these technologies cannot be further improved, limiting the further application of Turbo technology in processors and hindering further performance improvements. Furthermore, the large amount of heat generated by the processor under high loads necessitates a cooling system to lower its temperature, further increasing cooling costs. For example, when data center energy consumption increases, a high-performance cooling system is required to cool the data center. For example, due to high energy consumption, the standby time of terminal devices is reduced, making it impossible to work for a long time.

[0129] To address the above issues, this application provides a voltage regulation method. The steps executed by the processor in the method provided in this application can also be executed by a chip applied within the processor, and the steps executed by the power supply can also be executed by a chip applied within the power supply. The following embodiments use the processor and the power supply as the execution entities, respectively.

[0130] Figure 4 shows a schematic flowchart of the voltage regulation method provided in an embodiment of this application. As shown in Figure 4, an embodiment of this application provides a voltage regulation method. This method is applied to an electronic device having a processor and a power supply. The power supply can supply power to the processor. The method includes:

[0131] Step 101: The processor sends power supply adjustment information to the power supply based on the next time period's clock frequency. This power supply adjustment information includes the set supply voltage V for the next time period's clock frequency, defined as the set supply voltage determined by the processor based on the next time period's clock frequency when the processor is running at a certain clock frequency. This can generally be determined using a single DVFS technique. That is, based on the next time period's clock frequency, the set supply voltage corresponding to the next time period's clock frequency is found from the correspondence between the processor's clock frequency and the set supply voltage.

[0132] The duration of the next time period can be measured in minutes and determined based on the actual situation. For example, the duration of the next time period can be 10ms to 50ms. For instance, the duration of the next time period is 50ms. In practical applications, the clock frequency of the next time period refers to the clock frequency predicted based on the current clock frequency. That is, before step 101, step 100 should also be included: the processor predicts the clock frequency of the next time period based on the current load.

[0133] For example, the processor collects the current load in real time, predicts the load for the next time period based on the collected current load, and determines the clock speed for the next time period based on the load for the next time period. The current load can be processor utilization, application execution volume, or task volume, etc.

[0134] For example, a table mapping load to clock speed can be stored in the motherboard or processor's built-in memory. This table can be configured to specify a load range corresponding to the same clock speed. Then, based on the predicted load for the next time period, the predicted load range is first determined in the load-clock speed mapping table, and finally, the clock speed for the next time period is determined based on that load range.

[0135] For example, frequency switching information can be stored in the motherboard or processor's built-in memory. A preset clock speed is determined based on the predicted load for the next time period, and then the clock speed for the next time period is retrieved from the frequency switching information based on this preset clock speed. In practical applications, the frequency switching information includes multiple clock speed points. The lowest clock speed point above the preset clock speed is selected as the clock speed for the next time period. For example, the frequency switching information may include multiple frequency points such as 1.0GHz, 1.5GHz, and 2.0GHz. If the clock speed for the next time period is 1.3GHz, then the clock speed should be switched to 1.5GHz. If the clock speed for the next time period is 1.7GHz, then the clock speed should be switched to 2.0GHz.

[0136] Step 102: The power supply receives power adjustment information sent by the processor. For example, if the processor and power supply communicate via a PMBus bus, the power supply receives power adjustment information via the PMBus interface.

[0137] Step 103: The power supply provides the processor with a power supply voltage V based on the set supply voltage V of the main frequency for the next time period and the set voltage slope R of the main frequency for the next time period. out The voltage slope here refers to the supply voltage V as the load current of the power supply increases. out The rate of decrease of the supply voltage (V), also known as the loadline value, is expressed in units of resistance. out It decreases as the load current of the power supply increases. V min ≤V out ≤V, V minThis is the minimum supply voltage required for normal operation during the next period of main frequency operation, under conditions of increased load current. For example: V min This refers to the minimum supply voltage that the power supply provides to the processor when the load current increases to its maximum value. This minimum supply voltage is sufficient for the processor to operate normally.

[0138] To coordinate with the constant voltage adjustment of the power supply, the above method also includes: if the processor determines that the clock speed for the next time period is not equal to the current clock speed, setting the current clock speed to equal the clock speed for the next time period. The processor clock speed is essentially the product of the front-side bus (FSB) and the multiplier. For example, if a CPU has an FSB of 100MHz and a multiplier of 8.5, the CPU clock speed = FSB × multiplier = 100MHz × 8.5 = 850MHz. Therefore, the processor clock speed can be adjusted by changing either the multiplier or the FSB. Furthermore, the method of adjusting the processor clock speed should also be determined based on the processor model. For example, if the processor is an Intel CPU, since Intel CPUs prevent multiplier modification, the clock speed can only be modified by changing the FSB. As another example, CPUs from Advanced Micro Devices, Inc. (AMD) allow multiplier modification, but modifying the multiplier does not improve CPU performance as much as modifying the FSB.

[0139] For example, when switching the processor's clock speed, the processor's internal PLL is used to adjust the clock multiplier so that the processor's current clock speed is equal to the clock speed for the next time period determined by the processor core.

[0140] When switching processor clock speeds, the timing of the switch must be determined based on the relationship between the current clock speed and the clock speed for the next time period. As shown in Figure 5, when the processor determines that the clock speed for the next time period is not equal to the current clock speed, setting the current clock speed to equal the clock speed for the next time period includes:

[0141] Step 100a: The processor determines that the clock frequency in the next time period is less than the current clock frequency, sets the current clock frequency to be equal to the clock frequency in the next time period, and executes step 101.

[0142] Step 100b: The processor determines that the clock frequency in the next time period is greater than the current clock frequency, and then executes step 101.

[0143] When the processor determines that the clock frequency for the next time period is greater than the current clock frequency, after step 103 above, the above method further includes: step 104: the processor sets the current clock frequency to be equal to the clock frequency for the next time period.

[0144] In the method provided in this application embodiment, the next time period main frequency refers to the main frequency predicted based on the current main frequency, and the power supply provides the processor with a power supply voltage V based on the set supply voltage V of the next time period main frequency and the set voltage slope R of the next time period main frequency.out This adapts to the processor's next clock frequency. Furthermore, because the load current periodically increases from minimum to maximum, in existing technologies where the power supply outputs a constant voltage to the load terminal, the load terminal voltage passively decreases as the load current increases. The method provided in this application actively controls the power supply output voltage V. out The voltage decreases as the load current increases, resulting in a decrease in the supply voltage V output by the power supply when the load current begins to rise. out The active voltage decreases as the load current increases. At this time, the supply voltage V... out When the processor's operating frequency is less than the set supply voltage V for the next clock cycle and greater than or equal to the maximum load current, the minimum supply voltage V required for normal operation under increased load current conditions during the next clock cycle. min Therefore, compared with the prior art, the power supply voltage V provided by the power source in the method provided in this application embodiment is significantly higher. out This method reduces processor power consumption while ensuring normal processor operation, thereby improving processor performance. Furthermore, since a higher processor clock speed results in a higher processor load, the method provided in this application ensures that regardless of the processor load, the power supply can provide power to the processor at a voltage lower than the current clock speed setting when the load current increases, thus ensuring low power consumption while the processor operates normally.

[0145] As can be seen from the above, compared with the single DVFS technology to reduce processor power consumption, the method provided in this application embodiment can reduce power consumption not only when the processor is under light load, but also when the processor is under heavy load, achieving a reduction in power consumption across the entire range, thereby reducing the processor's heat generation. Furthermore, when the processor is under a relatively high load, the processor's heat generation is relatively low. Therefore, using Turbo technology can further increase the clock frequency and alleviate the application limitation problem caused by the high processor heat generation of Turbo technology.

[0146] As one possible implementation, the supply voltage output by the VRM power supply has the characteristic of decreasing linearly as the load current of the load line increases. The aforementioned supply voltage V... out =VI*R, where I is the load current of the power supply. As can be seen from this formula, the method of this application, based on the power reduction of DVFS technology in the prior art, takes into account the characteristic that the voltage slope decreases as the load current increases, and uses the product of the set voltage slope and the load current to finely adjust the power supply voltage determined by DVFS technology, thereby achieving power reduction across the entire domain.

[0147] In addition, the aforementioned power supply voltage V outThe voltage slope R of the processor in the next time period, the set supply voltage V in the next time period, and the load current I are determined. Since the voltage slope refers to the rate at which the supply voltage decreases as the load current of the power supply increases, the product of the set voltage slope R and the load current I in the next time period essentially represents the active decrease in supply voltage when the load current of the power supply increases. As long as this active decrease is greater than or equal to the maximum passive decrease in load-side voltage under increased load current conditions in the prior art, the supply voltage V can be kept within acceptable limits. out It is always greater than or equal to the minimum supply voltage V that the processor operates normally under increased load current during the next operating period. min .

[0148] The power supply includes a VRM chip, logic control circuitry, and a Buck converter. The VRM chip determines the reference voltage V based on the set supply voltage V for the next clock cycle, and determines the reference voltage slope R based on the set voltage slope R for the next clock cycle. The VRM chip transmits the reference voltage and its slope to the logic control circuitry. The logic control circuitry outputs a variable voltage based on the reference voltage and its slope, which is then varied by the Buck converter to output a supply voltage V that meets the processor's operating requirements. out .

[0149] Figure 6 shows a schematic diagram of the power supply load transient process. Figure 7 shows a schematic diagram of the power supply loadline characteristics. In Figure 6, V... min The minimum supply voltage for the processor. max This represents the maximum load current. The principle behind this application's method of ensuring processor operation at lower voltages is analyzed below with reference to Figures 6 and 7.

[0150] As shown by line a in Figure 6, when the Loadline value = 0, it indicates that the power supply provides the processor with a DC voltage, and the supply voltage does not decrease; that is, the supply voltage V0 does not change with the load current. Curve a in Figure 7 is the transient curve of the load current. Curve b in Figure 7 represents the transient response curve of the power supply voltage when the Loadline value = 0. As shown by curves a and b in Figure 7, under the impact of the load current, due to insufficient capacitance at the output of the Buck converter, the supply voltage provided by the power supply passively drops. The drop process lasts from a few μs to tens of μs, and then gradually recovers to the DC voltage.

[0151] Specifically, referring to curves a and b in Figure 7, it can be seen that when the load current is at its minimum, the supply voltage is V0 and remains constant. As the load current rises from its minimum to its maximum, the supply voltage passively decreases from V0 to its minimum value V. minThen it gradually rises. As the load current decreases from its maximum value to its minimum value, the supply voltage rapidly rises back to its maximum value V. max Then it gradually decreases until the supply voltage equals V0. Throughout this process, the difference between the minimum and maximum supply voltage can reach V... max -V min Furthermore, when the supply voltage passively drops from V0 to its minimum value V... min At this time, the processor can still operate normally, therefore, the passive maximum voltage drop ΔV of the supply voltage is... max =V0-V min .

[0152] As shown by line b in Figure 6, when the Loadline value > 0, it indicates that the DC voltage actively and linearly decreases as the load current increases, and the voltage drop slope is equal to the Loadline value. Figure 7c shows the transient response curve of the power supply voltage when the Loadline value > 0. As shown by curve c in Figure 7, under load current surges, the power supply actively controls the voltage drop, as long as the voltage drop amplitude ΔV is not lower than the passive maximum voltage drop ΔV on curve b. max This ensures the processor functions normally. Therefore, the method provided in this application can guarantee the processor's normal operation. If the power supply voltage drop ΔV is less than the maximum passive voltage drop on curve b, the processor will not function normally.

[0153] As can be seen from the above, in the method provided by the embodiments of this application, as long as the supply voltage V is guaranteed to be at its minimum value when the load current is equal to the minimum value, out If the supply voltage V is equal to the set supply voltage V of the main frequency in the next time period, and the load current increases, then R*I must always be less than or equal to the passive maximum voltage drop of the set supply voltage V of the main frequency in the next time period to ensure the supply voltage V. out The minimum power supply voltage is greater than or equal to the main frequency of the next time period.

[0154] To verify that the method provided in this application can reduce processor power consumption under heavy load, an analysis is conducted below in conjunction with DVFS technology.

[0155] DVFS (Dynamic Voltage and Frequency Scaling) technology is a technique that can reduce power consumption to some extent. It achieves this reduction by lowering the chip's operating voltage and frequency.

[0156] Taking a chip as an example: the formula for calculating the power consumption of a chip is as follows: It is the chip's dynamic power consumption, V cc ·I LEAK It is the chip's static power consumption, V cc Where is the chip's operating voltage, f is the chip's operating frequency, and I... LEAKLet α be the leakage current of the chip, α be the average switching rate of the circuit at the chip's current operating frequency, and C be the capacitance of the load capacitor. It should be understood that the power consumption calculation formula for a chip also applies to processors or integrated circuits with information processing functions.

[0157] The power consumption calculation formula for a chip shows that the dynamic power consumption of a chip is related to its operating voltage V. cc The dynamic power consumption exhibits a quadratic relationship with the chip's operating frequency f, showing a linear relationship of first degree. Furthermore, when the chip's operating voltage V... cc The higher the chip's operating frequency f, the higher its dynamic power consumption. Therefore, DVFS technology can reduce power consumption by lowering the chip's power supply voltage and operating frequency.

[0158] Figure 8 illustrates the mechanism by which DVFS technology reduces power consumption. Timing a in Figure 8 is the voltage timing diagram; timing b is the clock frequency timing diagram. As shown in Figure 8, when the processor load is light, both the processor's clock frequency and supply voltage are relatively low. When the processor load is heavy, both the processor's clock frequency and supply voltage are relatively high, and remain at their rated values.

[0159] Figure 9 shows a comparison of the method of this application, DVFS technology, and fixed voltage power supply. The horizontal axis represents the load current (which can be considered the maximum load current), and the vertical axis represents the supply voltage. Line a in Figure 9 represents the voltage variation when using the fixed voltage power supply method. Line a shows that regardless of the processor's clock frequency, the processor's supply voltage remains a fixed rated supply voltage. Line b in Figure 9 represents the voltage variation when using a single DVFS power supply. Line b shows that in low-power mode, the CPU's clock frequency is F1, and the CPU's supply voltage is V11; in rated mode, the CPU's clock frequency is F2, and the CPU's supply voltage is V12; in the first overclocking mode, the CPU's clock frequency is F3, and the CPU's supply voltage is V13; in the second overclocking mode, the CPU's clock frequency is F4, and the CPU's supply voltage is V14. Line c in Figure 9 represents the voltage variation when using the method of this application. As shown by line c, in low-power mode, the CPU's clock speed is F1 and its power supply voltage is V21; in rated mode, the CPU's clock speed is F2 and its power supply voltage is V22; in the first overclocking mode, the CPU's clock speed is F3 and its power supply voltage is V23; and in the second overclocking mode, the CPU's clock speed is F4 and its power supply voltage is V24. It should be understood that as power consumption increases, the CPU's clock speed also increases; therefore, F1 < F2 < F3 < F4.

[0160] As shown in Figure 9, when using a single DVFS power supply, V11 < V12 < V13 < V14. The CPU's supply voltage increases in a stepwise manner with increasing clock speed and power consumption, until it equals the supply voltage V14. The first shaded area P1 in Figure 9 represents the power consumption gain area compared to the fixed voltage method using DVFS technology. This shows that at higher CPU clock speeds, DVFS technology does not reduce CPU power consumption. Therefore, DVFS technology can reduce power consumption under light processor loads, but it cannot reduce power consumption under heavy processor loads.

[0161] When using the power supply method of this application embodiment, V21 < V22 < V23 < V24. Although the CPU power supply voltage increases in a stepwise manner with the increase of clock speed and power consumption, the power supply voltage in each power mode is lower than the power supply voltage using DVFS technology. The second shaded area P2 in Figure 9 represents the power consumption gain area of ​​the method of this application embodiment compared to DVFS technology. Verification shows that compared to DVFS technology, the method of this application embodiment can guarantee an overall CPU power consumption gain of over 10%.

[0162] As can be seen from the above, the method of this application can further reduce the power consumption of the processor regardless of the clock frequency. Therefore, compared with DVFS technology, the method provided by the embodiments of this application can not only further reduce the power consumption of the processor, but also enable the processor to operate normally at the lowest supply voltage in multiple power consumption modes such as low power mode, rated mode, and overclocking mode (first overclocking mode, second overclocking mode), thereby achieving global power reduction of the processor, thereby reducing the degree of processor heat generation under heavy load, enabling the processor to work at a higher clock frequency or even overclock, and improving processor performance.

[0163] As one possible implementation, the set supply voltage V for the next time period main frequency can be provided by the processor, while the set voltage slope R for the next time period main frequency can exist in the power supply or be provided by the processor.

[0164] When the processor only supplies the power supply with the set voltage V for the next clock frequency, in practical applications, the stored set voltage slope can be stored in the storage medium of the electronic device or in the storage medium of the power supply.

[0165] For example, the aforementioned set voltage slope exists in the power supply as a constant voltage slope. The processor does not need to dynamically set the set voltage slope R of the next time period's main frequency within the power supply using the processor-power supply communication interface, thereby effectively reducing communication latency and voltage regulation latency, and improving voltage regulation speed. For instance, the processor sending power supply adjustment information to the power supply based on the next time period's main frequency includes:

[0166] Step 1011A: The processor searches for the set power supply voltage V of the next time period's main frequency from the target correspondence based on the main frequency of the next time period.

[0167] Step 1012A: The processor sends the set supply voltage V for the next time period's main frequency to the power supply.

[0168] After the processor finds the set power supply voltage for the next time period's main frequency from the target correspondence based on the main frequency of the next time period, it sends it to the power supply through the processor's PMBus interface, and the power supply's PMBus interface receives the set power supply voltage for the next time period's main frequency.

[0169] The aforementioned target correspondence can be the correspondence between the processor's clock speed, the set supply voltage, and the voltage slope. Alternatively, the target correspondence can be the correspondence between the processor's clock speed and the set supply voltage determined using DVFS technology.

[0170] In practical applications, the power supply described above stores the set voltage slope R of the next time period's main frequency in the form of a constant voltage slope. This constant voltage slope is the minimum value R of the voltage slope allowed by the processor's set supply voltage at each main frequency. min R min >0. Because R min A value greater than 0 ensures that the power supply always provides the processor with a voltage less than or equal to the set supply voltage, regardless of the load or clock frequency, resulting in lower power consumption. Furthermore, using a constant voltage slope as the set voltage slope R for the next clock frequency period allows control over the product of the set voltage slope and the load current, ensuring normal processor operation and preventing issues caused by a large constant voltage slope leading to increased load current and insufficient supply voltage V. out An error occurred that prevented the system from functioning properly.

[0171] When the processor supplies the power supply with the set supply voltage V and the set voltage slope R for the next clock frequency, the aforementioned power supply adjustment information also includes the set voltage slope R for the next clock frequency. At this time, the processor sends the following power supply adjustment information to the power supply based on the next clock frequency:

[0172] Step 1011B: The processor searches for the set power supply voltage V and the set voltage slope R of the next time period main frequency from the target correspondence based on the main frequency of the next time period.

[0173] Step 1012B: The processor sends the set supply voltage V for the next time period's main frequency and the set voltage slope R for the next time period's main frequency to the power supply.

[0174] When the processor finds the set supply voltage and set voltage slope of the next time period main frequency from the target correspondence based on the main frequency of the next time period, it sends them to the power supply through the processor's PMBus interface. The power supply's PMBus interface receives the set supply voltage and set voltage slope of the next time period main frequency.

[0175] In practical applications, the processor sends the set supply voltage for the next time period's clock frequency to the power supply in VID encoding form, and uses 8-16 bits of data as the set voltage slope for the next time period. For VID encoding, the VID encoding used in DVFS technology can be directly transmitted. For 8-16 bits of data, the power supply receives the data and performs simple data processing to obtain the set voltage slope for the next time period. For example, when the power supply includes a VRM chip, logic control circuit, and Buck converter, the VRM chip can determine the set supply voltage V and the set voltage slope R for the next time period's clock frequency based on the VID encoding and the 8-16 bits of data. In this case, the set supply voltage V for the next time period's clock frequency is used as the reference voltage, and the set voltage slope R for the next time period's clock frequency is used as the voltage slope of the reference voltage. The VRM chip sends the reference voltage and its slope to the logic control circuit. The logic control circuit adjusts the voltage based on the reference voltage and its slope, and then performs voltage conversion via a buck converter to obtain the supply voltage V. out Then, power is supplied to the processor via the power supply's power interface.

[0176] The above target correspondence refers to the relationship between the processor's clock speed, the set supply voltage, and the set voltage slope. The set voltage slopes for all clock speeds can be completely unequal, partially equal, or completely equal.

[0177] When the set voltage slopes of all clock frequencies are completely unequal or partially equal, the set voltage slope of the processor at each clock frequency is the voltage slope allowed by the set supply voltage of the processor at each clock frequency. In this case, the set voltage slope of each clock frequency in the above target correspondence is the voltage slope allowed by the set supply voltage of the processor at each clock frequency. The power supply voltage V is determined by the power supply. out While ensuring the processor operates normally, the goal is to optimize processor power consumption. Table 1 shows the target correlation when the set voltage slope is equal for certain CPU frequencies. It should be understood that the power consumption modes shown in Table 1 are only illustrative examples; in practical applications, various other power consumption modes may exist.

[0178] Table 1 shows the target correspondence for equal voltage slopes at some main frequencies.

[0179]

[0180] As shown in Table 1, when the CPU's next clock speed is 1.5GHz, the CPU searches for a set supply voltage V of 1.1V for the next clock speed, and the set operating voltage slope R for the next clock speed is 0.1mOhm. At this time, the CPU sets the reference voltage in the power supply to 1.0V via communication interfaces such as PMBus, and the reference voltage slope is 0.1mOhm. When the CPU's next clock speed is 2.5GHz, the CPU searches for a set supply voltage V of 1.2V for the next clock speed, and the set operating voltage slope R for the next clock speed is 0.2mOhm. At this time, the CPU sets the reference voltage in the power supply to 1.2V via communication interfaces such as PMBus, and the reference voltage slope is 0.2mOhm.

[0181] When the set voltage slopes are exactly equal across all clock frequencies, the set voltage slope needs to be applicable to power supply voltage adjustments at all clock frequencies. In other words, the processor's set voltage slope at all clock frequencies must be equal to a constant voltage slope. At this point, the set voltage slope corresponding to all clock frequencies in the above target correspondence is equal to a constant voltage slope. This constant voltage slope is applicable to power supply voltage adjustments at various clock frequencies, and it is the minimum voltage slope R allowed by the processor's set power supply voltage at each clock frequency. min R min >0. For example: R selected from Table 1 min =0.1mOhm. When all the set voltage slopes in Table 1 are set to 0.1mOhm, the target correspondence of equal set voltage slopes for all main frequencies, as shown in Table 2, can be obtained. It should be understood that the power consumption modes shown in Table 2 are only illustrative examples; in practical applications, various other power consumption modes may exist.

[0182] Table 2 shows the target correspondence for all main frequencies with equal set voltage slopes.

[0183]

[0184] The set voltage slopes in Table 2 can be pre-stored in the power supply register of the electronic device. In this case, the power supply adjustment information provided by the processor may only contain the set supply voltage V for the next clock frequency. Of course, if the set voltage slopes are not pre-stored in the power supply register, after the processor first provides the power supply with the set supply voltage V and the set voltage slope R for the next clock frequency, the power supply can store the set voltage slope R for the next clock frequency in the electronic device's storage medium or the power supply register in the form of a constant voltage slope. For example, the set voltage slope R for the next clock frequency can be statically configured into the register all at once. Since the set voltage slopes for all clock frequencies in the target correspondence are equal to the constant voltage slope, the power supply essentially stores the set voltage slopes for all clock frequencies in the target correspondence in the form of a constant voltage slope.

[0185] After this, the power supply needs to readjust the voltage V supplied to the processor. out In this case, the processor only needs to dynamically set the internal reference voltage of the power supply through the communication interface, thereby reducing communication latency and voltage regulation latency, and shortening the voltage regulation time. For example, if the power supply does not store the voltage slope set in Table 2, and the CPU's next clock frequency is 1.5GHz, the CPU determines the set supply voltage for the next clock frequency to be 1.1V, and the set operating voltage slope R for the next clock frequency is 0.1mOhm. The CPU sets the internal reference voltage of the power supply to 1.0V through communication interfaces such as PMBus, and the voltage slope of the reference voltage is 0.1mohm. If the power supply stores the set voltage slope in Table 2 in the form of a constant voltage slope, the CPU only needs to look up the set supply voltage V of the next clock frequency as 1.1V from the target correspondence shown in Table 2, and set the internal reference voltage of the power supply to 1.1V through communication interfaces such as PMBus. The power supply then provides the processor with the supply voltage V based on the set voltage slope of 0.1mohm and the reference voltage of 1.1V. out .

[0186] For example, if the power supply does not store the voltage slope settings in Table 2, and the CPU's next clock speed is 2.5GHz, then the CPU will find a set supply voltage V of 1.2V for the next clock speed, and a set operating voltage slope R of 0.1mOhm. The CPU sets the reference voltage in the power supply to 1.2V with a voltage slope of 0.1mOhm via a communication interface such as PMBus. If the power supply stores the voltage slope settings in Table 2 as a constant voltage slope, the CPU only needs to determine that the set supply voltage V for the next clock speed is 1.2V and set the reference voltage in the power supply to 1.2V via a communication interface such as PMBus. The power supply then provides the processor with a supply voltage V based on the set voltage slope of 0.1mOhm and the reference voltage of 1.2V. out .

[0187] It should be noted that when the set voltage slope R of the next time period's main frequency exists within the power supply as a constant voltage slope, the target correspondence can be either the target correspondence shown in Tables 1 and 2, or the correspondence between the main frequency and the set supply voltage shown in Table 3. It should be understood that the power consumption modes shown in Table 3 are merely illustrative examples; in practical applications, various other power consumption modes may exist.

[0188] Table 3. Correspondence between main frequency and set power supply voltage

[0189]

[0190] The correspondence between clock frequency and set power supply voltage shown in Table 3 can be directly referenced from the correspondence between clock frequency and set power supply voltage used in existing DVFS technology. Of course, users can also reconstruct it themselves.

[0191] It should be noted that when the above target correspondence is a correspondence between the processor's clock speed, the set power supply voltage, and the set voltage slope, regardless of whether the set voltage slopes in the target correspondence are exactly equal, they are all stored in the storage medium using one of the following methods. The storage medium includes, but is not limited to, the motherboard's BIOS memory or the processor's internal memory.

[0192] The first method of storage: The target correspondence is stored in the storage medium in the form of a correspondence or a correspondence table of the processor's main frequency, set power supply voltage, and set voltage slope.

[0193] The second storage method: The target correspondence essentially includes two sub-correspondences. For example, these two sub-correspondences include the correspondence between the processor's clock speed and the set supply voltage, and the correspondence between the processor's clock speed and the set voltage slope. Another example: These two sub-correspondences include the correspondence between the set voltage slope and the set supply voltage, and the correspondence between the processor's clock speed and the processor's set supply voltage. Yet another example: These two sub-correspondences include the correspondence between the set voltage slope and the set supply voltage, and the correspondence between the processor's clock speed and the processor's set voltage slope.

[0194] As one possible implementation, the aforementioned target correspondence can be stored in a storage medium before or after leaving the factory.

[0195] After the electronic device leaves the factory, the target correspondence or the corresponding table formed by the target correspondence is determined and stored in the storage medium. It should be understood that after the electronic device leaves the factory, the performance of the processor inside the electronic device is determined. Therefore, the target correspondence obtained by directly debugging the electronic device after it leaves the factory is the target correspondence of the processor within the electronic device, where the storage medium is located. At this time, the compatibility between the target correspondence and the processor included in the electronic device is optimal.

[0196] For example, before electronic devices leave the factory, the target correspondence or the relationship table formed by the target correspondence is stored in the storage medium.

[0197] In practical applications, using the same target mapping for processors with different performance characteristics can lead to a mismatch between the target mapping and the processors included in the electronic device. In mass production, the target mapping stored in the storage medium before shipment should have broad applicability, allowing different processors to use the same target mapping. For example, the target mapping mentioned above is for a reference processor. The reference processor is the processor with the highest minimum supply voltage among multiple processors operating at the same clock frequency. In this case, the reference processor is the worst performing processor among the multiple processors. If a CPM circuit is used to measure multiple processors, it will be found that when multiple processors operate at the same clock frequency, the CPM circuit corresponding to the reference processor has the longest delay time and the highest oscillation frequency. In this case, the target mapping of the reference processor can be applied to any of the multiple processors. Therefore, when using the target mapping of the reference processor as the target mapping, this target mapping has broad applicability. It should be understood that the minimum supply voltage for each processor operating at a given clock frequency determines the processor's performance. For high-performance processors or chips, the minimum supply voltage at a given clock frequency is relatively low; for low-performance processors or chips, the minimum supply voltage at a given clock frequency is relatively high. Performance differences between processors are primarily caused by manufacturing processes or aging. Even within the same processor model, variations can occur between different batches.

[0198] The following examples illustrate various processor classification methods and the selection principles for benchmark processors. These explanations are for illustrative purposes only and are not intended to be limiting.

[0199] Processors or chips with relatively poor performance are defined as slow chips, and processors or chips with relatively good performance are also defined as slow chips. Taking into account the differences in various aspects between the highest-performing fast chips (the best-performing fast chips) and the lowest-performing slow chips (the worst-performing slow chips) (such as differences in aging and process variations), all processors between the highest-performing fast chips and the lowest-performing slow chips are divided into n processor tiers. One processor can be selected from each processor tier as the processor for that tier. At a given clock speed (e.g., 0.9GHz to 1.5GHz), the minimum supply voltage of the processors in the n tiers is measured. The processor or chip with the lowest minimum supply voltage is selected as the benchmark processor. Then, the target correspondence of this benchmark processor is determined and stored in a storage medium.

[0200] It should be noted that slow-motion films can be of one type or multiple types. When there are multiple types of slow-motion films, the main difference between them lies in their production processes. Similarly, fast-moving films can be of one type or multiple types. When there are multiple types of fast-moving films, the main difference between them lies in their production processes.

[0201] Given the differences between the processors in electronic devices and the benchmark processor (in terms of process, performance, etc.), if the target correspondence of the benchmark processor is directly used to find the set power supply voltage V and the set voltage slope R of the next period's main frequency, although it can still reduce processor power consumption to some extent, the search results are relatively biased, resulting in unsatisfactory power reduction effect and reliability.

[0202] To ensure good compatibility between the target mapping and the processors included in the electronic device, the reference processor should be calibrated. For example, AVS technology can be used to calibrate the reference processor. Specifically, as shown in Figure 10, before the processor searches for the set power supply voltage for the next time period's main frequency from the target mapping based on the next time period's main frequency, the method further includes:

[0203] Step 100c: The processor calibrates the target correspondence based on the performance difference information, ensuring that the calibrated target correspondence matches the processors included in the electronic device. The performance difference information is determined by the CPM circuit. Depending on the method of characterizing the performance difference information, it can be a delay level such as delay time or an oscillation frequency. Based on the source of the difference, the performance difference information can be process performance difference information, operating temperature performance difference information, or aging performance difference information. For example: processors in the same batch may have different minimum supply voltages at a given clock frequency due to process differences. Another example: at a given clock frequency, the same processor may have different minimum supply voltages in different temperature ranges. Yet another example: at a given clock frequency, the same processor may have different minimum supply voltages at different aging stages.

[0204] To facilitate processor calibration of the target correspondence without considering temperature differences, the storage medium should also pre-store the correspondence between various processor performance differences and minimum supply voltage differences, regardless of temperature variations. For ease of description, the correspondence between various processor performance differences and minimum supply voltage differences will be referred to as the multi-processor difference correspondence below.

[0205] In the correspondence of various processor differences, the performance difference of each processor can be represented by its latency level (such as latency time) or oscillation frequency, or indirectly by the difference in latency or oscillation frequency between the processor and the benchmark processor at the same voltage. The minimum supply voltage difference corresponding to the performance difference of each processor refers to the minimum supply voltage difference between the processor and the benchmark processor at the same clock frequency.

[0206] Without considering the influence of temperature, the performance difference information detected by the CPM circuit, and the processor's calibration of the target correspondence based on this performance difference information to match the target correspondence with the processor, include:

[0207] The processor searches for the lowest supply voltage difference from multiple processor difference mappings based on performance difference information. It then calibrates the set supply voltage corresponding to each clock frequency in the target mapping based on this lowest supply voltage difference, ensuring that the calibrated target mapping matches the processors included in the electronic device. Since performance difference information reflects the current state of the processors in the electronic device (such as performance, aging level, process deviation, and operating environment), searching for the lowest supply voltage difference from multiple processor difference mappings ensures a better match between the target mapping and the processors included in the electronic device after the processor calibrates the set supply voltage for each clock frequency included in the target mapping based on this lowest supply voltage difference.

[0208] Taking temperature effects into account, in order to facilitate processor calibration of the target correspondence, the storage medium should also pre-store the correspondence between the performance differences of multiple processors at multiple temperature levels and the differences in minimum supply voltage. For ease of description, the correspondence between the performance differences of multiple processors at multiple temperature levels and the differences in minimum supply voltage will be referred to as the difference correspondence between multiple processors at multiple temperature levels.

[0209] Taking temperature effects into account, the CPM circuit detects performance differences, and the processor calibrates the target correspondence based on this performance difference information to match the target correspondence with the processors included in the electronic device.

[0210] The processor searches for the corresponding relationships between the performance differences and minimum supply voltage differences of various processors at multiple temperature levels based on the current temperature. Then, it searches for the minimum supply voltage difference that matches the current performance difference information from the same relationships. Finally, it calibrates the set supply voltage corresponding to each main frequency in the target correspondence based on the minimum supply voltage difference that matches the performance difference information. This calibrated target correspondence matches the processors included in the electronic device, taking into account the impact of the current temperature on the target correspondence, thereby further improving the compatibility between the target correspondence and the processors included in the electronic device.

[0211] The correspondence between different processors at multiple temperature levels can be categorized into n temperature levels based on operating temperature. Each temperature level includes the correspondence between different processors at that specific temperature level. Alternatively, the target correspondence between different processors can also be categorized into n processor levels; each processor level includes the correspondence between processors at that specific temperature level across multiple temperature levels.

[0212] For the same processor, different operating temperatures will result in different performance differences measured by the processor's built-in CPM circuit. If the impact of temperature on performance difference information is disregarded, the accuracy of the minimum supply voltage difference found will not be very high. For example, if the storage medium contains the correspondence between the differences measured by multiple processors at 25°C and the target correspondence of a benchmark processor, and the processor's built-in CPM circuit measures performance differences at 45°C upon power-up after the electronic device leaves the factory, the minimum supply voltage difference found based on the 45°C performance difference information from the correspondence between the differences measured by multiple processors at 25°C will have a relatively large deviation.

[0213] If the impact of temperature on performance difference information is considered, the accuracy of the lowest supply voltage difference found is relatively high. For example, when the storage medium stores the correspondence between the differences of various processors at multiple temperature levels (including 45°C) and the target correspondence of the benchmark processor, when the electronic device is powered on after leaving the factory, the CPM circuit built into the processor measures the performance difference information at 45°C. This makes the deviation of the lowest supply voltage difference found from various processors at multiple temperature levels (including 45°C) based on the performance difference information measured at 45°C smaller compared to a solution that does not consider the impact of temperature on performance difference information.

[0214] It's important to note that regardless of whether temperature differences are considered, if the impact of clock speed on the minimum supply voltage difference is taken into account, the found minimum supply voltage difference essentially includes the minimum supply voltage differences of the processor at multiple clock speeds. These clock speeds correspond one-to-one with the clock speeds included in the target correspondence. In this case, the set supply voltages for multiple clock speeds in the target correspondence are calibrated based on the minimum supply voltage differences of the processor at multiple clock speeds. If the impact of clock speed on the minimum supply voltage difference is not considered, the found minimum supply voltage difference essentially includes the minimum supply voltage difference of the processor at a specific clock speed. In this case, the set supply voltages for all clock speeds in the target correspondence are calibrated based on the minimum supply voltage difference of the processor at that specific clock speed. The following descriptions of calibration for the target correspondence can refer to this section regarding whether clock speed is considered.

[0215] When the storage medium stores the difference correspondence in the form of a correspondence table, the method by which the processor calibrates the target correspondence based on the performance difference information is defined as the lookup table method. The specific process of the lookup table method is explained below with the processor having a built-in CPM circuit.

[0216] The first step, before shipment, is to test the target mapping table of the benchmark processor, using it as the test object. The target mapping table of the benchmark processor is then stored in a storage medium.

[0217] The second step, before shipping, is to divide the operating temperature range into multiple temperature levels, select one temperature from each level, and determine the correspondence between the differences of various processors at the corresponding temperature levels. The target correspondences for multiple temperature levels are then stored in the storage medium.

[0218] For example, the operating temperature range is 0℃~100℃. The 0℃~100℃ range is divided into five temperature ranges in 20℃ increments: 0℃~20℃, 21℃~40℃, 41℃~60℃, 61℃~80℃, and 81℃~100℃. From 0℃~20℃, 15℃ is selected; from 21℃~40℃, 28℃; from 41℃~60℃, 50℃; from 61℃~80℃, 75℃; and from 81℃~100℃, 90℃. Then, the delay time and minimum supply voltage of the CPM circuits built into various processors and a benchmark processor are tested at 15℃, 28℃, 50℃, 75℃, and 90℃. Based on the differences in delay time and minimum supply voltage of the CPM circuits built into the various processors and the benchmark processor, a table showing the differences between the various processors at the five temperature ranges is obtained. Table 4 shows the differences between the three processors at the 50℃ temperature range.

[0219] Table 4. Correspondence of differences among the three processors at 50℃ temperature ranges.

[0220] Processor type latency difference / ns Minimum supply voltage difference / V First processor ΔX1 Δv1 Second processor ΔX2 Δv2 Third processor ΔX3 Δv3

[0221] ΔX1 represents the delay difference of the built-in CPM circuit between the first processor and the benchmark processor; ΔX2 represents the delay difference of the built-in CPM circuit between the second processor and the benchmark processor; ΔX3 represents the delay difference of the built-in CPM circuit between the third processor and the benchmark processor; Δv1 represents the minimum supply voltage difference between the first processor and the benchmark processor; Δv2 represents the minimum supply voltage difference between the second processor and the benchmark processor; and Δv3 represents the minimum supply voltage difference between the third processor and the benchmark processor.

[0222] Step 3: After leaving the factory, under the condition of electronic equipment use, the CPM circuit measures the current delay time. The processor, based on the current temperature, looks up the difference between various processors at the current temperature range in a table showing the differences between processors at multiple temperature levels. Based on the current delay time measured by the processor's built-in CPM circuit and the current delay time measured by the reference processor's built-in CPM circuit, the current delay difference is determined. Based on the current delay difference, the lowest supply voltage difference corresponding to a delay time close to or the same as the current delay difference (the degree of closeness can be set according to actual conditions) is found in the table showing the differences between various processors at the current temperature range. The set supply voltage for each clock frequency in the target correspondence of the reference processor is calibrated based on the found lowest supply voltage difference.

[0223] For example: The current operating temperature is 45℃. The CPM circuit measures the delay time at 45℃. The current delay difference is obtained by comparing the delay time measured by the processor's built-in CPM circuit at 45℃ with the delay time measured by the reference processor's built-in CPM circuit at 50℃. Since 45℃ falls within the temperature range of 41℃ to 60℃, a delay difference that is close to or the same as the current delay difference is found in Table 4. Then, the lowest supply voltage difference is found in Table 4 based on the found delay difference. If the set supply voltage for a certain frequency in the target correspondence of the reference processor is V, and the determined lowest supply voltage difference is Δv3, then the calibrated set supply voltage is equal to V + Δv3.

[0224] When the difference correspondence is stored in the storage medium in the form of a mathematical function expression, the method by which the processor calibrates the target correspondence based on the performance difference information is defined as the mathematical deduction method. The specific process of the mathematical deduction method is explained below with the processor having a built-in CPM circuit.

[0225] The first step, before shipment, is to test the target mapping table of the benchmark processor, using it as the test object. The target mapping table of the benchmark processor is then stored in a storage medium.

[0226] The second step, before shipment, is to divide the operating temperature range into multiple temperature levels. From each temperature level, one temperature is selected, and the difference in latency between various processors and the minimum supply voltage at that temperature is determined. This temperature is then fitted to determine a functional relationship between the latency difference between various processors and the minimum supply voltage at that temperature. This functional relationship is Δv = kΔX + a, where k is a coefficient, a is a fixed constant, ΔX is the latency difference, and Δv is the minimum operating voltage difference. This mathematical expression is then stored in a storage medium.

[0227] For example, the operating temperature range is 0℃~100℃. Divide the 0℃~100℃ range into five temperature increments of 20℃: 0℃~20℃, 21℃~40℃, 41℃~60℃, 61℃~80℃, and 81℃~100℃. Select 15℃ from 0℃~20℃, 28℃ from 21℃~40℃, 50℃ from 41℃~60℃, 75℃ from 61℃~80℃, and 90℃ from 81℃~100℃. Then, fit five mathematical functions at 15℃, 28℃, 50℃, 75℃, and 90℃ respectively, with each function corresponding to one of the five temperature increments.

[0228] The third step is that after leaving the factory, when the electronic device is in use, the CPM circuit measures the current delay time. The processor selects a mathematical function relationship based on the current temperature range. Based on the delay time of the CPM circuit built into the processor at the current temperature and the delay time of the CPM circuit built into the reference processor at the current temperature, the current delay difference is obtained. The current delay difference is substituted into the selected mathematical function relationship to calculate the minimum supply voltage difference. Then, the target correspondence of the reference processor is calibrated based on the minimum supply voltage difference.

[0229] For example: The current operating temperature is 45℃. The CPM circuit built into the CPM circuit measures the current delay time at 45℃. The current delay difference is obtained by comparing the current delay time measured by the processor's built-in CPM circuit at 45℃ with the delay time measured by the reference processor's built-in CPM circuit at 45℃. This current delay difference is then substituted into the mathematical function relationship for the temperature range at 50℃, fitted to the reference processor, to obtain the minimum supply voltage difference. If the set supply voltage for a certain frequency in the target correspondence of the reference processor is V, and the determined minimum supply voltage difference is Δv3, then the calibrated set supply voltage is equal to V + Δv3.

[0230] It should be noted that, without considering the influence of temperature, the determined correspondence of differences among multiple processors can be viewed as a correspondence of differences among multiple processors within a single temperature range, albeit a wide range. For example, when considering the influence of temperature, the operating temperature range of 0℃ to 100℃ is divided into five temperature ranges: 0℃ to 20℃, 21℃ to 40℃, 41℃ to 60℃, 61℃ to 80℃, and 81℃ to 100℃. If the influence of temperature is ignored, then the correspondence of differences among multiple processors can be considered as a correspondence of differences among multiple processors measured within the 0℃ to 100℃ temperature range.

[0231] One possible implementation is to write multiple target mappings before the electronic device leaves the factory, and then determine the final target mappings after debugging. At this time, the storage medium stores the target mappings of the reference processor at multiple temperature levels or the target mappings of multiple processors.

[0232] When the storage medium stores the target correspondence of the reference processor at multiple temperature levels as described above, as shown in Figure 10, before the processor sends power supply adjustment information to the power supply according to the main frequency of the next time period, the above method further includes:

[0233] Step 100d: The processor searches for the target correspondence of the reference processor at multiple temperature ranges based on the current temperature. This target correspondence is the target correspondence of the reference processor at the current temperature range. At this point, the determined target correspondence of the reference processor takes into account the influence of temperature on the target correspondence, resulting in better matching between the calibrated target correspondence and the processors included in the electronic device.

[0234] The following section uses the lookup table method described earlier as an example to illustrate the process of determining and calibrating the target correspondence of the aforementioned benchmark processor.

[0235] The first step, before leaving the factory, is to determine the operating temperature range of the benchmark processor, which is 0℃~100℃. This range is then divided into five temperature increments of 20℃ each: 0℃~20℃, 21℃~40℃, 41℃~60℃, 61℃~80℃, and 81℃~100℃. From 0℃~20℃, 15℃ is selected; from 21℃~40℃, 28℃; from 41℃~60℃, 50℃; from 61℃~80℃, 75℃; and from 81℃~100℃, 90℃. The target temperature correspondence of the benchmark processor at these five temperature increments is then tested to obtain the corresponding temperature profiles for the processor across these five temperature ranges.

[0236] The second step, before shipment, involves testing the delay time and minimum supply voltage of the CPM circuits built into various processors and a benchmark processor at 15℃, 28℃, 50℃, 75℃, and 90℃. Based on the differences in delay time and minimum supply voltage of the CPM circuits built into the various processors and the benchmark processor, a table showing the differences between the various processors at 15℃, 28℃, 50℃, 75℃, and 90℃ is obtained, representing the differences between the various processors at multiple temperature ranges.

[0237] Step 3: After leaving the factory, under the condition of electronic equipment use, the current operating temperature is 45℃. The processor looks up the target correspondence of the reference processor at the 45℃ temperature level from the target correspondence table of the five temperature levels (i.e., the target correspondence of multiple processors at 50℃). The processor obtains the current delay difference value based on the delay time measured by the processor's built-in CPM circuit at 45℃ and the delay time of the reference processor's built-in CPM circuit at 45℃. Then, it finds a delay difference value that is close to or the same as the current delay difference value from Table 4. Based on the found delay difference value, it finds the lowest supply voltage difference from Table 4. If the set supply voltage of a certain frequency in the found target correspondence is V, and the determined lowest supply voltage difference is Δv3, then the calibrated set supply voltage is equal to V + Δv3.

[0238] When the storage medium stores target correspondences for multiple processors, without considering the influence of temperature, upon powering on the electronic device, the CPM circuit detects performance difference information. As shown in Figure 11, before the processor searches for the set power supply voltage for the next time period's main frequency from the target correspondences based on the next time period's main frequency, the above method further includes:

[0239] Step 100e: The processor searches for a target mapping that matches the processor included in the electronic device from the target mapping of multiple processors based on the performance difference information.

[0240] Ignoring temperature, each processor incorporates a CPM (Continuous Performance Monitoring) circuit. To facilitate the processor's search for a target correspondence with the processors included in the electronic device, the performance differences, such as oscillation frequency or delay time, of various processors can be measured using the built-in CPM circuit of each processor before shipment. This establishes a link between the performance differences and the target correspondence of the various processors. The performance difference information and the target correspondence are stored in a storage medium. For example, the performance difference information for each processor is its delay time. When the electronic device is powered on at the factory, the built-in CPM circuit determines the target correspondence based on the delay time.

[0241] Taking temperature into account, as shown in Figure 12, before the processor sends power supply adjustment information to the power supply according to the main frequency of the next time period, the above method further includes:

[0242] Step 100f: The processor searches for the target correspondence of multiple processors at multiple temperature levels based on the current temperature; and searches for the target correspondence that matches the processor included in the electronic device based on the performance difference information from the target correspondence of multiple processors at the current temperature level.

[0243] The target correspondence of the aforementioned multiple processors across multiple temperature levels can be divided into n temperature level target correspondences based on operating temperature. Each temperature level target correspondence includes the target correspondence of multiple processors at that temperature level. Alternatively, the target correspondence of multiple processors can also be divided into n processor level target correspondences based on different processor levels. Each processor level target correspondence includes the target correspondence of processors at the same level across n temperature levels. It should be understood that the target correspondence of processors at the same level across n temperature levels means: selecting one processor from all processors at that level as the test object and testing its target correspondence across n temperature levels. Furthermore, when n equals 1, the target correspondence of multiple processors has only one temperature level; this can be considered as the target correspondence of multiple processors without considering temperature. When n is an integer greater than or equal to 2, the target correspondence of multiple processors has two or more temperature levels. Moreover, the larger n is, the more temperature levels there are, and the closer the final determined target correspondence of the processors is to the actual target correspondence.

[0244] To facilitate the lookup of target mappings for processors within an electronic device based on performance difference information from multiple processor target mappings, the storage medium should also pre-store performance difference information for multiple processors at multiple temperature levels. Furthermore, the performance difference information for multiple processors at multiple temperature levels should be interdependent with the target mappings for multiple processors at multiple temperature levels, and then this performance difference information and the target mappings for multiple processors at multiple temperature levels should be stored in the storage medium.

[0245] In one scenario, performance differences among multiple processors at various temperature levels can be categorized according to temperature level, yielding multiple types of performance difference information corresponding one-to-one with each temperature level. Each type of performance difference information includes the performance differences among multiple processors at that temperature level (such as latency or oscillation frequency).

[0246] In another scenario, performance differences between various processors at multiple temperature levels can be categorized according to processor level, yielding multiple types of performance difference information corresponding one-to-one with each processor level. Each type of performance difference information includes performance differences between processors at the same level across multiple temperature levels (such as latency or oscillation frequency).

[0247] For example, the processor's operating temperature range is 0℃ to 100℃. The 0℃ to 100℃ range is divided into five temperature levels in 20℃ increments: 0℃ to 20℃, 21℃ to 40℃, 41℃ to 60℃, 61℃ to 80℃, and 81℃ to 100℃. Then, 15℃ is selected from 0℃ to 20℃, 28℃ from 21℃ to 40℃, 50℃ from 41℃ to 60℃, 75℃ from 61℃ to 80℃, and 90℃ from 81℃ to 100℃. Next, the target correspondence and latency of various processors are measured at 15℃, 28℃, 50℃, 75℃, and 90℃ respectively. This yields the target correspondence and latency of various processors at the five temperature levels, and establishes the dependency relationship between the target correspondence and latency of various processors at each temperature level. When the electronic device is powered on, the processor's built-in CPM circuit detects the current delay time at 45°C. It searches for similar or identical delay times among various processors at the same temperature range of 45°C (i.e., the delay times of various processors at 50°C), and determines the corresponding target correspondence based on the found delay times.

[0248] As one possible implementation, regardless of when the target correspondence stored in the aforementioned storage medium is entered into the storage medium, and regardless of how many types of processor target storage relationships are included in the target correspondence stored in the storage medium, the set supply voltage and set voltage slope in each target correspondence are determined in the following manner to ensure that the supply voltage V provided by the power supply to the processor is guaranteed. out It can reliably and stably reduce processor power consumption.

[0249] The power supply voltage set in the above target correspondence relationship can be determined according to the following relationship: the set power supply voltage of the processor at each clock frequency is V. (i) That is, the set supply voltage for each main frequency in the target correspondence is V. (i) .

[0250] V (i) =V min(i) +ΔV (i) V min(i) ΔV represents the minimum supply voltage required for the processor to operate normally at each clock frequency under increased load current. (i) This represents the power supply voltage margin for the processor at each clock frequency. ΔV (i) =20mV~60mV. For example: 40mV or 50mV, of course, can also be set according to the actual situation.

[0251] The allowable voltage slope of the processor's set supply voltage at each clock frequency can be determined according to the following relationship: The allowable voltage slope of the processor's set supply voltage at each clock frequency is R.(i) R (i) =R max(i) -ΔR (i) R max(i) ΔR is the maximum voltage slope of the set supply voltage for the processor at each clock frequency. (i) This represents the voltage slope margin for the processor at each clock frequency. Where ΔR... (i) = 0.03mOhm~0.08mOhm. For example: 0.05mOhm or 0.07mOhm. It should be understood that, for the target correspondence of equal set voltage slopes for all main frequencies, the allowable voltage slope R of the set supply voltage at each main frequency is determined. (i) After that, the allowable voltage slope R of the set power supply voltage for each main frequency should also be considered. (i) Select the minimum value and ensure that it is greater than 0. Use this minimum value as the set voltage slope that can be shared by multiple main frequencies, i.e., the constant voltage slope mentioned above.

[0252] The following examples illustrate the process of determining the target correspondence involved in the method provided in the embodiments of this application. These examples are for illustrative purposes only and are not intended to limit the scope of the application.

[0253] Step 1: Processing the Correspondence between Processor Frequency and Specified Power Supply Voltage: Before the CPU leaves the factory, the relationship between the CPU's frequency and minimum power supply voltage is measured using a CPU evaluation board. During testing, the power supply voltage slope is set to 0 Ohm. The test sample covers typical chips (also known as TT chips) and process deviation chips (also known as Corner chips). The test temperature covers the ambient temperature (i.e., operating temperature) of the CPU's claimed specifications, resulting in a set of processor frequency and minimum power supply voltage curves. The minimum power supply voltage should be the minimum power supply voltage that ensures the processor can operate normally. Simultaneously, a power supply voltage margin is added to the minimum power supply voltage for each frequency to obtain the processor's specified power supply voltage, preventing the power supply voltage from failing to guarantee normal processor operation when the load current increases. The power supply voltage margin refers to the allowable voltage deviation value for the minimum power supply voltage. Figure 13 shows the processor's frequency and power supply voltage curves. The X-axis represents the frequency, and the Y-axis represents the power supply voltage. Specifically, curve a in Figure 13 represents the processor's frequency and minimum power supply voltage curve, and curve b in Figure 13 represents the processor's frequency and specified power supply voltage curve. Curve a in Figure 13 can be obtained by increasing the minimum operating voltage by 50mV to obtain curve b in Figure 13.

[0254] As can be seen from curve b in Figure 13, curve b covers the frequency and set supply voltage under various typical modes, including low-power mode, rated mode, and two overclocking modes. Table 3, shown above, illustrates the correspondence between the CPU frequency and set supply voltage for curve b in different modes. As shown in Table 3, when the CPU operates in low-power mode, the CPU frequency is relatively low at 0.5GHz, and the set supply voltage is 0.9V; when the CPU operates in rated mode, the CPU frequency is 1.5GHz, and the set supply voltage is 1.1V; when the CPU operates in the first overclocking mode, the CPU frequency exceeds the rated frequency, reaching 2.5GHz, and the set supply voltage is 1.2V; when the CPU operates in the second overclocking mode, the CPU frequency further increases to 3.0GHz, and the set supply voltage is 1.3V.

[0255] It should be noted that the correspondence between the processor's clock frequency and the set power supply voltage in the method of this application can also be formed based on the correspondence table between the processor's clock frequency and the set power supply voltage used in the existing DVFS technology.

[0256] The second step is the process of generating the correspondence between the processor's clock speed, the set power supply voltage, and the set voltage slope: According to the settings of the clock speed and voltage in each CPU mode, the maximum voltage slope that can ensure the normal operation of the processor in each mode is determined, and a certain voltage slope margin is reserved. The voltage slope margin refers to the allowable error of the maximum voltage slope.

[0257] For example, Figure 14 shows the voltage slope diagram of the set supply voltage in rated mode. Line a in Figure 14 represents the maximum voltage slope of the set supply voltage in rated mode. When the processor is in rated mode, the set supply voltage is 1.1V. When the load current increases, the set supply voltage is actively reduced to the minimum value according to different voltage slopes. The maximum voltage slope that ensures normal operation of the processor is selected from these, and a certain voltage slope margin is subtracted from this to obtain the set voltage slope of the set supply voltage in rated mode, i.e., line b in Figure 14.

[0258] It should be understood that the voltage slope setting cannot be too large; otherwise, the processor will malfunction when the load current increases. Conversely, the voltage slope setting cannot be too small; otherwise, the reduction in processor power consumption will be insignificant. Therefore, the voltage slope setting for each mode, or rather, each clock speed, should be determined through repeated testing and cannot be set using a uniform standard. The process for determining the voltage slope setting for low-power mode, first overclocking mode, and second overclocking mode should refer to the process for determining the voltage slope setting for rated mode.

[0259] Figure 15 shows the voltage loadline curves under different power consumption modes. The X-axis represents the load current, and the Y-axis represents the set power supply voltage. Curve a in Figure 15 is the voltage slope curve for low power consumption mode, curve b is the voltage slope curve for rated mode, curve c is the voltage slope curve for the first overclocking mode, and curve d is the voltage slope curve for the second overclocking mode. Based on curve b in Figure 13 and curves a through d in Figure 15, the target correspondence shown in Table 1 can be determined.

[0260] It should be noted that when the set voltage slope corresponding to all main frequencies in the above target correspondence is equal to the constant voltage slope, after the second step, the smallest set voltage slope should be found from all the set voltage slopes corresponding to all main frequencies, and it should be ensured that this set voltage slope is greater than 0. This set voltage slope is used as the voltage slope shared by all main frequencies, i.e., the constant voltage slope. For example, in Table 1, the smallest set voltage slope that is not equal to 0 in low power mode, rated mode, first overclocking mode and second overclocking mode is 0.1V. Therefore, 0.1V is used as the set voltage slope shared by low power mode, rated mode, first overclocking mode and second overclocking mode.

[0261] The above mainly describes the solutions provided by the embodiments of this application from the perspective of interaction between various network elements. It is understood that each network element, such as a processor and power supply, includes corresponding hardware structures and / or software modules to perform the above functions. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the various examples described in the embodiments disclosed herein, the embodiments of this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed by hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.

[0262] In the case of using physical hardware, Figure 16 illustrates a device provided by an embodiment of this application. This device is applied to communication devices or terminal devices, but is not limited thereto. As shown in Figure 16, the device 200 includes a processor 201 and a power supply 202. The processor 201 is used to support the electronic device in performing step 101 as performed by the processor in the above embodiments. The power supply 202 is used to support the electronic device in performing steps 102 and 103 as performed by the power supply in the above embodiments.

[0263] In one possible implementation, as shown in FIG16, the processor 201 is further configured to perform step 100 as performed by the processor in the above embodiment.

[0264] In one possible implementation, as shown in FIG16, the processor 201 is further configured to support the electronic device in performing step 100a as performed by the processor in the above embodiment.

[0265] The processor 201 described above is also used to support the electronic device in performing steps 100b and 104 as performed by the processor in the above embodiments.

[0266] In one possible implementation, as shown in FIG16, the device 200 further includes a storage medium 203 for storing the correspondence between a computer program and a target. The power supply 202 stores a set voltage slope in the form of a constant voltage slope. The processor 201 is specifically used to execute steps 1011A and 1012A as executed by the processor in the above embodiments.

[0267] In another possible implementation, as shown in FIG16, the device 200 further includes a storage medium 203 for storing the correspondence between a computer program and a target. The processor 201 is specifically used to execute steps 1011B and 1012B as performed by the processor in the above embodiments.

[0268] In one possible implementation, as shown in FIG16, the device 200 further includes a storage medium 203 for storing a target correspondence between a computer program and a benchmark processor, and the processor 201 is further used to support the electronic device in performing step 100c as executed by the processor in the above embodiment.

[0269] In order to cooperate with the processor to perform the corresponding steps, as shown in Figure 16, the storage medium 203 is also used to store the correspondence between the differences of multiple processors, or the correspondence between the differences of multiple processors at multiple temperature levels.

[0270] In another possible implementation, as shown in FIG16, the device 200 further includes a storage medium 203 for storing the target correspondence between the computer program and the reference processor at multiple temperature levels. The processor 201 is also used to support the electronic device in executing step 100d as performed by the processor in the above embodiment. To cooperate with the processor in performing the corresponding steps, the storage medium 203 is also used to store the differential correspondence between various processors at multiple temperature levels.

[0271] In another possible implementation, as shown in FIG16, the device 200 further includes a storage medium 203 for storing computer programs and target correspondences with various processors. The processor 201 is also used to support the electronic device in executing step 100e as described in the above embodiment. To cooperate with the processor in executing the corresponding steps, the storage medium 203 is also used to store information on the performance differences of various processors.

[0272] In another possible implementation, as shown in Figure 16, the device 200 further includes a storage medium 203 for storing computer programs and target correspondences between various processors at multiple temperature levels. The processor 201 is also used to support the electronic device in executing step 100f as described in the above embodiment. To facilitate the processor in executing the corresponding steps, the storage medium 203 is also used to store performance difference information of various processors at multiple temperature levels.

[0273] This application embodiment can divide the processor and power supply into functional modules according to the above method example. For example, each function can be divided into a separate functional module, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0274] Figure 17 shows a schematic diagram of a voltage regulation device involved in the above embodiments, where each functional module is divided according to its corresponding function. This voltage regulation device is a processor or a chip applied to a processor. As shown in Figure 17, the voltage regulation device 300 includes: a sending module 303, used to support the voltage regulation device in executing step 101 executed by the processor in the above embodiments.

[0275] In one possible implementation, as shown in FIG17, the voltage regulation device 300 further includes a prediction module 301, which supports the voltage regulation device in performing step 100 executed by the processor in the above embodiment.

[0276] In one possible implementation, as shown in FIG17, the voltage regulation device 300 further includes a frequency synthesis module 304 for supporting the voltage regulation device in performing step 100a, or steps 100b and 104 executed by the processor in the above embodiment.

[0277] In one possible implementation, as shown in FIG17, the voltage regulating device 300 further includes a selection module 302 and a storage module 305. The storage module 305 is used to store target correspondences. The selection module 302 is also used to support the voltage regulating device in performing step 1011A executed by the processor in the above embodiment, and the sending module 303 is also used to support the voltage regulating device in performing step 1012A executed by the processor in the above embodiment.

[0278] In another possible implementation, as shown in FIG17, the voltage regulating device 300 further includes a selection module 302 and a storage module 305. The storage module 305 is used to store target correspondences. The selection module 302 is also used to support the voltage regulating device in performing step 1011B executed by the processor in the above embodiment, and the sending module 303 is also used to support the voltage regulating device in performing step 1012B executed by the processor in the above embodiment.

[0279] In one possible implementation, as shown in FIG17, the voltage regulation device 400 further includes a relationship correction module 306.

[0280] In one example, as shown in Figure 17, the storage module 305 is used to store the target correspondence of the reference processor. The correspondence correction module 306 is used to support the voltage regulation device in performing step 100c executed by the processor in the above embodiment.

[0281] In order to cooperate with the processor to perform the corresponding steps, the storage module 305 is also used to store the correspondence between different processors, or the correspondence between different processors at multiple temperature levels.

[0282] In another possible implementation, as shown in Figure 17, the storage module 305 stores the target correspondence of the reference processor at multiple temperature levels and the difference correspondence of various processors at multiple temperature levels. The relationship correction module 306 supports the voltage regulation device in performing step 100d executed by the processor in the above embodiment.

[0283] In another example, as shown in Figure 17, storage module 305 is used to store target correspondences among multiple processors and performance difference information among multiple processors. Relationship correction module 306 is used to support the voltage regulation device in performing step 100e executed by the processor in the above embodiments.

[0284] In another example, as shown in Figure 17, storage module 305 stores target correspondences among multiple processors and performance differences among multiple processors at multiple temperature levels. Relationship correction module 306 supports the voltage regulation device in executing step 100f performed by the processor in the above embodiments.

[0285] Figure 18 shows a schematic diagram of another voltage regulation device involved in the above embodiments, where each functional module is divided according to its corresponding function. This voltage regulation device is a power supply or a chip applied to a power supply. As shown in Figure 18, the voltage regulation device includes a receiving module 401 and a power supply module 402. The receiving module 401 supports the voltage regulation device in performing step 102 performed by the power supply in the above embodiments. The power supply module 402 supports the voltage regulation device in performing step 103 performed by the power supply in the above embodiments.

[0286] In one possible implementation, as shown in Figure 18, when the voltage regulation information includes the set supply voltage V of the main frequency for the next time period and the set voltage slope R for the next time period, the voltage regulation device 400 further includes a voltage identification module 404 and a slope identification module 405. The voltage identification module 404 supports the voltage regulation device in executing the above embodiment, whereby the power supply identifies the set supply voltage V of the main frequency for the next time period, thereby determining the reference voltage. The slope identification module 405 supports the voltage regulation device in executing the above embodiment, whereby the power supply determines the set voltage slope R for the next time period, thereby determining the voltage slope of the reference voltage.

[0287] In one possible implementation, as shown in FIG18, the voltage regulation device 400 further includes a storage medium 403 for storing a set voltage slope that exists at a constant voltage slope. The voltage regulation device 400 also includes a voltage identification module 404 for supporting the voltage regulation device in performing the above embodiment by identifying the set supply voltage V of the main frequency for the next time period, thereby determining the reference voltage.

[0288] All relevant content of each step involved in the above method embodiments can be referenced from the functional description of the corresponding functional module, and will not be repeated here.

[0289] FIG19 illustrates a voltage regulating device provided in an embodiment of this application when using an integrated unit. As shown in FIG19, the voltage regulating device 500 may include a communication unit 501. Optionally, the voltage regulating device 500 may further include a processing unit 502.

[0290] In one example, as shown in FIG19, the voltage regulating device 500 is a processor, or a chip applied in a processor. In this case, the processing unit 502 is used to support the voltage regulating device in performing step 100 executed by the processor in the above embodiment. The communication unit 501 is used to support the voltage regulating device in performing step 101 executed by the processor in the above embodiment.

[0291] In one possible implementation, as shown in FIG19, the processing unit 502 is further configured to support the voltage regulation device in performing steps 100a or 100b and 104 executed by the processor in the above embodiments.

[0292] In one possible implementation, as shown in FIG19, the voltage regulating device further includes a storage unit 503 for storing target correspondences. The processing unit 502 is also configured to support the voltage regulating device in executing step 1011A executed by the processor in the above embodiment. The communication unit 501 is also configured to support the voltage regulating device in executing step 1012A executed by the processor in the above embodiment.

[0293] In another possible implementation, as shown in FIG19, the voltage regulating device 500 further includes a storage unit 503 for storing target correspondences. The processing unit 502 is also used to support the voltage regulating device in executing step 1011B executed by the processor in the above embodiment, and the communication unit 501 is also used to support the voltage regulating device in executing step 1012B executed by the processor in the above embodiment.

[0294] In one possible implementation, as shown in FIG19, the storage unit 503 is used to store the target correspondence of the reference processor. The processing unit 502 is also used to support the voltage regulation device in performing step 100c executed by the processor in the above embodiment.

[0295] In order to cooperate with the processing unit 502 to perform the corresponding steps, the storage unit 503 is also used to store the correspondence between multiple processor differences, or the correspondence between multiple processor differences at multiple temperature levels.

[0296] In another possible implementation, as shown in Figure 19, the storage unit 503 is used to store the target correspondence of the reference processor at multiple temperature levels. The processing unit 502 is also used to support the voltage regulation device in performing step 100d executed by the processor in the above embodiment. To cooperate with the processing unit 502 in performing the corresponding steps, the storage unit 503 is also used to store the differential correspondence of various processors at multiple temperature levels.

[0297] In another possible implementation, as shown in Figure 19, the storage unit 503 is used to store target correspondences among multiple processors. The processing unit 502 is also used to support the voltage regulation device in performing step 100e executed by the processor in the above embodiments. To cooperate with the processing unit 502 in performing the corresponding steps, the storage unit 503 is also used to store performance difference information among multiple processors.

[0298] In another possible implementation, as shown in Figure 19, the storage unit 503 is used to store the target correspondences of various processors at multiple temperature levels. The processing unit 502 is also used to support the voltage regulation device in performing step 100f executed by the processor in the above embodiment. To cooperate with the processing unit 502 in performing the corresponding steps, the storage unit 503 is also used to store performance difference information of various processors at multiple temperature levels.

[0299] In another example, as shown in FIG19, the voltage regulator 500 is a power supply or a chip applied in a power supply. In this case, the communication unit 501 is used to support the voltage regulator in performing step 102 performed by the power supply in the above embodiments. The processing unit 502 is used to support the voltage regulator in performing step 103 performed by the power supply in the above embodiments.

[0300] In one possible implementation, as shown in FIG19, the voltage regulating device 500 may further include a storage unit 503 for storing data such as a set voltage slope existing at a constant voltage slope and program code executable by the voltage regulating device.

[0301] The processing unit 502 can be a processor or controller, such as a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this invention. The processing unit can also be a combination that implements computational functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc. The communication unit can be a transceiver, transceiver circuitry, or communication interface, etc. The storage unit can be a memory.

[0302] The communication unit described above can be a communication interface of the device, used to receive signals from other devices. For example, when the device is implemented as a chip, the communication unit is the communication interface used by the chip to receive or send signals from other chips or devices.

[0303] When the processing unit 502 shown in FIG19 includes a VRM chip, a logic control circuit and a Buck converter, the communication unit 501 includes a communication interface and a power interface, and the storage unit 503 is a memory, the voltage regulation device 500 involved in the embodiment of the present invention can be the power supply shown in FIG2.

[0304] When the processing unit 502 shown in FIG19 is a processor, the communication unit 501 is a communication interface, and the storage unit 503 is a memory, the voltage regulation device 500 involved in the embodiment of the present invention can be the processor shown in FIG2.

[0305] Figure 20 shows a schematic diagram of a chip structure. As shown in Figure 20, the chip 600 includes one or more processors 601 and a communication interface 602.

[0306] Optionally, as shown in Figure 20, the chip also includes a memory 603. The memory 603 may include read-only memory and random access memory, and provides operation instructions and data to the processor 602. A portion of the memory 603 may also include non-volatile random access memory (NVRAM).

[0307] In some implementations, memory 603 stores elements such as execution modules or data structures, or subsets thereof, or extended sets thereof.

[0308] In this embodiment of the application, as shown in FIG20, the processor 601 performs corresponding operations by calling the target correspondence stored in the memory 603.

[0309] In one possible implementation, the chips used for the processor and power supply have similar structures, and different devices can use different chips to achieve their respective functions.

[0310] As shown in Figure 20, the processor 601 controls the processing operations of either the processor or the power supply included in the electronic device in this embodiment of the application. The processor 601 can also be referred to as a central processing unit (CPU).

[0311] As shown in Figure 20, memory 603 includes read-only memory and random access memory, and provides instructions and data to processor 603. A portion of memory 603 may also include NVRAM. For example, in an application, memory, communication interface 602, and memory 603 are coupled together via bus system 604, which includes not only data buses but also power buses, control buses, and status signal buses. However, for clarity, all buses are labeled as bus system 604 in Figure 20.

[0312] In one possible implementation, as shown in FIG20, the communication interface 602 is used to support the chip in performing the receiving and transmitting steps of the processor and power supply in the above embodiments. The processor 601 is used to support the chip in performing the processing steps of the processor and power supply in the above embodiments.

[0313] On the one hand, a computer-readable storage medium is provided, in which instructions are stored, which, when executed, implement the functions of a processor as shown in any of the figures in Figures 4, 5, and 10-12.

[0314] On the other hand, a computer-readable storage medium is provided, which stores instructions that, when executed, implement the function of a power supply as shown in any of the figures in Figures 4, 5, and 10-12.

[0315] On the one hand, a computer program product including instructions is provided, wherein when the instructions are executed, the processor functions as shown in any of the figures in Figures 4, 5 and 10-12.

[0316] On the other hand, a computer program product including instructions is provided, wherein when the instructions are executed, the power supply function is implemented as shown in any of the figures in Figures 4, 5 and 10-12.

[0317] On the one hand, a chip is provided that is used in a processor. The chip includes at least one processor and a communication interface, the communication interface being coupled to at least one processor. The processor is used to execute instructions to implement the functions of the processor as illustrated in any of Figures 4, 5, and 10-12.

[0318] On the other hand, a chip is provided for use in a power supply. The chip includes at least one processor and a communication interface coupled to the at least one processor. The processor is used to execute instructions to implement the functions of the power supply as illustrated in any of Figures 4, 5 and 10-12.

[0319] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.

[0320] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0321] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0322] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0323] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0324] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, or the parts that contribute to the prior art, or parts of the technical solutions, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0325] The above are merely specific embodiments of this application, but the protection scope of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this application should be included within the protection scope of this application. Therefore, the protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A voltage regulation method, characterized in that, applied to an electronic device having a processor and a power supply, the method comprising: the processor sending power supply regulation information to the power supply according to the main frequency of the next time period; the power supply regulation information includes the set supply voltage V of the main frequency of the next time period, and the main frequency of the next time period refers to the main frequency predicted according to the current main frequency; The power supply supplies the supply voltage V to the processor according to the set supply voltage V of the main frequency in the next time period and the set voltage slope R of the main frequency in the next time period out ; Among them, the voltage slope refers to the decreasing speed of the supply voltage V as the load current of the power supply increases. out The supply voltage V out decreases as the load current increases; V min ≤V out ≤V, V min is the minimum supply voltage for the normal operation of the processor when the main frequency runs in the next time period under the condition that the load current increases.

2. The method according to claim 1, characterized in that, The supply voltage V out = V - I * R, where I is the load current of the power supply.

3. The method according to claim 1 or 2, characterized in that, the processor sending the set supply voltage V of the processor at the main frequency of the next time period to the power supply according to the main frequency of the next time period includes: the processor looking up the set supply voltage V of the main frequency of the next time period from the target correspondence relationship and sending the set supply voltage V of the main frequency of the next time period to the power supply; wherein, the target correspondence relationship is the correspondence relationship between the main frequency, the set supply voltage and the set voltage slope of the processor or the correspondence relationship between the main frequency and the set supply voltage of the processor.

4. The method according to any one of claims 1 to 3, characterized in that, The set voltage slope R of the next time period main frequency exists in the power supply in the form of a constant voltage slope, and the constant voltage slope is the minimum value R of the voltage slopes allowed by the set supply voltages of the processor at each main frequency min , R min > 0.

5. The method according to claim 1 or 2, characterized in that, the power supply regulation information further includes the set voltage slope R of the main frequency of the next time period.

6. The method according to claim 5, characterized in that, the processor sending power supply regulation information to the power supply according to the main frequency of the next time period includes: the processor looking up the set supply voltage V of the main frequency of the next time period and the set voltage slope R of the main frequency of the next time period from the target correspondence relationship and sending the set supply voltage V of the main frequency of the next time period and the set voltage slope R of the main frequency of the next time period to the power supply; wherein, the target correspondence relationship is the correspondence relationship between the main frequency, the set supply voltage and the set voltage slope of the processor.

7. The method according to claim 3 or 6, characterized in that, before the processor sends power supply regulation information to the power supply according to the main frequency of the next time period, the method further includes: the processor calibrating the target correspondence relationship according to the performance difference information so that the calibrated target correspondence relationship matches the processor included in the electronic device, wherein the performance difference information includes the delay time or the oscillation frequency.

8. The method according to claim 7, characterized in that, the processor calibrating the target correspondence relationship according to the performance difference information so that the calibrated target correspondence relationship matches the processor includes: the processor looking up the lowest supply voltage difference matching the performance difference information from the correspondence relationship between various processor performance differences and the lowest supply voltage differences; calibrating the set supply voltage of each main frequency in the target correspondence relationship according to the lowest supply voltage difference matching the performance difference information so that the calibrated target correspondence relationship matches the processor included in the electronic device; or, The processor looks up the corresponding relationship between the performance differences and the minimum supply voltage differences of multiple processors at the temperature range where the current temperature is located from the corresponding relationship between the performance differences and the minimum supply voltage differences of multiple processors at multiple temperature ranges according to the current temperature; looks up the minimum supply voltage difference matching the performance difference information from the corresponding relationship between the performance differences and the minimum supply voltage differences of multiple processors at the temperature range where the current temperature is located according to the performance difference information; calibrates the set supply voltage of each main frequency in the target corresponding relationship according to the minimum supply voltage difference matching the performance difference information, so that the calibrated target corresponding relationship matches the processor included in the electronic device.

9. The method according to any one of claims 3, 6 to 8, wherein, the target corresponding relationship is the target corresponding relationship of a reference processor, and the reference processor is the processor with the largest minimum supply voltage among multiple processors at the same main frequency.

10. The method according to any one of claims 3, 6 to 9, wherein, before the processor sends power supply adjustment information to the power supply according to the main frequency of the next time period, the method further includes: the processor looks up the target corresponding relationship from the target corresponding relationships of the reference processor at multiple temperature ranges according to the current temperature; the target corresponding relationship is the target corresponding relationship of the reference processor at the temperature range where the current temperature is located, and the reference processor is the processor with the largest minimum supply voltage among multiple processors at the same main frequency.

11. The method according to claim 3 or 6, wherein, before the processor sends power supply adjustment information to the power supply according to the main frequency of the next time period, the method further includes: the processor looks up the target corresponding relationship matching the processor included in the electronic device from the target corresponding relationships of multiple processors according to the performance difference information; the performance difference information includes the delay time or the oscillation frequency; or, the processor looks up the target corresponding relationships of multiple processors at the temperature range where the current temperature is located from the target corresponding relationships of multiple processors at multiple temperature ranges according to the current temperature; looks up the target corresponding relationship matching the processor included in the electronic device from the target corresponding relationships of multiple processors at the temperature range where the current temperature is located according to the performance difference information; the performance difference information includes the delay time or the oscillation frequency.

12. The method according to any one of claims 1 to 11, wherein, the set voltage slope of the processor at each main frequency is the voltage slope allowed by the set supply voltage of the processor at each main frequency; or, The set voltage slope of the processor at all main frequencies is equal to a constant voltage slope; the constant voltage slope is the minimum value R of the voltage slopes allowed by the set supply voltages of the processor at each main frequency min , R min > 0.

13. The method according to claim 4 or 12, wherein, The voltage slope allowed by the set supply voltage of the processor at each of the main frequencies is R (i) , R (i) = R max(i) -ΔR (i) , R max(i) is the maximum voltage slope of the set supply voltage of the processor at each of the main frequencies, and ΔR (i) is the voltage slope margin of the processor at each of the main frequencies.

14. The method according to any one of claims 1 to 13, wherein, The set supply voltage of the processor at each of the main frequencies is V (i) , V (i) = V min(i) + ΔV (i) , V min(i) is the minimum supply voltage at which the processor operates normally when the load current increases during operation at each of the main frequencies, and ΔV (i) is the supply voltage margin of the processor at each of the main frequencies.

15. The method according to any one of claims 1 to 14, wherein, the method further includes: when the processor determines that the main frequency of the next time period is not equal to the current main frequency, setting the current main frequency equal to the main frequency of the next time period.

16. An electronic device, wherein, Including: A processor, configured to send power supply adjustment information to a power supply according to the main frequency of the next time period; The power supply adjustment information includes a set power supply voltage V of the main frequency of the next time period, and the main frequency of the next time period refers to the main frequency predicted according to the current main frequency; A power supply, configured to supply a power supply voltage V to the processor according to a set supply voltage V of the main frequency in the next time period and a set voltage slope R of the main frequency in the next time period out ; Wherein, the voltage slope refers to the decreasing speed of the supply voltage V as the load current of the power supply increases. out The supply voltage V out decreases as the load current increases; V min ≤V out ≤V, V min is the minimum supply voltage for the processor to operate normally when the load current increases during the main frequency operation in the next time period.

17. The device according to claim 16, wherein, The supply voltage V out = V - I * R, where I is the load current of the power supply.

18. The device according to claim 16 or 17, wherein, The processor is specifically configured to look up the set power supply voltage V of the main frequency of the next time period from a target correspondence relationship, and send the set power supply voltage V of the next time period to the power supply; wherein, the target correspondence relationship is the correspondence relationship between the main frequency, set power supply voltage and set voltage slope of the processor or the correspondence relationship between the main frequency and set power supply voltage of the processor.

19. The device according to any one of claims 16 to 18, wherein, The set voltage slope R of the next time period main frequency exists in the power supply in the form of a constant voltage slope, and the constant voltage slope is the minimum value R of the voltage slopes allowed by the set supply voltages of the processor at each main frequency min , R min > 0.

20. The device according to claim 16 or 17, wherein, The power supply adjustment information includes a set voltage slope R of the main frequency of the next time period.

21. The device according to claim 20, wherein, The processor is specifically configured to look up the set power supply voltage V of the main frequency of the next time period and the set voltage slope R of the main frequency of the next time period from a target correspondence relationship, and send the set power supply voltage V of the main frequency of the next time period and the set voltage slope R of the main frequency of the next time period to the power supply; wherein, the target correspondence relationship is the correspondence relationship between the main frequency, set power supply voltage and set voltage slope of the processor.

22. The device according to claim 18 or 21, wherein, Before the processor sends power supply adjustment information to the power supply according to the main frequency of the next time period, the processor also calibrates the target correspondence relationship according to performance difference information, so that the calibrated target correspondence relationship matches the processor included in the electronic device, wherein the performance difference information includes delay time or oscillation frequency.

23. The device according to claim 22, wherein, The processor is specifically configured to look up the minimum power supply voltage difference matching the performance difference information from the correspondence relationship between various processor performance differences and minimum power supply voltage differences; calibrate the set power supply voltage of each main frequency in the target correspondence relationship according to the minimum power supply voltage difference matching the performance difference information, so that the calibrated target correspondence relationship matches the processor included in the electronic device; or, The processor is specifically configured to look up the correspondence relationship between the performance differences of multiple processors and the minimum power supply voltage differences at multiple temperature levels of the multiple processors at the current temperature from the correspondence relationship between the performance differences of multiple processors and the minimum power supply voltage differences at multiple temperature levels of the multiple processors; Find the minimum power supply voltage difference that matches the performance difference information from the corresponding relationship between the performance differences and the minimum power supply voltage differences of multiple processors at the temperature range where the current temperature is located; calibrate the set power supply voltage for each main frequency in the target corresponding relationship according to the minimum power supply voltage difference that matches the performance difference information, so that the calibrated target corresponding relationship matches the processor included in the electronic device.

24. The device according to any one of claims 18, 21 to 23, wherein, the target corresponding relationship is the target corresponding relationship of a reference processor, and the reference processor is the processor with the largest minimum power supply voltage among multiple processors at the same main frequency.

25. The device according to any one of claims 18, 21 to 24, wherein, before the processor sends power supply adjustment information to the power supply according to the main frequency of the next time period, find the target corresponding relationship from the target corresponding relationships of the reference processor at multiple temperature ranges according to the current temperature; the target corresponding relationship is the target corresponding relationship of the reference processor at the temperature range where the current temperature is located, and the reference processor is the processor with the largest minimum power supply voltage among multiple processors at the same main frequency.

26. The device according to claim 18 or 21, wherein, before the processor sends power supply adjustment information to the power supply according to the main frequency of the next time period, find the target corresponding relationship that matches the processor included in the electronic device from the target corresponding relationships of multiple processors according to the performance difference information; the performance difference information includes delay time or oscillation frequency; or, before the processor sends power supply adjustment information to the power supply according to the main frequency of the next time period, find the target corresponding relationship of multiple processors at the temperature range where the current temperature is located from the target corresponding relationships of multiple processors at multiple temperature ranges according to the current temperature; Find the target corresponding relationship that matches the processor included in the electronic device from the target corresponding relationships of multiple processors at the temperature range where the current temperature is located according to the performance difference information; the performance difference information includes delay time or oscillation frequency.

27. The device according to any one of claims 16 to 26, wherein, the set voltage slope of the processor at each main frequency is the voltage slope allowed by the set power supply voltage of the processor at each main frequency; or, The set voltage slopes of the processor at all main frequencies are equal to a constant voltage slope; the constant voltage slope is the minimum value R of the voltage slopes allowed by the set supply voltages of the processor at each main frequency min , R min > 0.

28. The device according to claim 19 or 27, wherein, The voltage slope allowed by the set supply voltage of the processor at each of the main frequencies is R (i) , R (i) = R max(i) - ΔR (i) , R max(i) is the maximum voltage slope of the lowest supply voltage of the processor at each of the main frequencies, and ΔR (i) is the voltage slope margin of the processor at each of the main frequencies.

29. The device according to any one of claims 16 to 27, wherein, The set supply voltage of the processor at each of the main frequencies is V (i) , V (i) = V min(i) + ΔV (i) , V min(i) is the minimum supply voltage for the processor to operate normally when the load current increases during operation at each of the main frequencies, and ΔV (i) is the supply voltage margin of the processor at each of the main frequencies.

30. The device according to any one of claims 16 to 29, wherein, when the processor determines that the main frequency of the next time period is not equal to the current main frequency, set the current main frequency to be equal to the main frequency of the next time period.

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