Device and method for producing a semiconductor wafer using reduced autodoping

Abstract

The invention relates to a wafer depositing assembly (1) for an epitaxial reactor for producing a semiconductor wafer with at least one epitaxial layer, wherein the layer depositing assembly (1) has a perforated susceptor unit (1.1) and a preheat ring (1.2), and the perforated susceptor unit (1.1) has a perforated susceptor unit upper face (1.12) and a perforated susceptor unit lower face (1.13). At least during an epitaxial depositing mode, (i) the preheat ring (1.2) at least partly surrounds the perforated susceptor unit (1.1) in spaced relation thereto via a gap unit (1.3), in particular in the form of an air gap ring, and the perforated susceptor unit (1.1) is designed to rotate relative to the preheat ring (1.2) about a vertical axis of the perforated susceptor unit (1.1) at a specifiable rotational speed, and (ii) the layer depositing assembly (1) additionally comprises at least one seal ring unit (1.4) which is provided on the layer depositing assembly (1) and is designed to provide a physical barrier unit on the gap unit (1 .3) between the perforated susceptor unit upper face (1.12) and the perforated susceptor unit lower face (1.13).

Description

Apparatus and method for producing a semiconductor wafer with reduced autodoping Technical area The invention relates to a layer deposition arrangement for an epi-reactor for producing a semiconductor wafer with at least one epitaxial layer. The invention further relates to a method for producing a semiconductor wafer, comprising depositing at least one epitaxial layer using the layer deposition arrangement. Finally, the invention relates to a semiconductor wafer comprising a doped substrate wafer and at least one epitaxial layer deposited thereon. State of the art and technical task In connection with epi-coating processes of (highly) doped substrate wafers in epi-reactors, the problem is known that during the deposition of an epitaxial layer on a (highly) doped substrate wafer (e.g. boron-doped substrate wafer) to produce a semiconductor wafer, due to the high prevailing epi-process temperatures, dopants from the substrate wafer, which are deposited in a hole susceptor unit in the layer deposition arrangement, initially pass from the back of the substrate wafer (i.e. the side of the substrate wafer facing a hole susceptor unit within the epi-reactor) during the epi-deposition mode via the gas phase into the deposition gas (uncontrolled) and then finally are incorporated into the epitaxial layer predominantly in the edge region of the front side of the substrate wafer (i.e. the side of the substrate wafer on which an epitaxial layer is deposited during the epi-deposition mode).This undesirable phenomenon is known as "autodoping," which leads to a radial fluctuation in the resistivity along the deposited epitaxial layer of the semiconductor wafer, which is usually specified by the parameter "radial resistance variation" (RRV). The RRV value [%] is calculated from measured, individual R values ​​resulting from a predefined number of measurement points on a measurement grid (cross-shaped measurement grid) on the epitaxial layer of the semiconductor wafer according to the equation RRV [%] = (R ma x - Rmin) / (Rmax + Rmin) (in particular according to Semi Standards M62-0317 (Specification for Silicon Epitaxial Wafers), 2017). To improve the RRV value, it is known from the prior art to first seal the (highly) doped substrate wafer with an LTO (Low Thermal Oxide) layer on the back of the semiconductor wafer (i.e., the side of the substrate wafer facing a hole susceptor unit within the epi-reactor). The substrate wafer, including the applied LTO layer, is then placed in an epi-reactor within a hole susceptor unit and subjected to the epi-deposition mode. This LTO layer acts as a dopant diffusion barrier layer and serves to prevent, as far as possible, the out-diffusion of dopants from the substrate wafer into the (at least one) epitaxial layer during the epi-coating process.Although the provision of such an oxide layer results in comparatively lower radial resistivities (RRV) after epitaxial deposition, the retention of such an oxide layer on a manufactured semiconductor wafer can be detrimental as the final product. Even after manual and / or chemical post-processing (e.g., by cleaning with HF) to remove this layer, undesirable defects remain as residues on the semiconductor wafer, particularly due to the fact that inhomogeneous, epitaxial growth occurs at the edge of the oxide layer during the epi-process. These defects can be detected as light point defects using an inspection device, in particular an EBI unit, by scattered light measurement (e.g., using an EBI unit from Nanophotonics AG with a functionality as described in paragraph 52 of the document DE102009011622 A1).These defects typically occur in the form of a substantially ring-shaped defect ring with a high defect density or number of defects in the vicinity of the edge region of the semiconductor wafer. The present invention is therefore based on the objective, technical problem of producing, in an epi-deposition mode by means of a compact hole susceptor unit of a layer deposition arrangement, a semiconductor wafer with an epitaxial layer from a (highly) doped substrate wafer, which does not have the above-mentioned disadvantages or at least has them to a lesser extent and which in particular has a low RRV value in combination with a comparatively defect-reduced surface of the free substrate wafer area of ​​the final semiconductor wafer. The object is achieved according to the first aspect of the present invention by providing a layer deposition arrangement with a susceptor unit according to the features in claim 1, is further achieved according to a second aspect by the method for producing a semiconductor wafer using the Layer deposition arrangement comprising the deposition of at least one epitaxial layer according to the features of claim 7, and finally solved according to a third aspect by the provision of a semiconductor wafer according to the features of claim 10. Preferred embodiments are the subject of the dependent claims. The invention is based on the technical teaching that a semiconductor wafer with a comparatively low RRV (i.e. low RRV value) of the deposited epitaxial layer of the semiconductor wafer with a comparatively defect-reduced second wafer side of the doped substrate wafer can be obtained in a simple manner if (i) the layer deposition arrangement for producing the semiconductor wafer is designed with a correspondingly designed hole susceptor unit so as to be rotatable relative to the preheating ring (and spaced apart from each other via a correspondingly designed gap unit),so that a reliable rotation of the hole susceptor unit relative to the preheating ring and thus a continuous and uniform deposition of the epitaxial layer is ensured during the epi deposition mode, and (ii) to combat the occurrence of the "autodoping" phenomenon in the semiconductor wafer to be produced during the epi deposition mode, the layer deposition arrangement with its hole susceptor unit is designed such that a reliable physical barrier unit against unwanted flows is ensured between the top and bottom of the layer deposition arrangement during the epi deposition mode. General description of the invention According to a first aspect, the invention therefore relates to a layer deposition arrangement for an epi-reactor for producing a semiconductor wafer with at least one epitaxial layer, wherein the layer deposition arrangement comprises a hole susceptor unit and a preheating ring, wherein the hole susceptor unit has a hole susceptor unit top side and a hole susceptor unit bottom side, and wherein, at least during an epi-deposition mode, ■ the preheating ring surrounds the hole susceptor unit at least partially via a gap unit, in particular in the form of an air gap ring, wherein the hole susceptor unit is designed to rotate at a predeterminable rotational speed about a height axis, in particular a height center axis, of the hole susceptor unit relative to the preheating ring, and wherein ■ the layer separation arrangement further comprises at least one sealing ring unit which is arranged on the layer separation arrangement and is designed to Gap unit to provide a physical barrier unit between the hole susceptor unit top and the hole susceptor unit bottom. The term "between" in the sense of the invention does not represent a directional restriction for the effect of the physical barrier (unit). As a result of the design of a layer deposition arrangement according to the invention (in particular due to the selected relative arrangement of the components of the layer deposition arrangement or arrangement of the gap unit to one another) and in particular as a result of the special design of the component of the sealing ring unit with respect to the gap unit, an exchange of at least one of deposition process gases and dopants via the gap unit between the hole susceptor unit underside and the hole susceptor unit top side can be reduced, in particular substantially avoided, during an epi-deposition mode of the layer deposition arrangement. However, it is particularly advantageous that a flow of deposition process gases via the gap unit from the direction of the hole susceptor unit top side towards the hole susceptor unit bottom side and a flow of dopant via the gap unit from the direction of the hole susceptor unit bottom side towards the hole susceptor unit top side can be reduced, preferably substantially avoided. For this purpose, the sealing ring unit can in principle be arranged at any desired location on the layer separation arrangement, as long as the described function of creating a blocking effect or a physical barrier (unit) between the top and the bottom of the layer separation arrangement is ensured in order to contribute to reducing or, ideally, avoiding the "autodoping" effect.In particularly advantageous variants of the layer deposition arrangement, the sealing ring unit is arranged on the hole susceptor unit, in particular on the hole susceptor unit underside or the hole susceptor unit top side, and arranged with respect to the preheat ring in such a way that a flow of deposition process gases via the gap unit from the direction of the hole susceptor unit top side into the hole susceptor unit underside is reduced, preferably substantially avoided, and that a flow of dopant via the gap unit from the direction of the hole susceptor unit underside into the hole susceptor unit top side is reduced, preferably substantially avoided.Alternatively, it can be provided that the sealing ring unit is arranged on the preheating ring, in particular on the side of the layer deposition arrangement facing the hole susceptor unit underside or the hole susceptor unit top side, and is arranged with respect to the hole susceptor unit in such a way that a flow of. Deposition process gases via the gap unit from the direction of the hole susceptor unit top side into the hole susceptor unit bottom side is substantially reduced, preferably substantially avoided, and that a flow of dopant via the gap unit from the direction of the hole susceptor unit bottom side into the hole susceptor unit top side is reduced, preferably substantially avoided. Additionally or alternatively, the sealing ring unit can be arranged at a location on the side of the layer deposition arrangement facing the hole susceptor unit's underside, in particular directly on the hole susceptor unit's underside. In an alternative variant, the sealing ring unit can be arranged at a location on the side of the layer deposition arrangement facing the hole susceptor unit's top side, in particular on an upper side of the preheat ring. Additionally or alternatively, the sealing ring unit can be arranged on the layer deposition arrangement in such a way that it at least partially overlaps the hole susceptor unit and the preheat ring, viewed in a radial direction of the hole susceptor unit, and substantially completely projects beyond the gap unit, in particular in the form of an air gap ring, viewed in the radial direction. In other words, it is also conceivable that the sealing ring unit can be arranged on the layer deposition arrangement within the gap unit, as long as the above-described function of the sealing ring unit as a physical barrier unit is ensured and at the same time, despite the internal arrangement within the gap unit, the reliable rotation of the hole susceptor unit relative to the preheat ring during the epi-deposition mode is ensured. Although a single sealing ring unit arranged accordingly on the layer deposition arrangement already reliably assumes the function of creating a physical barrier unit, in further preferred variants, at least one further sealing ring unit can be arranged. In such a layer deposition arrangement, for example, a first sealing ring unit can be arranged on the underside of the susceptor unit according to one of the variants described herein, and a second sealing ring unit can be arranged on the top side of the preheat ring according to one of the variants described herein. This achieves particularly advantageous reductions, even preventing the occurrence of the "autodoping" effect during the epi-deposition mode. In principle, the geometric design of the hole susceptor unit and the preheat ring and the position of the split ring and the sealing ring unit can be designed in any way as long as the above-described requirements for the layer deposition arrangement with regard to production of the semiconductor wafer without the occurrence of an "autodoping" effect and with regard to reliable rotation of the hole susceptor unit relative to the preheating ring and uniform deposition of the epitaxial layer during epi deposition mode are ensured. In particularly advantageous variants of the invention, however, it is preferably provided that the preheating ring unit, preferably starting from a circumferential edge of the hole susceptor unit, is arranged at a distance with respect to a radial direction of the hole susceptor unit via a gap unit formed substantially annularly around the hole susceptor unit, in particular in the form of an air gap ring, and the preheating ring surrounds the hole susceptor unit at least in sections, preferably completely, at least along a circumferential direction of the hole susceptor unit.This results in particularly compact, reliable designs of the layer separation arrangement. The sealing ring unit can, in principle, be of any geometric design, as long as it achieves the functions described in detail above in the layer separation arrangement. In particularly advantageous variants, the sealing ring unit is preferably designed essentially in the shape of an annular disk; in this case, the sealing ring unit can be designed with essentially plane-parallel surfaces in radial section or have a different shape in radial section, such as an L-shape or Z-shape. In further advantageous variants, the sealing ring unit can be substantially annular and, viewed along its radial direction, have a sealing ring width in a range from 5 mm to 50 mm, preferably in a range from 15 mm to 25 mm. In addition, the gap unit can be designed in the form of an air gap ring and, viewed in the radial direction of the hole susceptor unit, have a gap width in the range from 1.2 mm to 2.6 mm, preferably in the range from 1.5 mm to 2.2 mm, more preferably substantially 1.9 mm, wherein in particular the gap width is substantially constant along the circumferential direction. In all these variants of the sealing ring design, the functions of the sealing ring unit on the layer separation arrangement described above are fully achieved. In principle, the radial direction can be understood as any direction starting from a center point (or center axis) of the, in particular essentially symmetrical, hole susceptor unit in the direction of the gap unit and along a hole susceptor unit radius. In principle, the sealing ring unit can be attached to the layer separation arrangement in any desired manner or be a physical part thereof. In an advantageous variant, the sealing ring unit is preferably arranged in a detachably attached manner to the layer separation arrangement, for example, to the hole susceptor unit or to the preheating ring. Such designs allow very flexible replacement of the component and access to more internal components (in particular the gap unit) during repairs, maintenance, or other intervention situations in the layer separation arrangement. The sealing ring unit is preferably detachably attached to the hole susceptor unit or to the preheating ring via a clamp connection, plug connection, or screw connection. Preferably, the sealing ring unit is made of a material comprising SiC or graphite or quartz. As an alternative to these variants, the sealing ring unit can be designed essentially as a monolithic unit with the hole susceptor unit or with the preheat ring. Such a design advantageously reduces the number of joints in the layer deposition arrangement compared to detachable connection points of the sealing ring unit. The invention has further recognized that in order to further reduce (or in particular substantially avoid) the "autodoping" phenomenon in the semiconductor wafer to be produced during the epi deposition mode, the layer deposition arrangement with its hole susceptor unit should preferably be designed such that a reliable physical barrier unit is ensured between the top side and the bottom side of the layer deposition arrangement and also between the support surface for the semiconductor wafer on the hole susceptor unit and the top side of the hole susceptor unit. The receiving location on the hole susceptor unit for the substrate wafer can, in principle, be designed as desired. Particularly advantageous embodiments for reducing or avoiding the "autodoping" effect in the semiconductor wafer to be produced are achieved if a reliable physical barrier unit is also ensured between the support surface for the semiconductor wafer on the hole susceptor unit and the top side of the hole susceptor unit. This can be advantageously achieved by preferably designing and inclining the support surface (i.e., by designing its geometric shape) in such a way that the substrate wafer placed thereon itself becomes or acts as a physical barrier unit.In order to achieve this advantageous effect, in particularly advantageous variants it is provided that the hole susceptor unit has a recess in the form of a substrate wafer receiving unit on the hole susceptor unit top side, which in turn has a. Substrate wafer receiving surface which is essentially designed in the manner of an inner surface of a truncated cone or funnel-shaped, wherein this surface, starting from a ledge reference point on a reference circle on the substrate wafer receiving surface, has an inclination with respect to a radial direction of the hole susceptor unit and a horizontal plane of the hole susceptor unit in the form of a ledge angle, wherein the ledge angle has an angular size in the range from 0.0° to 2.0°, preferably in the range from 0.1° to 1.0°, more preferably in the range from 0.2° to 0.5°, and viewed along a circumferential direction of the hole susceptor unit is essentially constant with a maximum scatter of 1%, preferably a maximum of 0.5%, more preferably a maximum of 0.25%, along the circumferential direction. In other words, by carefully selecting the geometric design of the support surface, namely in the form of this truncated cone-shaped or funnel-shaped substrate wafer receiving surface within the hole susceptor unit, a support surface for a substrate wafer can be created which, when a substrate wafer is deposited during the epi-deposition mode, then creates a largely joint-free, i.e. "tight" (in particular essentially annular) contact area (between the substrate wafer and the support surface on the hole susceptor unit), which forms a further physical barrier against unwanted flows between the top and bottom of the layer deposition arrangement and thus makes a positive contribution to reducing or essentially avoiding the "autodoping" effect in the epitaxial layer. In particularly advantageous variants, in order to reduce, and in particular prevent, the "autodoping" effect, the substrate wafer receiving surface itself does not include any perforated units. However, perforated units are preferably distributed within the inner bottom surface of the substrate wafer receiving unit of the hole susceptor unit, as is also provided for the generic hole susceptor unit (which will not be discussed in detail here). It is also particularly advantageous if the substrate wafer receiving surface preferably has a flatness-shape tolerance in the range of 0.002 mm to 0.012 mm, preferably in the range of 0.005 mm to 0.008 mm. Such flatness of the substrate wafer receiving surface also contributes to a largely seamless, i.e., "tight," support of a substrate wafer when placed on top, thus ensuring the required physical barrier. The position of the reference circle particularly defines the starting range of the inclination (ledge angle QL) of the substrate wafer receiving surface within the substrate wafer receiving unit. Preferably, the reference circle coincides with the inner peripheral edge of the phase of the substrate wafer receiving unit. In alternative, advantageous variants, the reference circle can extend from this inner peripheral edge toward the height center axis of the Hole susceptor unit; can therefore have a smaller reference radius than the (imaginary) radius to the inner peripheral edge of the Substrate wafer holding unit. A further advantageous contribution to reducing or substantially avoiding the "autodoping" phenomenon in the epitaxial layer during epi deposition mode can be achieved if, preferably, a purge unit with a purge gas, in particular hydrogen, is provided on the side of the layer deposition arrangement facing the underside of the hole susceptor unit. In this case, the geometric orientation of a purge nozzle of the purge unit and the purge pressure of the purge gas at the purge unit can be preset and adjustable. By providing the physical barrier units described above, it is possible to advantageously reduce, in particular substantially prevent, process gases from passing from the top side to the bottom side of the layer deposition arrangement and causing coatings or deposits, whereby a purge gas purge, which is in particular a hydrogen purge, can advantageously be reduced by means of the purge unit under the hole susceptor unit to 3 slm (compared to typically higher values ​​in the range of 8 slm to 30 slm). According to a further, second aspect, the invention relates to a method for producing a semiconductor wafer using the layer deposition arrangement just described according to one of the variants described above (or combinations thereof), comprising the deposition of at least one epitaxial layer on a (highly) doped substrate wafer, which has no dopant diffusion barrier layer, in particular no LTO layer, for producing the semiconductor wafer in an epi reactor, wherein the method comprises the following steps: ■ Positioning a second wafer side of the doped substrate wafer on a hole susceptor unit, in particular on a substrate wafer receiving surface, of a layer deposition arrangement according to one of the above-described embodiments or variants for the layer deposition arrangement (or any combination of the above-described preferred variants), Starting an epi-deposition mode of the layer deposition arrangement Depositing at least one epitaxial layer on a first wafer side of the doped substrate wafer during the epi deposition mode. It is provided that at least during the epi-deposition mode, a rotation of the hole susceptor unit takes place about a height center axis of the hole susceptor unit relative to the preheat ring at a predeterminable rotation speed, in particular in the range of 25 rpm to 60 rpm. The epi-deposition mode is preferably understood to mean the process mode which comprises the complete deposition process of at least one epitaxial layer onto the substrate wafer within a (conventionally designed) epi-reactor. Preferably, the epi deposition mode includes, in addition to the actual deposition process, upstream and downstream process times during which, for example, only the hole susceptor unit with the substrate wafer placed thereon rotates relative to the preheat ring without deposition taking place at the same time. The layer deposition arrangement is preferably designed so that different epi-deposition modes can be carried out at different times, wherein the modes can differ, for example, in the flow rate of the deposition gases in the epi-reactor, the type of deposition medium, the predetermined epi-process temperature window, the rotational speed of the hole susceptor unit, etc. Preferably, the substrate wafer is formed as a single-crystalline silicon wafer and the deposited at least one epitaxial layer is a single-crystalline silicon layer. By means of the method according to the invention using the layer deposition arrangement described above (ie with essentially avoiding an "autodoping" effect during the epi-deposition mode), a semiconductor wafer with the advantageous properties described above with regard to the RRV value of the epitaxial layer and with a comparatively defect-reduced surface quality of the final semiconductor wafer (in particular with regard to the surface side of the substrate wafer, which in the prior art is at least temporarily provided with an LTO layer) can be fully achieved. A further advantageous contribution to reducing or essentially avoiding the “autodoping” phenomenon in the epitaxial layer during the epi-deposition mode can be can be achieved if the method further preferably provides that during the epi-deposition mode, a purge unit with a purge gas, in particular in the form of hydrogen, is provided on the side of the layer deposition arrangement facing a hole susceptor unit underside, wherein the purge by means of the purge gas, in particular in the form of a hydrogen purge, under the hole susceptor unit can be maintained in a predeterminable, controlled and variable manner, in particular at at least 3 slm and a maximum of 30 slm, via the epi-deposition mode. In further preferred variants of the method, it is preferably provided that after completion of the deposition of at least one epitaxial layer and after termination of the epi-deposition mode, the semiconductor wafer produced undergoes a final cleaning step which comprises chemical cleaning of the semiconductor wafer. According to a further, third aspect, the invention finally relates to a semiconductor wafer comprising a substrate wafer and at least one epitaxial layer, wherein ■ the substrate wafer is doped by means of at least one dopant, in particular boron, ■ the at least one epitaxial layer is arranged on a first side of the substrate wafer, and ■ the semiconductor wafer: has a radial resistance variation (RRV) in a range from 1.30% to 2.20%, and has at least 1 defect and fewer than 200 defects on a second wafer side of the substrate wafer, which defects can be detected as light point defects using an inspection device by means of scattered light measurement, and which are arranged on a defect ring which is, at least in sections, essentially annular and which extends within an essentially annular region on the second wafer side, the region having a radial width of 3 mm and its outer circumference essentially coinciding with the semiconductor wafer edge. The semiconductor wafer according to the invention with its advantageous RRV value and simultaneously its comparatively defect-reduced second wafer side is a direct result of an epitaxial deposition on a boron-doped substrate wafer according to the inventive method carried out on the layer deposition arrangement according to the invention (i.e. in the complete absence of an LTO layer). These few (at least 1 defect and less than 200) defects on the inventive In this case, the defects on the semiconductor wafer result, in particular, only from scratches or from frictional deposition conditions of the semiconductor wafer edge on the substrate wafer support surface during epi mode (and not additionally from a large number of additional defects due to LTO layer residues in this area, as is the case in the prior art). The number of these defects is preferably in a range from 1 defect to 100 defects, more preferably in a range from 6 to 100 defects. These defects (in their advantageously comparatively small number) can be detected as light point defects, in particular using an inspection device by means of scattered light measurement, in particular using an EBI unit (e.g. from Nanophotonics AG with a function as described in paragraph 1).

[0053] described in DE102009011622 A1). In other words, it is preferably provided that no layer in the form of a dopant diffusion barrier layer, in particular in the form of a low thermal oxide (LTO) layer, is arranged on the second wafer side of the substrate wafer, wherein, in particular, at no time during the production of the semiconductor wafer is a low thermal oxide (LTO) layer arranged on the second wafer side of the substrate wafer. In other words, it is particularly provided that no residues in the form of defects of a low thermal oxide (LTO) layer are arranged on the second wafer side of the substrate wafer. In preferred variants, it can be provided that the doped substrate wafer with dopant boron forms a substrate resistance of the substrate wafer between 0.005 and 0.020 Ohmcm, and / or the semiconductor wafer has an RRV in a range of 1.40% to 2.10%, preferably in a range of 1.45% to 2.00%. Preferably, the substrate wafer is formed as a single-crystalline silicon wafer and the deposited at least one epitaxial layer is a single-crystalline silicon layer. Preferably, the deposited epitaxial layer has an average layer thickness in a range of 1.5 pm to 20 pm. However, the invention is not limited to this range, and a larger or smaller layer thickness of the deposited epitaxial layer is possible. Preferably, the substrate wafer has an average layer thickness of substantially 775 pm. However, the invention is not limited to this range, and a larger or smaller layer thickness of the substrate wafer is possible. The invention is particularly suitable for manufactured semiconductor wafers with a target diameter in a range of 290 to 310 mm, in particular for a semiconductor wafer with a target diameter of substantially 300 mm ("300 mm wafer"), but is not limited thereto. For example, the production of a "200 mm" wafer is also conceivable (with a corresponding adjustment of the diameter of the recess unit of the susceptor unit). In further preferred variants of the semiconductor wafer, the semiconductor wafer can be designed such that, for a doped substrate wafer of the semiconductor wafer with a substrate resistance in a range of 0.005 to 0.008 Ohmcm, it forms an RRV of the semiconductor wafer in a range of 1.40% to 2.10%, preferably in a range of 1.45% to 2.00%. Alternatively, the semiconductor wafer can be designed such that, for a doped substrate wafer of the semiconductor wafer with a substrate resistance in a range greater than 0.008 to 0.016 Ohmcm, it forms an RRV of the semiconductor wafer in a range of 1.40% to 1.80%, preferably in a range of 1.45% to 1.60%, more preferably substantially of 1.50%.In particular, the described RRV values ​​can be achieved in an epi deposition mode of an epi process which is carried out at a temperature in the range of 1080°C to 1125°C, preferably in the range of 1100°C to 1120°C, and in particular the substrate wafer is boron-doped. In relation to semiconductor wafers manufactured using conventional hole susceptor units (i.e., in particular, without a sealing ring and / or without a correspondingly geometrically designed substrate wafer receiving surface within the hole susceptor unit), the described preferred variants of the semiconductor wafers further exhibit the advantage that their RRV values ​​are significantly lower compared to RRV values ​​of those semiconductor wafers manufactured using these conventional hole susceptor units and using substrate wafers (likewise) without a dopant diffusion barrier layer. Furthermore, the RRV value of the semiconductor wafer is subject to a lower sensitivity with respect to a dependence on the amount of dopant in the substrate wafer (in other words, a lower dependence on the substrate resistance).The latter effect enables a flexible use of the layer deposition arrangement in the epi-reactor for different epi-processing procedures, since faster settings or conversions of the epi-reactor for substrate wafers with different dopant quantities can be realized. Comparison to known designs of the layer deposition arrangement (with conventional hole susceptor). For example, in advantageous variants of the semiconductor wafer, the substrate resistance of the substrate wafer of the semiconductor wafer can be in a range from 0.005 to 0.008 Ohmcm and the RRV of the semiconductor wafer can correspond to a percentage value in the range from 40% to 50% of a reference RRV which, with the same substrate resistance and the same design of the substrate wafer, is formed as a reference substrate wafer of a reference semiconductor wafer, the at least one epitaxial layer of which is deposited on the reference substrate wafer using a (conventional) hole susceptor unit, ie in particular without a sealing ring unit and / or without a correspondingly geometrically designed substrate wafer receiving surface within the hole susceptor unit, with the same epi deposition mode settings.Alternatively, the substrate resistance of the substrate wafer of the semiconductor wafer can be in a range greater than 0.008 to 0.012 Ohmcm and the RRV of the semiconductor wafer can correspond to a percentage value in the range of 40% to 65% of a reference RRV which, with the same substrate resistance and the same substrate wafer design, is formed as a reference substrate wafer of a reference semiconductor wafer, the at least one epitaxial layer of which is deposited on the reference substrate wafer using a (conventional) hole susceptor unit, ie in particular without a sealing ring unit and / or without a correspondingly geometrically designed substrate wafer receiving surface within the hole susceptor unit, with the same epi deposition mode settings.Alternatively, the substrate resistance of the substrate wafer of the semiconductor wafer can be in a range greater than 0.012 to 0.016 Ohmcm and the RRV of the semiconductor wafer can correspond to a percentage value in the range of 60% to 85% of a reference RRV which, with the same substrate resistance and the same design of the substrate wafer, is formed as a reference substrate wafer of a reference semiconductor wafer, the at least one epitaxial layer of which is deposited on the substrate wafer using a (conventional) hole susceptor unit, ie in particular without a sealing ring unit and / or without a correspondingly geometrically designed substrate wafer receiving surface within the hole susceptor unit, with the same epi deposition mode settings.In particular, the described RRV values ​​can be achieved in an epi deposition mode of an epi process that is carried out at a temperature in the range of 1080°C to 1125°C, preferably in the range of 1100°C to 1120°C. In particular, the substrate wafer is boron-doped. Short description of the figure Figure 1 shows a schematic section of a three-dimensional view of a layer deposition arrangement 1 with a hole susceptor unit 1.1, preheat ring 1.2, gap unit 1.3 and sealing ring unit 1.4 (flushing unit not shown). Preferred embodiment A preferred embodiment of the layer deposition arrangement 1 according to the invention is described below. Furthermore, a preferred embodiment of the semiconductor wafer according to the invention (comprising a boron-doped silicon substrate wafer and a deposited epitaxial monocrystalline silicon layer) is described, which is produced by means of this layer deposition arrangement 1 according to the method according to the invention. Figure 1 shows a schematic section of a three-dimensional view of the layer deposition arrangement 1 with a hole susceptor unit 1.1 and a preheat ring 1.2. Here, the preheat ring 1.2 is arranged at a distance from a circumferential edge 1.11 of the hole susceptor unit 1.1 in relation to a radial direction of the hole susceptor unit 1.1 via a gap ring unit 1.3 in the form of an air gap ring 1.3, which is essentially annular around the hole susceptor unit 1.1, and the preheat ring surrounds the hole susceptor unit 1.1 along the circumferential direction of the hole susceptor unit 1.1. The air gap ring 1.3 has a gap width of 1.9 mm when viewed in the radial direction of the hole susceptor unit 1.1, wherein the gap width remains essentially constant along the circumferential direction. This design ensures reliable rotation (with a predeterminable rotational speed, e.g.in the range of 25 rpm to 60 rpm, here essentially at a height of 50 rpm) of the hole susceptor unit 1.1 relative to the preheat ring 1.2 around the height center axis and thereby a uniform deposition of the epitaxial layer on the substrate wafer deposited on the hole susceptor unit 1.1 (specifically on a first wafer side of the substrate wafer) during an epi deposition mode. The sealing ring unit 1.4 of the layer deposition arrangement 1, as shown in Figure 1, is designed to provide a physical barrier unit on the air gap ring 1.3 between a hole susceptor unit top side 1.12 and the hole susceptor unit bottom side 1.13. In the present exemplary embodiment, the sealing ring unit 1.4 is essentially annular disk-shaped, is made of SiC, and is arranged directly on the hole susceptor unit underside 1.13. The annular disk-shaped design of the sealing ring unit has a substantially Z-shaped form in the radial section in Figure 1, with the sealing ring unit 1.4 being fastened to the hole susceptor unit via several detachable clamp connections on the hole susceptor unit underside 1.13, extending along the circumferential direction 1.11 (not shown in detail). Furthermore, the sealing ring unit 1.4 is attached to the layer deposition arrangement 1 such that it partially overlaps the hole susceptor unit 1.1 and the preheat ring 1.2, viewed in a radial direction of the hole susceptor unit 1.1, and completely projects beyond the air gap ring in the radial direction. In the present exemplary embodiment, a clearance 1.5 remains between the underside of the preheat ring 1.2 and the facing side of the sealing ring leg 1.41, wherein the size of the clearance 1.5 is subject to the proviso that the clearance 1.5 should be as large as necessary to ensure a safe, reliable operation of the epi separation mode, but should be as small as possible to continue to ensure the necessary physical barrier. In the present case, the clearance 1.5 in the vertical direction is 1.0 mm. For this purpose, the sealing ring unit in the present embodiment also has a corresponding length along the radial direction, in the present case of 20 mm (so that an unwanted flow path between the hole susceptor unit top side 1.12 and the hole susceptor unit bottom side 1.13 is extended or made more difficult). It is understood that in other embodiments, other dimensions, geometric designs and locations (e.g. on the preheat ring top side) for the sealing ring unit as well as a clearance 1.5 of a different size can be selected, as long as the sealing ring unit 1.4 ensures the function of a physical barrier unit between the hole susceptor unit top side 1.12 and the hole susceptor unit bottom side 1.13 (in other words, to substantially prevent the exchange of deposition process gases and boron dopants via the gap unit 1.3). The layer deposition assembly 1 comprises a recess in the form of a substrate wafer receiving unit 1.15 for receiving the deposited substrate wafer, which in turn comprises a substrate wafer receiving surface 1.14 and also an inner bottom surface 1.16 (which is provided with perforated units as in conventional perforated susceptors). Specifically, a second wafer side of the deposited substrate wafer faces the substrate wafer receiving surface 1.14. The substrate wafer receiving surface 1.14 is essentially designed in the manner of an inner surface of a truncated cone or essentially funnel-shaped, wherein the substrate wafer receiving surface 1.14, starting from an (imaginary) ledge reference point L-BP on an (imaginary) reference circle BK on the substrate wafer receiving surface 1.14, has an inclination relative to a radial direction of the hole susceptor unit and a horizontal plane of the hole susceptor unit in the form of a ledge angle QL. The ledge angle QL in the present exemplary embodiment has an angular size of 0.2° and, viewed along the circumferential direction of the hole susceptor unit 1.1, is essentially constant with a maximum scatter of 0.25% along the circumferential direction. This geometric design of the substrate wafer receiving surface 1.14 ensures a largely joint-free, i.e. "tight" support for the substrate wafer and thus represents a physical barrier between the support surface for the semiconductor wafer on the hole susceptor unit 1.1 and the hole susceptor unit top side 1.12, which further reduces the “autodoping” effect, in particular avoids it. The position of the reference circle BK defines the starting range of the inclination (ledge angle QL) of the substrate wafer receiving surface 1.14 within the substrate wafer receiving unit 1.15. In the present embodiment, the reference circle coincides with the inner peripheral edge of the phase of the substrate wafer receiving unit 1.15. It is understood that in other advantageous variants, the reference circle BK can be spaced from this inner peripheral edge in the direction of the vertical center axis, i.e., have a smaller reference radius. The radial direction can be understood as any direction starting from the height center axis of the essentially symmetrical hole susceptor unit 1.1 and perpendicular to the height center axis in the direction of the air gap ring 1.3 and along a hole susceptor unit radius. Furthermore, the substrate wafer support surface has a flatness-shape tolerance of 0.010 mm. This geometric design of the substrate wafer support surface 1.14 also ensures a largely seamless, i.e., "tight" support for the substrate wafer, thus creating a physical barrier between the support surface for the semiconductor wafer on the hole susceptor unit 1.1 and the hole susceptor unit top surface 1.12, which further reduces, and in particular essentially eliminates, the "autodoping" effect. To achieve a reduction of the "autodoping" effect, it is further provided that the substrate wafer receiving surface 1.14 itself does not comprise any perforation units. However, within the inner bottom surface 1.16 of the substrate wafer receiving unit 1.15 of the hole susceptor unit 1.1, perforation units are distributed, as is also provided for the generic hole susceptor unit (which is not mentioned here). will be discussed in more detail; in Figure 1, a small number of hole units are indicated as an example in the center of the hole susceptor). To further advantageously reduce or substantially avoid the "autodoping" phenomenon in the epitaxial layer to be deposited during the epi deposition mode, the present exemplary embodiment further provides for a purge unit 1.6 provided with a purge gas in the form of hydrogen on the side of the layer deposition arrangement 1 facing the hole susceptor unit underside 1.13, the purge gas purge being reducible to 3 slm thanks to the provision of the sealing ring unit 1.4 on the layer deposition arrangement hole susceptor unit and thanks to the design and additional function of the support surface (barrier unit) under the hole susceptor unit 1.1. In particular, the interaction of all these structural (arrangement of the sealing ring unit 1.4; geometric design of the substrate wafer receiving surface 1.14; geometric design of the gap unit 1.3) and process-related precautions (reduced rinsing by rinsing unit 1.6 of the hole susceptor unit underside 1.13) on the layer deposition arrangement 1 achieves particularly advantageous reductions with regard to the "autodoping" effect up to the complete avoidance of the "autodoping" effect on the semiconductor wafer to be produced. The deposition of the epitaxial layer on the first wafer side of the boron-doped substrate wafer during the epi-deposition mode takes place in a temperature range of 1100°C to 1120°C. After the complete deposition of the epitaxial layer on the first wafer side of the boron-doped substrate wafer during the epi-deposition mode and after the complete completion of the epi-deposition mode, the produced semiconductor wafer is removed from the epi-reactor. The semiconductor wafer produced by means of layer deposition arrangement 1, whose boron-localized substrate wafer has a substrate resistance of 0.005 Ohmcm (determined by means of sheet resistance measurement in accordance with SEMI Standards MF673 “TEST METHODS FOR MEASURING RESISTIVITY OF SEMICONDUCTOR WAFERS OR SHEET RESISTANCE OF SEMICONDUCTOR FILMS WITH A NONCONTACT EDDY-CURRENT GAUGE”), has an RRV of the epitaxial layer of essentially 2.10%. This RRV value was determined using the determination method according to SEMI Standards M62-0317 (Specification for Silicon Epitaxial Wafers), 2017) (RRV [%] = (R ma x - Rmin) / (Rmax + Rmin)) taking into account nine determined R values ​​resulting from nine measuring points on the epitaxial layer determined (wherein the nine measuring points were arranged on a cross-shaped measuring grid on the epitaxial layer, wherein the measuring grid leads through the semiconductor wafer notch; the four measuring points assigned to the edge region of the semiconductor wafer are arranged taking into account an edge exclusion, wherein the measuring point in the vicinity of the notch is selected taking into account an edge exclusion of 10 mm (i.e. arranged on the measuring grid 10 mm from the edge in a radial direction) and the remaining three measuring points, which are in the edge region of the semiconductor wafer, are selected taking into account an edge exclusion of 5 mm (i.e. arranged on the measuring grid 5 mm from the edge in a radial direction). The RRV of the epitaxial layer of the semiconductor wafer of 2.10% basically corresponds to the RRV value that the semiconductor wafer would achieve after epitaxial deposition if an LTO layer were provided as a dopant diffusion barrier layer on the second layer side of the substrate wafer during conventional production on a conventional hole susceptor unit, but now with the advantage that after the epi deposition mode, no LTO layer at all needs to be removed manually and / or chemically (e.g. with HF component) and thus the surface properties on the second side of the substrate wafer are advantageously improved compared to the prior art with LTO layer in that the second side of the doped substrate wafer has comparatively fewer defects.Specifically, in the present exemplary embodiment, the second wafer side of the substrate wafer has 6 defects which are arranged on a defect ring which is, at least in sections, substantially annular and extends within a substantially annular region on the second wafer side, wherein the region has a radial width of 3 mm and its outer circumference substantially coincides with the semiconductor wafer edge. These 6 defects (in their advantageously small number) on the semiconductor wafer are defects which were detected as light point defects using an inspection device by means of scattered light measurement (defects resulting from residues of a removed LTO layer (state of the art) would in principle also be detected as light point defects in this semiconductor wafer area and moreover in high numbers (together with the other defects as light point defects in total over 200); due to the lack of LTO layer residues in the semiconductor wafer according to the invention, the 6 light point defects detected represent exclusively defects resulting from scratches or friction points on the substrate wafer receiving surface or similar scenarios and this in this comparatively small number of defects). In relation to semiconductor wafers which are manufactured using conventional hole susceptor units (i.e. in particular without a sealing ring and / or without a correspondingly geometrically designed substrate wafer receiving surface within the hole susceptor unit), the semiconductor wafer further has the advantage that its RRV value (2.10%) is significantly lower than the RRV value of those semiconductor wafers which were manufactured using these conventional hole susceptor units with the same substrate resistance (0.005 Ohmcm) and which were (likewise) manufactured using a substrate wafer without a dopant diffusion barrier layer. In the present exemplary embodiment, the RRV of the semiconductor wafer corresponds to approximately 40% of a reference RRV which, with the same substrate resistance and identically designed substrate wafer, is formed from a reference semiconductor wafer whose epitaxial layer was formed using a (conventional) hole susceptor without a sealing ring unit 1.4 and without providing a correspondingly geometrically designed substrate wafer receiving surface 1.14 on a substrate wafer equivalent to the substrate wafer.

Claims

Patent claims 1. Layer deposition arrangement (1) for an epi-reactor for producing a semiconductor wafer with at least one epitaxial layer, wherein ■ the layer deposition arrangement (1) comprises a hole susceptor unit (1.1) and a preheat ring (1.2), wherein the hole susceptor unit (1.1) has a hole susceptor unit top side (1.12) and a hole susceptor unit bottom side (1.13), wherein, at least during an epi-deposition mode, ■ the preheating ring (1.2) surrounds the hole susceptor unit (1.1) at a distance at least in sections via a gap unit (1.3), in particular in the form of an air gap ring, wherein the hole susceptor unit (1.1) is designed to rotate at a predeterminable rotational speed about a height axis of the hole susceptor unit (1.1) opposite the preheating ring (1.2), and ■ the layer separation arrangement (1) further comprises at least one sealing ring unit (1.4) which is arranged on the layer separation arrangement (1) and is designed to provide a physical barrier unit between the hole susceptor unit top side (1.12) and the hole susceptor unit bottom side (1.13) on the gap unit (1.3).

2. Layer deposition arrangement according to claim 1, wherein ■ the sealing ring unit (1.3) is essentially annular disc-shaped, and / or ■ the sealing ring unit (1.4) is arranged at a location on the side of the layer separation arrangement (1) facing the hole susceptor unit bottom side (1.13), in particular directly on the hole susceptor unit bottom side (1.13), or at a location on the side of the layer separation arrangement (1) facing the hole susceptor unit top side (1.12), in particular on an upper side of the preheat ring (1.2), and / or ■ the sealing ring unit (1.4) is arranged on the layer deposition arrangement (1) in such a way that it at least partially overlaps the hole susceptor unit (1.1) and the preheat ring (1.2), viewed in a radial direction of the hole susceptor unit (1.1), and substantially completely projects beyond the gap unit (1.4), in particular in the form of an air gap ring, viewed in the radial direction.

3. Layer deposition arrangement according to claim 1 or 2, wherein ■ the sealing ring unit (1.4) is essentially annular and, viewed along its radial direction, has a sealing ring width in a range from 5 mm to 50 mm, preferably in a range from 15 mm to 25 mm, and the gap unit (1.3) in the form of an air gap ring, viewed in the radial direction of the hole susceptor unit (1.1), has a gap width in the range from 1.2 mm to 2.6 mm, preferably in the range from 1.5 mm to 2.2 mm, more preferably essentially 1.9 mm, wherein in particular the gap width is essentially constant along the circumferential direction.

4. Layer deposition arrangement according to one of the preceding claims, wherein ■ the sealing ring unit (1.4) is arranged detachably fastened to the layer deposition arrangement (1), in particular to the hole susceptor unit (1.1) or to the preheat ring (1.2), and the sealing ring unit (1.4) is made in particular from material which comprises SiC or graphite or quartz, or ■ the sealing ring unit (1.4) is essentially designed as a monolithic unit with the hole susceptor unit (1.1) or the preheat ring (1.2).

5. Layer deposition arrangement according to one of the preceding claims, wherein the hole susceptor unit (1.1) comprises on the hole susceptor unit top side (1.12) a recess in the form of a substrate wafer receiving unit (1.15) which comprises a substrate wafer receiving surface (1.14), wherein ■ the substrate wafer receiving surface (1.14) is designed essentially in the manner of an inner surface of a truncated cone, wherein, starting from a ledge reference point on a reference circle on the substrate wafer receiving surface (1.14), it has an inclination with respect to a radial direction of the hole susceptor unit (1.1) and a horizontal plane of the hole susceptor unit (1.1) in the form of a ledge angle, wherein the ledge angle has an angular size in the range from 0.0° to 2.0°, preferably in the range from 0.1° to 1.0°, more preferably in the range from 0.2° to 0.5°, and viewed along a circumferential direction of the hole susceptor unit (1.1) is essentially constant with a maximum scatter of 1%, preferably a maximum of 0.5%, more preferably a maximum of 0.25%, along the circumferential direction, and / or the substrate wafer receiving surface (1.1) has a flatness-shape tolerance in a range of 0.002 mm to 0.012 mm, preferably 0.005 mm to 0.008 mm.

6. Layer deposition arrangement according to one of the preceding claims, wherein a purge unit with a purge gas, in particular with hydrogen, is provided on the side of the layer deposition arrangement (1) facing the hole susceptor unit underside (1.13), wherein a purge gas purge, in particular hydrogen purge, under the hole susceptor unit (1.1) can be reduced to 3 slm.

7. A method for producing a semiconductor wafer, comprising depositing at least one epitaxial layer on a doped substrate wafer, which has no dopant diffusion barrier layer, in particular no LTO layer, in an epi-reactor for producing the semiconductor wafer, the method comprising the following steps: ■ Positioning a second wafer side of the doped substrate wafer on a hole susceptor unit (1.1), in particular on a substrate wafer receiving surface (1.14), of a layer deposition arrangement (1) according to one of claims 1 to 6, ■ Starting an epi-deposition mode of the layer deposition arrangement (1), ■ Depositing at least one epitaxial layer on a first wafer side of the doped substrate wafer during the epi deposition mode.

8. The method according to claim 7, wherein ■ at least during the epi-deposition mode, a rotation of the hole susceptor unit (1.1) about a height center axis of the hole susceptor unit (1.1) relative to the preheat ring (1.2) takes place at a predeterminable rotation speed, and ■ during the epi-deposition mode, a purge unit with a purge gas, in particular in the form of hydrogen, is provided on the side of the layer deposition arrangement (1) facing a hole susceptor unit underside (1.13), wherein the purge by means of the purge gas, in particular in the form of a hydrogen purge, under the hole susceptor unit (1.1) is controlled in a predeterminable manner and is variable via the epi-deposition mode.

9. The method according to claim 7 or 8, wherein after completion of the deposition of at least one epitaxial layer and after termination of the epi-deposition mode, the semiconductor wafer undergoes a final cleaning step which comprises chemical cleaning of the semiconductor wafer.

10. A semiconductor wafer comprising a substrate wafer and at least one epitaxial layer, wherein ■ the substrate wafer is doped with at least one dopant, ■ the at least one epitaxial layer is arranged on a first side of the substrate wafer, ■ the semiconductor wafer o has a radial resistance variation (RRV) in a range from 1.30% to 2.20%, and o has at least 1 defect and fewer than 200 defects on a second wafer side of the substrate wafer, which defects can be detected as light point defects using an inspection device by means of scattered light measurement, and which are arranged on a defect ring which is, at least in sections, essentially annular and which extends within an essentially annular region on the second wafer side, the region having a radial width of 3 mm and its outer circumference essentially coinciding with the semiconductor wafer edge.

11. Semiconductor wafer according to claim 10, wherein no layer in the form of a dopant diffusion barrier layer, in particular in the form of a Low Thermal Oxide (LTO) layer, in particular at no time during the production of the semiconductor wafer, is arranged on the second wafer side of the substrate wafer.

12. Semiconductor wafer according to claim 10 or 11, wherein no residues in the form of defects of a Low Thermal Oxide (LTO) layer are arranged on the second wafer side of the substrate wafer.

13. Semiconductor wafer according to one of claims 10 to 12, wherein the doped substrate wafer with dopant boron forms a substrate resistance of the substrate wafer between 0.005 and 0.020 Ohmcm, and / or the Semiconductor wafer has an RRV in a range of 1.40% to 2.10%, preferably 1.45% to 2.00%.

14. Semiconductor wafer according to one of claims 10 to 13, wherein ■ the semiconductor wafer is designed such that it forms an RRV of the semiconductor wafer in a range of 1.40% to 2.10%, preferably in a range of 1.45% to 2.00%, for a doped substrate wafer of the semiconductor wafer with a substrate resistance in a range of 0.005 to 0.008 Ohmcm, or ■ the semiconductor wafer is designed such that it forms an RRV of the semiconductor wafer in a range of 1.40% to 1.80%, preferably in a range of 1.45% to 1.60%, more preferably substantially of 1.50%, for a doped substrate wafer of the semiconductor wafer with a substrate resistance in a range greater than 0.008 to 0.016 Ohmcm.

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