Display substrate, display panel, and display apparatus

Abstract

The present application provides a display substrate, a display panel, and a display apparatus. None of the orthographic projections, on a base substrate, of pixel openings of first-color sub-pixels, second-color sub-pixels and third-color sub-pixels of the display substate overlaps with the orthographic projections, on the base substrate, of channels of drive transistors of the sub-pixels. Or, the orthographic projection, on the base substrate, of the pixel opening of at least one sub-pixel overlaps with the orthographic projection, on the base substrate, of the channel of the drive transistor of the sub-pixel; the orthographic projections, in a first direction, of the pixel opening of at least one second-color sub-pixel and the pixel openings of the first-color sub-pixels and the third-color sub-pixels overlap; none of the orthographic projections, in a second direction, of the pixel openings of the second-color sub-pixels, the first-color sub-pixels and the third-color sub-pixels overlaps; and the first direction intersects the second direction.

Description

TECHNICAL FIELDThe present application relates to the field of display technology, and in particular, to a display substrate, a display panel and a display device. BACKGROUNDOrganic light emitting diodes have advantages of self-luminescence,high efficiency, bright colors, light weight, power saving, and wideoperating temperature range, etc., and have been gradually applied in fields of large-area display, lighting, and vehicle-mounted display. SUMMARYAccording to a first aspect of examples of the present disclosure, thereis provided a display substrate, including a base substrate and a plurality of sub-pixels disposed on the base substrate; the plurality of sub-pixels includes a plurality of first color sub-pixels,a plurality of second color sub-pixels and a plurality of third color sub-pixels,human eyes are more sensitive to the first color than to the third color, andhuman eyes are more sensitive to the third color than to the second color; the sub-pixel includes an organic light emitting element and a pixel circuitfor driving the organic light emitting element; the organic light emitting element includes a first electrode, a second electrode, and an organic lightemitting material disposed between the first electrode and the secondelectrode; the first electrode of the sub-pixel is electrically connected to the pixel circuit; the pixel circuit includes a driving transistor; the display substrate further includes an active semiconductor layer anda pixel defining layer, the active semiconductor layer includes channels andsource and drain regions of the driving transistors of the sub-pixels; the pixeldefining layer is provided with pixel openings corresponding to the sub- pixels one to one; an orthographic projection of the pixel opening of the first color sub-pixel on the base substrate has no overlap with an orthographic projectionof the channel of the driving transistor of the first color sub-pixel on the base substrate, an orthographic projection of the pixel opening of the secondcolor sub-pixel on the base substrate has no overlap with an orthographicprojection of the channel of the driving transistor of the second color sub- pixel on the base substrate, an orthographic projection of the pixel openingof the third color sub-pixel on the base substrate has no overlap with anorthographic projection of the channel of the driving transistor of the third color sub-pixel on the base substrate; or,an orthographic projection of the pixel opening of at least one sub-pixel on the base substrate has overlap with an orthographic projection of the channel of the driving transistor thereof on the base substrate, anorthographic projection of the pixel opening of at least one of the second color sub-pixels in a first direction has overlap with an orthographicprojection of the pixel opening of the first color sub-pixel in the first direction and an orthographic projection of the pixel opening of the thirdcolor sub-pixel in the first direction, and the orthographic projection of thepixel opening of the second color sub-pixel in a second direction has no overlap with either an orthographic projection of the pixel opening of the first color sub-pixel in the second direction or an orthographic projection of the pixel opening of the third color sub-pixel in the second direction, wherethe first direction intersects with the second direction. In an example, the orthographic projection of the pixel opening of thefirst color sub-pixel on the base substrate has overlap with the orthographicprojection of the channel of the driving transistor of the first color sub-pixel on the base substrate, the orthographic projection of the pixel opening of the second color sub-pixel on the base substrate has overlap with theorthographic projection of the channel of the driving transistor of the second color sub-pixel on the base substrate, and the orthographic projection of the pixel opening of the third color sub-pixel on the base substrate has overlap with the orthographic projection of the channel of the driving transistor ofthe third color sub-pixel on the base substrate.In an example, the plurality of sub-pixels are divided into a plurality ofpixel groups, and each of the pixel groups includes a first color sub-pixel, asecond color sub-pixel and a third color sub-pixel; at least one of the pixelgroups includes two rows of sub-pixels arranged along the first direction,wherein one row of sub-pixels arranged along the first direction includes first color sub-pixels and third color sub-pixels which are alternatelyarranged, and the other row of sub-pixels arranged along the first directionincludes second color sub-pixels.In an example, in at least one of the pixel groups, the orthographic projection of the pixel opening corresponding to each of the sub-pixels on the base substrate has no overlap with an orthographic projection of the gateelectrode of the driving transistor of any one of the sub-pixels on the base substrate, orthe orthographic projection of the pixel opening corresponding to each of the sub-pixels on the base substrate has an overlapping region with theorthographic projection of the gate electrode of the driving transistor of anyone of the sub-pixels on the base substrate, and a ratio of an area of theoverlapping region to an area of the gate electrode is not more than 10%.In an example, the display substrate is further provided with a pluralityof scan signal lines extending along the first direc20 tion, the scan signal linesbeing configured to provide scan signals for the pixel groups; in at least one pixel group, in the second direction, a distance from the channel of the driving transistor of the second color sub-pixel to the scansignal line is different from a distance from the channel of the drivingtransistor of the first color sub-pixel to the scan signal line. In an example, in at least one pixel group, in the second direction, the distance from the channel of the driving transistor of the second color sub-pixel to the scan signal line is longer than the distance from the channel ofthe driving transistor of the first color sub-pixel to the scan signal line.In an example, the display substrate is further provided with scan signal lines extending along the first direction, the scan signal lines beingconfigured to provide scan signals for the pixel groups;in at least one pixel group, an orthographic projection of the scan signal line in the second direction has overlap with an orthographic projection ofthe gate electrode of the driving transistor of the sub-pixel in the seconddirection, where the second direction is perpendicular to the first direction.In an example, the display substrate is further provided with scan signal lines extending along the first direction, the scan signal lines beingconfigured to provide scan signals for the pixel groups; the scan signal line includes a main body portion of the scan signal line and a protruding portionprotruding from one side of the main body portion of the scan signal line;the main body portion of the scan signal line includes a first scan sub-line, a second scan sub-line and a connection part, the first scan sub-line isconnected to the second scan sub-line through the connection part, the firstscan sub-line is connected to the pixel circuit of the first color sub-pixel, the second scan sub-line is connected to the pixel circuit of the second colorsub-pixel, and extension direction of part of the connection part intersects with the extension direction of the first scan sub-line;the pixel circuit includes a compensation transistor, and thecompensation transistor includes a first gate electrode and a second gateelectrode; in the compensation transistor, the first gate electrode is a part ofthe connection part that overlaps with an orthographic projection of the active semiconductor layer on the base substrate, and the second gateelectrode is a part of the protruding portion that overlaps the orthographicprojection of the active semiconductor layer on the base substrate. In an example, the connection part includes a first connection sub-part,a second connection sub-part and a third connection sub-part which are connected in sequence, extension direction of the first connection sub-part and the third connection sub-part intersect with extension direction of thefirst scan sub-line, and extension direction of the second connection sub-part is the same as the extension direction of the first scan sub-line;the first gate electrode is a part of the second connection sub-part that overlaps with the orthographic projection of the active semiconductor layeron the base substrate.In an example, the active semiconductor layer includes a first section,a second section, a third section and a fourth section which are connected insequence; the second section, the fourth section and the main body portionof the scan signal line extend along the first direction, the first section andthe third section extend in the second direction, where the second direction intersects with the first direction; the display substrate further includes a reset control signal line extending along the first direction and disposed in the same layer as the scan signal line; the pixel circuit includes a resettransistor, and the reset transistor includes a gate electrode;the second gate electrode is a part of the protruding portion that overlaps with an orthographic projection of the fourth section on the base substrate, the gate electrode of the reset transistor includes a part of the resetcontrol signal line that overlaps an orthographic projection of the firstsection on the base substrate.In an example, the pixel circuit further includes a threshold compensation transistor, the threshold compensation transistor includes agate electrode; the display substrate further includes a connection structure,one end of the connection structure is connected to the gate electrode of the driving transistor, and the other end of the connection structure is connectedto source and drain regions of the threshold compensation transistor; the connection structure includes a first portion and a second portionconnected to the first portion, an orthographic projection of the first portionon the base substrate and an orthographic projection of the protruding part on the base substrate are disposed at are located on the same side of an orthographic projection of the main body portion of the scan signal line on the base substrate; a length of the first portion in the second direction islarger than a length of the protruding portion in the second direction.In an example, a size of the connection structure in the second direction ranges from 35 μm to 70 μm.In an example, the display substrate is further provided with a plurality of scan signal lines and reset control signal lines extending along the firstdirection, the scan signal lines being configured to provide scan signals forthe pixel groups, the reset control signal lines being configured to providereset control signals for the pixel groups; an orthographic projection of the first electrode of at least one of thesecond color sub-pixels on the base substrate has overlap with an orthographic projection of the reset control signal line on the base substrateand an orthographic projection of the scan signal line on the base substrate.In an example, any one of the orthographic projection of the pixelopening of the first color sub-pixel on the base substrate, the orthographicprojection of the pixel opening of the second color sub-pixel on the base substrate or the orthographic projection of the pixel opening of the third color sub-pixel on the base substrate has no overlap with any one of the orthographic projection of the channel of the driving transistor of the first color sub-pixel on the base substrate, the orthographic projection of the channel of the driving transistor of the second color sub-pixel on the base substrate, or the orthographic projection of the channel of the driving transistor of the third color sub-pixel on the base substrate. In an example, the display substrate is further provided with scan signallines, the scan signal lines being configured to provide scan signals for the pixel groups; a distance between the channel of the driving transistor of thesub-pixel and the scan signal line in the second direction ranges from 1 μmto 50 μm.. In an example, the pixel circuit further includes a capacitor, and the capacitor includes a first polar plate and a second polar plate disposed on a side of the first polar plate away from the base substrate; an area of thesecond polar plate of the second color sub-pixel is larger than an area of the second polar plate of the first color sub-pixel, and the area of the secondpolar plate of the second color sub-pixel is larger than an area of the secondpolar plate of the third color sub-pixel. In an example, the display substrate further includes a first powersupply line and a second power supply line disposed on a side of the first power supply line away from the base substrate; the first power supply lineand the second power supply line are configured to provide a power supplysignal for the pixel circuit; the first power supply line is electrically connected to the second power supply line;the second power supply line includes a first power supply sub-lineextending along the first direction and a second power supply sub-line extending along the second direction, the first power supply sub-lineintersects with the second power supply sub-line.In an example, the pixel circuit further includes an emission controltransistor and an electrode connection structure, and the electrode connection structure electrically connects the first electrode of the sub-pixelto source and drain regions of the emission control transistor; areas of the electrode connection structures of at least two of the sub-pixels are different.In an example, the electrode connection structure at least includes afirst electrode connection sub-structure and a second electrode connection sub-structure on a side of the first electrode connection sub-structure away from the base substrate; areas of the first electrode connection sub-structureand / or the second electrode connection sub-structure of at least two of thesub-pixels are different.In an example, the display substrate further includes a shielding line and a reset power supply signal line, the reset power supply signal line being configured to provide a reset power signal for the sub-pixels; the shieldingline is electrically connected to the reset power signal line.In an example, a size of the first color sub-pixel in the first directionranges from 35 μm to 110 μm, and a size of the first color sub-pixel in thesecond direction ranges from 20 μm to 60 μm; a size of the second color sub-pixel in the first direction ranges from 35 μm to 120 μm, and a size ofthe second color sub-pixel in the second direction ranges from 20 μm to 80 μm; a size of the third color sub-pixel in the first direction ranges from 35μm to 70 μm, and a size of the third color sub-pixel in the second directionranges from 20 μm to 60 μmAccording to a second aspect of examples of the present disclosure,there is provided a display panel, including the display substrate describedabove.According to a third aspect of examples of the present disclosure, there is provided a display device, including the display panel described above.BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic circuit diagram of a pixel circuit provided by anexample of the present application; FIGS. 2 to 7 are partial schematic views of each layer of a displaysubstrate provided by an example of the present application; FIG. 2A is apartial enlarged view of FIG. 2; FIG. 7A is a schematic diagram of part of film layers of a plurality ofpixel groups of a display substrate provided by an example of the present application; FIG. 8 is a partial cross-sectional view at a position of a displaysubstrate provided by an example of the present application; FIG. 9 is a partial cross-sectional view of another position of the displaysubstrate provided by an example of the present application; FIG. 10 is a partial schematic diagram of a plurality of film layers of a display substrate provided by another example of the present application; FIG. 10A is a partial enlarged view of a scan signal line in FIG. 10; FIG. 11 is a partial schematic diagram of a part of a film layer of adisplay substrate provided by an example of the present application;FIGS. 12 to 16 are partial schematic views of layers of a display substrate provided by still another example of the present application.DETAILED DESCRIPTION OF THE EMBODIMENTSExamples will be described in detail herein, with the illustrationsthereof represented in the drawings. When the following descriptionsinvolve the drawings, like numerals in different drawings refer to like orsimilar elements unless otherwise indicated. The embodiments described in the following examples do not represent all embodiments consistent with the present disclosure. Rather, they are merely examples of apparatuses andmethods consistent with some aspects of the present disclosure as detailed in the appended claims.The terms used in the present disclosure are for the purpose ofdescribing particular examples only, and are not intended to limit the presentdisclosure. Terms determined by "a", "the" and "said" in their singular forms in the present disclosure and the appended claims are also intended to include plurality, unless clearly indicated otherwise in the context. It should also be understood that the term "and / or" as used herein is and includes anyand all possible combinations of one or more of the associated listed items.It is to be understood that, although terms "first," "second," "third," and the like can be used in the present disclosure to describe variousinformation, such information should not be limited to these terms. Theseterms are only used to distinguish one category of information from another. For example, without departing from the scope of the present disclosure,first information can be referred as second information; and similarly, second information can also be referred as first information. Depending onthe context, the word "if" as used herein can be interpreted as "when" or "upon" or "in response to determining". Embodiments of the present application provide a display substrate, a display panel, and a display device. The display substrate, the display panel and the display device in the embodiments of the present application will be described in detail below with reference to the accompanying drawings. Thefeatures of the embodiments described below can complement each other orbe combined with each other without conflict.Embodiments of the present application provide a display substrate, a display panel, and a display device. The display substrate, the display paneland the display device in the embodiments of the present application will be described in detail below with reference to the accompanying drawings. Thefeatures of the embodiments described below can complement each other orbe combined with each other without conflict.An embodiment of the present application provides a display substrate. The display substrate includes a base substrate and a plurality of sub-pixelsdisposed on the base substrate. The plurality of sub-pixels are arranged at intervals on the base substrate. The plurality of sub-pixels include a plurality of first color sub-pixels,a plurality of second color sub-pixels, and a plurality of third color sub-pixels, and human eyes are more sensitive to the first color than to the third color, and more sensitive to the third color than to the second color. Thecolor of the sub-pixel refers to a color of light emitted by the sub-pixel. Insome embodiments, the first color is green, the second color is blue, and thethird color is red.The sub-pixel includes an organic light emitting element and a pixel circuit for driving the organic light emitting element. The organic light emitting element includes a first electrode, a second electrode, and anorganic light emitting material disposed between the first electrode and thesecond electrode. The first electrode of the sub-pixel is electrically connected to the pixel circuit. In some embodiments, the first electrode can be an anode and the second electrode can be a cathode.In one embodiment, the display substrate further includes a pixeldefining layer, and the pixel defining layer is provided with pixel openingscorresponding to the sub-pixels one to one. The pixel defining layer isdisposed between adjacent sub-pixels, and the pixel openings are used to define light emitting regions of the sub-pixels of the colors. An orthographicprojection of the pixel opening of the pixel defining layer on the base substrate is located within an orthographic projection of the first electrodeof the corresponding sub-pixel on the base substrate.In some embodiments, the organic light emitting material is disposed on a side of the first electrode away from the base substrate. The firstelectrode of the sub-pixel of a color is in contact with the organic lightemitting material at the pixel opening of the pixel defining layer, and the pixel opening of the pixel defining layer defines the shape of the lightemitting region of the sub-pixel. For example, the first electrode (e.g., the anode) of the organic light emitting element can be disposed under the pixeldefining layer, and the pixel opening of the pixel defining layer exposes apart of the first electrode. When the organic light emitting material is formedin the pixel opening in the pixel defining layer, the organic light emittingmaterial is in contact with the first electrode, so that this part of the firstelectrode can drive the organic light emitting material to emit light.In some embodiments, an orthographic projection of the pixel opening of the pixel defining layer on the base substrate is located within anorthographic projection of the corresponding organic light emitting materialon the base substrate. That is, the organic light emitting material covers thepixel opening of the pixel defining layer. For example, an area of the organiclight emitting material is larger than an area of the corresponding pixel opening. That is, the organic light emitting material includes at least a partof the solid structure covering the pixel defining layer in addition to a partinside the pixel opening. Generally, the solid structures of the pixel defininglayers at boundaries of the pixel openings are all covered with organic lightemitting materials. It should be noted that the above description of thepattern of the organic light emitting material is based on the patterned organic light emitting materials of the sub-pixels formed by, for example, aFMM process. Apart from FMM production process, in some cases, organic light emitting material forms an integral film layer in the entire display areaby an open mask process, having a continuous orthogra20 phic projection onthe base substrate, in which case, the organic light emitting material must have a part located in the pixel opening and a part on the solid structure of the pixel defining layer. In one embodiment, the plurality of sub-pixels are divided into aplurality of pixel groups, and the organic light emitting elements of the plurality of pixel groups are arranged on the base substrate along a firstdirection and a second direction, and the first direction and the seconddirection intersect with each other. The pixel groups include sub-pixels of afirst color, sub-pixels of a second color, and sub-pixels of a third color. Insome embodiments, the first direction and the second direction are perpendicular to each other. In some embodiments, the first direction is therow direction and the second direction is the column direction. In someembodiments, the pixel circuits of the sub-pixels in each of the pixel groupsare arranged at intervals in the first direction.In one embodiment, the area covered by the orthographic projection ofthe pixel circuit of the sub-pixel on the base substrate is approximatelylocated within a rectangular box. The orthographic projection of the pixel circuit on the base substrate mainly includes the orthographic projections ofthe structures of various transistors, capacitors and other elements on the base substrate. The display substrate further includes a plurality of signal lines, and the signal lines are used to drive the pixel circuits. It should be noted that some signal lines include a portion inside the rectangular box and a portion extending outside the rectangular box. The pixel circuit furtherincludes an electrode connection structure, and the electrode connectionstructure electrically connects the pixel circuit of the sub-pixel to the firstelectrode.In one embodiment, as shown in FIG. 1, the pixel circuit 221 includes a driver circuit 222. The driving circuit 222 includes a control terminal, afirst terminal and a second terminal, and is configured to provide to theorganic light emitting element 220 a driving current for driving the organiclight emitting element 220 to emit light.In one embodiment, as shown in FIG. 1, the pixel circuit 221 includes a first light emitting control circuit 223 and a second light emitting controlcircuit 224. For example, the first light emitting control circuit 223 isconnected to a first terminal of the driving circuit 222 and a first voltage terminal VDD, and is configured to turn on or off the connection betweenthe driving circuit 222 and the first voltage terminal VDD. The second light emitting control circuit 224 is connected to a second terminal f the drivingcircuit 222 and the first electrode of the organic light emitting element 220,and is configured to turn on or off the connection between the driving circuit222 and the organic light emitting element 220. In one embodiment, as shown in FIG. 1, the pixel circuit 221 further includes a data writing circuit 226, a storage circuit 227, a thresholdcompensation circuit 228 and a reset circuit 229. The data writing circuit226 is electrically connected to the first terminal of the driving circuit 222and is configured to write a data signal into the storage circuit 227 under thecontrol of a scan signal. The storage circuit 227 is electrically connected toa control terminal of the driving circuit 222 and the first voltage terminalVDD, and is configured to store a data signal. The threshold compensation circuit 228 is electrically connected to the control terminal and the secondterminal of the driving circuit 222 and is configured to perform thresholdcompensation on the driving circuit 222. The reset circuit 229 is electrically connected to the control terminal of the driving circuit 222 and the firstelectrode of the organic light emitting element 220, and is configured to reset the control terminal of the driving circuit 222 and the first electrode ofthe organic light emitting element 220 under the control of a reset controlsignal. In one embodiment, as shown in FIG. 1, the driving circuit 222 includesa driving transistor T1, the control terminal of the driving circuit 222includes a gate electrode of the driving transistor T1, the first terminal ofthe driving circuit 222 includes a first electrode of the driving transistor T1,and the second terminal of the driving circuit 222 includes the second electrode of the driving transistor T1.In one embodiment, as shown in FIG. 1, the data writing circuit 226 includes a data writing transistor T2. The storage circuit 227 includes acapacitor C. The threshold compensation circuit 228 includes a thresholdcompensation transistor T3. The first light emitting control circuit 223includes a first light emitting control transistor T4. The second light emittingcontrol circuit 224 includes a second light emitting control transistor T5. The reset circuit 229 includes a first reset transistor T6 and a second reset transistor T7. The reset control signal can include a first reset control sub-signal and a second reset control sub-signal. In one embodiment, as shown in FIG. 1, a first electrode of the datawriting transistor T2 is electrically connected to the first electrode of the driving transistor T1, and a second electrode of the data writing transistorT2 is configured to be electrically connected to a data line Vd to receive adata signal. A gate electrode of the data writing transistor T2 is configured to be electrically connected to a scan signal line Ga1 to receive a scan signal.A first electrode of the capacitor C is electrically connected to a first powersupply terminal VDD, and a second electrode of the capacitor C iselectrically connected to a gate electrode of the driving transistor T1. A first electrode of the threshold compensation transistor T3 is electrically connected to the second electrode of the driving transistor T1, a secondelectrode of the threshold compensation transistor T3 is electrically connected to the gate electrode of the driving transistor T1, and a gateelectrode of the threshold compensation transistor T3 is configured to be electrically connected to a scan signal line Ga2 to receive a compensationcontrol signal. A first electrode of the first reset transistor T6 is configuredto be electrically connected to a reset power supply terminal Vinit1 toreceive a first reset signal, a second electrode of the first reset transistor T6 is electrically connected to the gate electrode of the driving transistor T1, and a gate electrode of the first reset transistor T6 is configured to be electrically connected to a reset control signal line Rst1 to receive a firstreset control sub-signal. A first electrode of the second reset transistor T7 is configured to be electrically connected to a reset power supply terminalVinit2 to receive a second reset signal, a second electrode of the second reset transistor T7 is electrically connected to the first electrode of the organiclight emitting element 220, and a gate electrode of the second reset transistorT7 is configured to be electrically connected to a reset control signal line Rst2 to receive a second reset control sub-signal. A first electrode of the first light emitting control transistor T4 is electrically connected to the firstpower supply terminal VDD, and ae second electrode of the first lightemitting control transistor T4 is electrically connected to the first electrodeof the driving transistor T1. A gate electrode of the first light emittingcontrol transistor T4 is configured to be electrically connected to a lightemitting control signal line EM1 to receive a first light emitting control signal. A first electrode of the second light emitting control transistor T5 is electrically connected to the second electrode of the driving transistor T1, asecond electrode of the second light emitting control transistor T5 iselectrically connected to the second electrode of the organic light emitting element 220, and a gate electrode of the second light emitting controltransistor T5 is configured to be electrically connected to a light emitting control signal line EM2 to receive a second light emitting control signal. The first electrode of the organic light emitting element 220 is electrically connected to a second power supply terminal VSS.In one embodiment, one of the first power supply terminal VDD andthe second power supply terminal VSS is a high voltage terminal, and the other is a low voltage terminal. In the embodiment shown in FIG. 1, the first power supply terminal VDD is a voltage source to output a constant firstvoltage, and the first voltage is a positive voltage; and the second powersupply terminal VSS can be a voltage source to output a constant secondvoltage, and the second voltage is a negative voltage, and so on. In some examples, the second power supply terminal VSS can be grounded. In one embodiment, as shown in FIG. 1, the scan signal and the compensation control signal can be the same signal. That is, the gateelectrode of the data writing transistor T2 and the gate electrode of the threshold compensation transistor T3 can be electrically connected to the same signal line. For example, the scan signal line Ga1 is used to receive the same signal (e.g., a scan signal). In this case, the display substrate 1000can omit the scan signal line Ga2 to reduce the number of signal lines. Foranother example, the gate electrode of the data writing transistor T2 and the gate electrode of the threshold compensation transistor T3 can also be electrically connected to different signal lines respectively. That is, the gate electrode of the data writing transistor T2 is electrically connected to the scan signal line Ga1, and the gate electrode of the threshold compensationtransistor T3 is electrically connected to the scan signal line Ga2, and thescan signal line Ga1 and the scan signal line Ga2 transmit the same signal.It should be noted that the scan signal and the compensation control signal can also be different signals, so that the gate electrode of the datawriting transistor T2 and the threshold compensation transistor T3 can becontrolled separately and independently, increasing the flexibility ofcontrolling the pixel circuit.In one embodiment, as shown in FIG. 1, the first lighting control signaland the second lighting control signal can be the same signal. That is, thegate electrode of the first lighting control transistor T4 and the gate electrode of the second lighting control transistor T5 can be electrically connected to the same signal line, such as the light emitting control signal line EM1, to receive the same signal (for example, the first light emitting control signal).In this case, the display substrate 1000 can omit the light emission controlsignal line EM2, thereby reducing the number of signal lines. In other embodiments, the gate electrode of the first light emitting control transistorT4 and the gate electrode of the second light emitting control transistor T5can also be electrically connected to different signal lines respectively. Thatis, the gate electrode of the first light emitting control transistor T4 is electrically connected to the light emitting control signal line EM1 and the gate electrode of the second light emitting control transistor T5 iselectrically connected to the light emitting control signal line EM2, and the light emitting control signal line EM1 and the light emitting control signalline EM2 transmit the same signal.It should be noted that when the first light emitting control transistor T4 and the second light emitting control transistor T5 are different types oftransistors, for example, the first light emitting control transistor T4 is a P-type transistor, and the second light emitting control transistor T5 is an N-type transistor, the first light emitting control signal and the second lightemitting control signal can also be different signals, which is not limited in the embodiments of the present application. In one embodiment, the first reset control sub-signal and the second reset control sub-signal can be the same signal. That is, the gate electrodeof the first reset transistor T6 and the gate electrode of the second resettransistor T7 can be electrically connected to the same signal line, such as the reset control signal line Rst1, to receive the same signal (for example,the first reset control sub-signal). In this case, the display substrate 1000 canomit the reset control signal line Rst2 to reduce the number of signal lines.For another example, the gate electrode of the first reset transistor T6 andthe gate electrode of the second reset transistor T7 can also be electrically connected to different signal lines respectively. That is, the gate electrodeof the first reset transistor T6 is electrically connected to the reset control signal line Rst1, and the gate electrodes of the second reset transistor T7 iselectrically connected to the reset control signal line Rst2, and the resetcontrol signal line Rst1 and the reset control signal line Rst2 transmit thesame signal. It should be noted that the first reset control sub-signal and thesecond reset control sub-signal can also be different signals. In another embodiment, the first reset control sub-signal is different from the secondreset control sub-signal, the pulse width of the reset control signal line Rst2 is larger than the pulse width of the reset control signal line Rst1, and thepulse width of the reset control signal line Rst2 is smaller than the pulse width of the light emitting control signal line EM2 when the second light emitting control transistor T5 is turned off. In this way, the lifetime of the organic light emitting element of the sub-pixel can be improved.In one embodiment, the second reset control sub-signal can be the sameas the scan signal. That is, the gate electrode of the second reset transistorT7 can be electrically connected to the scan signal line Ga1 to receive the scan signal as the second reset control sub-signal.In one embodiment, the gate electrode of the first reset transistor T6 and the source electrode of the second reset transistor T7 are connected to the first reset power supply terminal Vinit1 and the second reset powersupply terminal Vinit2, respectively, and the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be aDC reference voltage terminal to output a constant DC reference voltage.The first reset power supply terminal Vinit1 and the second reset powersupply terminal Vinit2 can be the same signal, for example, the gate electrode of the first reset transistor T6 and the source electrode of the second reset transistor T7 are connected to the same reset power supplyterminal. The first reset power supply terminal Vinit1 and the second resetpower supply terminal Vinit2 can be high voltage terminals or low voltageterminals, as long as they can provide the first reset signal and the secondreset signal to the gate electrode of the driving transistor T1 and the firstelectrode of the light emitting element 220 for reset, which is not limited inthis application.It should be noted that the driving circuit 222, the data writing circuit226, the storage circuit 227, the threshold compensation circuit 228 and thereset circuit 229 in the pixel circuit shown in FIG 1 are only for illustration,and the specific structures of the writing circuit 226, the storage circuit 227,the threshold compensation circuit 228, and the reset circuit 229 can be provided according to actual application requirements, which are notspecifically limited in the embodiments of the present application.According to the characteristics of transistors, transistors can bedivided into N-type transistors and P-type transistors. For the sake of clarity, the embodiments of the present application describe the present application in detail by taking the transistors as P-type transistors (e.g., P-type MOS transistors) as an example. That is, in the description of this application, thedriving transistor T1, the data writing transistor T2, the thresholdcompensation transistor T3, the first light emitting control transistor T4, thesecond light emitting control transistor T5, the first reset transistor T6 and the second reset transistor T7 and the like can all be P-type transistors. However, the transistors in the embodiments of the present application are not limited to P-type transistors. Those skilled in the art can also use N-type transistors (e.g., N-type MOS transistors) to implement the functions of one or more transistors in the embodiments of the present application according to actual needs.It should be noted that the transistors used in the embodiments of the present application can be thin film transistors or field effect transistors orother switching devices with the same characteristics, and the thin filmtransistors can include oxide semiconductor thin film transistors, amorphous silicon thin film transistors or polysilicon thin film transistors, etc. The source and drain electrodes of the transistor can be symmetrical in structure,so the source and drain electrodes of the transistor can be indistinguishable in physical structure. In the embodiments of the present application, in orderto distinguish the transistors, except for the gate electrodes serving as thecontrol electrodes, one of the source and drain electrodes is simply referred to as the first electrode and the other as the second electrode. Therefore, in the embodiments of the present application, the first and second electrodes of all or some of the transistors are interchangeable as required.It should be noted that, in the embodiment of the present application,the pixel circuit of the sub-pixel can be a 7T1C (that is, seven transistors and one capacitor) structure shown in FIG. 1, and can also include other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2Cstructure, or a 9T2C structure, which is not limited in this embodiment ofthe present application.FIGS. 2-7 are schematic diagrams of various layers of a pixel circuitaccording to an embodiment of the present application. The followingdescribes the positional relationship of each circuit in the pixel circuit on the backplane with reference to FIGS. 2-7. The example shown in FIG. 2-7takes the pixel circuit 221 of one pixel group as an example, and takes thepositions of the transistors included in the first color sub-pixel 110 forillustration. The positions of the transistors in the pixel circuits of the second color sub-pixel 120 and the third color sub-pixel 130 are substantially thesame as the positions of the transistors included in the first color sub-pixel.As shown in FIG. 2, the pixel circuit 221 of the first color sub-pixel 110includes a driving transistor T1, a data writing transistor T2, a thresholdcompensation transistor T3, a first light emitting control transistor T4, and a second light emitting control transistor T5, a first reset transistor T6, a second reset transistor T7 and a capacitor C, as shown in FIG. 1.FIG. 2-7 also shows a scan signal line Ga1, a reset control signal line Rst1, a reset power supply signal line Init1, a light emitting control signalline EM1, a data line Vd, power supply signal lines (including a first power supply signal line VDD1, a second power supply signal line VDD3 and athird power supply signal line VDD2 of the first power supply terminal VDD)and a shielding line 344. The first power supply signal line VDD1 and thesecond power supply signal line VDD3 are electrically connected to each other, and the first power supply signal line VDD1 and the third powersupply signal line VDD2 are electrically connected to each other. The second power supply line VDD3 includes a first power supply sub-line VDD31 extending along a first direction Y and a second power supply sub-line VDD32 extending along a second direction X. The first power supplysub-line VDD31 intersects with the second power supply sub-line VDD32.The scan signal line Ga1 is configured to provide a scan signal for thepixel group; the reset control signal line Rst1 is configured to provide a reset control signal for the pixel group; the reset power supply signal line Init1 is configured to provide a reset power signal for the pixel group; the lightemitting control signal line EM1 is configured to provide a light emitting control signal for the pixel group; the data line Vd is configured to provide a light emitting data signal for the pixel group; the first power supply signal line VDD1, the second power supply signal line VDD3 and the third powersupply signal line VDD2 are configured to provide power signals to pixelgroups.For example, FIG. 2 shows an active semiconductor layer 310 of thepixel circuit in the display substrate. The active semiconductor layer 310 can be formed by patterning a semiconductor material. The active semiconductor layer 310 can be used to fabricate channels for the drivingtransistor T1, the data writing transistor T2, the threshold compensationtransistor T3, the first light emitting control transistor T4, the second lightemitting control transistor T5, the first reset transistor T6 and the second reset transistor T7 as described above. The active semiconductor layer 310includes channels and source and drain regions of the transistors of the sub-pixels (i.e., the source region s and the drain region d shown in the secondcolor sub-pixel, for example), and a channel and source and drain regions ofeach transistor in the same pixel circuit are integrally formed. The active semiconductor layer 310 shown in FIG. 2 includes a channel 301 of a firstcolor sub-pixel, a channel 302 of a second color sub-pixel, and a channel303 of a third color sub-pixel.It should be noted that the active semiconductor layer can include anintegrally formed low temperature polysilicon layer, and the source regionand the drain region can become conductive by doping or the like to achieve electrical connection of the components. That is, the active semiconductor layer of each transistor of each sub-pixel is an overall pattern formed by p-silicon, and the transistors in the same pixel circuit include source and drainregions (i.e., source region s and drain region d) and channels, the channels of different transistors are separated by source and drain regions.In one embodiment, the active semiconductor layers in the pixel circuits of sub-pixels of different colors arranged along the first direction have noconnection relationship and are disconnected from each other. The active semiconductor layers in the pixel circuits of the sub-pixels of the same colorarranged along the second direction can be integrally arranged ordisconnected from each other. In one embodiment, the active semiconductor layer 310 can be made ofamorphous silicon, polysilicon, oxide semiconductor materials, or the like.It should be noted that, the above-mentioned source region and drain regioncan be regions doped with n-type impurities or p-type impurities.For example, a gate metal layer of the pixel circuit can include a first conductive layer and a second conductive layer. A gate insulating layer 103(as shown in FIG. 8 and FIG. 9) is formed on the above-mentioned active semiconductor layer 310 to protect the above-mentioned active semiconductor layer 310, and the active semiconductor layer 310 is disposedon the base substrate 100. FIG. 3 shows the first conductive layer 320 included in the display substrate. The first conductive layer 320 is disposedon the gate insulating layer so as to be insulated from the active semiconductor layer 310. The first conductive layer 320 can include asecond polar plate CC2 of the capacitor C, a scan signal line Ga1, a resetcontrol signal line Rst1, a light emitting control signal line EM1, a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, and gate electrodes of a first light emitting control transistorT4, a second light emitting control transistor T5, a first reset transistor T6 and a second reset transistor T7. The scan signal line Ga1 includes a main body portion Ga11 of the scan signal line and a protruding portion Pprotruding from one side of the main body portion Ga11 of the scan signal line.For example, as shown in FIG. 3, the gate electrode of the data writingtransistor T2 can be the portion where the scan signal line Ga1 and the active semiconductor layer 310 overlap. The gate electrode of the first lightemitting control transistor T4 can be a first part where light emitting controlsignal line EM1 overlaps with the active semiconductor layer 310, the gate electrode of the second light emitting control transistor T5 can be a second part where the light emitting control signal line EM1 overlaps with theactive semiconductor layer 310. The gate electrode of the first resettransistor T6 is a first part where the reset control signal line Rst1 overlapswith the active semiconductor layer 310, and the gate electrode of the second reset transistor T7 is a second part where the reset control signal line Rst1 overlaps with the active semiconductor layer 310. The thresholdcompensation transistor T3 can be the thin film transistor with double gateelectrode structure, the first gate electrode of the threshold compensationtransistor T3 can be the portion where the scan signal line Ga1 overlaps with the active semiconductor layer 310, and the second gate electrode of the threshold compensation transistor T3 can be the part where the protrudingportion P of the scan signal line Ga1 overlaps with the active semiconductorlayer 310. As shown in FIGS. 1 and 3, the gate electrode of the drivingtransistor T1 can be the second polar plate CC2 of the capacitor C. It should be noted that the dotted-line rectangle boxes in FIG. 2 showthe parts where the first conductive layer 320 overlaps with the active semiconductor layer 310.For example, as shown in FIG. 3, the scan signal line Ga1, the resetcontrol signal line Rst1, and the light emitting control signal line EM1 are arranged in the second direction X. The scan signal line Ga1 is disposedbetween the reset control signal line Rst1 and the light emitting controlsignal line EM1. The signal line extending in the first direction means thatthe row of the signal line as a whole extends in the first direction, and an area of the part of the signal line extending in the first direction is much larger than an area of the part extending in the second direction. The signalline extending in the second direction means that the row of the signal line as a whole extends along the second direction, and an area of the part of thesignal line extending in the second direction is much larger than an area ofthe part extending in the first direction.For example, in the second direction X, the second polar plate CC2 ofthe capacitor C (i.e. the gate electrode of the driving transistor T1) is disposed between the scan signal line Ga1 and the light emitting controlsignal line EM1. The protruding portion P of the scan signal line Ga1 isdisposed on the side of the scan signal line Ga1 away from the light emittingcontrol signal line EM1.For example, as shown in FIG. 2, in the second direction X, the gate electrode of the data writing transistor T2, the gate electrode of the thresholdcompensation transistor T3, the gate electrode of the first reset transistor T6,and the gate electrode of the second reset transistor T7 are both disposed on a first side of the gate electrode of the driving transistor T1. The gate electrode of the first light emitting control transistor T4 and the gate electrode of the second light emitting control transistor T5 are both disposed on a second side of the gate electrode of the driving transistor T1. Forexample, in the examples shown in FIGS. 2-7, the first side and the secondside of the gate electrode of the driving transistor T1 of the pixel circuit ofthe first color sub-pixel are two sides of the gate electrode of the driving transistor T1 in the second direction X which are opposite with respect to each other. For example, as shown in FIGS. 2-7, in the XY plane, the firstside of the gate electrode of the driving transistor T1 of the pixel circuit ofthe first color sub-pixel can be the upper side of the gate electrode of thedriving transistor T1, and the second side of the gate electrode of the driving transistor T1 of the pixel circuit of the first color sub-pixel can be the lowerside of the gate electrode of the driving transistor T1. For the lower side, forexample, the side of the display substrate used to bind the driving chip is the lower side of the display substrate, and the lower side of the gate electrodeof the driving transistor T1 is the side of the gate electrode of the drivingtransistor T1 that is closer to the driving chip. The upper side is the oppositeside to the lower side, for example, the side of the gate electrode of the driving transistor T1 that is farther from the driving chip.For example, in some embodiments, as shown in FIGS. 2-7, in the firstdirection Y, the gate electrode of the data writing transistor T2 and the gateelectrode of the first light emitting control transistor T4 are both disposed ata third side of the gate electrode of the driving transistor T1, the first gate electrode of the threshold compensation transistor T3, the gate electrode ofthe second light emitting control transistor T5 and the gate electrode of thesecond reset transistor T7 are both disposed on a fourth side of the gate electrode of the driving transistor T1. For example, in the examples shownin FIGS. 2-7, the third side and the fourth side of the gate electrode of the driving transistor T1 of the pixel circuit of the first color sub-pixel are twosides of the gate electrode of the driving transistor T1 in the first directionY which are opposite with respect to each other. For example, as shown in FIGS. 2-7, the third side of the gate electrode of the driving transistor T1 of the pixel circuit of the first color sub-pixel can be the left side of the gate electrode of the driving transistor T1 of the pixel circuit of the first colorsub-pixel, and the fourth side of the gate electrode of the driving transistorT1 of the pixel circuit of the first color sub-pixel can be the right side of the gate electrode of the driving transistor T1 of the pixel circuit of the firstcolor sub-pixel. For the left side and the right side, for example, in the same pixel circuit, the data line is on the left side of the first power supply signalline VDD1, and the first power supply signal line VDD1 is on the right side of the data line.For example, a first insulating layer 104 (as shown in FIG. 8 and FIG. 9) is formed on the above-mentioned first conductive layer 320 to protect the above-mentioned first conductive layer 320. FIG. 4 shows the secondconductive layer 330 of the pixel circuit. The second conductive layer 330includes the first polar plate CC1 of the capacitor C, the reset power supply signal line Init1, the third power supply signal line VDD2 and the light shielding portion S. The third power supply signal line VDD2 is integrally formed with the first polar plate CC1 of the capacitor C. The first polar plateCC1 of the capacitor C and the second polar plate CC2 of the capacitor C at least partially overlap to form the capacitor C.For example, a second insulating layer 105 (as shown in FIG. 8 and FIG.9) is formed on the above-mentioned second conductive layer 330 to protectthe above-mentioned second conductive layer 330. FIG. 5 shows a source-drain metal layer 340 of the pixel circuit. The source-drain metal layer 340 includes a data line Vd, a first power supply signal line VDD1 and ashielding line 344. The data line Vd, the first power supply signal line VDD1and the shielding line 344 all extend along the second direction X. Theshielding line 344 and the data line Vd are disposed in the same layer and made of the same material, so that the shielding line and the data line can be formed in the same patterning process at the same time, eliminatingadditional patterning process for making the shielding line, therebysimplifying the production process of the display substrate, and loweringthe production cost. For example, the source-drain metal layer 340 furtherincludes a connection structure 341, a connection part 342 and a first electrode connection sub-structure 343 of the electrode connection structure.One end of the connection structure 341 is connected to the gate electrodeof the driving transistor T1, and the other end of the connection structure341 is connected to the source and drain regions of the thresholdcompensation transistor T3. FIG. 5 also shows exemplary locations of a plurality of via holesthrough which the source-drain metal layer 340 passes to connect to aplurality of film layers disposed between the source-drain metal layer 340and the base substrate. For example, the source-drain metal layer 340 isconnected to the active semiconductor layer 310 shown in FIG. 2 through via holes 381, 382, 384, 387 and 352, and the source-drain metal layer 340passes through the via holes 3832, 386, 385, 331 and 332 and connected tothe second conductive layer 330 shown in FIG. 4. The specific film layer where each via hole is disposed and the specific connection relationship willbe described in detail with reference to FIG. 7 later. For example, a third insulating layer 106 and a fourth insulating layer107 (as shown in FIGS. 8 and 9) are formed on the above-mentioned source- drain metal layer 340 to protect the above-mentioned source-drain metallayer 340. The organic light emitting element of each sub-pixel can bedisposed on a side of the third insulating layer and the fourth insulating layeraway from the base substrate.FIG. 6 shows the third conductive layer 350 of the pixel circuit. The third conductive layer 350 includes a second electrode connection sub-structure 353 of the electrode connection structure and second power supplysignal lines VDD3 distributed along the second direction X and the firstdirection Y respectively and intersect with one another. FIG. 6 also showsexemplary locations of a plurality of via holes 351 and 354 through which the third conductive layer 350 is connected to the source-drain metal layer340.FIG. 7 is a schematic diagram of the stacking positional relationship ofthe active semiconductor layer 310, the first conductive layer 320, thesecond conductive layer 330, the source-drain metal layer 340 and the thirdconductive layer 350 described above. As shown in FIGS. 2-7, the data lineVd is connected to the source region of the data writing transistor T2 in the active semiconductor layer 310 through at least one via hole (e.g., the viahole 381) in the gate insulating layer, the first insulating layer, and thesecond insulating layer. The first power supply signal line VDD1 communicates with the source region of the corresponding first lightemitting control transistor T4 in the active semiconductor layer 310 throughat least one via hole (e.g., the via hole 382) in the gate insulating layer, the first insulating layer, and the second insulating layer. As shown in FIGS. 2-7, one end of the connection structure 341 is connected to the drain region of the corresponding threshold compensationtransistor T3 in the active semiconductor layer 310 through at least one viahole (e.g., the via hole 384) in the gate insulating layer, the first insulatinglayer and the second insulating layer, and the other end of the connection structure 341 is connected to the gate electrode of the driving transistor T1 (i.e., the second polar plate CC2 of the capacitor C) in the first conductivelayer 320 through at least one via (e.g., the via hole 385) in the first insulating layer and the second insulating layer. One end of the connectionpart 342 is connected to the reset power supply signal line Init1 through a via hole (for example, the via hole 386) in the second insulating layer, andthe other end of the connection part 342 is connected to the drain region ofthe second reset transistor T7 in the active semiconductor layer 310 through at least one via (e.g., the via hole 387) in the gate insulating layer, the firstinsulating layer and the second insulating layer. The first electrodeconnection sub-structure 343 is connected to the drain region of the secondlight emitting control transistor T5 in the active semiconductor layer 310through at least one via hole (e.g., the via hole 352) in the gate insulating layer, the first insulating layer, and the second insulating layer. It should be noted that the source region and the drain region of the transistor mentionedin the embodiments of the present disclosure can be the same in structure,so the source region and the drain region of the transistor can beindistinguishable in structure. Therefore, the two are interchangeable as required.For example, as shown in FIGS. 2-7, the first power supply signal line VDD1 passes through at least one via hole (e.g., via hole 3832) in the secondinsulating layer between the second conductive layer 330 and the source-drain metal layer 340 and connected to the first polar plate CC1 of the capacitor C in the second conductive layer 330.For example, as shown in FIGS. 2-7, the shielding line 344 extendsalong the second direction X, and an orthographic projection of the shieldingline 344 on the base substrate is disposed between an orthographic projection of the driving transistor on the base substrate and an orthographic projection of the data line on the base substrate. For example, the shieldingline in the pixel circuit of the first color sub-pixel can reduce the influenceof the signal transmitted through the data line in the pixel circuit of the second color sub-pixel on the performance of the threshold compensationtransistor T3 of the first color sub-pixel, further, reduce the influence of the coupling between the gate electrode of the driving transistor of the first colorsub-pixel and the data line of the second color sub-pixel, and alleviate theproblem of crosstalk.For example, as shown in FIGS. 2-7, the shielding line 344 is connected to the reset power signal line Init1 through at least one via hole (e.g., the via hole 332) in the second insulating layer, except that the shielding line has afixed potential, and also makes the voltage of the initialization signal transmitted on the reset power supply signal line more stable, which is morebeneficial to the working performance of the pixel driving circuit. For example, as shown in FIGS. 2-7, the shielding line 344 iselectrically connected to the reset power signal line so that the shielding line has a fixed potential. The shielding line 344 can be electrically connected to the two reset power signal lines Init1 extending in the Y directionrespectively, and the two reset power signal lines Init1 are respectivelydisposed on two sides of the shielding line 344 along the X direction. Forexample, the two reset power supply signal lines correspond to the pixelcircuits of the nth row and the (n+1)th row respectively. For example, the shielding line 344 in the same column can be a whole shielding line, and the whole shielding line includes a plurality of sub-sections disposed between two adjacent reset power supply signal lines, andeach sub-section is respectively disposed within each pixel circuit area inthe column. For example, in addition to coupling the shielding line 344 with thereset power signal line, the shielding line 344 can also be coupled with thefirst power signal line, so that the shielding line 344 has the same fixedpotential as the first power signal line. For example, an orthographic projection of the shielding line 344 onthe base substrate is disposed between an orthographic projection of the threshold compensation transistor T3 on the base substrate and anorthographic projection of the data line Vd on the base substrate, so that theshielding line 344 can reduce the influence of the change in signaltransmitted on the data line on the performance of the thresholdcompensation transistor T3, further reduce the influence of the couplingbetween the gate electrode of the driving transistor and the data signal line Vd(n+1), and solve the problem of vertical crosstalk, so that when thedisplay substrate can achieve a better display effect when being used fordisplay. For example, the orthographic projection of the shielding line 344 onthe base substrate can be disposed between the orthographic projection of the connection structure 341 on the base substrate and the orthographicprojection of the data line on the base substrate. The orthographic projectionof the shielding line 344 on the base substrate T1 is disposed between the orthographic projection of the driving transistor T1 on the base substrate andthe orthographic projection of the data line on the base substrate. The above-mentioned configuration can well reduce a first crosstalkgenerated between the data line and the threshold compensation transistor, and a second crosstalk generated between the data line and the connection structure, thereby reducing indirect crosstalk to the driving transistor due to the first crosstalk and the second crosstalk. In addition, the above-mentioned configuration can also reduce direct crosstalk between the data line and thedriving transistor, thereby better ensuring the working performance of the display substrate. For example, the shielding line 344 is not limited to the above-mentioned configuration, and the shielding line 344 can also be only coupled with the reset power supply signal line corresponding to the pixel circuit in the nth row, or only with the reset power supply signal line correspondingto the pixel circuit in the (n+1)th row. Moreover, the length of the shielding line 344 extending in the second direction X can also be set according to actual needs. For example, the pixel circuit of a sub-pixel of a color also includes alight shielding portion S. The light shielding portion S and the shielding line344 are disposed in different layers, and an orthographic projection of the light shielding portion S on the base substrate has overlap with an orthographic projection of the shielding line 344 on the base substrate. Theshielding line 344 is connected to the light shielding portion S in the secondconductive layer 330 through the via hole 331 in the second insulating layer, so that the light shielding portion S has a fixed potential, thereby betterreducing coupling effect between the threshold compensation transistor T3 and other conductive patterns nearby, making the working performance ofthe display substrate more stable.For example, the light shielding portion S has overlap with the active semiconductor layer 310 between and the two gate electrodes of thethreshold compensation transistor T3, to prevent the active semiconductorlayer 310 from being illuminated to change characteristics, such as thevoltage of this part of the active semiconductor layer is prevented from changing to prevent crosstalk. This example schematically shows that the light shielding portion beingconnected to the shielding line, but it is not limited to this, and the two can also be in disconnection.For example, as shown in FIGS. 2-7, the second power supply signalline VDD3 is connected to the first power supply signal line VDD1 through at least one via hole 351 in the third insulating layer and the fourth insulatinglayer, and the second electrode connection sub-structure 353 is connected to the first electrode connection sub-structure 343 through the via hole 354 in the third insulating layer and the fourth insulating layer. For example, the third insulating layer can be a passivation layer, the fourth insulating layer can be a planarization layer, and the third insulatinglayer is disposed between the fourth insulating layer and the base substrate.The fourth insulating layer can be an organic layer, and the thickness of theorganic layer is thicker than that of the inorganic layers such as thepassivation layer. For example, the via hole 351 and the via hole 354 are both nested via holes. That is, the via hole 351 includes a first via hole in the third insulatinglayer and a second via hole in the fourth insulating layer, with the positionof the first via hole in the third insulating layer being opposite to the positionof the second via hole in the fourth insulating layer, and an orthographicprojection of the second via holes in the fourth insulating layer on the base substrate being located within an orthographic projection of the first via hole in the third insulating layer on the base substrate.For example, the second power supply signal lines VDD3 are distributed in a grid form. An orthographic projection of the second powersupply sub-line VDD32 of the second power supply signal line VDD3extending along the X direction on the base substrate is substantially coincides with an orthographic projection of the first power supply line VDD1 on the base substrate, or the orthographic projection of the first powersupply line VDD1 on the base substrate is located within the orthographicprojection of second power supply sub-line VDD32 on the base substrate.In addition, the power supply signal line VDD3 being electrically connected to the first power supply signal line VDD1 can reduce the voltage drop ofthe first power supply signal line VDD1, thereby improving the uniformityof the display device.For example, the second power supply signal line VDD3 can be made of the same material as the source-drain metal layer. For example, as shown in FIG. 5, the first electrode connection sub-structures 343 of the first color sub-pixel, the second color sub-pixel and thethird color sub-pixel are all block structures. The subsequently formed first electrode of a sub-pixels of a color will be connected to the correspondingsecond electrode connection sub-structure 353 through a via hole so as to be connected to the drain region of the second light emitting control transistorT5.This embodiment includes, but is not limited to, the position of the second electrode connection sub-structure in a sub-pixel of a color isdetermined according to the arrangement of the organic light emitting elements and the position of the light emitting region.For example, FIG. 8 is a schematic diagram of a partial cross-sectionalstructure of the display substrate where the layer shown in FIG. 7 is disposed,and FIG. 7 only illustrates part of the film layers in FIG. 8. As shown in FIGS. 7 and 8, in the active semiconductor layer in the pixel circuit of thesecond color sub-pixel 120, a gate insulating layer 103 is disposed on a side of the second electrode (e.g., the drain electrode T5d) of the second light emitting control transistor T5 away from the side of the base substrate 100,a light emitting control signal line EM1 is provided on a side of the gateinsulating layer 103 away from the base substrate 100, a first insulating layer104 is disposed on a side of the light emitting control signal line EM1 awayfrom the base substrate 100, a third power supply signal line VDD2 is disposed on a side of the first insulating layer 104 away from the base substrate 100, a second insulating layer 105 is disposed on a side of the thirdpower supply signal line VDD2 away from the base substrate 100, and a first electrode connection sub-structure 343 is disposed on a side of thesecond insulating layer 105 away from the base substrate 100. The first electrode connection sub-structure 343 of the second color sub-pixel 120 isconnected to the second electrode T5d of the second light emitting control transistor T5 in the active semiconductor layer 310 through the via hole 352in the gate insulating layer 103, the first insulating layer 104 and the secondinsulating layer 105. The first electrode connection sub-structure 343 has overlap with both the third power supply signal line VDD2 and the lightemitting control signal line EM1. On a side of the first electrode connectionsub-structure 343 away from the base substrate 100 is provided with a thirdinsulating layer 106 and a fourth insulating layer 107 in this order, and on a side of the fourth insulating layer 107 away from the base substrate 100 is provided with a second electrode connection sub-structure 353 and a second power supply signal line VDD3. The second power supply signal line VDD3 has overlap with the third power supply signal line VDD2. The second electrode connection sub-structure 353 is connected to the first electrodeconnection sub-structure 343 through a nested via hole 354 in the third insulating layer 106 and the fourth insulating layer 107, thereby realizing connection with the second light emitting control transistor.For example, as shown in FIG. 8, the data line Vd is connected to thesource electrode T2s of the data writing transistor T2 through the via hole381 in the gate insulating layer 103, the first insulating layer 104 and the second insulating layer 105. One end of the connection structure 341 is connected to the drain electrode T3d of the threshold compensation transistor T3 through the via hole 384 in the gate insulating layer 103, the first insulating layer 104 and the second insulating layer 105, and the otherend of the connection structure 341 is connected to the gate electrode of thedriving transistor T1 (i.e., the second polar plate CC2 of the capacitor C)through the via hole 385 in the first insulating layer 104, the second insulating layer 105. The channel T1c of the driving transistor T1 is disposed on the side of the gate electrode facing the base substrate 100, and has nooverlap with the via hole 385, the source electrode T1d of the drivingtransistor T1 has overlap with both the its gate electrode and the firstelectrode polar plate CC1 of the capacitor C. For example, FIG. 9 is a schematic diagram of a partial cross-sectionalstructure of the display substrate where the layer shown in FIG. 7 is disposed,and FIG. 7 only illustrates a part of the film layers in FIG. 9. As shown in FIGS. 7-9, the difference between the first color sub-pixel 110 and the second color sub-pixel 120 is that in the second color sub-pixel 120, an orthographic projection of the second electrode connection sub-structure353 on the base substrate 100 has no overlap with an orthographic projectionof the second electrode T5d of the second light emitting control transistorT5 thereof on the base substrate 100, while in the first color sub-pixel 130,an orthographic projection of the second electrode connection sub-structure 353 on the base substrate 100 has overlap with an orthographic projectionof the second electrode T5d of the second light emitting control transistor T5 thereof on the base substrate 100. In the first color sub-pixel 110, the first electrode connection sub-structure 343 has no overlap with either thethird power supply signal line VDD2 or the light emitting control signal line EM1. In the first color sub-pixel 110, the channel T1c of the drivingtransistor T1 is disposed on a side of the gate electrode of the drivingtransistor T1 facing the base substrate 100 and has overlap with the via hole385. From this, it can be seen that the width of the channel of the drivingtransistor of the first color sub-pixel is larger than the width of the channel of the second color sub-pixel.For example, as shown in FIGS. 2-7, in the second direction X, the scan signal line Ga1, the reset control signal line Rst1 and the reset power supply signal line Init1 are all disposed on a first side of the gate electrode of the driving transistor T1 of the pixel circuit of the first color sub-pixel, the light emitting control signal line EM 1 is disposed on a second side of the drivingtransistor T1 of the pixel circuit of the first color sub-pixel. For example, the scan signal line Ga1, the reset control signal line Rst1,the light emitting control signal line EM1, and the reset power supply signal line Init1 all extend in the first direction Y, and the data line Vd extends inthe second direction X.It should be noted that the positional arrangement relationship of the driving circuit, the first light emitting control circuit, the second lightemitting control circuit, the data writing circuit, the storage circuit, thethreshold compensation circuit and the reset circuit in each pixel circuit isnot limited to the examples shown in FIGS. 2-7, the positions of the drivingcircuit, the first light emitting control circuit, the second light emitting control circuit, the data writing circuit, the storage circuit, the thresholdcompensation circuit and the reset circuit can be specifically set accordingto actual application requirements.For example, as shown in FIGS. 2-9, the first electrode 11 of the firstcolor sub-pixel is connected to the second electrode connection sub- structure 353 through the via hole (not shown) of the fifth insulating layer, thereby realizing connection with the drain region of the second light emitting control transistor T5. Similarly, the first electrode 13 of the organiclight emitting element of the third color sub-pixel is connected to the secondelectrode connection sub-structure 353 through the via hole (not shown) of the fifth insulating layer, so as to realize the connection with the drain regionof the second light emitting control transistor T5. The first electrode 12 ofthe second color sub-pixel is connected to the second electrode connection sub-structure 353 through the via hole of the fifth insulating layer, and thenconnected to the second electrode connection sub-structure 343, so as torealize the connection with the drain region of the second light emittingcontrol transistor T5. The embodiment of the present application provides a novel pixelarrangement, which will be introduced below. As shown in FIG. 7, an orthographic projection of the pixel opening 21 of the first color sub-pixelon the base substrate has no overlap with an orthographic projection of the channel 301 of the driving transistor of the first color sub-pixel on the base substrate. An orthographic projection of the pixel opening 22 of the second color sub-pixel on the base substrate has no overlap with an orthographicprojection of the channel 302 of the driving transistor of the second colorsub-pixel on the base substrate. An orthographic projection of the pixelopening 23 of the third color sub-pixel on the base substrate has no overlap with an orthographic projection of the channel 303 of the driving transistorof the third color sub-pixel on the base substrate. The above-mentioned arrangement of pixels is different from the arrangement of pixels in displaypanels existing in the art.In one embodiment, the plurality of sub-pixels are divided into aplurality of pixel groups, each of the pixel groups including a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. At least one ofthe pixel groups includes two rows of sub-pixels arranged along the first direction, wherein one row of sub-pixels arranged along the first direction includes first color sub-pixels and third color sub-pixels which are alternately arranged, and the other row of sub-pixels arranged along the firstdirection includes second color sub-pixels. Here, a row of sub-pixels arranged along the first direction refers to that the organic light emittingelements of the sub-pixels are arranged along the first direction.In one embodiment, the first electrode of the sub-pixel or the pixel opening can be used as a reference to divide the plurality of sub-pixels intoa plurality of pixel groups. In other embodiments, the pixel circuit of thesub-pixel can also be used as a reference to divide the plurality of sub-pixels into a plurality of pixel groups. FIG. 7A is a schematic diagram of part ofthe film layers of the plurality of pixel groups 101 in the display substrate where the layer shown in FIG. 7 is disposed, and illustrates the arrangementof the pixel openings of the plurality of pixel groups 101. Referring to FIG. 7A, the pixel openings of the same pixel group 101 are divided into tworows, wherein one row of first electrodes arranged along the first direction include pixel openings 21 of the first color sub-pixels and pixel openings 23of the third color sub-pixels which are alternately arranged, and the otherrow of first electrodes arranged along the first direction include pixel openings 22 of the second color sub-pixels. In the embodiment shown in FIG. 7A, the pixel circuits of the same pixel group 101 are disposed in the same row. In other embodiments, the pixel circuits of the same pixel group101 can also be disposed in different rows.In one embodiment, referring to FIG. 7, any one of the orthographic projection of the pixel opening 21 of the first color sub-pixel on the base substrate, the orthographic projection of the pixel opening 22 of the secondcolor sub-pixel on the base substrate or the orthographic projection of the pixel opening 23 of the third color sub-pixel on the base substrate has nooverlap with any one of the orthographic projection of the channel 301 of the driving transistor of the first color sub-pixel on the base substrate, the orthographic projection of the channel 302 of the driving transistor of thesecond color sub-pixel on the base substrate, or the orthographic projectionof the channel 303 of the driving transistor of the third color sub-pixel onthe base substrate. When displayed at high temperature, the lifespan of the display panel existing in the art is short, and a color shift phenomenon tends to occurduring display. The inventor found that the reason for this problem is thatwhen the display panel is displaying, the current of the driving transistor ofthe blue sub-pixel is relatively large. For example, the current of the drivingtransistor of the blue sub-pixel is 2.15 times that of the current of the drivingtransistor of the green sub-pixel. The channel of the driving transistor of theblue sub-pixel overlaps with the organic light emitting element of the greensub-pixel, resulting in a large temperature rise of the organic light emittingelement of the green sub-pixel, which in turn causes the green sub-pixel todecay too quickly and shortens the lifespan. In addition, the brightnessattenuation speeds of the sub-pixels of different colors are quite different, so that the color shift phenomenon occurs in the display screen. The above-mentioned arrangement of the sub-pixels can prevent the driving transistorof the second color sub-pixel from increasing the temperature of the organiclight emitting element of the first color sub-pixel or the third color sub-pixeltoo much and resulting in an excessively fast luminance decay of the organic light emitting element. It helps to improve the lifespan of sub-pixels, canreduce the difference in the brightness decay speeds of sub-pixels ofdifferent colors and alleviate the color shift problem of the display substrate.Since the pixel openings of sub-pixels of each color and the channels of thedriving transistor do not overlap, so that the temperature of the organic light emitting elements of the sub-pixels of the colors can be lowered, and theservice life and color shift problems of the display panel can be improved.In one embodiment, in at least one pixel group, a distance between the channel of the driving transistor of the sub-pixel and the scan signal line in the second direction X ranges from 1 μm to 50 μm. Specifically, a distance between the channel 301 of the driving transistor of the first color sub-pixeland the scan signal line Ga1 in the second direction ranges from 1 μm to 50μm. A distance between the channel 302 of the driving transistor of thesecond color sub-pixel and the scan signal line Ga1 in the second direction ranges from 1 μm to 50 μm. A distance between the channel 303 of thedriving transistor of the third color sub-pixel and the scan signal line Ga1 inthe second direction ranges from 1 μm to 50 μm.Further, in at least one pixel group, the distance between the channel ofthe driving transistor of the sub-pixel and the scan signal line in the second direction ranges from 10 μm to 50 μm. For example, the distance between the channel of the driving transistor of the sub-pixel and the scan signal line in the second direction is 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40μm, 45 μm, 50 μm, and so on.In one embodiment, as shown in FIG. 7, in at least one of the pixelgroups, the orthographic projection of the pixel opening corresponding to each of the sub-pixels on the base substrate has no overlap with theorthographic projection of the gate electrode of the driving transistor of any of the sub-pixels on the base substrate; or, the orthographic projection of the pixel opening corresponding to each of the sub-pixels on the base substrate has an overlapping region with the orthographic projection of the gateelectrode of the driving transistor of any of the sub-pixels on the base substrate, and a ratio of the area of the overlapping region to the area of the gate electrode is not more than 10%. When the temperature of the drivingtransistor increases, the heat generated by the driving transistor is mainly transmitted to the organic light emitting element of the sub-pixel throughthe gate electrode. With the orthographic projection of the pixel openingcorresponding to each of the sub-pixels on the base substrate having no overlap with the orthographic projection of the gate electrode of the drivingtransistor of any of the sub-pixels on the base substrate; or, the orthographic projection of the pixel opening corresponding to each of the sub-pixels onthe base substrate having a relatively small area of an overlapping region with the orthographic projection of the gate electrode of the driving transistor of any of the sub-pixels on the base substrate, it can effectively reduce the amount of heat generated by the driving transistor that is transmitted to the organic light emitting element, and the temperature of theorganic light emitting element can be prevented from rising too much, whichwould otherwise cause the organic light emitting element to decay too quickly and shorten its service life. It can improve the service life of subpixelsand alleviate the color shift problem of display substrate.Further, in the embodiment shown in FIG. 7, the distance between thegate electrode of the driving transistor of the sub-pixel and the scan signal line Ga1 in the second direction ranges from 2 μm to 10 μm. The distance between the gate electrode of the driving transistor of the sub-pixel and thescan signal line Ga1 in the second direction is, for example, 2 μm, 4 μm, 6μm, 8 μm, 10 μm, and so on.In one embodiment, referring to FIG. 10, in at least one pixel group, theorthographic projection of the scan signal line Ga1 in the second direction X has overlap with the orthographic projection of the gate electrode of thedriving transistor of the sub-pixel in the second direction X, where the second direction X is perpendicular to the first direction Y. The orthographic projections of the scan signal line and the gate electrode of the drivingtransistor on the second direction X refer to the orthographic projections ofthe scan signal line and the gate electrode of the driving transistor on a straight line extending along the second direction X. As shown in FIG. 10, the orthographic projection of the scan signal line Ga1 in the seconddirection X has overlap with the orthographic projection of the gateelectrode 321 of the driving transistor of the first color sub-pixel in thesecond direction X. The orthographic projection of the scan signal line Ga1is in the second direction X has overlap with the orthographic projection of the gate electrode 322 of the driving transistor of the second color sub-pixelin the second direction X. The orthographic projection of the scan signalline Ga1 in the second direction X has overlap with the orthographic projection of the gate electrodes 323 of the driving transistor of the thirdcolor sub-pixel in the second direction X. Such configuration can make the arrangement of the components in the display substrate relatively closer toone another, which can increase the density of the sub-pixels in the displaysubstrate.In one embodiment, as shown in FIG. 10, the scan signal line Ga1includes a main body portion Ga11 of the scan signal line and a protruding portion P protruding from one side of the main body portion Ga11 of the scan signal line. The main body portion Ga11 of the scan signal line extendsalong the first direction Y as a whole, and the protruding portion P extendsalong the second direction X. The threshold compensation transistor T3 ofthe sub-pixel includes a first gate electrode and a second gate electrode. In the threshold compensation transistor, the first gate electrode is a part of themain body portion Ga11 of the scan signal line that overlaps with theorthographic projection of the active semiconductor layer on the base substrate, and the second gate electrode is the part of the protruding portionP that overlaps the orthographic projection of the active semiconductor layeron the base substrate.Further, as shown in FIG. 10 and FIG. 10A, the main body portion Ga11 of the scan signal line includes a first scan sub-line 324, a second scan sub-line 326 and a connection part 325. The first scan sub-line 324 is connected to the second scan sub-line 326 through the connection part 325. The firstscan sub-line 324 and the second scan sub-line 326 extend substantially along the first direction Y. In the same scan signal line, in the first direction,the protruding portion P and the connection part 325 are disposed on both sides of the first scan sub-line 324. In the illustrated embodiment, theprotruding portion P is disposed on the side of the first scan sub-line 324close to the first reset control signal line Rst1, and the connection part 325is disposed on the side of the first scan sub-line 324 away from the first reset control signal line Rst1. In other embodiments, the connection part 325 canbe disposed on the side of the first scan sub-line 324 close to the first resetcontrol signal line Rst1, and the protruding portion P can be disposed on theside of the first scan sub-line 324 away from the first reset control signal line Rst1. The first scan sub-line 324 is connected to the pixel circuit of the firstcolor sub-pixel, the second scan sub-line 326 is connected to the pixel circuitof the second color sub-pixel, and extension direction of part of theconnection part 325 intersects with the extension direction of the first scan sub-line 324. In the threshold compensation transistor, the first gate electrode is the part of the connection part 325 that overlaps with theorthographic projection of the active semiconductor layer on the base substrate.Further, the orthographic projection of the connection part 325 in thesecond direction X has overlap with the orthographic projection of the gate electrode of the driving transistor of the sub-pixel in the second direction X. As shown in FIG. 10, the orthographic projection of the connection part 325in the second direction X has overlap with all of the orthographic projectionof the gate electrode 321 of the first color sub-pixel in the second directionX, the orthographic projection of the gate electrode 322 of the second colorsub-pixel in the second direction X and the orthographic projection of thegate electrode 323 of the third color sub-pixel in the second direction X. In one embodiment, as shown in FIG. 10 and FIG. 10A, the connectionpart 325 includes a first connection sub-part 3251, a second connection sub-part 3252 and a third connection sub-part 3253 that are connected insequence. The extension direction of the first connection sub-part 3251 andthe third connection sub-part 3253 intersect with the extension direction of the first scan sub-line 324, and the extension direction of the second connection sub-part 3252 is the same as the extension direction of the firstscan sub-line 324. The third connection sub-part 3253 is connected to the first scan sub-line 324, and the first connection sub-part 3251 is connected to the second scan sub-line 326. In the threshold compensation transistor, the first gate electrode is a part of the second connection sub-part 3252 thatoverlaps with the orthographic projection of the active semiconductor layeron the base substrate.In one embodiment, as shown in FIG. 2 and FIG. 2A, the active semiconductor layer 310 includes a first section 311, a second section 312, a third section 313 and a fourth section 314 that are connected in sequence. The second section 312, the fourth section 314 and the main body portionGa11 of the scan signal line extend along the first direction Y, the firstsection 311 and the third section 313 extend in the second direction X. The second gate electrode of the threshold compensation transistor T3 is the part of the protruding portion P that overlaps with the orthographic projection ofthe fourth section 314 on the base substrate. The gate electrode of the resettransistor includes a part where the reset control signal line Rst1 overlaps with the orthographic projection of the first section 311 on the base substrate. Specifically, the first reset transistor T6 includes two gate electrodes, one of which includes the part of the reset control signal line Rst1 that overlaps theorthographic projection of the first section 311 on the base substrate. Sucharrangement is convenient for the threshold compensation transistor T3 andthe first reset transistor T6 to form a double gate electrode structure.Further, as shown in FIG. 10, in at least one pixel group, theorthographic projection of the gate electrode of the driving transistor of atleast one sub-pixel on the base substrate has overlap with the orthographic projection of its corresponding pixel opening on the base substrate.Specifically, the orthographic projection of the gate electrode 321 of thedriving transistor of the first color sub-pixel on the base substrate has overlap with the orthographic projection of its corresponding pixel opening21 on the base substrate; the orthographic projection of the gate electrode 323 of the driving transistor of the third color sub-pixel on the base substratehas overlap with the orthographic projection of its corresponding pixel opening 23 on the base substrate.Further, the part where the orthographic projection of the gate electrodeof at least the sub-pixel on the base substrate overlaps with the corresponding pixel opening on the base substrate has a size in the seconddirection X ranging from 0 to 30 μm. In the embodiment shown in FIG. 10,the orthographic projections of the gate electrode of the first color sub-pixel,the gate electrode of the second color sub-pixel and the gate electrode of the third color sub-pixel on the base substrate each has an overlapping part with the corresponding pixel opening on the base substrate of a size larger than 0in the second direction X.In one embodiment, as shown in FIG. 11, the connection structure 341includes a first portion 3411 and a second portion 3412 connected to the firstportion 3411. The orthographic projection of the first portion 3411 on the base substrate and the orthographic projection of the protruding portion Pon the base substrate are located on the same side of the orthographicprojection of the main body portion Ga11 of the scan signal line on the basesubstrate. The length of the first portion 3411 in the second direction X is larger than the length of the protruding portion P in the second direction X.Here, in the second direction X, the orthographic projection of the main body portion Ga11 of the scan signal line on the base substrate includes twoopposite sides (for example, the upper side and the lower side), and theorthographic projection of the first portion 3411 on the base substrate and the orthographic projection of the protruding portion P on the base substratebeing located on the same side of the orthographic projection of the mainbody portion Ga11 of the scan signal line on the base substrate refers to that both the orthographic projection of the first portion 3411 on the base substrate and the orthographic projection of the protruding portion P on the base substrate being located on the upper side, or the lower side of the orthographic projection of the main body portion Ga11 of the scan signalline on the base substrate. In the illustrated embodiment, the orthographic projection of the first portion 3411 on the base substrate and the orthographic projection of the protruding portion P on the base substrate areboth located on the upper side of the orthographic projection of the mainportion Ga11 of the scan signal line on the base substrate. Such arrangement can facilitate connecting the end of the first portion 3411 to the gate electrode of the driving transistor T1.Further, the size of the connection structure 341 in the second direction X ranges from 35 μm to 70 μm. Scuh arrangement ensures that both ends of the connection structure 341 are electrically connected to the gate electrodeof the driving transistor T1 in the first conductive layer 320 and the source and drain regions of the threshold compensation transistor T3 in the active semiconductor layer 310 respectively. In some embodiments, the size of the connection structure 341 in the second direction X is 35 μm, 40 μm, 45 μm,50 μm, 55 μm, 60 μm, 65 μm, 70 μm, and so on.In one embodiment, as shown in FIG. 7 and FIG. 10, the orthographic projection of the first electrode 12 of at least one of the second color sub-pixels on the base substrate has overlap with the orthographic projection ofthe reset control signal line Rst1 on the base substrate and the orthographicprojection of the scan signal line Ga1 on the base substrate overlap. In someembodiments, the orthographic projection of the first electrode 12 of eachsecond color sub-pixel of the display panel on the base substrate has overlapwith the orthographic projection of one reset control signal line Rst1 on thebase substrate and the orthographic projection of one scan signal line Ga1on the base substrate. Such arrangement helps to increase the pixel densityof the display substrate.In one embodiment, the size of the first color sub-pixel in the firstdirection Y ranges from 35 μm to 110 μm, and the size of the first color sub- pixel in the second direction X ranges from 20 μm to 60 μm. The size of thesecond color sub-pixel in the first direction Y ranges from 35 μm to 120 μm,and the size of the second color sub-pixel in the second direction X rangesfrom 20 μm to 80 μm. The size of the third color sub-pixel in the firstdirection in Y ranges from 35 μm to 70 μm, and the size of the third color sub-pixel in the second direction X ranges from 20 μm to 60 μm. The sizeof the sub-pixel in the first direction refers to its maximum size in the firstdirection Y, and the maximum size of the sub-pixel in the first direction Y refers to the maximum size of an overlapping part of the orthographic projection of the pixel opening of the sub-pixel on the base substrate and the orthographic projection of the first electrode on the base substrate in the firstdirection Y. The size of the sub-pixel in the first direction X refers to itsmaximum size in the second direction X. The maximum size of the sub-pixelin the second direction X refers to the maximum size of an overlapping part of the orthographic projection of the pixel opening of the sub-pixel on the base substrate and the orthographic projection of the first electrode on thebase substrate in the first direction Y. In some examples, the size of the first color sub-pixel in the firstdirection Y is, for example, 35 μm, 45 μm, 55 μm, 65 μm, 75 μm, 85 μm, 95 μm, 105 μm, 110 μm, and so on. The size of the first color sub-pixel in the second direction X is, for example, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, and so on. The size of the second color sub-pixelin the first direction Y is, for example, 35 μm, 45 μm, 55 μm, 65 μm, 75 μm,85 μm, 95 μm, 105 μm, 115 μm, 120 μm, and so on. The size of the secondcolor sub-pixel in the second direction X is, for example, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, and so on. The size of the third color sub-pixel in the first direction Y is 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm,65 μm, 70 μm. The size of the third color sub-pixel in the second directionX is, for example, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, and so on. Further, the area of the second color sub-pixel is larger than the area ofthe first color sub-pixel, and the area of the first color sub-pixel is larger than the area of the third color sub-pixel. Such arrangement can reduce thedifference in the lifetimes of the sub-pixels of each color. The embodiment of the present application also provides another new pixel arrangement. Referring to FIGS. 12 to 16, the orthographic projectionof the pixel opening of at least one sub-pixel on the base substrate has overlap with the orthographic projection of the channel of its drivingtransistor on the base substrate, and the orthographic projection of the pixelopening 22 of at least one of the second color sub-pixels in the first direction has overlap with the orthographic projection of the pixel opening 21 of thefirst color sub-pixel in the first direction Y and the orthographic projection of the pixel opening 23 of the third color sub-pixel in the first direction Y, and the orthographic projection of the pixel opening 22 of at least one of the second color sub-pixels in the second direction X has no overlap with eitherthe orthographic projection of the pixel opening 21 of the first color sub-pixel in the second direction X or the orthographic projection of the pixel opening 23 of the third color sub-pixel in the second direction X, where the first direction Y intersects with the second direction X. The pixelarrangement provided by the embodiments of the present application is different from the pixel arrangement in the display panel existing in the art. The orthographic projection of the pixel opening on the first direction Y refers to the orthographic projection of the pixel opening on a straight lineextending along the first direction Y. In one embodiment, as shown in FIG. 16, the orthographic projectionof the pixel opening 21 of the first color sub-pixel on the base substrate hasoverlap with the orthographic projection of the channel 301 of the driving transistor thereof on the base substrate, the orthographic projection of the pixel opening 23 of the third color sub-pixel on the base substrate hasoverlap with the orthographic projection of the channel 303 of the drivingtransistor thereof on the base substrate, and the orthographic projection ofthe pixel opening 22 of the second color sub-pixel on the base substrate hasoverlap with the orthographic projection of the channel 302 of the drivingtransistor thereof on the base substrate. Further, as shown in FIG. 16, the orthographic projection of the channel301 of the driving transistor of the first color sub-pixel on the base substrate falls within the orthographic projection of the pixel opening 21 on the base substrate, the orthographic projection of the channel 302 of the drivingtransistor of the second color sub-pixel on the base substrate falls within the orthographic projection of the pixel opening 22 on the base substrate, andthe orthographic projection of the channel 303 of the driving transistor ofthe third color sub-pixel on the base substrate falls within the orthographicprojection of the pixel opening 23 on the base substrate.In other embodiments, in the first color sub-pixel, the second color sub- pixel and the third color sub-pixel, only orthographic projections of the pixelopenings of the sub-pixels of one color or the sub-pixels of two colors onthe base substrate have overlap with the orthographic projection of thechannel of the driving transistor thereof on the base substrate.In one embodiment, as shown in FIG. 16, the orthographic projection of the pixel opening 21 of the first color sub-pixel on the base substrate hasno overlap with either the orthographic projection of the channel 302 of thedriving transistor of the second color sub-pixel on the base substrate or the orthographic projection of the channel 303 of the driving transistor of thethird color sub-pixel on the base substrate. The orthographic projection ofthe pixel opening 22 of the second color sub-pixel on the base substrate hasno overlap with either the orthographic projection of the channel 301 of thedriving transistor of the first color sub-pixel on the base substrate or the orthographic projection of the channel 303 of the driving transistor of thethird color sub-pixel on the base substrate. The orthograph30 ic projection ofthe pixel opening 23 of the third color sub-pixel on the base substrate hasno overlap with either the orthographic projection of the channel 301 of thedriving transistor of the first color sub-pixel on the base substrate or the orthographic projection of the channel 302 of the driving transistor of thesecond color sub-pixel on the base substrate. In such arrangement, theorthographic projection of the channel of the driving transistor of each sub-pixel on the base substrate only has overlap with the orthographic projection of its pixel opening on the base substrate, and has no overlap with theorthographic projection of the pixel opening of other sub-pixels on the base substrate. This is more helpful to reduce the difference in the luminancedecay speed of the organic light emitting elements of each sub-pixel, thereby alleviating the color shift problem of the display substrate. In another embodiment of the present application, the orthographicprojection of the channel of the driving transistor of the first color sub-pixel on the base substrate and the orthographic projection of the channel of the driving transistor of the second color sub-pixel on the base substrate are located within the orthographic projection of the pixel opening corresponding to the second color sub-pixel on the base substrate. The orthographic projection of the channel of the driving transistor of the third color on the base substrate is located within the orthographic projection ofthe pixel opening corresponding to the third color sub-pixel on the base substrate. Such arrangement can prevent the driving transistor of the second color sub-pixel with a larger driving current from increasing the temperatureof the organic light emitting element of the first color sub-pixel too much,which otherwise would cause an excessively fast luminance decay rate anda shortened life of the first color sub-pixel. The problem can be avoided that the luminance decay speed of the first color sub-pixel is significantlydifferent from the luminance decay speed of the second color sub-pixel andthe third color sub-pixel, and the color shift phenomenon of the displaysubstrate can be alleviated.In yet another embodiment of the present application, the orthographic projection of the channel of the driving transistor of the second color sub- pixel on the base substrate has no overlap with the orthographic projectionof the pixel opening corresponding to the first color sub-pixel on the basesubstrate, the orthographic projection of the pixel opening corresponding to the second color sub-pixel on the base substrate, and the orthographic projection of the pixel opening corresponding to the third color sub-pixel onthe base substrate. In such arrangement, the driving transistors of the second color sub-pixels with larger driving currents have less influence on the organic light emitting elements of the respective color sub-pixels, which is more helpful to improve the service life of the display substrate and alleviatethe color shift problem of the display substrate.Further, the orthographic projection of the channel of the drivingtransistor of the first color sub-pixel on the base substrate and the orthographic projection of the channel of the driving transistor of the third color on the base substrate are both located within the orthographicprojection of the pixel opening corresponding to the second color sub-pixel on the base substrate. Alternatively, the orthographic projection of the channel of the driving transistor of the first color sub-pixel on the base substrate is located within the orthographic projection of the pixel openingcorresponding to the second color sub-pixel on the base substrate, and the orthographic projection of the channel of the driving transistor of the third color on the base substrate is located within the orthographic projection ofthe pixel opening corresponding to the third color sub-pixel on the base substrate.In one embodiment, the plurality of sub-pixels are divided into aplurality of pixel groups, each of the pixel groups including a first color sub-pixel, a second color sub-pixel and a third color sub-pixel. At least one ofthe pixel groups includes two rows of sub-pixels arranged along the first direction, wherein one row of sub-pixels arranged along the first direction includes first color sub-pixels and third color sub-pixels which arealternately arranged, and the other row of sub-pixels arranged along the firstdirection includes second color sub-pixels.In one embodiment, as shown in FIG. 16, in at least one pixel group, in the second direction X, the distance from the channel 302 of the drivingtransistor of the second color sub-pixel to the scan signal line Ga1 isdifferent from the distance from the channel 301 of the driving transistor ofthe first color sub-pixel to the scan signal line Ga1. Further, in the seconddirection X, the distance from the channel 303 of the driving transistor ofthe third color sub-pixel to the scan signal line Ga1 is approximately equalto the distance from the channel 301 of the driving transistor of the first color sub-pixel to the scan signal line Ga1. Such arrangement is morehelpful to avoid overlap between the orthographic projections of the channel302 of the driving transistor of the second color sub-pixel and of the pixel opening of the first color sub-pixel on the base substrate.Further, in at least one pixel group, in the second direction X, the distance from the channel 302 of the driving transistor of the second colorsub-pixel to the scan signal line Ga1 is longer than the distance from thechannel 301 of the driving transistor of the first color sub-pixel to the scansignal line Ga1. Such arrangement is more helpful to avoid the problem that the heat generated by the driving transistor of the second color sub-pixel causes the brightness of the second color sub-pixel to attenuate too quicklyand the life span to be shortened.Further, in at least one pixel group, in the second direction X, thedistance from the channel 302 of the driving transistor of the second colorsub-pixel to the scan signal line Ga1 ranges from 1 μm to 60 μm, the distance from the channel 301 of the driving transistor of the first color sub-pixel tothe scan signal line Ga1 ranges from 1 μm to 50 μm, and the distance fromthe channel 301 of the driving transistor of the third color sub-pixel to thescan signal line Ga1 ranges from 1 μm to 50 μm. In the second direction X,the distance from the channel 302 of the driving transistor of the second color sub-pixel to the scan signal line Ga1 is, for example, 1 μm, 10 μm, 20μm, 30 μm, 40 μm, 50 μm, 60 μm, and the distance from the channel 301 ofthe driving transistor of the first color sub-pixel to the scan signal line Ga1and the distance from the channel 301 of the driving transistor of the thirdcolor sub-pixel to the scan signal line Ga1 are, for example, 1 μm, 10 μm, 20 μm, 30μm, 40μm, 50μm,and so on.In one embodiment, referring to FIG. 13, the area of the second polarplate CC12 of the second color sub-pixel is larger than the area of the second polar plate CC11 of the first color sub-pixel, the area of the second polar plate CC12 of the second color sub-pixel is larger than the area of the second polar plate CC13 of the third color sub-pixel. Generally, a width to lengthratio of the channel of the driving transistor of the second color sub-pixel is larger than a width to length ratio of the channel of the driving transistor ofthe first color sub-pixel or of the second color sub-pixel, so as to prevent thephenomenon of insufficient brightness of the second color when the display substrate displays white light at the highest gray level, which wouldotherwise cause the white balance color coordinate of the white light of the highest gray level to shift from the design value. By setting the area of thesecond polar plate CC12 of the second color sub-pixel larger than the areaof the second polar plate CC11 of the first color sub-pixel and the secondpolar plate CC13 of the third color sub-pixel, the second polar plate CC12of the second color sub-pixel can cover the channel of driving transistor. In one embodiment, the areas of the electrode connection structures aredifferent for at least two of the sub-pixels.Further, referring to FIG. 14 and FIG. 15, the electrode connection structure includes a first electrode connection sub-structure 343 and asecond electrode connection sub-structure 353. The areas of the first electrode connection sub-structure 343 and / or the second electrodeconnection sub-structure 353 are different for at least two of the sub-pixels.Further, as shown in FIG. 15, the area of the second electrodeconnection sub-structure 3532 of the second color sub-pixel is smaller than the area of the second electrode connection sub-structure 3531 of the first color sub-pixel, and the area of the second electrode connection sub-structure 3532 of the second color sub-pixel is smaller than the area of thesecond electrode connection sub-structure 3533 of the third color sub-pixel.In one embodiment, referring to FIG. 16, the orthographic projection ofthe first electrode 12 of at least one of the second color sub-pixels on the base substrate has overlap with the orthographic projection of the resetcontrol signal line Rst1 on the base substrate and the orthographic projectionof the scan signal line Ga1 on the base substrate. In one embodiment, the connection structure 341 includes a firstportion and a second portion connected to the first portion, the orthographic projection of the first portion on the base substrate and the orthographicprojection of the protruding part P on the base substrate are located on the same side of the orthographic projection of the main portion Ga11 of the scan signal line on the base substrate. The length of the first portion in thesecond direction X is larger than the length of the protruding portion P in the second direction X. Such arrangement facilitates connecting the end ofthe first portion is connected to the gate electrode of the driving transistor T1.Further, the size of the connection structure 341 in the second direction X ranges from 35 μm to 70 μm. Such arrangement ensures electrical connection the two ends of the connection structure 341 to the gate electrodeof the driving transistor T1 in the first conductive layer 320 and the source and drain regions of the threshold compensation transistor T3 in the active semiconductor layer 310 respectively. In some embodiments, the size of the connection structure 341 in the second direction X is 35 μm, 40 μm, 45 μm,50 μm, 55 μm, 60 μm, 65 μm, 70 μm, and so on.In one embodiment, the size of the first color sub-pixel in the first direction Y ranges from 35 μm to110 μm, and the size of the first color sub-pixel in the second direction X ranges from 20 μm to 60 μm; the size of thesecond color sub-pixel in the first direction Y ranges from 35 μm to 120 μm,and the size of the second color sub-pixel in the second direction X rangesfrom 20 μm to 80 μm; the size of the third color sub-pixel in the first direction Y ranges from 35 μm to 70 μm, and the size of the third color sub-pixel in the second direction X ranges from 20 μm to 60 μm. The size of thesub-pixel in the first direction refers to its maximum size in the firstdirection Y, and the maximum size of the sub-pixel in the first direction Y refers to the maximum size of an overlapping part of the orthographic projection of the pixel opening of the sub-pixel on the base substrate and theorthographic projection of the first electrode on the base substrate in the firstdirection Y. The maximum size of the sub-pixel in the second direction Xrefers to the maximum size of an overlapping part of the orthographicprojection of the pixel opening of the sub-pixel on the base substrate and theorthographic projection of the first electrode on the base substrate in the firstdirection Y. In some examples, the size of the first color sub-pixel in the firstdirection Y is, for example, 35 μm, 45 μm, 55 μm, 65 μm, 75 μm, 85 μm, 95 μm, 105 μm, 110 μm, and so on. The size of the first color sub-pixel in thesecond direction X is, for example, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, and so on. The size of the second color sub-pixel in the first direction Y is, for example, 35 μm, 45 μm, 55 μm, 65 μm, 75 μm,85 μm, 95 μm, 105 μm, 115 μm, 120 μm, and so on. The size of the secondcolor sub-pixel in the second direction X is, for example, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, and so on. The size of the third color sub-pixel in the first direction Y is 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, 65 μm, 70 μm. The size of the third color sub-pixel in the second directionX is, for example, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, and so on. It should be noted that the features described in different embodimentsof the present application can complement each other without conflict. Forexample, in the case of no conflict, the features in the embodiments shownin FIGS. 2 to 10 can also have the same features in the embodiment shownin FIG. 11 and the embodiments shown in FIGS.12 to 16. The features ofthe embodiment shown in FIG. 12 to FIG. 16 can also have the same features in the embodiment shown in FIG. 2 to FIG. 10. An embodiment of the present application further provides a displaypanel, where the display panel includes the display substrate described in any of the foregoing embodiments. The display panel can further include a glass cover plate on the side ofthe display substrate away from the base substrate. An embodiment of the present application further provides a displaydevice, and the display device includes the above-mentioned display panel.The display device can further include a housing in which the display panel can be embedded.The display device in this embodiment can be any product orcomponent with display function, such as an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a vehicle display device, and so on.It should be noted that, in the drawings, the sizes of layers and regionscan be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or intervening layers can be present. In addition, it will be understood that when an element or layer isreferred to as being "under" another element or layer, it can be directly underthe other element, or more than one intervening layer or element can be present. In addition, it will also be understood that when a layer or elementis referred to as being 'between' two layers or elements, it can be the only layer between the two layers or elements, or more than one intervening layeror element can also be present. Like reference numerals indicate like elements throughout.Other implementations of the present disclosure will be apparent tothose skilled in the art from consideration of the specification and practiceof the present disclosure herein. The present disclosure is intended to coverany variations, uses, modification or adaptations of the present disclosure that follow the general principles thereof and include common knowledgeor conventional technical means in the related art that are not disclosed in the present disclosure. The specification and examples are considered as exemplary only, with a true scope and spirit of the present disclosure beingindicated by the following claims.It is to be understood that the present disclosure is not limited to the precise structure described above and shown in the accompanying drawings,and that various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited onlyby the appended claims.

Claims

1. A display substrate comprising a base substrate and a plurality of sub-pixels disposed on the base substrate; wherein the plurality of sub-pixels comprises a plurality of first color sub-pixels, a plurality of second color sub-pixels and a plurality of third color sub-pixels, human eyes are more sensitive to the first color than to the third color, and human eyes are more sensitive to the third color than to the second color; the sub-pixel comprises an organic light emitting element and a pixel circuit for driving the organic light emitting element; the organic light emitting element comprises a first electrode, a second electrode, and an organic light emitting material disposed between the first electrode and the second electrode; the first electrode of the sub-pixel is electrically connected to the pixel circuit; the pixel circuit comprises a driving transistor; the display substrate further comprises an active semiconductor layer and a pixel defining layer, the active semiconductor layer comprises channels and source and drain regions of the driving transistors of the sub- pixels; the pixel defining layer is provided with pixel openings corresponding to the sub-pixels one to one; an orthographic projection of the pixel opening of the first color sub- pixel on the base substrate has no overlap with an orthographic projection of the channel of the driving transistor of the first color sub-pixel on the base substrate, an orthographic projection of the pixel opening of the second color sub-pixel on the base substrate has no overlap with an orthographic projection of the channel of the driving transistor of the second color sub- pixel on the base substrate, an orthographic projection of the pixel opening of the third color sub-pixel on the base substrate has no overlap with an orthographic projection of the channel of the driving transistor of the third color sub-pixel on the base substrate; or, an orthographic projection of the pixel opening of at least one sub-pixel on the base substrate has overlap with an orthographic projection of the channel of the driving transistor thereof on the base substrate, an orthographic projection of the pixel opening of at least one of the second color sub-pixels in a first direction has overlap with an orthographic projection of the pixel opening of the first color sub-pixel in the first direction and an orthographic projection of the pixel opening of the third color sub-pixel in the first direction, and the orthographic projection of the pixel opening of the second color sub-pixel in a second direction has no overlap with either an orthographic projection of the pixel opening of the first color sub-pixel in the second direction or an orthographic projection of the pixel opening of the third color sub-pixel in the second direction, where the first direction intersects with the second direction.

2. The display substrate according to claim 1, wherein the orthographic projection of the pixel opening of the first color sub-pixel on the base substrate has overlap with the orthographic projection of the channel of the driving transistor of the first color sub-pixel on the base substrate, the orthographic projection of the pixel opening of the second color sub-pixel on the base substrate has overlap with the orthographic projection of the channel of the driving transistor of the second color sub-pixel on the base substrate, and the orthographic projection of the pixel opening of the third color sub-pixel on the base substrate has overlap with the orthographic projection of the channel of the driving transistor of the third color sub-pixel on the base substrate.

3. The display substrate according to claim 1, wherein the plurality of sub-pixels are divided into a plurality of pixel groups, and each of the pixel groups comprises a first color sub-pixel, a second color sub-pixel and a third color sub-pixel; at least one of the pixel groups comprises two rows of sub- pixels arranged along the first direction, wherein one row of sub-pixels arranged along the first direction comprises first color sub-pixels and third color sub-pixels which are alternately arranged, and the other row of sub- pixels arranged along the first direction comprises second color sub-pixels.

4. The display substrate according to claim 3, wherein, in at least one of the pixel groups, the orthographic projection of the pixel opening corresponding to each of the sub-pixels on the base substrate has no overlap with an orthographic projection of the gate electrode of the driving transistor of any one of the sub-pixels on the base substrate, or the orthographic projection of the pixel opening corresponding to each of the sub-pixels on the base substrate has an overlapping region with the orthographic projection of the gate electrode of the driving transistor of any one of the sub-pixels on the base substrate, and a ratio of an area of the overlapping region to an area of the gate electrode is not more than 10%.

5. The display substrate according to claim 3, wherein the display substrate is further provided with a plurality of scan signal lines extending along the first direction, the scan signal lines being configured to provide scan signals for the pixel groups; in at least one pixel group, in the second direction, a distance from the channel of the driving transistor of the second color sub-pixel to the scan signal line is different from a distance from the channel of the driving transistor of the first color sub-pixel to the scan signal line.

6. The display substrate according to claim 5, wherein, in at least one pixel group, in the second direction, the distance from the channel of the driving transistor of the second color sub-pixel to the scan signal line is longer than the distance from the channel of the driving transistor of the first color sub-pixel to the scan signal line.

7. The display substrate according to claim 3, wherein the display substrate is further provided with scan signal lines extending along the first direction, the scan signal lines being configured to provide scan signals for the pixel groups; in at least one pixel group, an orthographic projection of the scan signal line in the second direction has overlap with an orthographic projection of the gate electrode of the driving transistor of the sub-pixel in the second direction, where the second direction is perpendicular to the first direction.

8. The display substrate according to claim 3, wherein the display substrate is further provided with scan signal lines extending along the first direction, the scan signal lines being configured to provide scan signals for the pixel groups; the scan signal line comprises a main body portion of the scan signal line and a protruding portion protruding from one side of the main body portion of the scan signal line; the main body portion of the scan signal line comprises a first scan sub-line, a second scan sub-line and a connection part, the first scan sub-line is connected to the second scan sub- line through the connection part, the first scan sub-line is connected to the pixel circuit of the first color sub-pixel, the second scan sub-line is connected to the pixel circuit of the second color sub-pixel, and extension direction of part of the connection part intersects with the extension direction of the first scan sub-line; the pixel circuit comprises a compensation transistor, and the compensation transistor comprises a first gate electrode and a second gate electrode; in the compensation transistor, the first gate electrode is a part of the connection part that overlaps with an orthographic projection of the active semiconductor layer on the base substrate, and the second gate electrode is a part of the protruding portion that overlaps the orthographic projection of the active semiconductor layer on the base substrate.

9. The display substrate according to claim 8, wherein the connection part comprises a first connection sub-part, a second connection sub-part and a third connection sub-part which are connected in sequence, extension direction of the first connection sub-part and the third connection sub-part intersect with extension direction of the first scan sub-line, and extension direction of the second connection sub-part is the same as the extension direction of the first scan sub-line; the first gate electrode is a part of the second connection sub-part that overlaps with the orthographic projection of the active semiconductor layer on the base substrate.

10. The display substrate according to claim 8, wherein the active semiconductor layer comprises a first section, a second section, a third section and a fourth section which are connected in sequence; the second section, the fourth section and the main body portion of the scan signal line extend along the first direction, the first section and the third section extend in the second direction, where the second direction intersects with the first direction; the display substrate further comprises a reset control signal line extending along the first direction and disposed in the same layer as the scan signal line; the pixel circuit comprises a reset transistor, and the reset transistor comprises a gate electrode; the second gate electrode is a part of the protruding portion that overlaps with an orthographic projection of the fourth section on the base substrate, the gate electrode of the reset transistor comprises a part of the reset control signal line that overlaps an orthographic projection of the first section on the base substrate.

11. The display substrate according to claim 8, wherein the pixel circuit further comprises a threshold compensation transistor, the threshold compensation transistor comprises a gate electrode; the display substrate further comprises a connection structure, one end of the connection structure is connected to the gate electrode of the driving transistor, and the other end of the connection structure is connected to source and drain regions of the threshold compensation transistor; the connection structure comprises a first portion and a second portion connected to the first portion, an orthographic projection of the first portion on the base substrate and an orthographic projection of the protruding part on the base substrate are disposed at are located on the same side of an orthographic projection of the main body portion of the scan signal line on the base substrate; a length of the first portion in the second direction is larger than a length of the protruding portion in the second direction.

12. The display substrate according to claim 11, wherein a size of the connection structure in the second direction ranges from 35 μm to 70 μm.

13. The display substrate according to claim 3, wherein the display substrate is further provided with a plurality of scan signal lines and reset control signal lines extending along the first direction, the scan signal lines being configured to provide scan signals for the pixel groups, the reset control signal lines being configured to provide reset control signals for the pixel groups; an orthographic projection of the first electrode of at least one of the second color sub-pixels on the base substrate has overlap with an orthographic projection of the reset control signal line on the base substrate and an orthographic projection of the scan signal line on the base substrate.

14. The display substrate according to claim 1, wherein any one of the orthographic projection of the pixel opening of the first color sub-pixel on the base substrate, the orthographic projection of the pixel opening of the second color sub-pixel on the base substrate or the orthographic projection of the pixel opening of the third color sub-pixel on the base substrate has no overlap with any one of the orthographic projection of the channel of the driving transistor of the first color sub-pixel on the base substrate, the orthographic projection of the channel of the driving transistor of the second color sub-pixel on the base substrate, or the orthographic projection of the channel of the driving transistor of the third color sub-pixel on the base substrate.

15. The display substrate according to claim 14, wherein the display substrate is further provided with scan signal lines, the scan signal lines being configured to provide scan signals for the pixel groups; a distance between the channel of the driving transistor of the sub-pixel and the scan signal line in the second direction ranges from 1 μm to 50 μm..

16. The display substrate according to claim 1, wherein the pixel circuit further comprises a capacitor, and the capacitor comprises a first polar plate and a second polar plate disposed on a side of the first polar plate away from the base substrate; an area of the second polar plate of the second color sub- pixel is larger than an area of the second polar plate of the first color sub- pixel, and the area of the second polar plate of the second color sub-pixel is larger than an area of the second polar plate of the third color sub-pixel.

17. The display substrate according to claim 1, wherein the display substrate further comprises a first power supply line and a second power supply line disposed on a side of the first power supply line away from the base substrate; the first power supply line and the second power supply line are configured to provide a power supply signal for the pixel circuit; the first power supply line is electrically connected to the second power supply line; the second power supply line comprises a first power supply sub-line extending along the first direction and a second power supply sub-line extending along the second direction, the first power supply sub-line intersects with the second power supply sub-line.

18. The display substrate according to claim 1, wherein the pixel circuit further comprises an emission control transistor and an electrode connection structure, and the electrode connection structure electrically connects the first electrode of the sub-pixel to source and drain regions of the emission control transistor; areas of the electrode connection structures of at least two of the sub- pixels are different.

19. The display substrate according to claim 18, wherein the electrode connection structure at least comprises a first electrode connection sub- structure and a second electrode connection sub-structure on a side of the first electrode connection sub-structure away from the base substrate; areas of the first electrode connection sub-structure and / or the second electrode connection sub-structure of at least two of the sub-pixels are different.

20. The display substrate according to claim 1, wherein the display substrate further comprises a shielding line and a reset power supply signal line, the reset power supply signal line being configured to provide a reset power signal for the sub-pixels; the shielding line is electrically connected to the reset power signal line.

21. The display substrate according to any one of claims 1 to 20, wherein a size of the first color sub-pixel in the first direction ranges from 35 μm to 110 μm, and a size of the first color sub-pixel in the second direction ranges from 20 μm to 60 μm; a size of the second color sub-pixel in the first direction ranges from 35 μm to 120 μm, and a size of the second color sub-pixel in the second direction ranges from 20 μm to 80 μm; a size of the third color sub-pixel in the first direction ranges from 35 μm to 70 μm, and a size of the third color sub-pixel in the second direction ranges from 20 μm to 60 μm22. A display panel, comprising the display substrate according to any one of claims 1 to 21.

23. A display device, comprising the display panel according to claim 22.