Tunnel field-effect transistor (TFET) with gate-all-around epitaxial layer

Abstract

The present invention relates to a semiconductor device, particularly relating to Tunnel Field-Effect Transistors (TFETs) integrated with Gate-All-Around (GAA) structures and epitaxial layers. The proposed TFET include a semiconductor substrate, and a channel region (104) formed within the semiconductor substrate. The TFET include a gate dielectric region (108) surrounding the channel region and a gate electrode (110) encircling the gate dielectric region. The TFET further include an epitaxial layer (106) positioned between the channel region (104) and the gate dielectric region (108), where the barrier width at the tunneling interface is determined by the doping concentration of the epitaxial layer (106) and a source region (102) sandwiched within the channel region, where the sandwiched source activate both a line and point tunneling mechanism to improving the rate of tunneling across the source / channel interface.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a field of semiconductor devices,particularly relating to Tunnel Field-Effect Transistors (TFETs) integrated withGate-All-Around (GAA) structures and epitaxial layers.BACKGROUND

[0002] The evolution of semiconductor technology, driven by the pursuit ofsmaller, faster, and more efficient electronic devices, initially focused on Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). However, as devicedimensions were reduced, issues related to Short Channel Effects (SCEs), such asDrain Induced Barrier Lowering (DIBL) and Gate-Induced Drain Leakage(GIDL), became predominant. These effects posed significant challenges to theperformance and reliability of semiconductor devices.

[0003] To address SCEs, researchers turned their attention to Tunnel Field-EffectTransistors (TFETs) based on the Tunneling Transport Mechanism, specificallyBand-to-Band Tunneling (BTBT). While TFETs held promise in mitigating SCEs,they exhibited limitations, including minimal On-state current and ambipolarity,making them less practical compared to MOSFETs with unique dimensions. Inresponse, researchers explored various techniques to overcome these limitations.

[0004] Among the proposed solutions, Gate-All-Around (GAA) structuresemerged as a leading technique to enhance crucial DC / RF characteristics such asON-current (ION), OFF-current (IOFF), current switching ratio, Drain InvolvedBarrier Thinning (DIBT), and Subthreshold Swing (SSAVG). The implementationof GAA structures proved beneficial, yet challenges persists with the tunnellingmechanisms.

[0005] Therefore, there is a possibility of overcoming the limitations of traditionalTFETs, and provide an improved, secured, reliable, and more efficient solution tothe above-stated problem. There is, therefore, a need to provide tunnel field-effecttransistor (TFET) with gate-all-around epitaxial layer.OBJECTS OF THE PRESENT DISCLOSURE

[0006] An object of the present invention is to is to enhance tunnelingmechanisms within Tunnel Field-Effect Transistors (TFETs).

[0007] An object of the present invention is to provide an optimized epitaxiallayer be tween the channel and the gate dielectric region.

[0008] An object of the present invention is to achieve precise control overelectric fields across the channel region and the source-channel junction.

[0009] An object of the present invention is to enable accurate regulation of thetunneling probability at the tunneling interface.

[0010] An object of the present invention is to enhance Radio Frequency (RF)characteristics of the TFET.SUMMARY

[0011] Aspects of the present disclosure relate to field of semiconductor devices,particularly relating to Tunnel Field-Effect Transistors (TFETs) integrated withGate-All-Around (GAA) structures and epitaxial layers. The proposed TFET withGate-All-Around (GAA) structures with epitaxial layers activate both line andpoint tunneling mechanisms, significantly improving the rate of tunneling acrossthe source / channel interface.

[0012] In an aspect, the disclosed TFET may include a semiconductor substrate,and a channel region formed within the semiconductor substrate. The TFETinclude a gate dielectric region surrounding the channel region and a gateelectrode encircling the gate dielectric region. The TFET further include anepitaxial layer positioned between the channel region and the gate dielectricregion, where the barrier width at the tunneling interface is determined by thedoping concentration of the epitaxial layer and a source region sandwiched withinthe channel region, where the sandwiched source activate both a line and pointtunneling mechanism to improving the rate of tunneling across the source / channelinterface.

[0013] In an embodiment, the gate electrode forms a gate-all-around structure,ensuring precise control over the electric field across the channel region and thesource-channel junction.

[0014] In an embodiment, the presence of the epitaxial layer intensifies the impactof the electric field produced by the gate electrode, thereby enhancing deviceperformance and allowing accurate regulation of the tunneling probability at thetunneling interface.

[0015] In an embodiment, the doping concentration of the epitaxial layer isoptimized to manage crucial device parameters, including current switching ratio(CSR), OFF-state current, On-state current, and drain-induced barrier thinning(DIBT).

[0016] In another aspect of the present disclosure, method for fabricating a tunnelfield-effect transistor with gate-all-around epitaxial layer (GAA-Epi-TFET) isdisclosed. The method may involve creating a channel region within asemiconductor substrate; depositing an epitaxial layer onto the channel region;forming a gate dielectric region surrounding the channel region and the epitaxiallayer; depositing a gate electrode around the gate dielectric region; andintroducing a source region within the channel region, ensuring its placementbetween the channel region and activating both line and point tunnelingmechanisms at the source-channel junction.

[0017] In an embodiment, the method may include adjusting the dopingconcentration of the epitaxial layer during the deposition process to optimizedevice performance

[0018] In an embodiment, the semiconductor including the GAA-Epi-TFETexhibit enhanced DC / RF characteristics, including improved transconductance(gm) and cutoff frequency (fT) due to the heightened rate of tunneling at thechannel / source interface.

[0019] In an embodiment, the GAA-Epi-TFET exhibits minimal short channeleffects (SCEs), reduced drain-induced barrier lowering (DIBL), and gate-induceddrain leakage (GIDL) owing to the optimized epitaxial layer and gate-all-aroundstructure.

[0020] Various objects, features, aspects, and advantages of the inventive subjectmatter will become more apparent from the following detailed description ofpreferred embodiments and accompanying drawing figures in which numeralsrepresent like components.BRIEF DESCRIPTION OF DRAWINGS

[0021] The accompanying drawings are included to provide a furtherunderstanding of the present disclosure and are incorporated in and constitute apart of this specification. The drawings illustrate exemplary embodiments of thepresent disclosure and, together with the description, explain the principles of thepresent disclosure. The diagrams are for illustration only, which thus is not alimitation of the present disclosure.

[0022] Similar components and / or features may have the same reference label inthe figures. Further, various components of the same type may be distinguished byfollowing the reference label with a second label that distinguishes among thesimilar components. Suppose only the first reference label is used in thespecification. In that case, the description applies to any similar components withthe same first reference label, irrespective of the second reference label.

[0023] FIG. 1 illustrates a perspective view of the of proposed GAA-Epi-TFET, inaccordance with an embodiment of the present disclosure.

[0024] FIG. 2 illustrates exemplary 3-Dimensional 2-D cut view of GAA-Epi-TFET, in accordance with an embodiment of the present disclosure.

[0025] FIG. 3 illustrates an exemplary method for fabricating a tunnel field-effecttransistor with gate-all-around epitaxial layer, in accordance with an embodimentof the present disclosure.

[0026] FIG. 4 is a graph depicting Comparison of Transfer characteristics ofGAA-Epi-TET with conventional GAA-TFET, in accordance with an embodimentof the present disclosure.

[0027] FIG. 5 is a graph depicting epitaxial layer thickness optimization, inaccordance with an embodiment of the present disclosure.

[0028] FIG. 6 is a graph depicting SSAVG and CSR during optimization ofthickness of epitaxial layer, in accordance with an embodiment of the presentdisclosure.

[0029] FIG. 7 is a graph depicting variation in the concentration of the epitaxiallayer, in accordance with an embodiment of the present disclosure.DETAILED DESCRIPTION

[0030] The following is a detailed description of embodiments of the disclosuredepicted in the accompanying drawings. The embodiments are in such detail as tocommunicate the disclosure. However, the amount of detail offered is not intendedto limit the anticipated variations of embodiments; on the contrary, the intention isto cover all modifications, equivalents, and alternatives falling within the scope ofthe present disclosure as defined by the appended claims.

[0031] In the following description, numerous specific details are set forth inorder to provide a thorough understanding of the embodiments of the presentinvention. It will be apparent to one skilled in the art that embodiments of thepresent invention may be practiced without some of these specific details.

[0032] In the figures, similar components, and / or features may have the samereference label. Further, various components of the same type may bedistinguished by following the reference label with a second label thatdistinguishes among the similar components. If only the first reference label isused in the specification, the description is applicable to any one of the similarcomponents having the same first reference label irrespective of the secondreference label.

[0033] In an aspect, the disclosed TFET may include a semiconductor substrate,and a channel region formed within the semiconductor substrate. The TFETinclude a gate dielectric region surrounding the channel region and a gateelectrode encircling the gate dielectric region. The TFET further include anepitaxial layer positioned between the channel region and the gate dielectricregion, where the barrier width at the tunneling interface is determined by thedoping concentration of the epitaxial layer and a source region sandwiched withinthe channel region, where the sandwiched source activate both a line and pointtunneling mechanism to improving the rate of tunneling across the source / channelinterface.

[0034] In an embodiment, the gate electrode forms a gate-all-around structure,ensuring precise control over the electric field across the channel region and thesource-channel junction.

[0035] In an embodiment, the presence of the epitaxial layer intensifies the impactof the electric field produced by the gate electrode, thereby enhancing deviceperformance and allowing accurate regulation of the tunneling probability at thetunneling interface.

[0036] In an embodiment, the doping concentration of the epitaxial layer isoptimized to manage crucial device parameters, including current switching ratio(CSR), OFF-state current, On-state current, and drain-induced barrier thinning(DIBT).

[0037] In another aspect of the present disclosure, method for fabricating a tunnelfield-effect transistor with gate-all-around epitaxial layer (GAA-Epi-TFET) isdisclosed. The method may involve creating a channel region within asemiconductor substrate; depositing an epitaxial layer onto the channel region;forming a gate dielectric region surrounding the channel region and the epitaxiallayer; depositing a gate electrode around the gate dielectric region; andintroducing a source region within the channel region, ensuring its placementbetween the channel region and activating both line and point tunnelingmechanisms at the source-channel junction.

[0038] In an embodiment, the method may include adjusting the dopingconcentration of the epitaxial layer during the deposition process to optimizedevice performance.

[0039] In an embodiment, the semiconductor including the GAA-Epi-TFETexhibit enhanced DC / RF characteristics, including improved transconductance(gm) and cutoff frequency (fT) due to the heightened rate of tunneling at thechannel / source interface.

[0040] In an embodiment, the GAA-Epi-TFET exhibits minimal short channeleffects (SCEs), reduced drain-induced barrier lowering (DIBL), and gate-induceddrain leakage (GIDL) owing to the optimized epitaxial layer and gate-all-aroundstructure.

[0041] Referring to FIG.1 and FIG. 2, a tunnel field-effect transistor (TFET) withGate-All-Around Epitaxial Layer (GAA-Epi) that are used in semiconductordevices is disclosed. The proposed TFET may include a semiconductor substrate,providing the foundation and support for the entire device. In an example, thechoice of semiconductor material can vary based on the specific requirements ofthe application. The semiconductor material can be either a p-type or n-typesemiconductor or a combination of p and n type semiconductor. The TFET mayinclude a channel region formed within the semiconductor substrate. In anexample, this region is crucial as it acts as the conductive pathway through whichthe charge carriers flow when the transistor is in operation.

[0042] In an embodiment, surrounding the channel region, there may be a gatedielectric region. The gate dielectric region may insulate the gate electrode fromthe channel. It plays a vital role in controlling the flow of current through thechannel by modulating the electric field when a voltage is applied to the gateelectrode. Traditionally, in Field-Effect Transistors (FETs), the gate electrode isplaced on top of the channel region. In contrast, in the described TFET with thegate-all-around structure, the gate electrode completely encircles the gatedielectric region, which itself surrounds the channel region. This arrangementresembles a cylindrical shape, where the gate electrode forms a 360-degree looparound the channel. As a result, the gate electrode has electrical influence over thechannel not just from the top, but from all sides, providing comprehensive controlover the channel's conductive properties.

[0043] In an embodiment, a gate electrode may encircle the gate dielectric region.By applying a voltage to the gate electrode, the conductivity of the channel iscontrolled. In this configuration, the gate electrode surrounds the channel from allsides, making it a gate-all-around structure. This design provides precise controlover the electric field within the channel.

[0044] In an embodiment, the proposed TFET may further include an epitaxiallayer positioned between the channel region and the gate dielectric region. Theepitaxial layer's unique characteristic is that its doping concentration determinesthe barrier width at the tunneling interface. By controlling the dopingconcentration, the width of the barrier through which charge carriers tunnel can beprecisely adjusted. This feature allows fine-tuning of the tunneling process, acrucial aspect of TFET operation. In an example, the epitaxial layer, positionedbetween the gate dielectric and the channel region, acts as a modulating layer. Itsunique characteristic lies in its doping concentration, which directly influences thebarrier width at the tunneling interface. When a voltage is applied to the gateelectrode, it creates an electric field across the epitaxial layer. The dopingconcentration of this layer amplifies the electric field, making it more potent as itpenetrates the channel region.

[0045] Further, the intensified electric field significantly affects the tunnelingprobability at the tunneling interface, which is the boundary between the sourceand the channel. In Tunnel Field-Effect Transistors (TFETs), carriers (electrons orholes) tunnel through this interface to enable current flow. By regulating theelectric field strength precisely, the epitaxial layer optimizes the tunnelingprobability. This accurate control ensures that tunneling occurs efficiently andreliably, allowing for predictable and stable device behavior. Also, the enhancedelectric field, facilitated by the epitaxial layer, reduces the effective tunnelingbarriers for carriers.

[0046] In an illustrative example, by precisely adjusting the doping concentrationof the epitaxial layer, one can influence the energy barriers that carriers (electronsor holes) must overcome to tunnel from the source to the channel and vice versa.Optimizing the doping concentration allows for a balanced approach, it lowers thetunneling barrier for carriers in the ON state, enabling a robust flow of current,while simultaneously raising the barrier in the OFF state, minimizing leakagecurrent. This balance results in an improved CSR, indicating efficient currentswitching capabilities. In practical terms, this means that carriers require lessenergy to tunnel from the source to the channel. Lowering the tunneling barriersleads to improved ON-current (ION) characteristics, enabling the TFET to operatemore efficiently with lower applied voltages.

[0047] In an illustrative example, in the fabricated GAA-Epi-TFET, theconcentration of the Epitaxial layer is varied to optimize the device performancein-terms of DC parameters such as current switching ratio (CSR), OFF-state, Onstatecurrent and drain induced barrier thinning (DIBT). The optimized devicemetrics are shown in the table-1 below, and the Optimized transfer characteristicsare shown in the FIG.4- FIG.7.Parameter ValueThickness of Silicon channel 05 nmLength of the channel 60 nmThickness of dielectric oxide 02 nmDoping conc. of source 1 x 1020 cm-3Doping conc. of channel 1 x 1016 cm-3Doping conc. of Drain 5 x 1018 cm-3Doping conc. of Epi-layer 1 x 1018cm-3Metal (Gate) work function 4.1 eVTotal dimension of the device 90 nmTable 1: Specifications of the device

[0048] FIG.4 illustrates a comparison between the transfer characteristics of theGAA-Epi-TFET and the conventional GAA-TFET; FIG. 5 depicts theoptimization of epitaxial layer thickness; FIG. 6 displays the SSAVG and CSRvariation during epitaxial layer thickness optimization; and FIG. 7 presents thevariation in epitaxial layer concentration.

[0049] In TFETs, the epitaxial layer serves to create a tunnel junction, enablingelectrons to tunnel through a narrow barrier and into the semiconductor material'sconduction band. This process creates a significant electric field across the barrier,facilitating rapid transistor switching. The optimization process clearly showedthat reducing the epitaxial layer thickness from 3 nm to 1 nm led to improved DCcharacteristics of the device.

[0050] The proposed GAA-Epi-TFET demonstrates substantial enhancements inDC characteristics when compared to the conventional GAA-TFET, as evident inFIG. 4. In a non-limiting example, the proposed device exhibited a significantlyimproved current switching ratio due to enhanced tunneling probability. For anexample, the drain-induced barrier thinning (DIBT) reduced from 234 mV / V inthe conventional GAA-TFET to 88 mV / V in the proposed device. Additionally,SSAVG decreased from 61 mV / Dec in GAA-TFET to 31.2 mV / Dec in theoptimized GAA-Epi-TFET, as shown in FIG. 5, indicating improved performance.FIG. 6 demonstrates that reducing the epitaxial layer thickness from 3 to 1 nm ledto a decrease in SSAVG from 37.3 to 28.2 mV / Decade and an increase inION / IOFF ratio from 3 x 10^13 to 7.5 x 10^13, highlighting enhanced deviceefficiency. Moreover, the epitaxial layer's concentration played a crucial role incontrolling the tunnel barrier width, as depicted in FIG. 7. Increasing the epitaxiallayer concentration from 1 x 10^16 to 1 x 10^18 cm^-3 led to a tenfold reductionin OFF-state leakage current. This reduction occurred due to the flaring of thetunnel barrier width at the D / C interface, attributed to variations in the epitaxiallayer concentration. In conclusion, optimizing the epitaxial layer thickness andconcentration stands as a pivotal factor in designing high-performance, lowleakagecurrent TFETs.

[0051] Further as the proposed TFET include a source region within the channelregion, that is strategically sandwiched. This specific placement is significantbecause it activates both line and point tunneling mechanisms at thesource / channel interface. Line tunneling refers to tunneling along the length of thesource, while point tunneling involves tunneling through specific points in thesource region. Activating both mechanisms significantly enhances the rate oftunneling across the source / channel interface. This enhancement is vital forimproving the overall efficiency and performance of the TFET.

[0052] In another aspect of the present disclosure, a method for fabricating atunnel field-effect transistor with gate-all-around epitaxial layer is disclosed. Theproposed method may involve at step 302, creating a channel region within asemiconductor substrate. For an instance, the channel region is the pathwaythrough which charge carriers flow when the TFET is in operation. Creating thisregion involves defining a specific area within the semiconductor substrate.

[0053] The method may involve at step 304, depositing an epitaxial layer onto thechannel region. The epitaxial layer is deposited on the channel region to influencethe tunneling barrier characteristics at the source-channel interface. In an example,the doping concentration of the epitaxial layer directly impacts the tunnelingprobability and, subsequently, the device's performance. By depositing theepitaxial layer, one have a controlled platform to fine-tune the tunnelingprocesses.

[0054] The method may involve at step 306, forming a gate dielectric regionsurrounding the channel region and the epitaxial layer. The gate dielectric regionprovides electrical insulation between the gate electrode and the channel, allowingfor the controlled modulation of current flow.

[0055] The method at step may involve at step 308, depositing a gate electrodearound the gate dielectric region. The gate electrode, encircling the gate dielectricregion, generates an electric field within the channel region when a voltage isapplied. The gate electrode's configuration as a gate-all-around structure ensuresuniform and precise control over the electric field across the channel. Thisuniformity is crucial for stable and efficient device operation.

[0056] The method at step may involve at 310, introducing a source region withinthe channel region, ensuring its placement between the channel region andactivating both line and point tunneling mechanisms at the source-channeljunction. The source region, placed within the channel, activates both line andpoint tunneling mechanisms, enabling efficient carrier tunneling. In an example,by activating these tunneling mechanisms enhances the tunneling probability,ensuring swift carrier transport between the source and the channel. This is vitalfor achieving high device performance.

[0057] In an embodiment, the method may include adjusting the dopingconcentration of the epitaxial layer during the deposition process to optimizedevice performance. By adjusting the doping concentration of the epitaxial layer,engineers can precisely control the tunneling barrier width and overall devicecharacteristics. Further, Fine-tuning the doping concentration allows foroptimization of critical device parameters such as current switching ratio, OFFstatecurrent, ON-state current, and drain-induced barrier thinning. Thisoptimization ensures the TFET operates efficiently and reliably in variousconditions and applications.

[0058] Thus, by introducing the optimized epitaxial layer between the channeland the gate dielectric region enhance the mobility of charge carriers, leading tothe creation of a novel structure termed GAA-Epi-TFET. The proposed designcovers the source entirely from all directions within the channel, thereby furtherimproving the rate of tunneling at the channel / source interface.

[0059] The integration of these advancements results in substantial improvementsin Radio Frequency (RF) characteristics, including enhanced transconductance(gm) and cutoff frequency (fT). Further, by sandwiching the source region insidethe channel activate both line and point tunneling mechanisms, significantlyenhancing the rate of tunneling across the source / channel interface.

[0060] Thus, the proposed GAA-Epi-TFET address the limitations of traditionalTFETs, paving the way for a new era in semiconductor technology. Thedevelopment of GAA-Epi-TFET not only improved tunneling mechanisms butalso revolutionized the RF characteristics, marking a significant advancement inthe realm of high-performance electronic devices.

[0061] The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. As usedherein, for example, the singular forms "a," "an," and "the" are intended to includethe plural forms as well, unless the context clearly indicates otherwise. It will befurther understood that the terms "contains", "containing", "includes", "including,""comprises", and / or "comprising," and variations thereof, when used in thisspecification, specify the presence of stated features, integers, steps, operations,elements, and / or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements, components, and / orgroups thereof.

[0062] Terms of orientation are used herein merely for purposes of conventionand referencing and are not to be construed as limiting. However, it is recognizedthese terms could be used with reference to an operator or user. Accordingly, nolimitations are implied or to be inferred. Also, if used herein, the terms "coupled"or "coupled to" or "connected" or "connected to" or "attached" or "attached to"may indicate establishing either a direct or indirect connection, and are not limitedto either unless expressly referenced as such.

[0063] While the disclosure has described several exemplary embodiments, it willbe understood by those skilled in the art that various changes can be made, andequivalents can be substituted for elements thereof, without departing from thespirit and scope of the invention. In addition, many modifications will beappreciated by those skilled in the art to adapt a particular instrument, situation, ormaterial to embodiments of the disclosure without departing from the essentialscope thereof.

[0064] Therefore, it is intended that the invention not be limited to the particularembodiments disclosed, or to the best mode contemplated for carrying out thisinvention, but that the invention will include all embodiments falling within thescope of the appended claims. Moreover, reference in the appended claims to anapparatus or system or a component of an apparatus or system being adapted to,arranged to, capable of, configured to, enabled to, operable to, or operative toperform a particular function encompasses that apparatus, system, or component,whether or not it or that particular function is activated, turned on, or unlocked, aslong as that apparatus, system, or component is so adapted, arranged, capable,configured, enabled, operable, or operative.ADVANTAGES OF THE INVENTION

[0065] The proposed invention provides a GAA-Epi-TFET exhibits enhanced DCcharacteristics, including a higher current switching ratio (CSR), lower OFF-statecurrent (IOFF), and superior ON-state current (ION).

[0066] The proposed invention provides a GAA-Epi-TFET that incorporatesepitaxial layer, along with the gate-all-around structure, that enhances thetunneling probability at the source-channel interface.

[0067] The proposed invention provides a gate-all-around configuration thateffectively mitigates short channel effects like Drain Induced Barrier Lowering(DIBL) and Gate-Induced Drain Leakage (GIDL).

[0068] The proposed invention reduces OFF-state current and improved tunnelingthat lead to enhanced energy efficiency.

[0069] The proposed invention provides a GAA-Epi-TFET that generates largeelectric field across the tunnel junction that facilitates rapid electron tunneling,enabling high-speed switching.

Claims

1. A tunnel field-effect transistor (TFET) with Gate-All-Around Epitaxial Layer (GAA-Epi), comprising: a semiconductor substrate; a channel region (104) formed within the semiconductor substrate; a gate dielectric region (108) surrounding the channel region; a gate electrode (110) encircling the gate dielectric region; an epitaxial layer (106) positioned between the channel region (104) and the gate dielectric region, wherein the barrier width at the tunneling interface is determined by the doping concentration of the epitaxial layer; and a source region (102) sandwiched within the channel region, wherein the sandwiched source activate both a line and point tunneling mechanism to improving the rate of tunneling across the at least one of a source interface and a channel interface.

2. The TFET as claimed in claim 1, wherein the gate electrode (110) forms a gate-all-around structure, ensuring precise control over the electric field across the channel region (104) and the source-channel junction.

3. The TFET as claimed in claim 1, wherein the presence of the epitaxial layer (106) intensifies the impact of the electric field produced by the gate electrode, thereby enhancing device performance and allowing accurate regulation of the tunneling probability at the tunneling interface.

4. The TFET as claimed in claim 1, wherein the doping concentration of the epitaxial layer (106) is optimized to manage crucial device parameters, including current switching ratio (CSR), OFF-state current, On-state current, and draininduced barrier thinning (DIBT).

5. A method for fabricating a tunnel field-effect transistor with gate-allaround epitaxial layer (106) (GAA-Epi-TFET), comprising the steps of: creating a channel region (104) within a semiconductor substrate; depositing an epitaxial layer (106) onto the channel region; forming a gate dielectric region (108) surrounding the channel region (104) and the epitaxial layer; depositing a gate electrode (110) around the gate dielectric region; introducing a source region within the channel region, ensuring its placement between the channel region (104) and activating both line and point tunneling mechanisms at the source-channel junction.

6. The method as claimed in claim 5, further comprising the step of adjusting the doping concentration of the epitaxial layer (106) during the deposition process to optimize device performance.

7. A semiconductor device comprising the GAA-Epi-TFET as claimed in claim 1, wherein the semiconductor exhibit enhanced DC / RF characteristics, including improved transconductance (gm) and cutoff frequency (fT) due to the heightened rate of tunneling at the channel / source interface.

8. The semiconductor device as claimed in claim 7, wherein the GAA-Epi-TFET exhibits minimal short channel effects (SCEs), reduced drain-induced barrier lowering (DIBL), and gate-induced drain leakage (GIDL) owing to the optimized epitaxial layer (106) and gate-all-around structure.

9. The semiconductor device as claimed in claim 7, wherein the semiconductor material comprises at least one of a P-type semiconductor and a N type semiconductor.

Images