Integration of RacEr GPGPU FPGA to Wolfram Mathematica for High-Performance Computing

Abstract

Integration of RacEr GPGPU FPGA to Wolfram Mathematica for High-Performance Computing The present invention (100) presents a hardware-accelerated computing framework that enhances floating-point operations within Wolfram Mathematica (101) by integrating RacEr GPGPU FPGA technology (115). Traditional CPU-based execution struggles with latency and inefficiencies in complex mathematical computations, while GPUs provide parallelism but lack customization for specialized workloads. The proposed system introduces a custom FPGA-based floating-point accelerator, offloading computationally intensive tasks from Mathematica (101) to RacEr GPGPU FPGA hardware (115). Through a high-speed PCIe communication and a C-based API (104), users can seamlessly invoke FPGA-accelerated computations directly from Mathematica. The system (100) reduces execution time, and optimizes memory usage, making it particularly valuable for scientific simulations, artificial intelligence model training, financial analysis, and bioinformatics computations. By bridging the gap between symbolic computation and FPGA-based high-performance processing, the present invention offers an efficient, scalable solution for real-time, low-latency execution in complex mathematical modeling. FIG. 1

Description

FIELD OF THE INVENTION

[0001] The present invention relates to hardware-accelerated computing systemsdesigned to optimize floating-point operations in Wolfram Mathematica.Specifically, it integrates RacEr GPGPU FPGA (Field-Programmable Gate Array)technology to offload computationally intensive floating-point operations fromtraditional CPUs to a parallel processing framework, enhancing performance inscientific computing, artificial intelligence, financial modeling, and numericalsimulations.BACKGROUND OF THE INVENTION

[0002] Wolfram Mathematica is widely used in engineering, financial modeling,scientific research, and artificial intelligence for symbolic computation, numericalanalysis, and data visualization. However, its execution of floating-point operationson conventional CPU-based architectures suffers from high latency andinefficiencies, particularly when processing large-scale mathematical models.While GPUs offer better parallelization, their fixed architectures limitcustomization for domain-specific workloads, requiring significant reprogrammingin CUDA or OpenCL to optimize mathematical functions. This complexity hindersthe seamless integration of high-performance computing solutions withMathematica's computational framework.

[0003] The RacEr GPGPU FPGA architecture addresses these challenges by offeringa parallel computing solution, allowing direct offloading of floating-pointoperations from Wolfram Mathematica to a customized RacEr GPGPU FPGAexecution pipeline. Unlike GPUs, which have rigid hardware constraints, RacErGPGPU FPGA technology enables custom precision optimization, includingsingle-precision, and double-precision floating-point operations tailored to specificcomputational demands. This approach ensures low-latency execution, improvedpower efficiency, and scalable performance, benefiting scientific simulations, AImodel training, financial modeling, and cryptographic computations.

[0004] Document IN202411010483 discloses System Using Polynomials on FieldProgrammable Gate Array (FPGA). The present disclosure discloses a system(102) using polynomials on a Field Programmable Gate Array (FPGA), comprisinga polynomial-based encryption module (104) for transforming plain text into ciphertext using key polynomials, a polynomial-based decryption module (106) using theNewton-Raphson to decrypt cipher text and recover the original plain text and acoding and implementation module (108) for performing floating-point operations,including addition, subtraction, multiplication, and division of mantissa andexponential formats.

[0005] Document US11120188B2 discloses FPGA virtualization. An FPGAvirtualization platform including a network controller configured to provide aninterface to an external network; a static logic section coupled to the networkcontroller; and one or more reconfigurable regions each having a virtualized fieldprogrammable gate array FPGA) that includes a wrapper and a user design.

[0006] Document US11175957B1 discloses Hardware accelerator for executing acomputation task. The present disclosure relates to a hardware accelerator forexecuting a computation task composed of a set of operations. The hardwareaccelerator comprises a controller and a set of computation units. Each computationunit of the set of computation units is configured to receive input data of anoperation of the set of operations and to perform the operation, wherein the inputdata is represented with a distinct bit length associated with each computation unit.The controller is configured to receive the input data represented with a certain bitlength of the bit lengths and to select one of the set of computation units that candeliver a valid result and that is associated with a bit length smaller than or equalto the certain bit length.

[0007] Document IN202121003639 discloses FPGA Implementation of Low LatencyArchitecture of XGBoost for Inference and Method Therefor. Variousembodiments disclosed herein provides method and system for low latency FPGAbased system for inference such as recommendation models. Conventional modelsfor inference have high latency and low throughput in decision makingmodels / processes. The disclosed method and system exploit parallelism inprocessing of XGB models and hence enables minimum possible latency andmaximum possible throughput. Additionally, the disclosed system uses a trainedmodel that is (re)trained using only those features which the model had used duringtraining, remaining features are discarded during retraining of the model. The useof such selected set of features thus leads to reduction in the size of digital circuitsignificantly for the hardware implementation, thereby greatly enhancing thesystem performance.

[0008] Document IN806 / KOL / 2015 discloses System and Method for Dynamic PartialReconfiguration of Circuits Mapped or Configured on FPGA Platform. The presentinvention discloses a system for dynamically modifying / configuring circuitsmapped on field-programmable gate array (FPGA) platform. The present systemcomprises a FPGA platform having a static means for processing Dynamic PartialReconfiguration (DPR) file for modifying / configuring the circuits mapped on theFPGA platform in online condition, and a dynamic means having multipledynamically reconfigurable modules to facilitate flexibility and upgradability in themodification / configuration of the circuits by involving smaller sized DPR files inthe mapped circuits. The present system also includes a communication interfacefor establishing operative communication with the FPGA platform with remoteuser's computing platform for transferring the said smaller sized DPR file to saidFPGA platform.

[0009] In view of the foregoing, the present invention significantly reduces executiontime, enhances computational efficiency, and enables high-speed floating-pointprocessing, making it an essential tool for high-performance computingapplications.SUMMARY OF THE INVENTION

[0010] To address the foregoing problems, in whole or in part, and / or other problemsthat may have been observed by persons skilled in the art, the present disclosureprovides compositions and methods as described by way of example as set forthbelow.

[0011] The principal object of the present invention is to develop an efficienthardware-accelerated computing system that enhances the execution of floating-point operations in Wolfram Mathematica using RacEr GPGPU FPGA hardwareacceleration.

[0012] Another object of the invention is to develop a system using RacEr GPGPUFPGA to offload computationally intensive operations from general-purpose CPUsto optimized FPGA-based hardware.

[0013] Another object of the invention is to optimize execution time by enablingparallel floating-point computation with reduced power consumption and lowerlatency for real-time processing.

[0014] Another object of the invention is to establish a PCIe communication bridgeallowing direct data exchange between Wolfram Mathematica and RacEr GPGPUFPGA hardware.

[0015] Another object of the invention is to provide custom precision options (single-precision, and double-precision) for scientific and financial computations.

[0016] Another object of the invention is to implement efficient memory allocationand retrieval mechanisms, reducing computational bottlenecks and improving datatransfer rates.

[0017] Another object of the invention is to enable Mathematica API calls toeffortlessly invoke RacEr GPGPU FPGA execution, removing manual interventionin computational acceleration.

[0018] Another object of the invention is to support high-speed execution in domainssuch as scientific computing, AI model training, financial analysis, andcryptographic simulations.

[0019] In view of the foregoing, the present invention provides a ComputationalSystem for Hardware-Accelerated Floating-Point Operations, comprises a RacErGPGPU FPGA module optimized for parallel floating-point computations; a PCIe-based communication enabling direct data transfer between the RacEr GPGPUFPGA module and Wolfram Mathematica; a C-based API configured for managingmemory allocation, execution control, and seamless computation offloading fromMathematica to the RacEr GPGPU FPGA module; and a high-speed executionpipeline, allowing integration of RacEr GPGPU FPGA floating-point operationswithin Mathematica's computational framework, wherein said system reduceslatency, improves precision, and enhances efficiency for applications in financialmodeling, scientific computing, and artificial intelligence.

[0020] In another aspect of the invention, the RacEr GPGPU FPGA module supportsmixed-precision floating-point computation, including single-precision, anddouble-precision operations.

[0021] In another aspect, the memory allocation, data transfers, and tile group-sharedmemory are managed via RacEr_mc_device_malloc andRacEr_mc_device_memcpy API functions to ensure efficient execution offloating-point computations across multiple cores.

[0022] In another aspect, the PCIe communication is tuned for high-speed dataexchange, reducing computation bottlenecks between Wolfram Mathematica andthe RacEr GPGPU FPGA.

[0023] In another aspect, automated result visualization tools within Mathematicadynamically process and graph RacEr GPGPU FPGA results in real time.

[0024] In view of the foregoing, the present invention provides a Method for Off-loading Floating-Point Computations Using RacEr GPGPU FPGA, comprises initiatinga computational task within Wolfram Mathematica that requires floating-point operations; communicating data between Mathematica and the RacEr GPGPU FPGAvia PCIe; executing floating-point operations on the RacEr GPGPU FPGA's optimized computation module; and retrieving results seamlessly into Mathematica forfurther analysis and visualization, wherein the method optimizes execution time,reduces power consumption, and enhances real-time processing for data-intensiveapplications.

[0025] In another aspect, the RacEr GPGPU FPGA implements an optimized CUDAlite execution model, ensuring efficient parallelism across tile group processingcores.

[0026] In another aspect, a FIFO-based PCIe communication mechanism facilitatessynchronized data exchange between the host system and RacEr GPGPU FPGAhardware.

[0027] In another aspect, the RacEr manycore runtime framework employs a bulksynchronous processing model to optimize floating-point operations acrossmultiple FPGA cores.

[0028] In another aspect, the RacEr GPGPU FPGA incorporates dynamic executionscheduling, ensuring adaptive workload distribution based on input complexity.

[0029] Additional features of the invention will be or will become apparent to one withskill in the art upon examination of the following figures and detailed description.It is intended that all such additional features and advantages be included withinthis description, be within the scope of the invention, and be protected by theaccompanying claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Having thus described the subject matter of the present invention in generalterms, reference will now be made to the accompanying drawings, which are notnecessarily drawn to scale, and wherein:

[0031] Figure 1 illustrates Wolfram Mathematica and Alveo U250 data center cardconnection through PCIe, in accordance with an embodiment of the presentinvention;

[0032] Figure 2 illustrates CUDA-Lite Architecture, in accordance with anembodiment of the present invention;

[0033] Figure 3 illustrates compilation and execution pipeline for integrating RacErGPGPU FPGA with Wolfram API, in accordance with an embodiment of thepresent invention;

[0034] Figure 4 illustrates interface for communicating with the Manycore, inaccordance with an embodiment of the present invention;

[0035] Figure 5 illustrates RacEr GPGPU FPGA-Mathematica System DesignArchitecture, in accordance with an embodiment of the present invention;

[0036] Figure 6 illustrates RacEr GPU Architecture, in accordance with anembodiment of the present invention;

[0037] Skilled artisans will appreciate that elements in the drawings are illustrated forsimplicity and may not have necessarily been drawn to scale. Furthermore, in termsof the construction of the device, one or more components of the device may havebeen represented in the drawings by conventional symbols, and the drawings mayshow only those specific details that are pertinent to understanding theembodiments of the present invention so as not to obscure the drawings with detailsthat will be readily apparent to those of ordinary skill in the art having the benefitof the description herein.DETAILED DESCRIPTION OF THE INVENTION

[0038] The subject matter of the present invention now will be described more fullyhereinafter with reference to the accompanying drawings, in which some, but notall embodiments of the subject matter of the present invention are shown. Likenumbers refer to like elements throughout. The subject matter of the presentinvention may be embodied in many different forms and should not be construedas limited to the embodiments set forth herein; rather, these embodiments areprovided so that this disclosure will satisfy applicable legal requirements. Indeed,many modifications and other embodiments of the subject matter of the presentinvention set forth herein will come to mind to one skilled in the art to which thesubject matter of the present invention pertains having the benefit of the teachingspresented in the foregoing descriptions and the associated drawings. Allillustrations of the drawings are for the purpose of describing selected versions ofthe present invention and are not intended to limit the scope of the presentinvention. Therefore, it is to be understood that the subject matter of the presentinvention is not to be limited to the specific embodiments disclosed and thatmodifications and other embodiments are intended to be included within the scopeof the appended claims.

[0039] As a preliminary matter, it will readily be understood by one having ordinaryskill in the relevant art that the present disclosure has broad utility and application.As should be understood, any embodiment may incorporate only one or a pluralityof the above-disclosed aspects of the disclosure and may further incorporate onlyone or a plurality of the above-disclosed features. Furthermore, any embodimentdiscussed and identified as being "preferred" is considered to be part of a best modecontemplated for carrying out the embodiments of the present disclosure. Otherembodiments also may be discussed for additional illustrative purposes inproviding a full and enabling disclosure. Moreover, many embodiments, such asadaptations, variations, modifications, and equivalent arrangements, will beimplicitly disclosed by the embodiments described herein and fall within the scopeof the present disclosure.

[0040] Accordingly, while embodiments are described herein in detail in relation toone or more embodiments, it is to be understood that this disclosure is illustrativeand example of the present disclosure and are made merely for the purposes ofproviding a full and enabling disclosure. The detailed disclosure herein of one ormore embodiments is not intended, nor is to be construed, to limit the scope ofpatent protection afforded in any claim of a patent issuing here from, which scopeis to be defined by the claims and the equivalents thereof. It is not intended that thescope of patent protection be defined by reading into any claim a limitation foundherein that does not explicitly appear in the claim itself.

[0041] Thus, for example, any sequence(s) and / or temporal order of steps of variousprocesses or methods that are described herein are illustrative and not restrictive.Accordingly, it should be understood that, although steps of various processes ormethods may be shown and described as being in a sequence or temporal order, thesteps of any such processes or methods are not limited to being carried out in anyparticular sequence or order, absent an indication otherwise. Indeed, the steps insuch processes or methods generally may be carried out in various differentsequences and orders while still falling within the scope of the present invention.Accordingly, it is intended that the scope of patent protection is to be defined bythe issued claim(s) rather than the description set forth herein.

[0042] Additionally, it is important to note that each term used herein refers to thatwhich an ordinary artisan would understand such term to mean based on thecontextual use of such term herein. To the extent that the meaning of a term usedherein - as understood by the ordinary artisan based on the contextual use of suchterm - differs in any way from any particular dictionary definition of such term, itis intended that the meaning of the term as understood by the ordinary artisanshould prevail.

[0043] Furthermore, it is important to note that, as used herein, "a" and "an" eachgenerally denotes "at least one", but does not exclude a plurality unless thecontextual use dictates otherwise. When used herein to join a list of items, "or"denotes "at least one of the items", but does not exclude a plurality of items of thelist. Finally, when used herein to join a list of items, "and" denotes "all of the itemsof the list".

[0044] In an embodiment of the present invention, the present invention provides aComputational System for Hardware-Accelerated Floating-Point Operations (100),comprises a RacEr GPGPU FPGA module (115) optimized for parallel floating-point computations; a PCIe-based communication enabling direct data transferbetween the RacEr GPGPU FPGA module (115) and Wolfram Mathematica (101);a C-based API (104) configured for managing memory allocation, executioncontrol, and seamless computation offloading from Mathematica (101) to theRacEr GPGPU FPGA module(115); and a high-speed execution pipeline, allowingintegration of RacEr GPGPU FPGA (115) floating-point operations withinMathematica's (101) computational framework, wherein said system (100) reduceslatency, improves precision, and enhances efficiency for applications in financialmodeling, scientific computing, and artificial intelligence.

[0045] In an embodiment of the present invention, the RacEr GPGPU FPGA module(115) supports mixed-precision floating-point computation, including single-precision, and double-precision operations. Memory allocation, data transfers, andtile group-shared memory are managed via RacEr_mc_device_malloc andRacEr_mc_device_memcpy API functions to ensure efficient execution offloating-point computations across multiple cores. The PCIe communication istuned for high-speed data exchange, reducing computation bottlenecks betweenWolfram Mathematica and the RacEr GPGPU FPGA. Automated resultvisualization tools within Mathematica dynamically process and graph RacErGPGPU FPGA results in real time.

[0046] In an embodiment of the present invention, the present invention provides aMethod for Offloading Floating-Point Computations Using RacEr GPGPU FPGA(100), comprises initiating a computational task within Wolfram Mathematica(101) that requires floating-point operations; communicating data betweenMathematica (101) and the RacEr GPGPU FPGA (115) via PCIe (109); executingfloating-point operations on the RacEr GPGPU FPGA's optimized computationmodule; and retrieving results seamlessly into Mathematica for further analysis andvisualization, wherein the method optimizes execution time, reduces powerconsumption, and enhances real-time processing for data-intensive applications.

[0047] In an embodiment of the present invention, the RacEr GPGPU FPGAimplements an optimized CUDA-lite execution model, ensuring efficientparallelism across tile group processing cores. A FIFO-based PCIe communicationmechanism facilitates synchronized data exchange between the host system andRacEr GPGPU FPGA hardware. The RacEr manycore runtime framework employsa bulk synchronous processing model to optimize floating-point operations acrossmultiple FPGA cores. The RacEr GPGPU FPGA incorporates dynamic executionscheduling, ensuring adaptive workload distribution based on input complexity.

[0048] Figure 1 (100) illustrates Wolfram Mathematica and Alveo U250 data centercard connection through PCIe, in accordance with an embodiment of the presentinvention. The Host Processor (108) contains RAM (102), secondary storage (105),and software (118) components that specifically support Wolfram Mathematica'smath-function computation (101), with a wrapper (103), custom API calls (104),and a custom GPGPU kernel (106) that facilitate the Wolfram- RacEr GPGPUinterface (107). On the ALVEO U250 Data Center Accelerator Card (117), thesystem features an FPGA fabric (114) equipped with a PCIe controller, customRacEr GPGPU interface (110), on-board memory (111), and RacEr GPGPU (115),where the hardware accelerator (113) and internal memory (112) enable parallelfloating-point computations. The PCIe Bus (109) plays a vital role in facilitatinghigh-speed data exchange between Host Processor (108) and the accelerator card(117), ensuring seamless execution of floating-point operations directly on thededicated RacEr GPGPU FPGA hardware for optimized performance.

[0049] In accordance with an embodiment of the present invention, Figure 2 illustratesCUDA-Lite Architecture. The Tile Group-Shared Memory framework in RacErGPGPU FPGA provides a structured approach to efficient memory access,analogous to CUDA's hierarchical memory model. In CUDA, threads interact withmemory through private registers, block-shared memory, and global memory,relying on caches to optimize performance. RacEr follows a similar strategy,incorporating three primary memory types: private data memory, which isexclusive to each core; tile group-shared memory, which is collectively accessibleby all nodes within a tile group; and DRAM banks, strategically placed at the baseof each column for efficient data retrieval. This architecture enables remote loadand store operations across the manycore network, significantly reducing latencydue to the physical proximity of the processors. RacEr's hardware efficientlymanages memory distribution through optimized hashing mechanisms, ensuringhigh-speed data access while developers can allocate shared memory using specificmacros.

[0050] The Thread Loops with Nested Loops approach optimizes the execution ofkernel code by structuring computations within nested loops that iterate over blockdimensions. Instead of using conventional thread index variables like threadIdx.x,the system replaces them with loop counters. The distribution of threads per coreis precisely calculated based on the ratio of block size to tile group size, ensuringefficient workload allocation and reducing idle cycles. RacEr enforces threadsynchronization within a core by employing a sequential threadloop executionmodel, which inherently ensures synchronization between executing threads. Thethreadloop functions as an implicit barrier, meaning that before a thread pauses, itmust complete its current execution phase, and all threads must collectively reachthe synchronization point before continuing. When a synchronization primitivesuch as RacEr_tile_group_barrier appears within a threadloop, RacErautomatically splits the loop into two distinct segments, one before synchronizationand one after synchronization. This loop division mechanism acts as an implicitbarrier, ensuring that all threads within a tile group reach the synchronizationcheckpoint before proceeding to subsequent computations. In AdvancedSynchronization in Complex Control Flow, RacEr implements a structuredapproach to managing dependencies while maintaining parallel executionefficiency in control structures such as loops and conditionals. This method ensuressynchronization points are accurately handled, preventing executioninconsistencies in CUDA-like code. Inspired by MCUDA techniques, RacErdynamically resolves synchronization conflicts by adapting control flowmechanisms to parallel computing environments, allowing computations toproceed without compromising efficiency.

[0051] The transformation of thread loops into while loops involve restructuring theexecution process by converting for loops into while loops while carefullyextracting initialization and conditions. To maintain synchronization during thistransformation, a FIFO queue S is introduced, which systematically managessynchronization statements. The transformation process begins with theinitialization phase, where an empty FIFO queue S is created to managesynchronization points efficiently. All synchronization statements, such assyncthreads(), are identified and enqueued into S for orderly processing. Next, inthe iterative processing phase, synchronization points are systematically dequeuedand analysed. If a synchronization statement Si is found outside a thread loop, theenclosing scope is split into three segments: pre-synchronization thread loop, thesynchronization statement itself, and post-synchronization thread loop to maintainexecution order. If Si exists inside a thread loop, loop fission is applied to dividethe loop at Si, ensuring accurate synchronization handling. The Abstract SyntaxTree (AST) is then reconstructed to reflect these modifications, preservingexecution consistency.

[0052] Thread Synchronization and Memory Allocation plays a crucial role in ensuringcorrect execution and efficiency across multiple thread loops. Thread-privatevariables must persist throughout all thread loops they participate in to maintainsynchronization accuracy. To manage replication effectively, RacEr employsUniversal Replication, where thread-specific variables are stored in a 3D arraydimensioned to match the core's thread capacity parameter(RacEr_num_threads_per_core). Additionally, Selective Replication is appliedonly to critical variables, ensuring optimal memory usage. Replication is avoidedwhen there are no synchronization statements within the kernel or when a variable'slive range is fully contained within a single thread loop, meaning it is not accessedoutside of its execution scope. By implementing these replication strategies, RacErensures efficient memory allocation while maintaining correctness in threadsynchronization, allowing for high-performance execution in parallel computingenvironments.

[0053] Figure 3 illustrates compilation and execution pipeline for integrating RacErGPGPU FPGA with Wolfram API, in accordance with an embodiment of thepresent invention. Deployment and Usage of RacEr Manycore applications areoptimized for execution on AWS F1 instances, which integrate Xilinx Alveo DataCenter Accelerator Cards with cloud-based virtual machines to provide high-performance computing capabilities. To streamline deployment, pre-configuredLinux environments are provided, enabling users to immediately set up and runRacEr applications without additional configuration. Additionally, pre-builtAmazon RacEr GPGPU FPGA Images (AFIs / AGFIs) facilitate seamlessportability across different AWS regions.

[0054] The Software Ecosystem of RacEr Manycore provides a structured approachfor executing programs on an accelerator following compilation. The frameworkincludes memory access primitives, allowing host applications to efficientlytransfer data to and from the Manycore's memory space, ensuring optimized dataprocessing through flexible host-to-accelerator communication. Developers areprovided with comprehensive guidelines, covering program development,compilation workflows, and runtime implementation, simplifying Manycoreapplication deployment. RacEr also features kernel-level support, including pre-installed kernel drivers that enable seamless integration, with Amazon's specializeddriver offering memory-mapped access to RacEr GPGPU FPGA registers (via BaseAddress Registers), improving performance and accessibility through userspaceinteraction on AWS F1. At the user-level API, RacEr supports two operationalmodes. Master, responsible for controlling and coordinating execution, andWorker, which manages parallel tasks.

[0055] Figure 4 illustrates interface for communicating with the Manycore, inaccordance with an embodiment of the present invention. The FIFO Interface inRacEr Manycore enables efficient communication between the host and Manycorethrough dedicated PCIe FIFO channels that coordinate interactions. The Manycoreoperates with two distinct FIFO channels, one designated for master transactionsand another dedicated to worker transactions, ensuring structured communicationflow. Each FIFO channel is memory-mapped to a userspace address, allowing hostprograms to interact with them through API functions. The system automaticallyselects the appropriate FIFO channel based on the nature of the transaction. TheLoader mechanism in RacEr Manycore facilitates efficient binary execution acrossmultiple tiles and tile groups in a structured two-stage process. First, the tile groupis configured using the RacEr_mc_set_tile_group_origin() function, which assignsa specific tile to a designated tile group. Next, the binary is loaded into the allocatedtiles via the RacEr_mc_load_binary() function, requiring both the binary file pathand a list of (x, y) coordinates representing the target tiles. Once the data is loaded,the binary's instructions are stored in the instruction cache (icache) of each tile,along with a predetermined DRAM section, while the tile's local memory holds thedata segment. Execution control is managed through RacEr_mc_unfreeze(), whichinitiates execution, and RacEr_mc_freeze(), which allows pausing or resumingoperations.

[0056] The Memcopy API for Endpoint Physical Address (EPA) enables hostprograms to efficiently read from and write to Manycore memory using the Masterchannel. To write data, host applications utilize RacEr_mc_copy_to_epa(), whichtransfers a buffer from the host to RacEr Manycore memory, whileRacEr_mc_copy_from_epa() retrieves processed data from the Manycore andreturns it to the host. The Basic Program Structure requires host applications tobegin execution with RacEr_mc_init_host(), a critical function that facilitatesinteraction between the userspace program and the RacEr GPGPU FPGA throughthe User-Level Library. This function efficiently maps PCIe FIFOs to userspace,and additionally, the standard Linux directory stores the necessary API headers.Before executing a host program in RacEr Manycore, it is essential to ensure thatthe Xilinx Alveo Data Center Card is loaded with the appropriate bitstream,enabling optimized hardware operation. Additionally, the User-Level Library mustbe dynamically compiled and stored in the standard Linux library directory,ensuring smooth integration with the system. The kernel significantly enhancesefficiency and performance by executing floating-point operations on numericalvectors in parallel, improving computational speed and resource utilization.Arithmetic operations, such as addition, are executed on the RacEr GPGPU FPGAusing the RacEr_add(float a, float b) function, which is written in C. This functionenables seamless execution and efficient retrieval of results.

[0057] The RacEr GPGPU FPGA significantly enhances computational performanceby executing large number of floating point operations in parallel, in contrast totraditional CPUs, which handle only one or a few operations at a time. This isachieved through the RacEr Manycore Runtime, a CUDA-like runtime optimizedspecifically for RacEr GPGPU FPGA execution. The runtime efficiently facilitatesthe parallel processing of floating-point operations across multiple RacEr cores andensures optimal resource utilization by managing memory, scheduling tasks, andexecuting kernels. To interface with RacEr GPGPU FPGA, an API enablescommunication between the accelerator and a host computer running WolframMathematica. Since RacEr cannot directly access host RAM, memory must beexplicitly allocated and transmitted between the two systems. The acceleratorperforms floating point operations in parallel, after which results are retrieved,converted, and returned to Mathematica for analysis. For execution withinMathematica, API calls are utilized to initiate RacEr GPGPU FPGA computations.The RunProcess() function allows the compiled C binary to be executed directlyfrom the Mathematica environment, enabling real-time external computation.Results from RacEr are returned in raw numerical format, and Mathematicadynamically extracts them using StringCases(), ensuring efficient interpretation,processing, and visualization. This system seamlessly integrates RacEr GPGPUFPGA with Mathematica, allowing users to outsource intensive floating-pointcomputations with minimal effort while maintaining high-performance efficiency.

[0058] In accordance with an embodiment of the present invention, Figure 5 illustratesRacEr GPGPU FPGA-Mathematica System Design Architecture. The procedurefor executing RacEr GPGPU FPGA-accelerated computations within Mathematicafollows a structured approach. First, in the compilation phase, the interface files arecompiled using GCC, ensuring they are correctly linked with the RacEr ManycoreRuntime and Mathematica libraries for full compatibility with both the RacErGPGPU FPGA and Mathematica environment. Upon successful compilation, anexecutable binary is generated from the object files, which Mathematica candynamically invoke to perform RacEr-based computations. In the WolframMathematica execution phase, RacEr computations are initiated using theRunProcess() function. To process the results, Mathematica employsStringCases(), which parses and extracts raw numerical data returned by the RacErGPGPU FPGA. This allows users to analyse, plot, or compare results withconventional CPU-based computations.Table 1: CPU vs GPU vs your RacEr GPGPU FPGA system (RacEr).

[0059] Figure 6 illustrates RacEr GPU Architecture, in accordance with anembodiment of the present invention. The Enhanced Memory Management forHigh-Speed Data Exchange in RacEr GPU uses a manycore acceleratorarchitecture with external memory and I / O, structured within a tiled frameworkinterconnected through a 2D mesh network. Each tile is equipped with memory,communication routers, specialized accelerator cores, and CPU cores, optimizingenergy-performance efficiency. In certain cases, accelerator tiles replace CPUcores to better handle specific computational workloads. To improve memoryaccess efficiency, RacEr integrates victim cache tiles, typically located at theperiphery as column caches ($), though adaptable placements are possible. Thesetiles interface with memory controllers managing multiple parallel memorychannels, including HBM and DDR4, facilitating fast data transfer. Each CPU corehas a 4KB direct-mapped instruction cache and 4KB local data memory, supportingnon-blocking loads and stores, minimizing memory latency by overlappingexecution with remote memory accesses through the 2D mesh network.Additionally, RacEr organizes tiles into tile groups, which are physically adjacentto enable cooperative multiprocessing by sharing data structures and reservedmemory, ensuring efficient parallel execution. Operating under a bulk synchronousprogramming paradigm, RacEr progresses through exclusive, shared, and atomicmemory access phases, where synchronization barriers significantly enhanceparallelism, data locality, energy efficiency, and throughput compared to directDRAM or column cache access.

[0060] Terms and phrases used in this document, and variations thereof, unlessotherwise expressly stated, should be construed as open-ended as opposed tolimiting. As examples of the foregoing: the term "including" should be read asmean "including, without limitation" or the like; the term "example" is used toprovide exemplary instances of the item in discussion, not an exhaustive or limitinglist thereof; and adjectives such as "conventional," "traditional," "standard,""known" and terms of similar meaning should not be construed as limiting the itemdescribed to a given time period or to an item available as of a given time, butinstead should be read to encompass conventional, traditional, normal, or standardtechnologies that may be available or known now or at any time in the future.Likewise, a group of items linked with the conjunction "and" should not be read asrequiring that each and every one of those items be present in the grouping, butrather should be read as "and / or" unless expressly stated otherwise. Similarly, agroup of items linked with the conjunction "or" should not be read as requiringmutual exclusivity among that group, but rather should also be read as "and / or"unless expressly stated otherwise. Furthermore, although item, elements orcomponents of the disclosure may be described or claimed in the singular, the pluralis contemplated to be within the scope thereof unless limitation to the singular isexplicitly stated. The presence of broadening words and phrases such as "one ormore," "at least," "but not limited to" or other like phrases in some instances shallnot be read to mean that the narrower case is intended or required in instances wheresuch broadening phrases may be absent.

[0061] For the purposes of this specification and appended claims, unless otherwiseindicated, all numbers expressing amounts, sizes, dimensions, proportions, shapes,formulations, parameters, percentages, quantities, characteristics, and othernumerical values used in the specification and claims, are to be understood as beingmodified in all instances by the term "about" even though the term "about" maynot expressly appear with the value, amount, or range. Accordingly, unlessindicated to the contrary, the numerical parameters set forth in the followingspecification and attached claims are not and need not be exact, but may beapproximate and / or larger or smaller as desired, reflecting tolerances, conversionfactors, rounding off, measurement error and the like, and other factors known tothose of skill in the art depending on the desired properties sought to be obtainedby the subject matter of the present invention. For example, the term "about," whenreferring to a value can be meant to encompass variations of, in some embodiments± 100%, in some embodiments ± 50%, in some embodiments ± 20%, in someembodiments ± 10%, in some embodiments ± 5%, in some embodiments ± 1%, insome embodiments ± 0.5%, and in some embodiments ± 0.1% from the specifiedamount, as such variations are appropriate to perform the disclosed methods oremploy the disclosed compositions. Further, the term "about" when used inconnection with one or more numbers or numerical ranges, should be understoodto refer to all such numbers, including all numbers in a range and modifies thatrange by extending the boundaries above and below the numerical values set forth.The recitation of numerical ranges by endpoints includes all numbers, e.g., wholeintegers, including fractions thereof, subsumed within that range (for example, therecitation of 1 to 5 includes 1, 2, 3, 4, and 5, as well as fractions thereof, e.g., 1.5,2.25, 3.75, 4.1, and the like) and any range within that range.

[0062] All publications, patent applications, patents, and other references mentionedin the specification are indicative of the level of those skilled in the art to which thepresently disclosed subject matter pertains. All publications, patent applications,patents, and other references are herein incorporated by reference to the same extentas if each individual publication, patent application, patent, and other reference wasspecifically and individually indicated to be incorporated by reference. It will beunderstood that, although a number of patent applications, patents, and otherreferences are referred to herein, such reference does not constitute an admissionthat any of these documents forms part of the common general knowledge in theart. Although the foregoing subject matter has been described in some detail byway of illustration and example for purposes of clarity of understanding, it will beunderstood by those skilled in the art that certain changes and modifications can bepracticed within the scope of the appended claims.

Claims

1. A Computational System for Hardware-Accelerated Floating-Point Operations (100), comprising: a RacEr GPGPU FPGA module (115) optimized for parallel floating-point computations; a PCIe-based communication enabling direct data transfer between the RacEr GPGPU FPGA module (115) and Wolfram Mathematica (101); a C-based API (104) configured for managing memory allocation, execution control, and seamless computation offloading from Mathematica to the RacEr GPGPU FPGA module (115); and a high-speed execution pipeline, allowing integration of RacEr GPGPU FPGA (115) floating-point operations within Mathematica's (101) computational framework, wherein said system reduces latency, improves precision, and enhances efficiency for applications in financial modeling, scientific computing, and artificial intelligence.

2. The computational system (100) as claimed in claim 1, wherein the RacEr GPGPU FPGA module (115) supports mixed-precision floating-point computation, including single-precision, and double-precision operations.

3. The computational system (100) as claimed in claim 1, wherein memory allocation, data transfers, and tile group-shared memory are managed via RacEr_mc_device_malloc and RacEr_mc_device_memcpy API functions to ensure efficient execution of floating-point computations across multiple cores.

4. The computational system (100) as claimed in claim 1, wherein the PCIe communication is tuned for high-speed data exchange, reducing computation bottlenecks between Wolfram Mathematica (101) and the RacEr GPGPU FPGA (115).

5. The computational system (100) as claimed in claim 1, wherein automated result visualization tools within Mathematica (101) dynamically process and graph RacEr GPGPU FPGA (115) results in real time.

6. A Method for Offloading Floating-Point Computations Using RacEr GPGPU FPGA (100), comprising: initiating a computational task within Wolfram Mathematica (101) that requires floating-point operations; communicating data between Mathematica (101) and the RacEr GPGPU FPGA (115) via PCIe (109); executing floating-point operations on the RacEr GPGPU FPGA's optimized computation module (115); and retrieving results seamlessly into Mathematica for further analysis and visualization, wherein the method optimizes execution time, reduces power consumption, and enhances real-time processing for data-intensive applications.

7. The method claimed in claim 6, wherein RacEr GPGPU FPGA (115) implements an optimized CUDA-lite execution model, ensuring efficient parallelism across tile group processing cores.

8. The method claimed in claim 6, wherein a FIFO-based PCIe communication mechanism facilitates synchronized data exchange between the host system and RacEr GPGPU FPGA (115) hardware.

9. The method claimed in claim 6, wherein the RacEr manycore runtime framework employs a bulk synchronous processing model to optimize floating-point operations across multiple FPGA cores.

10. The method claimed in claim 6, wherein the RacEr GPGPU FPGA (115) incorporates dynamic execution scheduling, ensuring adaptive workload distribution based on input complexity.