A reversible logic based fault-tolerant ring-oscillator physically unclonable function

Abstract

ABSTRACT The present invention relates to an XOR gate based fault detection system having a ring-oscillator (RO) based physically unclonable function (PUF), which is based on the reversible logic (RL) and is fault-tolerant. The performance of the PUF is observed by calculating various parameters such as uniqueness, reliability and bit error rate. The system of the present invention includes following modules i.e., Fault-Tolerant RL based XOR Gate design, Reversible-Logic designing, Fault-Detection module, Fault-free path selection module and the Reversible RO-PUF module.

Description

FIELD OF INVENTION

[001] The present invention relates to a hardware security system. Particularly, the presentinvention relates to a reversible logic based fault-tolerant ring-oscillator physicallyunclonable function. More particularly the present invention relates to a system and methodhaving reversible logic based fault-tolerant ring-oscillator physically unclonable functionwith inbuilt fault detection technology.BACKGROUND OF THE INVENTION

[002] Hardware security is becoming increasingly important in today's world, as softwareand protocol security are no longer adequate. Key barriers to hardware security (unique chipIDs, verification and testing, physical integrity, and side channel suppression) includerequired Integrated Circuit (IC) infrastructure and high-level chip defenses (activation andlocking protocols, multichip systems, software interfaces). Decades of research in this fieldhave yielded several security primitives, such as Physically Unclonable Functions (PUFs)and True Random Number Generators (TRNGs), numerous defensive mechanisms, and otheruncountable applications to aid various parts of hardware security. Unfortunately, several ofthese security methods are nearing the end of their development cycles and rely heavily onexisting CMOS technology.

[003] Fault tolerance is another aspect of circuit and system resilience that refers to asystem's or equipment's ability to continue operating in the event of a fault. Depending on thefault tolerance mechanism used, systems with high fault tolerance can continue to operatecompletely or partially after a failure occurs. Fault-tolerant design necessitates carefulconsideration of faults that can occur at any time during the life cycle of the equipment, aswell as their likely causes and consequences. A good design should match the degree oftolerance to the severity of the fault, allowing for cost and resource efficiency optimizationoverall. To create a fault-tolerant system, every stage of the equipment life cycle must beworked on.

[004] As technology advances beyond the sub-10 nm node, the capacity to fit a few billiontransistors into a single IC increases. Moore's law's exponential representation, thesemiconductor device industry's fabrication and design have critical factors to calibratebetween better high-performance, increased cost, and circuit complexity in the final designof an IC. However, Moore's law appears to be facing some resistance in terms of shrinkingtransistor size beyond the 10nm node. One of the emerging research trends in recent yearshas been reversible computing and its implementation in the digital design of logic circuitsand systems using a reversible computing method.

[005] In today's digital design, the primary goal of reversible logic is to reduce powerdissipation. The primary domains that could benefit the most are low-power digital design,quantum computing, and so on. The new era of creativity in opposition to Moore's law israpidly fading, but it is not yet over. Quantum computing is rapidly evolving as one of themost promising alternatives for designing integrated circuits beyond the saturated approachof the semiconductor device fabrication era. This has the added benefit of allowing theevolution of reversible design methods in quantum computing for conventional digital ICdesign.

[006] To perform any arithmetic and logical operation in an ALU of a computing processor,digital logic gates exchange binary logic signals in a random manner across numerousintrinsic functional blocks of a digital design, such as exchange of logic 1's and logic 0'sacross multiple combinational and sequential blocks. Despite having a vast number oftransistors, these digital circuits can perform several different tasks at once. But the majorityof digital operations have a fundamental flaw in their irreversible manner of design, whichprevents the output signals from learning anything about the input signals. The binaryread / write operation in any register or memory is primarily volatile as information at any Nbit state vanishes after each set / reset of a digital logic circuit. This N-bit data can be visualizedto carry any of the 2N states that are feasible. As a result, the physical state of the hardwarechanges by deleting N-bit information, causing the associated bit sequence to be compressedinto lower entropy. According to Landauer's principle, the least amount of energy dissipatedfor every irreversible bit operation is about KTln2 (Joules), where Boltzmann's constant K =1.38x1023(J / K) and T is the absolute temperature of the computation. As a result, lower nodetechnology nodes will be hampered by excessive heat. This problem has the potential toreduce overall performance and hasten the ageing process. As a result, reversible logic couldbe helpful in advanced node high-performance computing and low-power VLSI circuits andsystems.

[007] The integrity and dependability of manufactured circuits have come under scrutinydue to security issues brought on by the globalization of the IC supply chain. Althoughperformance in both CMOS and post-CMOS devices should be repressed for reliabilityreasons, researchers have taken advantage of them for a variety of applications and specialprimitives for hardware-oriented security. Data security is becoming a major concern in thepractical and meaningful development of circuits and systems due to the advancement oftechnologies. The development of numerous hardware hacking techniques, including sidechannel assaults and machine learning algorithms, gives the attacker access to the securitykey that is stored in the non-volatile memory. Both reliability and security are crucial for theirrespective applications and need to be handled thoroughly.

[008] The resilience of any circuit and system has three primary precedence: integrity,availability, and confidentiality, where we view reliability as a blend of integrity andavailability. In contrast, security includes all three critical aspects. The integrity of circuitsand systems get affected by unreliable and insecure effects. Traditionally, IC reliability andsecurity mechanisms have evolved distinctly, resulting in system performance degradationand significant hardware cost overhead. The unreliability caused by design and technologydefects sometimes gives us opportunities to address the security challenges. Hence,considering the resilient systems, reliable and secure integrated circuits have become the needof recent technologies. The security includes various primitives such as PUFs, TRNGs,counterfeit electronics and Hardware Trojans. Researchers have advocated the use of PUFsand other types of unclonable identification to distinguish individual ICs and avoid digitalcloning. A PUF is a device function inherent in its physical structure that is simple to evaluatebut difficult to capture in it's entirely within standard time / memory restrictions. Suchunclonable identifiers are particularly critical for Field Programmable Gate Arrays (FPGA),which lack secure non-volatile memory for key storage. PUFs are secure one-way functionsthat utilize intrinsic physical variances in the manufacturing process to provide unique outputfor a given input. As a result, challenge-response pairs generated by PUF circuits made usingidentical manufacturing procedures are different. The current challenges and active researchtopics in this area include the development of methods for ensuring PUF stability underdifferent ambient conditions, and ensuring PUF robustness to sophisticated attacks.

[009] Therefore, in view of the problem associated with the state of the art, it is imperativeto provide a reversible logic-based RO-PUF with a parity-preserving feature and a faultdetection feature while consuming less power.OBJECTIVES OF THE INVENTION

[0010] The primary objective of the present invention is to provide a reversible logic basedfault-tolerant ring-oscillator physically unclonable function.

[0011] Another objective of the present invention is to provide a system and method havingring-oscillator (RO) based physically unclonable function (PUF), which is based on thereversible logic (RL) technology and is fault-tolerant.

[0012] Yet another objective is to provide a reversible logic-based RO-PUF with a paritypreserving nature, a fault-detection system, and a higher degree of uniqueness while usingless power.

[0013] Another objective of the present invention is to provide increased security bygenerating responses which will be highly unpredictable in addition to the system beingreliable and fault-tolerant.

[0014] Yet another objective is to provide Fault detection mechanism of the reversible gateusing XOR gates.

[0015] Other objects and advantages of the present invention will become apparent from thefollowing description taken in connection with the accompanying drawings, wherein, by wayof illustration and example, the aspects of the present invention are disclosed.SUMMARY OF THE INVENTION

[0016] The present invention relates to a reversible logic based fault-tolerant ring-oscillatorphysically unclonable function. The ring-oscillator (RO) of the present invention provides aphysically unclonable function (PUF), which is based on the reversible logic (RL) design andis fault-tolerant. The fault free output of the reversible gate is chosen using the XORfunctionality after the reversible gate has been chosen, and it is then sent to a fault detectionmodule. Multiplexers are used to choose the fault-free routes after the generation of fault-freeoutput. The RO-PUF module receives the output after which the RO chains are configuredusing the final output, which is actually a fault-free XOR logic. Moreover, multiplexers,counters, and a comparator are designed in order to obtain the PUF's architectural layout.Power dissipation is exceedingly minimal because the RO-PUF is based on reversible logic.The present invention provides a reversible logic-based RO-PUF with a parity-preservingfeature, a fault-detection system with less power consumption.BRIEF DESCRIPTION OF DRAWINGS

[0017] An understanding of the present invention may be obtained by reference to theaccompanying drawings, when taken in conjunction with the description herein and in which:

[0018] Figure 1 illustrates block diagram of the reversible gate based fault-tolerant XOR Gatedesign;

[0019] Figure 2 illustrates the Double-Feynman Gate (a) Block diagram of the DoubleFeynman Reversible Gate (b) Truth table of the Double-Feynman Gate.

[0020] Figure 3 illustrates Fault detection system module of the reversible gate based faulttolerant RO-PUF;

[0021] Figure 4 illustrates (a) Fault free path selection module of the reversible gate basedfault-tolerant RO-PUF (b) Functional table for the fault free path selection module;

[0022] Figure 5 illustrates architecture of the proposed design of Reversible-Logic basedRing-Oscillator PUF; and

[0023] Figure 6 illustrates the method of working of the present invention.DETAILED DESCRIPTION OF THE INVENTION

[0024] The following description describes various features and functions of the disclosedsystem with reference to the accompanying figures. In the figures, similar symbols identifysimilar components, unless context dictates otherwise. The illustrative aspects describedherein are not meant to be limiting. It may be readily understood that certain aspects of thedisclosed system can be arranged and combined in a wide variety of different configurations,all of which have not been contemplated herein.

[0025] Accordingly, those of ordinary skill in the art will recognize that various changes andmodifications of the embodiments described herein can be made without departing from thescope of invention. In addition, descriptions of well-known functions and constructions areomitted for clarity and conciseness.

[0026] Features that are described and / or illustrated with respect to one embodiment may beused in the same way or in a similar way in one or more other embodiments and / or incombination with or instead of the features of the other embodiments.

[0027] The terms and words used in the following description are not limited to thebibliographical meanings, but are merely used to enable a clear and consistent understandingof the invention. Accordingly, it should be apparent to those skilled in the art that thefollowing description of exemplary embodiments of the present invention are provided forillustrative purpose only and not for the purpose of limiting the invention.

[0028] It is to be understood that the singular forms "a", "an" and "the" include pluralreferents unless the context clearly dictates otherwise.

[0029] It should be emphasized that the term "comprises / comprising" when used in thisspecification is taken to specify the presence of stated features, integers, steps or componentsbut does not preclude the presence or addition of one or more other features, integers, steps,components or groups thereof. The equations used in the specification are only forcomputation purpose.

[0030] The present invention relates to a reversible logic-based RO-PUF technology that usesless power due to its reversible nature. Furthermore, the system will be fault-tolerant andsuitable for secure key generation while maintaining the system's parity-preserving nature.PUFs have become critical in terms of hardware security. Because of their simplicity indesign, delay-based PUFs, particularly RO-PUFs, have gained a lot of attention amongdifferent types of PUFs in recent decades. Furthermore, because of the one-to-one mapping,this RO-PUF will be based on a reversible gate, which consumes little power.

[0031] An XOR gate based fault detection system comprises a plurality of ring oscillatorembedded in the in a Physical Unclonable Function module; a plurality of multiplexer,wherein each multiplexer's first input is coupled to the corresponding ring oscillator and asecond input coupled to a corresponding counter; the plurality of counters, wherein eachcounter is coupled to a common comparator. Further the plurality of ring oscillators includesan odd number of double Feynman reversible Gate; the double Feynman reversible Gateoutput is coupled to the fault detection module; the fault detection module output is coupledto the Fault free Path Selection Module; the comparator compares the frequency of theplurality of ring oscillators and displays the output.

[0032] Figure 1 illustrates a block diagram of the system of the present invention i.e.,reversible logic gate, fault-free path selection module, fault detection module and the ROand ring oscillator- Physical Unclonable Function (RO-PUF) module. The first three modulesare for fault tolerant reversible logic XOR gate design and the last one for the PUF designand performance analysis. The modules are discussed herein in detail:

[0033] (1) Double-Feynman reversible gate: An n-input, n-output (denoted by nxn) circuitcreates a unique output pattern for each possible input pattern. There is a one-to-oneconnection between the input and output vectors. The gate used in the present invention is aDouble-Feynman reversible gate selected from but not limited to a group of gates i.e., asFeynman Gate, Fredkin Gate, Toffoli gate, Double-Feynman gate etc. Double-Feynman gateis a 3x3 fault-tolerant and configurable reversible gate having three inputs and three outputs.Further, the Double-Feynman gate has a lesser Quantum Cost (QC = 2) as compared to otherreversible gates. In the Double-Feynman gate two of the outputs are the XOR operation of itsinputs thus any of the fault-tolerant output can be used for the configuration of the physicalunclonable function PUF and the output which is the replica of the input that can be used asa buffer in the PUF design thus adding to the configurability of the PUF when to function itas a buffer chain or the inverter / XOR operation.

[0034] The gate functions as an inverter as the reversible gate for the implementation of RObased PUF is used, and since two out of the three outputs are XOR logic of the inputs andhence we can obtain two inverters from this reversible gate. In an exemplary embodiment thereversible gate will give the three outputs as P = A, Q = AB and R = AC as illustrated inFigure 2(a)). Further, Figure 2(b) illustrates the truth table for the Double-Feynman reversiblegate. Thus, the two outputs of the Double-Feynman reversible gate are used to configure theRO-PUF, and the remaining, which is acting as a buffer, is an output not required. The faulttolerance of this gate displays its parity preserving nature. Fault tolerance is a function thatallows a system to operate correctly even when one or more of its components fail. The faulttolerance of a reversible circuit represents the system's robustness. Fault detection inreversible logic circuits is incorporated using fault-tolerant reversible gates. The paritypreserving approach detects the occurrence of a problem in the circuit. In parity-preservingreversible circuits, any failure that affects only one signal is observable at the circuit'ssignificant outputs. This parity perseverance is checked if the XOR of all the inputs equalsthe XOR of all the outputs. From the truth table it can be concluded that the A (circled plus)B (circled plus)C =PQR and thus Double-Feynman reversible gate is a parity preserving reversible gate.

[0035] (2) Fault Detection Module: The module goes through fault detection aftergenerating the reversible logic, which has two XOR outputs, and then a fault-free path ischosen for further processing. Figure 3 illustrates an exemplary embodiment of the faultdetection system comprising four XOR gates that compare the principal inputs and the outputsfrom the Double-Feynman reversible gate. The XOR-I gate will supply the XOR logic of Aand B inputs, while the XOR-II gate will do the same for A and C inputs, producing theoutputs X and Y, respectively. The three outputs from the reversible gate are P = A (bufferoutput), Q = A B, and R = A C. The output X of the XOR-I and Q from the XOR-IIIgate will be compared by the reversible gate will give the three outputs as. If the reversiblegate output Q is fault-free, then the output of XOR-IV gate (S1) will be '0' else '1'. Similarly,for the second output of the reversible gate to be fault-free, the output of the XOR-IV (S0)gate (whose inputs are R and Y) will be '0' else '1'.

[0036] (3)Fault free Path Selection Module: The Double-Feynman reversible gate's twooutputs, as well as the outputs of the XOR-III and XOR-IV gates, are fed to the 4:1multiplexer, which selects fault-free paths, as shown in Figure 4(a). The output of the XORIII and XOR-IV gates serves as the multiplexer's select lines (S1S0). If S1S0 is '00,' bothreversible gate outputs are fault-free, thereby producing an option to select either of the twooutputs. In an exemplary embodiment Figure 4 illustrates, if S1S0 is '01,' Q is fault-free andR is faulty, so I1 equals Q. If S1S0 = '10,' Q is faulty and R is not, so I2 = R. If S1S0 = 11, Xis chosen as the output because it is the XOR of primary inputs A and B. The output will beused to create the RO-PUF. Therefore, the fault-tolerance probability of this fault detectionsystem is 75% because there is only one case where both outputs of the reversible gate arefaulty, and thus we use the reversible gate's primary inputs as the building logic of the ROPUF.

[0037] (4) RO and RO based PUF Module: The ring oscillator RO is built using faulttolerant XOR logic. Hence, the PUF is configurable as the XOR gate input behaves differentlywhen different logic bits are provided as the input. That is, depending on the functionality ofthe PUF, the same XOR is used as an inverter as well as a buffer. The PUF's configurabilitywill aid in increasing the number of challenge-response pairs. As a result, the reversible logicbased fault-tolerant RO-PUF is developed. Figure 5 illustrates that the RO-PUF architectureof the present invention consists of a number of cascaded chains of Double-Feynman gates(functioning as inverter / buffer as when required) and the output from these ROs is fed to themultiplexers to select the RO for comparison. The functionality of the multiplexers is decidedby the challenge / input given and then the counter counts the number of times the faster ROobtains its upper limit. The comparator finally compares the frequency of these ringoscillators and gives it to the output and thus the 1 bit PUF response is generated. On initiatingthis block n times n-bit PUF is generated.

[0038] Figure 6 illustrates the method for working of the system of the present invention,discussed herein:- selecting the reversible gate after checking the reversible gate and its outputs for thefault tolerance;- providing reversible gate to a fault detection module wherein the fault free output ofthe reversible gate is selected using the XOR functionality;- analyzing and investigating the fault tolerance for fault free mechanism;- checking if the output is fault free;- selecting the fault-free paths via multiplexers after the generation of fault-free output;- giving the output to the RO-PUF module to configure the RO chains;- implementing the PUF using ring oscillator RO circuit ; and- analyzing the performance of ring oscillator based in a Physical Unclonable Function(RO-PUF).

[0039] The advantages of the system of the present invention includes:- Fault-tolerant systems have the ability to detect and repair faults. If the logic circuitcomprises fault-tolerant components, fault detection and correction becomes cheaper,easier, and more straightforward.- The RO-PUF of the present invention is designed depending on reversible logic andhence power dissipation is extremely low.- A parity preserving reversible logic is used to design the RO. The design becomesfault-tolerant with respect to parity perseverance and dissipates less power because ofits reversible nature.- Fault detection mechanism of the reversible gate using XOR gates.- The fault-free path is selected and used to design reversible logic-based RO-PUF.

[0040] While this invention has been described in connection with what is presentlyconsidered to be the most practical and preferred embodiment, it is to be understood that theinvention is not limited to the disclosed embodiments, but, on the contrary, is intended tocover various modifications and equivalent arrangements included within the scope of theappended claims.

Claims

1. An XOR gate based fault detection system used for the design of reversible logic based ring-oscillator physically unclonable function comprising: - a plurality of ring oscillator embedded in a Physical Unclonable Function module; - a plurality of multiplexer, wherein each multiplexer's first input is coupled to the corresponding ring oscillator and a second input coupled to a corresponding counter; - the plurality of counters, wherein each counter is coupled to a common comparator; Wherein: i. the plurality of ring oscillators includes an odd number of double Feynman reversible Gate; ii. the double Feynman reversible Gate output is coupled to the fault detection module; iii. the fault detection module output is coupled to the Fault free Path Selection Module; iv. the comparator compares the frequency of the plurality of ring oscillators and displays the output.

2. The system as claimed in claim 1, wherein the plurality of ring oscillators comprises cascaded chains of double Feynman reversible Gate.

3. The system as claimed in claim 1, wherein the fault detection module comprises four XOR gates (XOR I, XOR II, XOR III, XOR IV) for comparing the primary inputs and the outputs from the double Feynman reversible Gate.

4. The system as claimed in claim 1, wherein the Double-Feynman reversible gate's two outputs and the outputs of the XOR-III and XOR-IV gates are received at the input of the multiplexer.

5. A method of working of the system as claimed in claimed 1 comprises the following steps: o selecting the reversible gate after checking the reversible gate and its outputs for the fault tolerance; o providing reversible gate to a fault detection module wherein the fault free output of the reversible gate is selected using the XOR functionality; o analyzing and investigating the fault tolerance for fault free mechanism; o checking if the output is fault free; o selecting the fault-free paths via multiplexers after the generation of fault-free output; o giving the output to the RO-PUF module to configure the RO chains; o implementing the PUF using ring oscillator RO circuit; and o analyzing the performance of ring oscillator based Physical Unclonable FunctionRO-PUF.