TRANSMISSION MODULE FOR A TRANSMISSION / RECEPTION EQUIPMENT OF A TERMINAL OF A SERIAL BUS SYSTEM AND PROCEDURE FOR TRANSMISSION OF A MESSAGE WITH DIFFERENTIAL SIGNALS IN A SERIAL BUS SYSTEM

Abstract

A transmitter module (121) for a transmit-receive device (12) of a subscriber station (10; 30) of a serial bus system (1) and a method for sending a message (45) with differential signals (CAN_H, CAN_L) in a serial bus system are provided. The transmitter module (121) is configured to send a digital transmit signal (TxD_INT) as an analog differential signal (CAN_H, CAN_L) to a bus (40) of the bus system (1) in order to send a message (45) to at least one other subscriber station (10; 20; 30) of the bus system (1), wherein the transmitter module (121) comprises transmit stages (121A; 121B; 121C; 121D) with parallel circuits (121A1; 121VB1; 121C1; 121D1) of switchable resistors (R_A1 ...R_AN; R_B1 ...R_BN; R_C1 ... R_CN; R_D1 ... R_DN), and a control unit (15) for stepwise control of the switching of the switchable resistors (R_A1 ... R_AN; R_B1 ... R_BN; R_C1 ... R_CN; R_D1 ... R_DN), where at least two of the switchable resistors (R_A2, R_A3; RA4 ... R_A7; R_A8 ... R_A16) are arranged in a resistor block (162; 163; 164) in a switchable manner, wherein at least two resistor blocks (161; 162; 163; 164) are provided, which have at least one of the switchable resistors (R_A2, R_A3; RA4 ... R_A7; R_A8 ... R_A16), and wherein the control part (15) is configured to generate the bus states (401; 402; 403; LV0; LV1) specified by the digital transmit signal (TxD) over time (t) on the bus (40) by stepwise changing over time (t) the number of actively switched resistor blocks (162; 163; 164).

Description

[0001] The present invention relates to a transmission module for a transmission / reception device of a subscriber station of a serial bus system and a method for transmitting a message with differential signals in a serial bus system. State of the art

[0002] Serial bus systems have a bus to which subscriber stations are connected via a transceiver device to communicate with each other over the bus. The transceiver device is also called a transceiver. During communication, data is exchanged between the subscriber stations, which can be, for example, sensors, control units in a vehicle or a technical production system, etc. Various standards or data transmission protocols exist for data transmission in serial bus systems. Well-known serial bus systems with differential signals include CAN XL, 10BASE-T1S Ethernet, FlexRay, LVDS (LVDS = Low Voltage Differential Signaling), and so on.

[0003] Each of these serial bus systems uses differential signals with different signal states, which serially signal the data to be exchanged. The desired signal states can be generated using a transmitter module connected to the bus and designed as a full bridge with a large number of switchable resistors. Depending on the number of conductive resistors, a corresponding resistance is established at the output of the full bridge, and a corresponding voltage can be generated on the bus. Thus, each desired signal state on the bus is determined by its open-circuit voltage and internal resistance. A differential voltage is generated on the bus for the differential signals sent on the bus.

[0004] The problem is that the transition between two signal states can cause electromagnetic emissions that can interfere with other electrical devices. Therefore, there are specifications for maximum permissible electromagnetic emissions that every transceiver must meet. However, these electromagnetic emission requirements represent one of the greatest challenges in the development of such a transceiver with switched resistors in the full bridge.

[0005] Electromagnetic emissions are caused by fluctuations in the common-mode signal on the bus. These arise in two ways: first, common-mode fluctuations caused by the transmitter module (transmitter), and second, by the external circuitry of the transceiver.

[0006] The common mode fluctuations caused by the transmitter module can arise from process variations, insufficient modeling of the components used, etc., resulting in signal states having different common modes, which cannot always be represented in simulations during the design phase.

[0007] The common-mode fluctuations on the bus caused by the external circuitry of the transceiver can be generated even if the transceiver generates a "perfect" signal with a constant common mode. This is because the external circuitry is not exactly symmetrical, and part of the differential signal is converted to a common-mode signal ("differential-to-common-mode conversion"). Therefore, it is important to also optimize the spectrum of the differential signal. The shape of the transition from one state to another is crucial for this.

[0008] Mathematically, it can be shown that the spectrally optimal form for transitions of the differential signal between two signal states is the error function, which is the integral of the Gaussian bell function. Therefore, the transitions should be approximated to this function as closely as possible using discrete steps, namely as transition states between static states. This can be achieved using appropriate control logic.

[0009] However, there is a conflict of objectives in the control concepts between flexibility, efficiency (chip area and power consumption), maximum possible performance (optimal emission behavior) and development effort.

[0010] Another problem is that vehicle communication standards have such high robustness requirements regarding the dielectric strength of the transceiver that the transceiver must be implemented in large process nodes. Such nodes or distributors are typically larger than 100 nm. As a result, the transceiver is limited in its maximum possible digital clock frequency. This means that, especially for a fast bus signal state transition, also known as an edge, only a few steps are available to approximate the transition shape of the bus signal(s) to the error function.

[0011] For example, CAN-XL, according to the specification, requires slew rates of t_rise < 20 ns (20-80%) for a bus signal. At a clock frequency of 500 MHz (2 ns / clock), this only allows a maximum of 10 discrete steps to approximate a continuous signal transition in this range. This results in a significant peak in the frequency spectrum of the signal transition at the clock frequency of the digital part. The same applies to other serial bus systems with differential signals.

[0012] It is possible to generate the transitions of the differential bus signal between two signal states using analog time step generators. These asynchronously specify a fixed form of time steps t1, t2, ..., tN for the transition by dimensioning capacitances and currents. These form the circuit output as individual step signals S_1, ..., S_N. Multiple chains are used to represent multiple static states. A minimum of three chains is required to generate the five CAN XL signal states (REC, SIC, DOM, LV0, LV1) on the bus.

[0013] The disadvantage of such a time-step generator, however, is that the three chains require a significant amount of circuitry and development effort, and they consume a lot of power during operation. Furthermore, while such a time-step generator is very well suited to the requirements of CAN XL, adapting it to transmit / receive devices to meet other communication standards is very complex. Disclosure of the invention

[0014] Therefore, the object of the present invention is to provide a transmission module for a transmission / reception device of a subscriber station of a serial bus system and a method for transmitting a message with differential signals in a serial bus system, which solve the aforementioned problems. In particular, a transmission module for a transmission / reception device of a subscriber station of a serial bus system and a method for transmitting a message with differential signals in a serial bus system are to be provided, which enable the reliable, error-free, and low-emission creation / generation of bus signals for any differential bus system in a manner as simple and cost-effective as possible.

[0015] The object is achieved by a transmission module for a transmission / reception device of a subscriber station of a serial bus system having the features of claim 1. In the bus system, the transmission module is designed to transmit a digital transmission signal as an analog differential signal to a bus of the bus system in order to send a message to at least one other subscriber station of the bus system.The transmission module has transmission stages with parallel circuits of switchable resistors, and a control part for the step-by-step control of the switching of the switchable resistors, wherein at least two of the switchable resistors are arranged in a resistor block so as to be switchable together, wherein at least two resistor blocks are provided which have at least one of the switchable resistors, wherein the control part is designed to generate the intermediate states on the bus predetermined by the digital transmission signal over time by step-by-step changing over time the number of actively switched resistor blocks.

[0016] The described transmitter module requires comparatively little circuitry and development effort for the described configuration of switchable resistor arrays. The slew rate for the transition between two signal states is adjustable.

[0017] As a result, the described transmitter module requires significantly less space than an implementation with multiple delay chains. This saves semiconductor area, making the described transmitter module extremely resource-efficient and cost-effective.

[0018] As a further consequence, the power consumption during operation of the transmitter module described is also very low, especially compared to a solution with multiple delay chains.

[0019] Thanks to the adjustable slew rate, the described transmitter module can be easily adapted to meet various communication standards for differential bus systems. In particular, the transmitter module can be used with a CAN SIC transmitter / receiver device and / or a CAN XL transmitter / receiver device and / or a 10BASE-T1S transmitter / receiver device and / or any other transmitter / receiver device for differential signals.

[0020] Another advantage is that the described transmitter module allows for very simple control between the states. This allows the transmitter / receiver device to cover a wide range of possibilities in a timely and continuous manner, ensuring a timely switching to the final state without abrupt transitions.

[0021] Another advantage is that the transmitter module ensures that even in the event of unforeseen incomplete transitions, no abrupt changes are possible at the transmitter module's output. This is because even after the circuit is reset, the changes only occur gradually. This ensures a continuous output at the transmitter module's output, which has a positive effect on the emission behavior of the transmitter module and the higher-level transmit / receive device.

[0022] In this way, the described transmitter module ensures that the bus does not experience abrupt transitions in the differential voltage and / or impedance. As a result, the transmitter / receiver device generates little to no emissions and reflections in the bus system.

[0023] Overall, the described transmitting / receiving device can not only realize communication in the bus system between other subscriber stations with the (high) bit rates required for the respective communication standard, but is also designed in such a way that the transmittable bit rate is not reduced by errors in the communication.

[0024] Advantageous further embodiments of the transmission module are described in the dependent claims.

[0025] All switchable resistors may have approximately the same resistance value.

[0026] It is conceivable that the resistance value of a first resistance block of the at least two resistance blocks is approximately half as large as the resistance value of a second resistance block of the at least two resistance blocks.

[0027] In a special embodiment, the transmit module also has a state processing block for evaluating the digital transmit signal in order to decide how the switchable resistors of the parallel circuits are to be switched step by step in order to set the desired state on the bus.

[0028] The state processing block may be configured to generate a slew rate signal, wherein the state processing block is configured to generate the slew rate signal based on an evaluation result of the digital transmission signal.

[0029] The state processing block may be configured to generate a step start signal, wherein the state processing block is configured to output the slew rate signal after being enabled by the step start signal for controlling the switchable resistors.

[0030] According to one embodiment, the transmitting module further comprises a step generator for generating a step signal based on a slew rate signal and for outputting the step signal to a logic block for controlling switches of the parallel circuit for switching the switchable resistors.

[0031] The state processing block may be configured to generate a reset signal for resetting the step generator to an initial value.

[0032] According to one embodiment, the transmitting module also has a logic block for generating a control signal for controlling the at least two resistance blocks of a transmitting stage.

[0033] Optionally, the logic block has at least two flip-flops arranged to generate a control signal for each of the at least two resistance blocks, wherein the logic block is configured to generate the control signal as a binary number with bits whose number is equal to the number of the at least two flip-flops and to output the bits to the at least two flip-flops.

[0034] According to one embodiment, the transmission module further comprises a memory block in which target values ​​for the resistance values ​​of the parallel circuits are stored, which target values ​​are to be generated for transitions between signal states on the bus for each intermediate state in the transition, wherein the state processing block is configured to generate, on the basis of the evaluation of the digital transmission signal, a selection signal and to output the selection signal to the logic block, and wherein the logic block is configured to generate the control signal for controlling the at least two resistance blocks of a transmission stage on the basis of the transitions selected by the selection signal.

[0035] The transmitting module may have a resistance cell in which resistance blocks are arranged for generating each intermediate state on the bus, the logic block for controlling each intermediate state on the bus having a control cell configured to control one of the resistance cells, and all control cells for each intermediate state are constructed identically.

[0036] In a specific embodiment, a first to fourth transmission stage are connected in a full bridge, in which the first and fourth transmission stages are connected in series and the third and second transmission stages are connected in series. The first to fourth transmission stages can be configured to generate differential bus signals for a bus of the bus system in response to the two different values ​​of the digital transmission signal such that the transmission module generates a first or second bus state on the bus in its first operating mode and generates a third or fourth bus state in its second operating mode, the bus signals forming a differential voltage on the bus whose voltage value is different for the first to fourth bus states.

[0037] The previously described transmit module may be part of a transmit / receive device which also has a receive module for receiving signals from the bus and for generating a digital receive signal from the analog differential signal.

[0038] The transmitting module may be designed to generate the analog differential signals in a first communication phase of the message with a different physical layer than in a second communication phase.

[0039] The previously described transmitting / receiving device can be part of a subscriber station for a serial bus system. The subscriber station can also be a communication control device for controlling communication in the bus system and for generating the first transmission signal. The subscriber station can be configured for communication in the bus system in such a way that exclusive, collision-free access of a subscriber station to the bus of the bus system is guaranteed, at least temporarily.

[0040] The above-mentioned object is also achieved by a method for transmitting a message with differential signals in a serial bus system having the features of claim 18.The method is carried out using a transmission module which has transmission stages with parallel circuits of switchable resistors and is designed to transmit a digital transmission signal as an analog differential signal onto a bus of the bus system in order to send a message to at least one other subscriber station of the bus system, wherein the method comprises the steps of stepwise controlling the switching of switchable resistors using a control part of the transmission module, wherein at least two of the switchable resistors are arranged so as to be switchable together in a resistor block, wherein at least two resistor blocks are provided which have at least one of the switchable resistors, and generating, and wherein the control part generates the bus states on the bus which are predetermined over time by the digital transmission signal by stepwise changing over time the number of actively switched resistor blocks.

[0041] The method offers the same advantages as previously mentioned with regard to the transmitter module.

[0042] Further possible implementations of the invention also include combinations of features or embodiments described above or below with respect to the exemplary embodiments not explicitly mentioned. In this case, the person skilled in the art will also add individual aspects as improvements or additions to the respective basic form of the invention. Drawings

[0043] The invention is described in more detail below with reference to the accompanying drawings and exemplary embodiments. They show: Fig. 1 a simplified block diagram of a bus system according to a first embodiment; Fig. 2 a diagram illustrating the structure of a message that can be sent by a subscriber station of the bus system according to the first embodiment; Fig. 3an example of the ideal time course of bus signals CAN_H, CAN_L, which are used by subscriber stations of the bus system for the message from Fig. 2 sent to a bus of the bus system; Fig. 4 the time course of a differential voltage VDIFF, which is equal to the bus voltage VBUS, in particular equal to VCAN, and which is on the bus of the bus system as a result of the bus signals from Fig. 3 trains; Fig. 5 an example of a time course of a digital transmission signal, which in an arbitration phase (SIC operating mode) is converted into bus signals CAN_H, CAN_L for a bus of the bus system of Fig. 1 should be implemented; Fig. 6 the time course of the bus signals CAN_H, CAN_L when changing between a recessive bus state to a dominant bus state and back to the recessive bus state, which in the arbitration phase (SIC operating mode) due to the transmission signal from Fig. 5 sent to the bus; Fig. 7an example of a time course of a digital transmission signal, which in a data phase is converted into bus signals CAN_H, CAN_L for the bus of the bus system of Fig. 1 should be implemented; Fig. 8 the time course of the bus signals CAN_H, CAN_L, which in the data phase due to the transmission signal from Fig. 7 sent to the bus; Fig. 9 a circuit diagram of a transmitting module for a transmitting / receiving device that can be used for a subscriber station of the bus system according to the first embodiment; Fig. 10 a block diagram of a control part of the transmitter module of Fig. 9 ; Fig. 11 a temporal progression of a signal state transition that is associated with the transmitter module of Fig. 9 can be generated; and Fig. 12 an electrical diagram of a part of a logic block of the control part of Fig. 10 and a resistor array for a transmitting stage of the transmitting module of Fig. 9 .

[0044] In the figures, identical or functionally equivalent elements are provided with the same reference numerals unless otherwise indicated. Description of the embodiments

[0045] Fig. 1 shows a bus system 1, which can, for example, at least in sections, be a CAN bus system, a CAN-FD bus system, etc. The bus system 1 can be used in a vehicle, in particular a motor vehicle, an aircraft, etc., or in a hospital, etc.

[0046] Although the bus system 1 is described below using CAN bus systems, the bus system 1 is not limited to CAN bus systems. Alternatively, the bus system 1 can be, in particular, a 10BASE-T1S bus system or another serial bus system 1 that uses, in particular, differential signals.

[0047] In Fig. 1The bus system 1 has a plurality of subscriber stations 10, 20, 30, each connected to a bus 40 or bus line with a first bus wire 41 and a second bus wire 42. In a CAN bus system, the bus wires 41, 42 can also be called CANH and CANL for transmitting CAN_H and CAN_L signals on the bus 40. In a 10BASE-T1S bus system, the bus wires 41, 42 are called LINE+ and LINE-.

[0048] Messages 45, 46, 47 can be transmitted in the form of signals between the individual subscriber stations 10, 20, 30 via the bus 40. Subscriber stations 10, 20, 30 are, for example, control units or display devices of a motor vehicle.

[0049] As in Fig. 1 As shown, the subscriber stations 10, 30 each have a communication control device 11 and a transmitting / receiving device 12. The transmitting / receiving device 12 has a transmitting module 121 and a receiving module 122.

[0050] The subscriber station 20 has a communication control device 21 and a transmitting / receiving device 22. The transmitting / receiving device 22 has a transmitting module 221 and a receiving module 222.

[0051] The transmitting / receiving devices 12 of the subscriber stations 10, 30 and the transmitting / receiving device 22 of the subscriber station 20 are each directly connected to the bus 40, even if this is Fig. 1 is not shown.

[0052] The communication control devices 11, 21 each serve to control communication of the respective subscriber station 10, 20, 30 via the bus 40 with at least one other subscriber station of the subscriber stations 10, 20, 30 that are connected to the bus 40.

[0053] The communication control device 11 creates and reads first messages 45, 47, which are, for example, modified CAN messages 45, 47. The modified CAN messages 45, 47 are structured, for example, based on the CAN XL format. The transmitting / receiving device 12 serves to transmit and receive the messages 45, 47 from the bus 40. The transmitting module 121 receives a digital transmit signal TxD created by the communication control device 11 for one of the messages 45, 47 and converts this into signals on the bus 40. The digital transmit signal TxD can be a pulse-width modulated signal, at least temporarily or in sections. The receiving module 122 receives signals transmitted on the bus 40 corresponding to the messages 45 to 47 and generates a digital receive signal RxD therefrom. The receiving module 122 sends the receive signal RxD to the communication control device 11.

[0054] In addition, the communication control device 11 can be configured to create and read second messages 46, which are, for example, CAN SIC messages 46. The transmitting / receiving device 12 can be configured accordingly.

[0055] The communication control device 21 can be designed like a conventional CAN controller according to ISO 11898-1:2015, i.e. like a CAN FD-tolerant Classical CAN controller or a CAN FD controller or a CAN SIC controller. The communication control device 21 creates and reads second messages 46, for example CAN FD messages or CAN SIC messages. The transmit / receive device 22 serves to transmit and receive the messages 46 from the bus 40. The transmit module 221 receives a digital transmit signal TxD created by the communication control device 21 and converts it into signals for a message 46 on the bus 40. The receive module 222 receives signals transmitted on the bus 40 corresponding to the messages 45 to 47 and generates a digital receive signal RxD therefrom. The transmitting / receiving device 22 may be designed as a conventional CAN FD transceiver or CAN-SIC transceiver.

[0056] To send messages 45, 46, and 47 with CAN SIC or CAN XL, proven features are adopted that are responsible for the robustness and user-friendliness of CAN and CAN FD, in particular the frame structure with identifier and arbitration according to the well-known CSMA / CR method. The CSMA / CR method requires so-called recessive states on bus 40, which can be overwritten by other subscriber stations 10, 20, and 30 with dominant levels or dominant states on bus 40.

[0057] The two subscriber stations 10, 30 can generate and then transmit messages 45, 47 using various CAN formats, in particular the CAN FD format, the CAN SIC format, or the CAN XL format, as well as receive such messages 45, 47. This is described in more detail below for one message 45.

[0058] Fig. 2shows a frame 450 for message 45, which is in particular a CAN XL frame, as provided by the communication control device 11 for the transmitting / receiving device 12 for transmission on the bus 40. In this embodiment, the communication control device 11 creates the frame 450 as compatible with CAN FD. Alternatively, the frame 450 is compatible with any successor standard to CAN FD.

[0059] According to Fig. 2The frame 450 for CAN communication on the bus 40 is divided into different communication phases 451, 452, namely an arbitration phase 451 (first communication phase) and a data phase 452 (second communication phase). After a start bit SOF, the frame 450 has an arbitration field 453, a control field 454, a first switching field 455, a data field 456, a checksum field 457, a second switching field 458, and a frame termination field 459. The checksum field 457, the second switching field 458, and the frame termination field 459 form a frame end phase 457, 458, 459 of the frame 450.

[0060] In the arbitration phase 451, using an identifier (ID) in the arbitration field 453, the subscriber stations 10, 20, 30 negotiate bit by bit to determine which subscriber station 10, 20, 30 wishes to send the message 45, 46 with the highest priority and will therefore receive exclusive access to the bus 40 of the bus system 1 for the next transmission time in the subsequent data phase 452. In the arbitration phase 451, a physical layer is used, similar to CAN and CAN-FD. The physical layer corresponds to the physical layer or layer 1 of the well-known OSI model (Open Systems Interconnection Model).

[0061] During phase 451, the well-known CSMA / CR method is used, which allows simultaneous access of the subscriber stations 10, 20, 30 to the bus 40 without destroying the higher-priority message 45, 46. This allows additional bus subscriber stations 10, 20, 30 to be added to the bus system 1 relatively easily, which is very advantageous.

[0062] The CSMA / CR method requires so-called recessive states on bus 40, which can be overwritten by other subscriber stations 10, 20, or 30 with dominant levels or dominant states on bus 40. In the recessive state, high-impedance conditions prevail at the individual subscriber stations 10, 20, or 30, which, in combination with the parasitics of the bus circuitry, results in longer time constants. This limits the maximum bit rate of today's CAN FD physical layer to approximately 2 megabits per second in real-world vehicle use.

[0063] At the end of the arbitration phase 451, the first switching field 455 is used to switch to the data phase 452.

[0064] In the data phase 452, in addition to a portion of the first switching field 455, the payload of the CAN-XL frame 450 or message 45 from the data field 456, as well as the checksum field 457 and a portion of the second switching field 458, are transmitted. At the end of the data phase 452, the system switches back to the arbitration phase 451 using the second switching field 458.

[0065] A sender of the message 45 begins sending bits of the data phase 452 to the bus 40 only when the subscriber station 10 as the sender has won the arbitration and the subscriber station 10 as the sender thus has exclusive access to the bus 40 of the bus system 1 for sending.

[0066] Thus, in the arbitration phase 451 as the first communication phase, the subscriber stations 10, 30 partially use, particularly up to the FDF bit (inclusive), a format known from CAN / CAN-FD according to ISO 11898-1:2015. However, compared to CAN or CAN FD, in the data phase 452 as the second communication phase, an increase in the net data transmission rate is possible, particularly to over 10 megabits per second. Furthermore, an increase in the size of the payload data per frame is possible, particularly to approximately 2 kbytes or any other value.

[0067] As in Fig. 3 As shown, the transmitting / receiving devices 12 use a first physical layer 451_P in the arbitration phase 451 to generate a transmit signal TxD ( Fig. 1) over time t as signals CAN_H, CAN_L on the bus 40. The same applies to the transmitting / receiving device 22. In contrast, the transmitting / receiving device 12 can use a second physical layer 452_P in the data phase 452, which is different from the first physical layer 451_P, to transmit the transmit signal TxD ( Fig. 1 ) as CAN_H, CAN_L signals on bus 40, as previously described. There are two operating modes for the physical layer 452_P, namely FAST_TX and FAST_RX, as described in more detail below.

[0068] Fig. 3shows on the left that in the arbitration phase 451, the subscriber stations 10, 20, and 30 each transmit signals CAN_H and CAN_L over time t to the bus 40, which have a first bit duration t_bt1. The signals CAN_H and CAN_L are serial signals and alternately have at least one dominant state 401, in which VCAN_H = 3.5 V and VCAN_L = 1.5 V, or at least one recessive state 402, in which VCAN_H = VCAN_L = 2.5. A dominant state 401 (dom) is driven during NRZ coding of the transmission signal TXD in phase 451 when TXD = 0 or LW (LOW). A recessive state 402 (rec) is generated, or occurs during NRZ encoding of the transmitted signal TXD in phase 451 if TXD = 1 or HI (HIGH). After arbitration in arbitration phase 451, one of the subscriber stations 10, 20, or 30 is determined to be the winner.

[0069] If the respective subscriber station 10, 20, 30 detects the signaling in the first switching field 455 of Fig. 2 For switching from the first to the second communication phase 451, 452, the associated transmitting / receiving device 12 switches its physical layer 451_P at the end of the arbitration phase 451 from a first operating mode (SLOW), which can alternatively be implemented as a SIC operating mode, to the physical layer 452_P of the data phase 452. For this purpose, the operating modes of the data phase 452 are activated as follows.

[0070] Assume that the first subscriber station 10 has won the arbitration. Then, the transmitting / receiving device 12 of the subscriber station 10 switches, in particular due to a signal in the first switching field 455 of Fig. 2, converts its physical layer 451_P at the end of the arbitration phase 451 from the first operating mode (SLOW) to the physical layer 452_P of the data phase 452 for a second operating mode (FAST_TX) of the transmitting / receiving device 12, since the subscriber station 10 is the sender of the message 45 in the data phase 452. As in Fig. 3As shown, in the data phase 452 or in the second operating mode (FAST_TX), the transmit module 121 then generates the states LV0 or LV1 with the physical layer 452_P for the signals CAN_H, CAN_L on the bus 40, one after the other and thus serially, depending on a transmit signal TxD. The state LV0 (VCAN_H = 3.0 V, VCAN_L = 2.0 V) is driven for a first PWM symbol in the transmit signal TXD during pulse width modulation (PWM coding) of the transmit signal TXD. The state LV1 (VCAN_H = 2.0 V and VCAN_L = 3.0 V) is driven for a second PWM symbol, which differs from the first PWM symbol, in the transmit signal TXD during pulse width modulation (PWM coding) of the transmit signal TXD.

[0071] The frequency of the signals CAN_H, CAN_L can be increased in the data phase 452. In the example of Fig. 3For this purpose, the bit time or bit duration t_bt2 in the data phase 452 is shorter or less than the bit time or bit duration t_bt1 in the arbitration phase 451. Thus, the net data transmission rate in the data phase 452 in the example of Fig. 3 increased compared to the arbitration phase 451.

[0072] In contrast, for example, the transmitting / receiving device 12 of the subscriber station 30 switches its physical layer 451_P at the end of the arbitration phase 451 from the first operating mode (SLOW or SIC) to the physical layer 452_P of the data phase 452 for a third operating mode (FAST_RX) of the transmitting / receiving device 12, since the subscriber station 30 is only a receiver, i.e. not a transmitter, of the frame 450 in the data phase 452.

[0073] If the transmitting / receiving device 12 detects, in particular with the signaling in the second switching field 458 of Fig. 2If a switchover from the data phase 452 back to the arbitration phase 451 is required, the transmitting / receiving device 12 is switched from transmitting (FAST_TX mode) and / or receiving (FAST_RX mode) signals with the physical layer 452_P to transmitting and / or receiving signals with the physical layer 451_P. Thus, after the end of the data phase 452, all transmitting / receiving devices 12 switch their operating mode to the first operating mode (SLOW or SIC). Thus, all transmitting / receiving devices 12 can not only switch between the bit durations t_bt1, t_bt2, but also switch their physical layer, as previously described.

[0074] The course of the corresponding signals in the transmitting / receiving device 12 during the switchover from phase 451 to phase 452, during the data phase 452 and during the switchover from phase 452 back to phase 451 is explained in more detail below with reference to Fig. 10 to Fig. 15.

[0075] According to Fig. 4 In the arbitration phase 451, a differential signal VDIFF = CAN_H - CAN_L with values ​​of VDIFF = 2V for dominant states 401 (dom) and VDIFF = 0V for recessive states 402 (rec) is ideally formed on the bus 40 over time t. The course of VDIFF in phase 451 is shown on the left side in Fig. 4 In contrast, in the data phase 452, a difference signal VDIFF = CAN_H - CAN_L is formed on the bus 40 over time t, corresponding to the states LV0, LV1 of Fig. 4 as shown on the right side in Fig. 4 shown. The LV0 state has a value of VDIFF = 1V. The LV1 state has a value of VDIFF = -1V.

[0076] The receiving module 122 can distinguish the states 401, 402 using two of the receiving thresholds T1, T2, T3, which are in the ranges TH_T1, TH_T2, TH_T3. For this purpose, the receiving module 122 samples the signals from Fig. 3 or Fig. 4 at times t_A, as in Fig. 4shown. To evaluate the sampling result, the receiving module 122 uses the receiving threshold T1 of, for example, 0.7 V and the receiving threshold T2 of, for example, -0.35 V in the arbitration phase 451. In contrast, the receiving module 122 in the data phase 452 only uses signals that were evaluated with the receiving threshold T3. When switching between the first to third operating modes (SLOW or SIC, FAST_TX, FAST_RX), which were previously described with respect to Fig. 3 described, the receiving module 122 switches the receiving thresholds T2, T3 respectively.

[0077] The reception threshold T2 is used to detect whether the bus 40 is free when the subscriber station 12 is newly connected to the communication on the bus 40 and attempts to integrate itself into the communication on the bus 40.

[0078] Upon receiving the corresponding signals from the bus 40, each transmitting / receiving device 12 generates the corresponding receive signal RxD, as shown in Fig. 1shown. The received signal RxD ideally has no time offset from the transmitted signal TxD.

[0079] Fig. 5 shows an example of a part of the digital transmission signal TxD, which the transmission module 121 receives from the communication control device 11 in the arbitration phase 451, and from which it generates the signals CAN_H, CAN_L for the bus 40. In Fig. 5 the transmit signal TxD changes from a state LW (Low) to a state HI (High) and back to the state LW (Low).

[0080] As in Fig. 6 As shown in more detail, the transmitting module 121 generates the transmit signal TxD of Fig. 5the signals CAN_H, CAN_L for the bus wires 41, 42 such that an additional state 403 (sic) is present. The state 403 (SIC) can have different lengths, as shown with the state 403_0 (SIC) during the transition from the state 402 (rec) to the state 401 (dom) and the state 403_1 (sic) during the transition from the state 401 (dom) to the state 402 (rec). The state 403_0 (sic) is shorter in time than the state 403_1 (sic). In order to transmit signals according to Fig. 6 To generate the signal, the transmitter module 121 is switched to a SIC operating mode (SIC mode).

[0081] Passing through the short sic state 403_0 is not required in CiA610-3, and the state depends on the implementation type. The duration of the "long" state 403_1 (sic) is specified for CAN-SIC as well as for the SIC mode in CAN-XL as t_sic < 530ns, starting with the rising edge of the transmit signal TxD from Fig. 5 .

[0082] In the "long" state 403_1 (SIC), the transmit module 121 should match the impedance between the bus wires 41 (CANH) and 42 (CANL) as closely as possible to the characteristic impedance Zw of the bus line used. Zw=100 ohms or 120 ohms. This matching prevents reflections and thus allows operation at higher bit rates. For simplicity, we will always refer to state 403 (sic) or sic state 403 below.

[0083] The transmitter module 121 can be used to generate signals for the bus 40 for the following CAN types: CAN-FD, CAN-SIC and CAN-XL. Table 1: CAN types for transmitter module 121 CAN type Communication phases / bit rate Bus states Transmitter module states CAN-FD Arbitration dom, rec dom, rec CAN-SIC Arbitration dom, sic, rec dom, sic, rec CAN-XL Arbitration or arbitration and data field in case no switch to fast mode occurs dom, sic, rec dom, sic, rec CAN-XL Data phase LV0, LV1 LV0, LV1

[0084] Thus, the transmit module state 403 (sic) can be generated not only in CAN-SIC or CAN-XL (xl_sic). The transmit module state 403 (sic) can also be generated in CAN-FD. However, in CAN-FD, the time for the transmit module state 403 (sic) can be shorter than in CAN-SIC or CAN-XL.

[0085] The transmitter module 121 can thus generate two different bus states for CAN FD, three different bus states for CAN SIC and five different states for CAN XL.

[0086] Fig. 7 shows an example of another part of the digital transmission signal TxD, which the transmission module 121 receives in the data phase 452 from the communication control device 11, and from which it generates the signals CAN_H, CAN_L for the bus 40. In Fig. 7 the transmit signal TxD changes several times from the HI state (High = High) to a LW state (Low = Low) and back to a HI state (High = High) and so on.

[0087] As in Fig. 8As shown in more detail, the transmitting module 121 generates the transmit signal TxD of Fig. 7 The CAN_H and CAN_L signals for bus wires 41 and 42 are configured in such a way that the LV0 state represents a LW (Low) state. Furthermore, the LV1 state represents a HI (High) state.

[0088] Fig. 9 shows the transmitter module 121 for the transceiver 12 in more detail, which can be used for one of the subscriber stations 10, 30. The transmitter module 221 for the transceiver 22 can be constructed in the same way as the transmitter module 121 for the transceiver 12. Therefore, the transmitter module 221 is not described separately.

[0089] The transmitter module 121 is connected to the bus 40, more specifically, its first bus wire 41 for CAN_H or CAN-XL_H or LINE+ and its second bus wire 42 for CAN_L or CAN-XL_L or LINE-. Each of the transmitter stages 121A to 121D is connected to the bus 40.

[0090] The transmitter module 121 from Fig. 9 For example, the signals CAN_H, CAN_L can be Fig. 6 with states 401, 402, 403 and signals CAN_H, CAN_L according to Fig. 8 with the states LV0, LV1.

[0091] The transmitting module 121 has a first to fourth transmitting stage 121A, 121B, 121C, 121D and a control part 15. As in Fig. 9 As shown, the transmission stages 121A to 121D are connected as a full bridge. The control part 15 serves to control the transmission stages 121A, 121B, 121C, 121D according to the transmission signal TxD and the set operating mode SIC, FAST_TX of the transmission module 121. For this purpose, the control part 15 generates at least one signal N_A_1 for controlling the first transmission stage 121A, at least one signal N_B_1 for controlling the second transmission stage 121B, at least one signal N_C_1 for controlling the third transmission stage 121C and at least one signal N_D_1 for controlling the fourth transmission stage 121D. This is with respect to Fig. 10 to Fig. 12 described in more detail.

[0092] The voltage supply for supplying the first and second bus wires 41, 42 with electrical energy, in particular the CAN supply voltage of typically 5V, is provided via at least one terminal 43. The connection to ground, in particular CAN_GND, is realized via a terminal 44. The first and second bus wires 41, 42 are terminated with a terminating resistor 49. The terminating resistor 49 is connected into the full bridge as an external load resistor. The resistor 49 is connected into the bridge branch between the terminals for the bus wires 41, 42.

[0093] The first transmitter stage 121A of Fig. 9has a polarity reversal diode D_A, a transistor HVP_A, and a parallel circuit 121A1, in which a series circuit of a first switch S_A1 and a first resistor R_A1 are connected in parallel to at least one series circuit of an N-th switch S_AN and an N-th resistor R_AN for a first to N-th current stage, as described in more detail in Fig. 11 shown and described below, where N is a natural number > 1. With respect to the transmitting stage 121A, the number N is also referred to as N_A. The transistor HVP_A is a CMOS transistor, in particular a PMOS transistor, whose control in Fig. 9Not shown in detail to simplify the drawing. The abbreviation "CMOS" refers to a semiconductor device that uses both p-channel and n-channel MOSFETs on a common substrate. CMOS stands for "complementary metal-oxide-semiconductor." MOSFET stands for metal-oxide field-effect transistor.

[0094] The second transmitter stage 121B of Fig. 9has a polarity reversal diode D_B, a transistor HVN_B, and a parallel circuit 121B1, in which a series circuit of a first switch S_B1 and a first resistor R_B1 are connected in parallel to at least one series circuit of an N-th switch S_BN and an N-th resistor R_BN for a first to N-th current stage, where N is the natural number > 1. With respect to the transmitting stage 121B, the number N is hereinafter also referred to as N_B. The transistor HVN_B is a CMOS transistor, in particular an NMOS transistor, whose control in Fig. 9 is not shown in more detail to simplify the drawing.

[0095] The third transmitter stage 121C of Fig. 9has a polarity reversal diode D_C, a transistor HVP_C, and a parallel circuit 121C1, in which a series circuit of a first switch S_C1 and a first resistor R_C1 are connected in parallel with at least one series circuit of an N-th switch S_CN and an N-th resistor R_CN for a first to N-th current stage, where N is the natural number > 1. With respect to the transmitting stage 121C, the number N is hereinafter also referred to as N_C. The transistor HVP_C is a CMOS transistor, in particular a PMOS transistor, whose control in Fig. 9 is not shown in more detail to simplify the drawing.

[0096] The fourth transmission stage 121D of Fig. 9has a polarity reversal diode D_D, a transistor HVN_D, and a parallel circuit 121 D1, in which a series circuit of a first switch S_D1 and a first resistor R_D1 are connected in parallel with at least one series circuit of an N-th switch S_DN and an N-th resistor R_DN for a first to N-th current stage, where N is the natural number > 1. With respect to the transmitting stage 121D, the number N is hereinafter also referred to as N_D. The transistor HVN_D is a CMOS transistor, in particular an NMOS transistor, whose control in Fig. 9 is not shown in more detail to simplify the drawing.

[0097] Each series circuit of the parallel circuits 121A1, 121B1, 121C1, 121D1 implements a current stage S1 to SN of the transmitting stages 121A to 121D. For this purpose, the current stages S1 to SN of the transmitting stages 121A to 121D are designed as resistance stages, which can also be called resistance fingers. The resistance stages are set by selecting the resistance value of the respective current stage, for example, by selecting resistors R_A1 to R_AN for the transmitting stage 121A, etc. As a result of setting the resistance values ​​of the resistors, the currents and thus current stages generated by the corresponding transmitting stage 121A to 121D are set. The number N can be freely selected. In particular, the number N and thus the number of stages or resistance stages or current stages can be selected between 1 and 60. Alternatively, a number greater than 60 can be chosen for N.

[0098] Each of the polarity reversal diodes D_A, D_B, D_C, and D_D protects the corresponding transmitter stage against positive feedback to terminal 44 (CAN supply) and negative feedback to terminal 43 (CAN_GND). Each of the polarity reversal diodes D_A, D_B, D_C, and D_D can also be referred to as a blocking diode.

[0099] Each of the parallel circuits 121A1, 121B1, 121C1, 121D1, more precisely controlled by the control unit 15, sets / sets a resistance value for the associated transmitting stage 121A, 121B, 121C, 121D depending on the operating mode (SLOW or SIC, FAST_TX) of the transmitting module 121 and the transmitting signal TxD. The resistance value of the individual transmitting stage 121A, 121B, 121C, 121D can thus be adjusted depending on the operating mode (SLOW or SIC, FAST_TX) of the transmitting module 121 and the transmitting signal TxD. This is explained in more detail below using Fig. 10 to Fig. 12 and Table 2 and Table 3.

[0100] Each of the transistors HVP_A, HVN_B, HVP_C, and HVN_D is an HV cascode and can also be referred to as an HV standoff device. Transistor HVP_A protects parallel circuit 121A1 by absorbing high voltage drops. Each of the transistors HVN_B, HVP_C, and HVN_D performs the same function for the respective associated parallel circuit 121B1, 121C1, and 121D1. Each of the transistors HVP_A, HVN_B, HVP_C, and HVN_D can be controlled accordingly at its control terminal, in particular by control section 15 or another control device not shown.

[0101] In the transmitter module 121, the transmitter stage 121A is connected between the voltage supply terminal 43 and the CAN_H terminal 41. The transmitter stage 121C is connected between the voltage supply terminal 43 and the CAN_L terminal 42 and the CAN_GND terminal 43. The transmitter stage 121D is connected between the CAN_H terminal 41 and the CAN_GND terminal 43. The transmitter stage 121B is connected between the CAN_L terminal 42 and the CAN_GND terminal 43. The transmitter stage 121B is connected between the CAN_L terminal 42 and the CAN_GND terminal 43. The transmitter stage 121A is thus connected to the CAN_GND path in the transmitter module 121. Second, transmit stage 121D is connected to the CANH path. Second, transmit stage 121C is connected to the CANL path. Second, transmit stage 121B is connected to the CANL path.

[0102] The signals CAN_H, CAN_L form the differential signal that is sent from the transmitting module 121 to the bus 40.

[0103] Thus, the transmit module 121 in the CANH path and the CANL path consists of a parallel circuit 121A1, 121B1, 121C1, 121D1 of a predetermined number of current stages or resistance fingers, as described above. The parallel circuit of all current stages in the CANH path and the CANL path is connected in series with an HV cascode HVP_A, HVN_B, HVP_C, HVN_D and a polarity reversal diode D_A, D_B, D_C, D_D, as described above. The HV cascodes HVP_A, HVN_B, HVP_C, HVN_D enable compliance with limit values ​​(maximum rating parameters), such as voltage at CANH and CANL from -27V to +40V.

[0104] The basic functionality of the circuit of Fig. 9depending on the operating mode of the transmit module 121 and the bus state 401 (dom), 403 (sic), 402 (rec) in the SIC operating mode (arbitration phase 451) and LV0, LV1 in the data phase 452 is based on Fig. 10 to Fig. 12 and the following tables 2, 3.

[0105] Fig. 10 shows the control part 15 of the transmitting module 121 for the transmitting / receiving device 12 in more detail, which can be used for the subscriber stations 10, 30 of the bus system 1. The transmitting / receiving device 22 for the subscriber station 20 can be constructed in the same way as described below for the transmitting / receiving device 12.

[0106] The control section 15 has a state processing block 151, a step generator 152, a logic block 153, and a memory block 154. The transmission signal TxD is input to the control section 15. The control section 15 generates a control signal for the transmission stages 121A to 121D from this signal. The state processing block 151, the step generator 152, and the logic block 153 form a control chain or chain for stepwise generation of the transmission currents of the transmission module 121, which are required for a low-emission transition between two bus signal states or bus states 401, 402, 403, LV0, LV1.

[0107] In Fig. 10The state processing block 151 has an evaluation unit 1511 and a signal generation unit 1512. The evaluation unit 1511 evaluates the transmission signal TxD with respect to the current signal state of the digital transmission signal TxD and the operating mode selected for the transmission module 121. The evaluation result of the evaluation unit 1511 for a received transmission signal TxD according to Fig. 5 or Fig. 7 can therefore be HI (high) or LW (low). The operating mode (SIC, FAST_TX) to which the transmit module 121 is switched then determines which of the bus signal states or bus states 401, 402, 403, LV0, LV1 is to be generated. Furthermore, the evaluation unit 1511 can evaluate whether the signal state of the digital transmit signal TxD has changed compared to the previous signal state of the digital transmit signal TxD and / or whether the operating mode of the transmit module 121 has changed.

[0108] The signal generation unit 1512 is configured to generate signals S_SL, S_SW, S_ST if the evaluation result of the evaluation unit 1512 indicates that switching between two of the bus states 401, 402, 403, LV0, LV1 is to be performed and thus a transition between two of the bus states 401, 402, 403, LV0, LV1 is to be generated. Accordingly, the signal generation unit 1512 generates a selection signal S_SL, a slew rate signal S_SW, and a step start signal S_ST depending on the evaluation of the evaluation unit 1511. The signals S_SL, S_SW, S_ST differ depending on the type of transition, for example, from state 401 (dom) to state 403 (sic). Optionally, at least one of the signals S_SL, S_SW, S_ST is generated using parameters 151P. The parameters 151P may be stored in the signal generation unit 1512 or are available by accessing the memory block 154.

[0109] The signal generation unit 1512 outputs the selection signal S_SL to the logic block 153. In contrast, the signal generation unit 1512 outputs the slew rate signal S_SW, the step start signal S_ST, and the reset signal S_RS to the step generator 152.

[0110] When the control of a transition between the two bus signal states is completed, for example for a transition from state 401 (dom) to state 403 (sic), the signal generation unit 1512 generates a reset signal S_RS.

[0111] The step generator 152 has an evaluation unit 1521 and a signal generation unit 1522. The evaluation unit 1521 evaluates the slew rate signal S_SW and the step start signal S_ST. Based on this evaluation, the signal generation unit 1522 generates a step signal S<1:X> and outputs it to the logic block 153, as described in more detail below. X is any natural number greater than 1. The step signal S<1:X> is designed to stepwise change the resistance values ​​and thus the transmission currents of the transmission stages 121A, 121B, 121C, 121D of the transmission module 121.

[0112] Logic block 153 can be configured as programmable logic. Logic block 153 controls transmission stages 121A, 121B, 121C, 121D of transmission module 121, in particular using control units 153A, 153B, 153C, 153D and parameters 154P. Parameters 154P are stored in memory block 154. Control unit 153A is configured to control transmission stage 121A, in particular its parallel circuit 121A1. Control unit 153B is configured to control transmission stage 121B, in particular its parallel circuit 121B1. Control unit 153C is configured to control transmission stage 121C, in particular its parallel circuit 121C1. The control unit 153D is designed to control the transmitting stage 121D, in particular its parallel circuit 121D1.

[0113] In the memory block 154, for all permitted transitions between signal states on the bus 40, setpoints, in particular as parameters 154P, for the parallel circuits 121A1, 121B1, 121C1, 121D1 of Fig. 9 stored. In a CAN bus system, the transitions are, for example, the transition from state 401 (dom) to state 403 (sic), the transition from state 403 (sic) to state 401 (dom), the transition from state LV0 to state LV1, and the transition from state LV1 to state LV0, and so on.

[0114] The logic block 153 is designed to carry out a control which determines the setpoints for the parallel circuits 121A1, 121B1, 121C1, 121D1 from Fig. 9 The setpoints for the parallel circuits 121A1, 121B1, 121C1, 121D1 of Fig. 9stored in the parameters 154P can be adjusted as desired so that, in particular, the emissions of the transmitter module 121 are low, so that the requirements for electromagnetic compatibility (EMC) of the transmitter module 121 are met.

[0115] The following Tables 2 and 3 show an example of setpoints that can be stored in the memory block 154. In the example of Tables 2 and 3, the logic block 153 controls the parallel circuits 121A1, 121B1, 121C1, 121D1 of Fig. 9 such that the parallel circuits 121A1, 121B1, 121C1, 121D1 of Fig. 9successively assume 30 different resistance values ​​R_A, R_B, R_C, R_D. As a result, for each of the 30 steps S1 to S30, different differential resistances R_DIFF or impedances of the transmitting stages 121A / 121B and 121C / 121D and different differential voltages VDIFF on the bus 40 are established, as indicated in Table 2. Thus, the transition 401 to 403 is completed in 30 steps S1 to S30. Table 3 specifies the number N_A of actively switched resistance fingers for the transmitting stage 121A, the number N_B of actively switched resistance fingers for the transmitting stage 121B, the number N_C of actively switched resistance fingers for the transmitting stage 121C, and the number N_D of actively switched resistance fingers for the transmitting stage 121D of the transmitting module 121.

[0116] The steps S1 to S30 are also referred to below as intermediate states on the bus 40. Table 2: Example electrical setpoints for transition 401 to 403 in 30 steps S1 to S30 or S1, ... S30 according to the number of resistance fingers in Table 3 Condition Step / intermediate state V_DIFF (V) R_DIFF (Ohms) R_A (Ohm) R_B (Ohm) R_C (Ohm) R_D (Ohm) 401 (cathedral) S0 2 40 20 20 infinite infinite Intermediate state S1 1,96 41 21 21 7k 7k Intermediate state S2 1,9 43 22 22 2.3k 2.3k Intermediate state ... ... ... ... ... ... ... Intermediate state S29 0,03 99 96 96 101 101 403 S30 0 100 100 100 100 100 Table 3: Example number of resistance fingers in parallel circuits 121A1, 121B1, 121C1, 121D1 of Fig. 9 for transition 401 to 403 in 30 steps S1 to S30 or S1, ... S30 for CAN XL for single resistance fingers with R_finger = 10 kOhm, reverse polarity diode protection voltages of 0.7V, Condition Step / intermediate state N / A N_B N_C N_D 401 (cathedral) S0 500 500 0 0 Intermediate state S1 485 485 1 1 Intermediate state S2 461 461 4 4 Intermediate state ... ... ... ... ... Intermediate state S29 104 104 98 98 403 S30 100 100 100 100

[0117] Power supply voltage Vcc = 5V at terminal 43 and an impedance Z_Bus = 50 Ohm for resistor 49

[0118] During operation of the transmit module 121, the state processing block 151 uses the transmit signal TxD at the input to decide when which transition is carried out, in particular with the evaluation unit 1511.

[0119] To initiate a transition, in particular from bus state 401 (dom) to bus state 403 (sic), the corresponding combination circuit for the number N_A, N_B, N_C, and N_D of resistors R_A1, etc., in parallel circuits 121A1, 121B1, 121C1, 121D1 is first selected by the selection signal S_SL in logic block 153. In addition, in particular simultaneously, the desired signal slew rate for the bus signal (CAN_H; CAN_L) is set for the upcoming transition according to the specification of the slew rate signal S_SW, and the chain, in particular the step generator 152, is reset to an initial value via the reset signal S_RS.

[0120] The circuit of Fig. 10This thus forms a delay chain that successively runs through the aforementioned steps S1 to SX in one direction. This simplifies the circuitry of a transition. Furthermore, the current consumption is reduced compared to a circuit with more than one delay chain, particularly with three delay chains or three times two delay chains, as previously described with reference to the prior art.

[0121] The state processing block 151 is configured to generate the step start signal S_ST such that the step generator 152 is only started after a predetermined delay time to complete the transition between the bus states. Thus, the delay chain is only started or triggered after a predetermined delay time to complete the transition between the two consecutive bus states. For example, the predetermined delay time is approximately 1 ns, in particular a time between 1 ns and 5 ns. The predetermined delay time ensures that both the step generator 152 and the logic block 153 are ready to complete the desired transition between the bus states.

[0122] The step generator 152, in particular its signal generation unit 1522, thus generates the control signals or step signals for the steps S1, ..., SX, which signals change their state one after the other at time intervals t_D1, t_DX, in particular to HI (high).

[0123] Fig. 11 shows an example of a curve of the bus voltage U in relation to the maximum voltage Um of the transition, which is generated by the control part 15 of Fig. 10 for the transmitting stage 121 between the states 401 (dom) and 403 (sic). Fig. 11 In the example shown, the control part 15 controls the transition over time t in steps S1, ..., SX and time intervals t_D1,..., t_DX. For the sake of clarity, Fig. 11 not all steps S1 to SX, which correspond to intermediate states on bus 40, and time intervals t_D1,..., t_DX are labeled.

[0124] The example of Fig. 11shows an asynchronous time step generation for generating the transition between the bus signal states 401 (dom), 403 (sic). Such time step generation by means of the control section 15 asynchronously specifies a fixed form of time steps S1, ..., SX for the transition, which, as individual signals for each of the intermediate states or steps S1, ..., SX, form the output of the step generator 152 and the control section 15. This also results in a predetermined rise time Δt_R of the edge between the two states on the bus 40.

[0125] The ratio of the length of a time step t_Dn to the total switching time t_S = t_D1 + ... + t_DX is constant. In the middle (the steepest part of the curve), the time steps are short and longer at the beginning and end. The total length t_S of the transition can be adjusted by setting a bias current to adjust the slew rate of the transition.

[0126] The transition between two states 401, 402, 403, LV0, and LV1 can be freely selected. By using longer time steps t_D1, ... t_DX at the beginning and end of the transition or sequence than in the middle, a spectrally optimal, "smooth" overall transition from one state to the other can be approximated.

[0127] The advantage of the previously described asynchronous step chain for the transmitting module 121 compared to a synchronous step chain controlled by a regular clock signal is primarily that the described step chain of the transmitting module 121 has significantly better emission behavior.

[0128] The reason for this is that the high-frequency spectral components of the signals on bus 40 are distributed more evenly across the frequency range rather than being concentrated at integer multiples of the clock frequency. For the same number of steps per transition or step sequence, the spectrum peak is significantly lower over the high-frequency range of 100 MHz to 3 GHz.

[0129] The speed of the step chain then defines the time in which this transition between states occurs. The speed of transitions 401, 402, 403, LV0, LV1 is limited only by the maximum switching speed of the resistor fingers used in the transmitting stages 121A, 121B, 121C, 121D.

[0130] To ensure a transition in accordance with Fig. 11 on the bus 40, each of the four resistor arrays or parallel circuits 121A1, 121B1, 121C1, 121D1 in the H-bridge of Fig. 9individual resistance cells, for each of which a control cell is provided in the logic block 153, as can be seen from Fig. 12 described.

[0131] Fig. 12 shows an example of one of the resistance cells 121A1_1 and a corresponding control cell 153A_1 for the parallel circuit 121A1 for the intermediate state or time step S1. For each time step S1, ..., SX, there is one resistance cell 121A1_1 and one corresponding control cell 153A_1 per parallel circuit 121A1, 121B1, 121C1, 121D1, as shown in Fig. 12 shown. All control cells 153A_1 for steps S2 to SX are identically constructed.

[0132] Accordingly, the transmitter module 121 has a total of 30 resistance cells 121A1_1 per individual transmitter stage 121A1, 121B1, 121C1, 121D1. Thus, each parallel circuit 121A1, 121B1, 121C1, 121D1 has a total of 30 resistance cells 121A1_1. In the present example for controlling 30 time steps, the transmitter module 121 has 4 times 30 = 120 resistance cells 121A1_1 and 4 times 30 = 120 control cells 153A_1.

[0133] According to Fig. 12The resistance cell 121A1_1 has binary-weighted switchable resistance elements S_A1, R_A1, etc., which are interconnected in resistance blocks 161, 162, 163, 164. The resistance values ​​of the resistance elements S_A1, R_A1, etc. and / or the resistance blocks 161, 162, 163, 164 can be selected as required for the individual resistance cell 121A1_1. The resistance values ​​of the resistance elements S_A1, R_A1, etc. and the resistance blocks 161, 162, 163, 164 can be identical or at least partially different for the resistance cells 121A1_1 of the individual transmission stages 121A1, 121B1, 121C1, 121D1.

[0134] Each of the parallel circuits 121A1, 121B1, 121C1, 121D1 thus has binary weighted switchable resistance elements which are used for the respective step S1 to SX ( Fig. 11 ) according to the step signal S<1:X> of Fig. 10 be switched on appropriately. In the example of Fig. 12 The resistance cell 121A1_1 can be switched with 4 bits.

[0135] Fig. 12 shows the configuration of the resistor cell 121A1_1 of the parallel circuit 121A1 for the example in which 16 resistor fingers or resistor elements are connected in four resistor blocks 161, 162, 163, 164, which have switches S_A1 to S16 and resistors R_A1 to R_A16. Therefore, N = 16 applies. The parallel circuits 121B1, 121C1, 121D1 are configured in the same way in this example and are therefore not described separately.

[0136] For example, resistors R_A1 to R_A16 all have the same resistance value. As an example, the resistance value of 8 kOhm is assumed below for each of resistors R_A1 to R_A16. Switches S_A1 to S16 can be CMOS transistors, particularly PMOS transistors. The same applies to switches S_A1 to S16 of parallel circuit 121C1. Switches S_A1 to S16 of parallel circuits 121B1, 121D1 can be CMOS transistors, particularly NMOS transistors.

[0137] The first resistor block 161 has a resistance in a series circuit formed by the first switch S_A1 and the first resistor R_A1. When the first switch S_A1 is switched on, the resistor block 161 acts in the resistor cell 121A1_1 with a total resistance of 8 kOhm in the example mentioned.

[0138] The second resistor block 162 has two resistors R_A2, R_A3 in two parallel series circuits. Thus, the block 162 has a series circuit consisting of a second switch S_A2 and a second resistor R_A2, and a series circuit consisting of a third switch S_A3 and a third resistor R_A3. When the second and third switches S_A2, S_A3 are conductive, the resistor block 162 acts in the resistor cell 121A1_1 with a total resistance of 4 kOhm.

[0139] The third resistor block 163 has four resistors R_A4 to R_A7 in four parallel series circuits. Thus, block 163 has a series circuit consisting of a fourth switch S_A4 and a fourth resistor R_A4, up to a series circuit consisting of a seventh switch S_A7 and a seventh resistor R_A7. When the fourth to seventh switches S_A4 to S_A7 are conductive, resistor block 163 acts in resistor cell 121A1_1 with a total resistance of 2 kOhm.

[0140] The fourth resistor block 164 has eight resistors R_A8 to R_A16 in eight parallel series circuits. Thus, block 164 has a series circuit consisting of an eighth switch S_A8 and an eighth resistor R_A8, up to a series circuit consisting of a sixteenth switch S_A16 and a sixteenth resistor R_A16. If the eighth to sixteenth switches S_A8 to S_A16 are conductive, resistor block 164 acts in resistor cell 121A1_1 with a total resistance of 1 kOhm.

[0141] For the sake of clarity, Fig. 12 Not all resistors of the resistors R_A1 to R_A16 and switches of the switches S_A1 to S16 are provided with a reference symbol.

[0142] The control unit 153A has four D flip-flops 3A1, 3A2, 3A3, 3A4. One of the bits N_A_1<0:3> of a binary number is connected to the D input of each of the flip-flops 3A1, 3A2, 3A3, 3A4. For the first D flip-flop 3A1 in Fig. 12The respective bit of the binary number N_A_1<0:3> is designated as A_1_0. For the second D flip-flop 3A2 in Fig. 12 The respective bit of the binary number N_A_1 <0:3> is designated as A_1_1. For the third D flip-flop 3A3 in Fig. 12 The respective bit of the binary number N_A_1<0:3> is designated as A_1_2. For the fourth D flip-flop 3A4 in Fig. 12 the respective one bit of the binary number N_A_1<0:3> is called A_1_3.

[0143] The binary number was converted by the signal generation unit 1512 into Fig. 10 selected from memory block 154 by selection signal S_SL. The bits N_A_1<0:3> of the binary number, i.e., the signals A_1_0, A_1_1, A_1_2, A_1_3, control which of the switches of the four resistor arrays 161 to 164 should be conductive after completing the step, i.e., step S1 in this case. An output acts for this purpose. Qof the first D-flip-flop 3A1 to the switch S_A1 of the first resistor block 161. An output Q of the second D-flip-flop 3A2 acts on the switches S_A2, S_A3 of the second resistor block 162. An output Q of the third D-flip-flop 3A3 acts on the switches S_A4 to S_A7 of the third resistor block 163. An output Q of the fourth D flip-flop 3A4 acts on the switches S_A8 to S_A16 of the fourth resistor block 164.

[0144] At the input C of each of the four D flip-flops 3A1, 3A2, 3A3, 3A4 there is a step signal or signal for step S1 as an example.

[0145] As soon as a rising edge in the signal for step S1 arrives at the input C of one of the D flip-flops 3A1, 3A2, 3A3, 3A4, the value of the signal at the input D is sent to the inverting output Qadopted, since the switches S_A1 to S_A16 in the example shown are designed as PMOS transistors. However, if the switches S_A1 to S_A16 are designed as NMOS transistors, as in the parallel circuits 121B1, 121D1, instead of the output Q the output Q is used to control the switches S_A1 to S16.

[0146] This allows at least one of the resistance blocks 161, 162, 163, 164 to be switched on.

[0147] The same control is performed, in particular simultaneously, for the resistance blocks 161, 162, 163, 164 of the resistance cells of the parallel circuits 121B1, 121C1, 121D1. Furthermore, such control is subsequently performed for the at least one next step S_X for the resistance blocks 161, 162, 163, 164 of the resistance cells of the parallel circuits 121A1, 121B1, 121C1, 121D1.

[0148] Once the entire transition is complete, depending on the values ​​controlled and then set by the control section 15, each resistance cell 121A1_1 of the parallel circuit 121A1 can have one of 16 equivalent resistance values ​​between infinity, at which all switches S1 to S16 are open, and a resistance value of approximately 533 ohms, at which all switches S1 to S16 are closed. Thus, each resistor array or each parallel circuit 121A1 can have a possible equivalent resistance value between infinity, at which all switches S1 to S16 are open, and a resistance value of approximately 18 ohms, at which all switches S1 to S16 are closed. The same applies to the parallel circuits 121B1, 121C1, 121D1 and their resistance cells 121A1.

[0149] This allows for simple adaptations to perform calibrations for individual components as well as for the development of transmitter modules 121 for standards other than those applicable to a CAN bus system. In particular, the transmitter module 121 can represent or generate all static states permitted in CAN-XL and / or 10Base-T1S, including their intermediate states. These intermediate states can also be called transition states.

[0150] By bundling the individual resistance fingers or resistance elements S_A1, R_A1, etc. into the resistance blocks 161, 162, 163, 164 with the binary coding, this solution results in only 30*4=120 control lines from the logic block 153 to the H-bridge of the transmitter module 121 per array for 450 individual resistance fingers. The transmitter module 121 guarantees that no more resistance fingers or resistance elements S_A1, R_A1, etc. than necessary are switched at once.

[0151] This avoids large switching peaks that would occur if, for example, the 450 resistance fingers or resistance elements S_A1, R_A1, etc. of a transmitter module 121 were directly controlled binary with nine lines, such as during a transition from 255 to 256 (binary: 011111111 to 100000000). During such a transition from 255 to 256 (binary: 011111111 to 100000000), conductive fingers would switch each individual line.

[0152] A further advantage is that even in the event of unforeseen incomplete transitions, no abrupt changes are possible at the output of the transmitter module 121. This is because, even after resetting the chain, the changes only occur or run step by step. This ensures continuous output and is thus beneficial for the emission behavior of the transmitter module 121 and the associated transceiver device 12.

[0153] The Fig. 12The circuit implementation of logic block 153 shown, which controls a logic function N(X, transition), where N = (N_A, N_B, N_C, N_D) is the vector of active resistance fingers that should be active at step S_X of a selected transition, is only one possibility for the implementation of logic block 153.

[0154] In general, logic functions N(X, transition) can be implemented for all transitions on the bus. The implementations of the different transitions can vary.

[0155] In addition, although the Fig. 12 The circuit implementation of the logic block 153 shown is circuit-technically uncomplicated and robust, but, for example, only allows for limited large steps or intermediate states for the transition.

[0156] The logic block 153 and / or the control of the switches for the resistors of the transmitting stages 121A, 121B, 121C, 121D can therefore enable a different design of the steps or intermediate states than in Fig. 11 shown or described in Tables 2 and 3 above. In particular, the logic block 153 and / or the control of the switches for the resistors of the transmit stages 121A, 121B, 121C, 121D can make the size of the steps and / or the duration of the intermediate states more flexible.

[0157] All previously described embodiments of the transmitting module 121, the transmitting / receiving device 12, the subscriber stations 10, 20, 30, the bus system 1, and the method implemented therein according to the exemplary embodiment and its modifications can be used individually or in all possible combinations. In addition, the following modifications are particularly conceivable.

[0158] The bus system 1 described above is based on a bus system based on the CAN protocol. However, the bus system 1 according to the exemplary embodiment can alternatively be another type of communication network in which the signals are transmitted as differential signals.

[0159] It is advantageous, but not a necessary requirement, that in the bus system 1 an exclusive, collision-free access of a subscriber station 10, 20, 30 to the bus 40 is guaranteed at least for certain periods of time.

[0160] The bus system 1 according to the exemplary embodiment and its modifications is, in particular, a bus system in which communication can take place between at least two of the subscriber stations 10, 20, 30 according to two different CAN standards, such as CAN-HS or CAN FD or CAN SIC or CAN XL. Thus, the functionality of the previously described exemplary embodiment can be used, for example, in transmitting / receiving devices 12, 22 that are to be operated in such a bus system.

[0161] The number and arrangement of the subscriber stations 10, 20, 30 in the bus system 1 according to the embodiment and its modifications can be selected as desired.

Claims

1. A transmission module (121) for a transmission-reception device (12) of a subscriber station (10; 30) of a serial bus system (1), in which the transmission module (121) is designed to transmit a digital transmission signal (TxD) as an analog differential signal (CAN_H, CAN_L) to a bus (40) of the bus system (1) in order to send a message (45) to at least one other subscriber station (10; 20; 30) of the bus system (1), wherein the transmission module (121) has transmission stages (121A; 121B; 121C; 121D) with parallel circuits (121A1; 121VB1; 121C1; 121D1) made of switchable resistors (R_A1 ... R_AN; R_B1 ... R_BN; R_C1 ... R_CN; R_D1 ... R_DN), and a control part (15) for stepwise control of the switching of the switchable resistors (R_A1 ... R_AN; R_B1 ... R_BN; R_C1 ... R_CN; R_D1 ... R_DN), wherein at least two of the switchable resistors (R_A2, R_A3; RA4 ... R_A7; R_A8 ...R_A16) are arranged in a resistor block (162; 163; 164) so as to be switchable together, wherein at least two resistor blocks (161; 162; 163; 164) are provided which have at least one of the switchable resistors (R_A2, R_A3; RA4 ... R_A7; R_A8 ... R_A16), and wherein the control part (15) is designed to generate the bus states (401; 402; 403; LV0; LV1) predetermined by the digital transmission signal (TxD) over time (t) on the bus (40) by gradually changing the number of actively switched resistor blocks (162; 163; 164) over time (t).

2. The transmitter module (121) according to claim 1, wherein all switchable resistors (R_A1 ... R_AN; R_B1 ... R_BN; R_C1 ... R_CN; R_D1 ... R_DN) have approximately the same resistance value.

3. The transmission module (121) according to claim 1 or 2, wherein the resistance value of a first resistance block (161; 162; 163; 164) of the at least two resistance blocks (161; 162; 163; 164) is approximately half the resistance value of a second resistance block (161; 162; 163; 164) of the at least two resistance blocks (161; 162; 163; 164).

4. Transmission module (121) according to one of the preceding claims, further comprising a state processing block (151) for evaluating the digital transmission signal (TxD) in order to decide how the switchable resistors (R_A1 ...R_AN; R_B1 ...R_BN; R_C1 ...R_CN; R_D1 ...R_DN) of the parallel circuits (121A1; 121B1; 121C1; 121D1) are to be switched step by step in order to set the desired state (401; 402; 403; LV0; LV1) on the bus (40).

5. The transmission module (121) according to claim 4, wherein the state processing block (151) is configured to generate a slew rate signal (S_SW), and wherein the state processing block (151) is configured to generate the slew rate signal (S_SW) based on an evaluation result of the digital transmission signal (TxD).

6. The transmission module (121) according to claim 5, wherein the state processing block (151) is configured to generate a step start signal (S_ST), and wherein the state processing block (151) is configured to output the slew rate signal (S_SW) after being enabled by the step start signal (S_ST) for controlling the switchable resistors (R_A1 ... R_AN; R_B1 ... R_BN; R_C1 ... R_CN; R_D1 ... R_DN).

7. A transmission module (121) according to any one of the preceding claims, further comprising a step generator (152) for generating a step signal (S_ST) based on a slew rate signal (S_SW) and for outputting the step signal (S_ST) to a logic block (153) for controlling switches (S_A1 to S_AN; S_B1 ... S_BN; S_C1 ... S_CN; S_D1 ... S_DN) of the parallel circuit 121A1; 121B1; 121C1; 121D1) for switching the switchable resistors (R_A1 ... R_AN; R_B1 ... R_BN; R_C1 ... R_CN; R_D1 ... R_DN).

8. The transmission module (121) according to claim 7, wherein the state processing block (151) is configured to generate a reset signal (S_RS) for resetting the step generator (152) to an initial value.

9. Transmission module (121) according to one of the preceding claims, further comprising a logic block (153) for generating a control signal (N_A_1; N_B_1; N_C_1; N_D_1) for controlling the at least two resistor blocks (161; 162; 163; 164) of a transmission stage (121A, 121B, 121C, 121D).

10. The transmission module (121) according to claim 9, wherein the logic block (153) comprises at least two flip-flops (3A1; 3A2; 3A3; 3A4) arranged to generate a control signal (A_1_1; A1_2; A1_3; A1_4) for each of the at least two resistance blocks (161; 162; 163; 164), and wherein the logic block (153) is configured to generate the control signal (N_A_1; N_B_1; N_C_1; N_D_1) as a binary number with bits whose number is equal to the number of the at least two flip-flops (3A1; 3A2; 3A3; 3A4) and to output the bits to the at least two flip-flops (3A1; 3A2; 3A3; 3A4).

11. Transmission module (121) according to claim 9 or 10, further comprising a memory block (154) in which target values (154P) for the resistance values of the parallel circuits (121A1, 121B1, 121C1, 121D1) are stored, which target values are to be generated for transitions between signal states (401; 402; 403; LV0; LV1) on the bus (40) for each intermediate state (S1 ... SX) in the transition, wherein the state processing block (151) is designed to generate, on the basis of the evaluation of the digital transmission signal (TxD), a selection signal (S_SL) and to output the selection signal (S_SL) to the logic block (153), and wherein the logic block (153) is designed to generate the control signal (N_A_1; N_B_1; N_C_1; N_D_1) for controlling the at least two resistor blocks (161; 162; 163; 164) of a transmitting stage (121A, 121B, 121C, 121D) on the basis of the transitions selected by the selection signal (S_SL).

12. The transmission module (121) according to any one of claims 9 to 11, wherein the transmission module (121) has a resistance cell (121A1_1) for generating each intermediate state (S1, ..., SX) on the bus (40), in which resistance blocks (161, 162; 163; 164) are arranged, wherein the logic block (153) for controlling each intermediate state (S1, ..., SX) on the bus (40) has a control cell (153A_1) which is designed to control one of the resistance cells (121A1_1), and wherein all control cells (153A_1) for each intermediate state (S1, ..., SX) are constructed identically.

13. A transmission module (121) according to any one of the preceding claims, wherein first to fourth transmission stages (121A, 121B, 121C, 121D) are connected in a full bridge, in which the first and fourth transmission stages (121A, 121D) are connected in series and the third and second transmission stages (121C, 121B) are connected in series.

14. Transmission module (121) according to claim 13, wherein the first to fourth transmission stages (121A, 121B, 121C, 121D) for generating differential bus signals (CAN_L, CAN_H) for a bus (40) of the bus system (1) in response to the two different values of the digital transmission signal (TxD) are designed such that the transmission module (121; 121_0) in its first operating mode (SLOW; SIC) generates a first or second bus state (401, 402) on the bus (40) and in its second operating mode (FAST_TX) generates a third or fourth bus state (LV0, LV1), and wherein the bus signals (CAN_L, CAN_H) on the bus (40) form a differential voltage (VDIFF), the voltage value of which for the first to fourth bus states (401, 402, LV0, LV1) is different.

15. Transmitting / receiving device (12), comprising a transmitting module (121) according to one of the preceding claims, and a receiving module (122) for receiving signals (CAN_H, CAN_L) from the bus (40) and for generating a digital received signal (RxD) from the analog differential signal (CAN_H, CAN_L).

16. Transmitting / receiving device (12) according to claim 15, wherein the transmitting module (121) is designed to generate the analog differential signals (CAN_H, CAN_L) in a first communication phase (451) of the message (45) with a different physical layer (451_P) than in a second communication phase (452).

17. Subscriber station (20) for a serial bus system (1), with a transmitting / receiving device (12) according to claim 15 or 16, and a communication control device (11) for controlling the communication in the bus system (1) and for generating the first transmission signal (TXD), wherein the subscriber station (20) is designed for communication in a bus system (1) in which at least temporarily exclusive, collision-free access of a subscriber station (10, 20, 30) to the bus (40) of the bus system (1) is guaranteed.

18. Method for transmitting a message (45) with differential signals (CAN_H, CAN_L) in a serial bus system (1), wherein the method is carried out with a transmitting module (121) which has transmitting stages (121A; 121B; 121C; 121D) with parallel circuits (121A1; 121VB1; 121C1; 121D1) of switchable resistors (R_A1 ... R_AN; R_B1 ... R_BN; R_C1 ... R_CN; R_D1 ... R_DN) and is designed to transmit a digital transmit signal (TxD_INT) as an analog differential signal (CAN_H, CAN_L) to a bus (40) of the bus system (1) in order to transmit a message (45) to at least one other subscriber station (10; 20; 30) of the bus system (1), wherein the Method comprising the step of stepwise controlling the switching of switchable resistors (R_A1 ... R_AN; R_B1 ... R_BN; R_C1 ... R_CN; R_D1 ... R_DN) with a control part (15) of the transmitter module (121), wherein at least two of the switchable resistors (R_A2, R_A3; RA4 ... R_A7; R_A8 ...R_A16) are arranged in a resistor block (162; 163; 164) so as to be switchable together, wherein at least two resistor blocks (161; 162; 163; 164) are provided which have at least one of the switchable resistors (R_A2, R_A3; RA4 ... R_A7; R_A8 ... R_A16), and wherein the control part (15) generates the bus states (401; 402; 403; LV0; LV1) predetermined by the digital transmission signal (TxD) over time (t) on the bus (40) by gradually changing the number of actively switched resistor blocks (162; 163; 164) over time (t).