MATRICE LOGICA PROGRAMMABILE.

Description

TITLE INV. DES. PRIORITY INTERNATIONAL BUSINESS MACHINES CORP. ARMONK NEW YORK USA PROGRAMMABLE LOGIC MATRIX. DAVIS JAMES W. JONES FRANK D. USA SUN. BREV. No. 68,377 OF 21 AUGUST 1979 Rome, The.................................................................................... Register A Protocol na 23527 A / 80 MINISTRY OF INDUSTRY, COMMERCE AND CRAFTS Provincial Office of Industry, Commerce and Crafts of Milan COPY OF THE MINUTES OF FILING FOR INDUSTRIAL INVENTION PATENT In the year 1980, on the eighteenth day of the month of July, at the hours and minutes ..... =. , Λ„ the company INTERNATIONAL BUSINESS MACHINES CORPORATION of American nationality with headquarters in ARMONK - NEW YORK 10504 (USA) Via through the agent Dr.lng, Camillo SAVI at IBM Italia s,pA, and with domicile for legal purposes in Milan - Via Andrea Doria 56 at the agent has presented to me, the undersigned: - Stamped application for the granting of a PATENT FOR A MAIN INDUSTRIAL INVENTION. venie per TITLE: "Programmable logic array" Priority of patent application in: U.S.A. No. 68,377 dated August 21, 1979. Inventor(s) designated: , James W. Davis, Frank D. Jones. accompanied by: - Description in duplicate of n. 9 pages of writing. - Drawings, plates no. 5 in duplo, - Declaration referring to Power of Attorney. - Priority document and Italian translation. Deed of transfer with certified translation (reservation). - Proof of payment into postal account no. 00668004 in the name of the Registry Office for Government Concession Taxes - Rome of Lit. 80,500.» issued by the Post Office of Milan 14 / 15 July 1980 no. 735 - Revenue stamp of Lit. 2,000,- Inventor's design certificate. The application, descriptions and drawings listed above have been signed by the applicant and countersigned by me and stamped with the office seal. THE DEPOSIT ...4......, For a copy compliant with the original THE OFFICIAL ROGA] p. the Infector (Salvatore Ravalli) THE PATENT OFFICE TOUR (Isoul Es / elfs) ON. MINISTRY OF INDUSTRY, TRADE AND CRAFTS CENTRAL PATENT OFFICE - ROME The applicant International Business Machines Corporation, of 3 5 2 1 wca, of US nationality, with registered office in ARMONK, NEW YORK 10504 ι ------ . ... ! ' J ', ff ' M . u (USA) and domiciled for all legal purposes in Milan, at its Agent Dr. Ing. Camillo Savi, c / o IBM Italia SpA, via A. Dori a 56, 20124 Milan, requests, through the aforementioned agent, that the Patent Certificate be granted for the industrial invention entitled: "PROGRAMMABLE LOGIC MATRIX" and this for the purpose of being able to manufacture, sell and use exclusively the said invention. Priority of patent application filed in the United States United States of America Serial No. 68,377 of 21 August 1979 Please attach the following documents to this letter: ' 1) Description in two copies of n. 9 pages of writing. I: 2) Drawings no. 5 tables in two copies, ; 3) Declaration of reference to the General Power of Attorney. 4) Proof of payment of Lit. 80,500 into postal account no. 00668004 in the name of the Registry Office for Government Concession Taxes - Rome. Post office Milan 14 n. 735 of 15 July 1980. 5) Revenue stamp of Lit. 2,000.* for the issue of the Certificate 6) Priority document and Italian translation. 7) Deed of Transfer with certified translation (reservation). 8) Act of designation of inventor. I i Designated Inventor(s): James W. Davis # Frank D. Jones. ........ ............+ p, Inierintioiia) hhr.hinns 1 l&rpo:aSion lo Savi ,v~· ·*"! p. International Boslnoss Machines Corporation Docket MA978006 / CS DESCRIPTION of the invention entitled! "Programmable logic array" in the name of! International Business Machines Corporation residing in ARMONK, New York 10504 (USA) of United States nationality filed on 1 8 fj.i £. |9iJQ with the number 3 ~ A / 80 Summary of the invention The inverter between the AND array and the OR arrays in known bipolar emitter-coupled logic (PLA) program logic arrays is eliminated by isolating each product term in an epitaxial layer and placing a resistor between the common collectors in that layer and the collector voltage. The collector node of the product term then becomes the output signal source which is inherently inverted and can therefore form the direct input to the OR matrix. Description of the invention This invention relates in general to semiconductor devices and more specifically to bipolar program logic arrays (PLAs). Figures 1A - 1D illustrate the relevant prior art. Figure 1A is a circuit diagram of the search array, inverter circuit assembly, and OR array of a bipolar coupled logic program logic array (PLA). p. International Business Machines Corporation at the emitter. Figure IB is a block diagram 2. of the logical operations performed by the circuit shown in Figure 1A. Figure 1C shows the arrangement and related physical dimensions of the circuit shown in Figure 1A. Figure 1D is a simplified circuit diagram that highlights the emitter-coupled logic topology of the circuit in Figure LA. The function of the lookup matrix is ​​to provide the product# logical function "AND", from the terms encoded along the product term. In the product term illustrated, the desired result A is the product of AB, AB and Co, indicated by ' AB * Co. The product term illustrated is realized by said logic in the following way. The signals AB, AB, and Co are passed through some external decoder to the basic inputs of devices 2, 3, and 6, respectively. With any or all of the inputs high, the current in the current drain (link) IS1 is diverted from the path RI, VR1 - T1, and diverted from Vcc through the devices with the inputs high, and into the device. This produces a logic level 'Ί 1' at Ql. The current path is only through RI and VR1 - Tl, if all input signals are low at devices 2, 3 and 6. The current through RI causes a logic ”0” at Ql. The logical expression for Ql can be given by AB . AB . Co. To arrive at p. International Business Machines Corporation to the desired product term output expression, Ql 3. must be inverted in order to determine an expression AB · AB · Co in Ql, Figures IA, 1B, IC, 1D are related in the following way. The "So" function of Figures IC 2 is developed in Figures IA» 1B with product terms 1 and 2 identified in each figure. Figure 1D illustrates product term 1 of Figures IA, 1B, and IC. In Figures IA, ITI 1 identifies the common collector connotation of devices 2, 3, and 6 of Figures 1D and all other input devices of the search matrix. All other expression and device points are identified accordingly in all three other figures. The known bipolar PLA circuit fulfills the purpose for which it was built very well, however there is a need for a higher circuit density, better performance, lower energy consumption and a lower physical design complexity. It is therefore the aim of the invention to increase the circuit density in a bipolar PLA circuit. Another object of the invention is to improve the performance of a bipolar PLA circuit. Yet another object of the invention is to reduce the power consumption in a bipolar PLA array circuit. A further object of the invention is to reduce the physical complexity of the design of a bipolar PLA circuit. p. International Business Machines Corporation I present! and other purposes, characteristics and advantages of the- 4. the invention is realized by means of the bipolar PIA circuit The NOR logic described here. The inverter between the AND array and the OR array in known bipolar emitter-coupled logic PIA arrays is eliminated by isolating each product term in an epitaxial layer and placing a resistor between the common collectors in that layer and the collector voltage. The collector node of the product term then becomes the output signal source, which is inherently inverted and can therefore form the direct input to the OR array. The resulting bipolar PIA circuit has higher density, better performance, lower power consumption, and less physical design complexity than those available in the prior art. The present and other objects, features and advantages of the invention may be better understood by reference to the accompanying drawings. Figures 1A - ID illustrate a known bipolar PIA circuit. Figures 2A - 2F illustrate the bipolar NOR logic PIA circuit of the invention. Figure 2A shows a circuit diagram of the bipolar NOR logic PIA circuit of the invention. Figure 2B is a block diagram showing the functions performed by the circuit of Figure 2A. Figure 2C shows, in stylized form, the arrangement of the bipolar NOR logic PIA circuit shown in Figure 2A. Figure 2E is a circuit diagram of the section shown in Figure 2D. Figure 2E is a circuit diagram of the section shown in Figure 5. simplified diagram highlighting the bipolar emitter-coupled logic topology of the circuit interactions shown in FIG. 2A. The function described above for the known circuit of FIGS. 1A - 1D is the same logic function that is performed by the circuit of FIGS. 2A - 2P, to permit a valid comparison of the known circuits with the improved circuit of the present invention. The function of the lookup matrix is ​​the same as that described in the prior art. The invention, as shown in Figure 2F, will perform these functions without the prior art inverter state, as illustrated in Figures 1D and 2F. The AB, AB and Co signals are transmitted through some external decoder to the base inputs of the T2 devices, T3 and T6 in Figure 2P. With any or all inputs high, the current path goes through RI and the devices with the inputs high, on the devices, through the current drain device 1S1 to ground. When current flows through RI, the output of product term 1 is at logic “0”. The current path is diverted from RI and routed through V&l - Tl only if all inputs to devices T2, T3 and T6 are low. This causes a logic “1” output from product term 1. The logical expression for product term 1 is given by AB · AB « Co. The expressions of the product term 1 of both figures 1D and ρ. International Business Machines Corporation 2F are the same. The invention provides this logic without the need for the inverter required in the prior art. Figures 2A - 2F are correlated in the following location. <e figure 2A e 2B sono diagrammi circuiteli e logici del progetto fisico PLA illustrato ìn figura 2C, funzione "So". La figure 2F B un ulteriore sviluppo del termine prodotto 1 delle figure 2A„ 2B e 2C. Le figure 2D, 2E sono un’espansione del progetto fisico effettivo dei dispositivi di entrata della matrice di ricerca. I termini prodotto discreti delle figure 2A, 2B vengono isolati l'uno dall'altro in strati EPI di collettori comuni separati,, EPI e EPI 2 delle figure 2D, 21 nella sezione del dispositivo di entrata della matrice dì ricerca. CIO permetteva connessione del resistere al collettori cortami. Figures 2F» 2D and 2E are related as follows. Figure 2F represents the product term 1 of Figures 2D and 2E. The input signals of Figure 2F are wired along the die of the second level of metallization. The inputs are supplied to the input devices T2, T3, and T6 of Figure 2F through the through-holes V1, V2, and V3 to the first metal connections of the input device bases: V1-B2, V2-M2-B3, and V3-M3-B6 of Figures 2F and 2E. These are through-holes, bases and first-level connections, respectively. The common collector of devices T2, T3, and T6, G1, B, is wired along the first metallization, MS2 in the IE to RI. The common emitter of devices T2, T3 and p. International Business Machines Corporation Tó is applied via cable along the first metallization, MSI in the 7. Figure 29, 2E to the emitter VR1-T1 and to the collector of IS1. For overall comparison, the known PIA circuit of Figure IC and the PIA circuit of Figure 2C claimed in the present invention perform the same function, as do those of Figures IA, 1B, Figures 2A, 2B and Figures 1D and 2F. A bipolar NOR logic PIA array has the following advantages: increased density - the area required for the inverter stage - three transistors and three resistors - is eliminated. Better performance - The inverter stage delay is eliminated and replaced by the shorter delay from the RC network associated with the common collector capacitance and RI. Less energy - the energy required for the inverter stage is eliminated. Lower physical complexity of the design - as illustrated in figure IC, the prior art was faced with the problem of having to drive long base strips to accommodate the encoded input bits. This represents not only a capacitive element but also a substantial resistive element for the last emitter in the strip. The claimed invention as illustrated in Figure 2C drives only discrete devices. It will be obvious to the skilled person that although the invention has been shown and described in detail in relation to a preferred embodiment thereof, certain interpretations may be made p. International Business Machines Corporation the above and other amendments of an incomplete or detailed nature «eiiza 8. to distance oneself neither from the spirit nor from the sphere of winter,

Claims

1. Claims 1. An improved bipolar integrated PIA circuit including a first epitaxial isolated region having a plurality of common collector bipolar transistors, selected transistors of said plurality of transistors having their emitters connected to a first emitter node and their bases connected. respectively to the input signal sources; a bipolar reference transmitter having its emitter connected to said emitter node, its base connected to a reference voltage and its collector connected to a collector voltage, said epitaxial base being connected at an output node through a resistor to said collector voltage; an OR array of bipolar transistors, one of which has its base connected to said output node for receiving an output signal from said epitaxial region, whereby an improved PIA array is formed.

2. The circuit of claim 1 wherein further, said plurality of common collector bipolar transistors in said first isolated epitaxial region serve as the search array for the PIA circuit.

3. The circuit of claim 2 wherein further said first isolated epitaxial region is of N-type conductivity and said plurality of p-collector bipolar transistors. International Business Machines Corporation common are NPN bipolar transistors.

4. The circuit of claim 3 wherein further: said output node of said first epitaxial region serves as the product term for said search matrix of said PIA circuit; a second isolated epitaxial region on said integrated bipolar circuit has a second plurality of common collector bipolar transistors, certain selected transistors of said second plurality of transistors having their emitters connected to a second emitter node and their bases connected respectively to the sources of entry signal; a second bipolar reference transistor has its emitter connected to said emitter node, its base connected to a reference voltage and its collector to a collector voltage, said second epitaxial region being connected at a second bipolar node output through a second resist at said voltage of. collector; a second bipolar transistor in said OR matrix has its base connected to said second output node of said isolated epitaxial region, to receive an output signal coming from said second epitaxial region as a second term produced by said search matrix of said PIA circuit . 5' I ΐ*' »1· e lA / veRv / r&M hmfttce bì Ricli or