MEMORIA DI SOLA LETTURA PROGRAMMABILE ELETTRICAMENTE.

Description

READ-ONLY MEMORY TITLE ELECTRICALLY PROGRAMMABLE. INV. DES MINORU FUKUDA SHIGERU ΥΛΜΑΤΑΝΙ KOTARO NISHIMURA AKIRA ENDO PRIORIIA JAPAN SUN. PATENT N. 76519 OF MAY 22, 1981 ? EJIC.198G ° Rome, Il.......................................... Register A with registered office jtneiaoijTuibx 1 no Protocol n° 21403 A / 82 MINISTRY OF INDUSTRY, COMMERCE AND CRAFTS Provincial Office for Industry, Commerce and Crafts of Milan COPY OF DEE VEUKAEE IH DEPOSIT FOR IIREVET'IO OF INVENTION INDES'I ΙίΙΛΙ, ι ·: Hermo 198? on the twenty day of the month of May Ja Company. HITACHI, Ltd, btafètflUSek of Japanese nationality Street and eleni vely domiciled at - the agent has prescnlato to me, undersigned: - Application with revenue stamp for the granting of a patent for inventions: indcktriaee having for III OLO . SOY MEMORY READING PROGRAMMAR!DE ELECTRICALLY invenloii designated: Minoiu RUKUDA, Shigeru ΥΑΜΑΤΛΝ1, Kotaro H1SHIMURA, Akira ERRO. Chiyoda--ku, Tokyo (Japan) MORIAMO & ASSOCIATI S.a.s. by Dr.Ing.C. through agent MORIANO & C. (Italian Patent Agency e ... Brand names) Via Meravigli 16 for legal purposes in Milan Priority of the patent application in: Japan H. 76519 dated 2? May 1981. accompanied by: - Description in duplo of n. 72 pages of writing. - Drawings, tables n. 8 in duplo. - Letter of appointment - Di»hiBWJrj»exjd<aEbt»Al)i»j^ikAitóiiÌkfiiSti»iJfix - Priority document and Italian translation (with reserve) - Deed of designation of the inventor. Proof of payment to postal current account no. 00668004 in the name of the Tax and Concession Registry Office of RomadlL. .509.OOO.- issued by the Uff. Post Office of Milan 15 on 12 / 5 / 82 n. 358 - L-3,000 revenue stamp. 148 for the · .1 tìvczìcne: he does not consider having to carry out, as a matter of principle, α^·.ίατζ^ι.ί not envisaged by the teams. The application, the descriptions and the drawings listed above were signed by the applicant and by the jpe, counter-signed and stamped with the official stamp II, DEPOSITOR __ ............ 'er copy conforming to the 1 'iginalc THE OFFICEM -M G&tta: -TO,·..· p. the (Salvatore Ravalli) THE HEAD OF THE OFFICE BREVEBJ (fy^W / Boletlì)__ f C 1 ι , c. ' ; ME t 21 / 735S?-sb iffiaaHW \ Hon. ΙΠ NI STERO INDUSTRIA ΟΟΜΦΚΟΪΟ IT WAS ARTISAN Central Patent Office - li 0 li A the firm» HITACHI, Ltd., oon sode and Chiyoda-ku, Tokyo (Japan), of Japanese nationality, through agent MODIANO & ASSOCIATI S.a.s. by Dr. Ing. 0. MODIANO & C. (Italian Patent Agency © Trademarks) and electively domi dilata in Milan, Via Meravigli 16, requests the oonoeeslone of go Patent for Industrial Invention entitled» » MEMORY OF S03..A PROGRAMMED READING »J«ETTRTCALY , ; THE Designated Inventors» Minora KUKUDA, Sbigeru YAMATANJ, KotarJ Ni SUIMURA, Akira ENDO. , Priority of Japanese patent application No. 76519 dated May 22, 1981. Do e urnen ta zi οne attached t e) Description in duplioe oopia. b) Drawings of no. 8 plates in duplioe oopia, o) Invoice letter. THE d) Act of designation of the inventors. e) Priority document with Italian translation (oon f) Proof of payment of the prescribed fees. g) Maroa stamp of L. 3,000.♦ * 1 I ί *4 » ·> · · · ' ~ I ΚΠΆ'ίΖΙϋΒ^νη ϊ! ! 2C.CSS2 0 2 Π03 Π|*Γ. I' 11 ’Ί rl servant) f 73582 / SE / ge (17163-1.1929-03?) «ELECTRICALLY PROGRAMMABLE READ ONLY MEMORY. / <^0 / Ο / -' f \ HITACHI, Ltd., a \A J Chiyoda-ku, Tokyo (Japan) Inventors _you exist in you,: Kinoru FUKUDA, Shigeru YAMATANI, Kotaro NISHIMURA, Akira ENEO. -0-0E deposited the g θ ΚΛ6. 198? No* ? 1O Skf -0-0R1HIRED An electrically programmed read-only memory 1 includes a plurality of non-volatile memory elements whose control gates are connected in common to a first line of words. At least one of the source electrodes of the plurality of nonvolatile memory elements is connected to the ground potential via the drain-to-source path of a first MISFET switch whose gate electrode is connected to the first word line. When a nonselect level word line drive signal is applied to the first line of words, the first MISEKT switch is nonconductive. Thus, the leakage current is prevented from flowing through the first MISEET switch. DESCRIPTION The present invention relates to a memory of only % THE - 2 1 shutter programmed 3 e electrically (abbreviated PPROL?'). follow hey lovers Before the present invention, a Rί was proposed by] 3 to the applicant of the present patent application J'ROK with its improved writing efficiency, which is described in Japanese patent application Ko, 9587367 (J Sugi ura et al,, Semiconductor beverage and Kethod for fabricating the same, Applicant's reference: 16764-K882, U.S. reference: 501 18112 X00, German patent application P 31 24 283.9, British patent application No, 81. 19691 ) In the PPROK, a non-voyl memory element thereof has a structure which includes a floating gate electrode and a superimposed control gate electrode on the first gate electrode, and a high impurity concentration region having the The same type of conductivity as that of a substrate is formed in that peripheral portion of the semiconductor surface of the nonvolatile memory element which lies beneath a gate insulating film and which extends in a direction of the channel. In the non-volatile memory element of this structure, when a source-drain current flows during a write operation, the presence of the high impurity concentration region improves the hot electron generation efficiency, whereby the speed - 3 i?a of writing re which augmented From the description of the aforementioned patent application, however, it does not teach a construction which solves other problems in KPBOM and a new problem arises in the case of the structure formed with the high impurity concentration region as stated above. The inventors' studies have revealed that, in order to increase the efficiency of writing charges in a floating gate, the write voltage to be applied to a non-volatile memory element must advantageously have a greater value in a range in which a pn junction does not substantially discharge or break down. However, in the case where the high impurity concentration region is arranged as stated above, the pn junction thus formed by the drain of the nonvolatile memory element and the high impurity concentration region will cause avalanche even for a relatively low reverse voltage. In the case where the pn junction of the *< 1 moment of non-volatile memory has undergone avalanche discharge due to an inefficiently controlled write voltage, gaps created in the pn junction as a result of the avalanche discharge are injected into the interface between a silicon substrate and silicon dioxide below the floating gate of the nonvolatile memory element. I) As a result, electrons which are injected by the rewrite to recombine with holes in the floating gate, and the rewrite efficiency deteriorates. This too was revealed by the inventors' studies. Therefore, the write voltage must have its level satisfactorily controlled. In an integrated circuit, a plurality of non-volatile memory elements are arranged in matrix form. Pieces of a plurality of disabled memory items arranged in the same column are connected with a common single-bit line, while the control gates of a plurality of disabled memory items arranged in the same row are connected with a single line of words in common. According to this arrangement, a non-volatile memory item is selected across a certain word line and a certain bit line. In order to write information into a non-volatile memory item, a write voltage is supplied to a bit line (selected bit line) with which the non-volatile memory item is coupled, and a word line signal at a selection level is fed to a line of words (selected line of words). The high level of the write voltage makes a relatively high voltage, and increases the potential of the floating gate to a non-negligible level through the parasitic capacitance between the drain and the floating gate of the non-volatile memory element. Accordingly, channel leakage currents run to the unselected non-volatile memory elements coupled with the selected bit line. The number of non-volatile elements to be coupled with a bit line increases proportionally to the increase in memory capacity. Therefore, the leakage currents increase as the storage capacity increases. In other words, in the case where the memory capacity has been increased, the leakage and rebound currents increase so as to make the power consumption high. When leakage currents increase excessively, the write current expected to flow to the selected non-volatile memory element decreases accordingly. Therefore, the current driving capability of a write circuit needs to be improved. This necessarily requires increasing the size of elements that make up the write circuit, where leakage currents fluctuate relatively large not only due to the manufacturing losses of the non-volatile memory elements but also due to « knows the variation of the operating temperature. For6 this requires a properly designed write circuit. Unless the proper write circuit is designed, product yield will be reduced. It is also known that leakage currents are reduced by connecting the sources of a plurality of nonvolatile memory elements to the circuit ground point through a single common resistor (refer to 1 * in the case one of 3' Kihara et al titled J'rogramabl and Read Only Memory, Applicant's reference 16245-M84 7 » U.S. reference: 501 ♦ 17417 XGO, published German patent application 3 037 315) Studies by the inventors have, however, revealed a drawback of known non-volatile memory elements which is that, since the magnitudes of the leakage currents depend on the resistance of the common resistor, large leakages occur. can occur in leakage or leakage currents, depending on fluctuations in the manufacturing factors of the integrated circuit. It is an object of the present invention to provide an ETROM which is capable of reducing its total leakage current to a very small value, and in which the total leakage current is not substantially affected by fluctuations in manufacturing factors. of an integrated circuit. In a first embodiment feasible according to the general inventive idea of ​​the present invention, the control gate electrodes of a plurality of. non-volatile memory elements are connected to a first line of words, the sources of the plurality of non-volatile memory elements are respectively connected to a circuitry ground point via the drain-to-source paths of the switching MIS'EKT, and the switching KISFET gate electrodes are connected to the first line in your words. In a second, more preferred embodiment, the control gate electrodes of a plurality of non-volatile memory elements are connected to a first line of words, the sources of the plurality of non-volatile memory elements are connected to a circuitry ground point across the drain-to-source path of a single K1SPET di. switching in common, and the gate electrode of the switching M1SPKT is connected to the first word line. In the third and more preferred feasible embodiment, the control gate electrodes of a plurality of non-volatile memory elements are connected to a first line of words, the control gate electrodes of a further plurality of non-volatile memory elements volatile are linked to a second line of words, the sources of the first non-volatile memory elements e those of the second nonvolatile memory elements executing O / po connected to a circuit ground point via the drain-to-source path of a first switching MlSPET and that of a second common switching MI SPET,', the the gate electrode of the first switching MISPET being connected to the first word line, and the gate electrode of the second switching MISPET being connected to the second word line In the above-described practicable forms, in the event that a word line drive signal at a non-select level is applied to a word line, the switching MlSPET whose port is connected to this word line becomes non-selectable. conductor, so that leakage or leakage current is prevented from flowing to the switching MlSPET When evaluated from the point of view of the integration density of an integrated circuit, the second feasible embodiment is more favorable than the first feasible embodiment, and the third feasible embodiment is even more favorable than the second embodiment. implemented. 1c From the point of view of reducing the leakage current, the third practicable embodiment is slightly inferior in reducing effect to the first and second practicable embodiments. In the 1st practicable embodiment, however, in the case in which a driving signal of the first line of words at a select level is applied to the first line of words, wherein a driving signal of the second line of words at a non-select level is applied to the second line of words, and where non-select level word line drive signals are applied to the other word lines, only the first switching W1SFKT becomes conductive so as to permit the passage of a reduced leakage current, and the second Switching KISKRT connected to the second word line the other switching KISPRTs connected to the other word lines become non-conducting so as to prevent the flow of any leakage current In the third embodiment which is feasible, therefore, the reduced leakage current flows only at the first KISPRT of switching in the condition of application of the driving signals of the word lines as previously said, so that the inferiority in the reduction of the leakage current does not affect the other non-volatile memory elements and the other switching K1SPRTs connected to the other word lines. In a very large memory capacity ΕΓΗ0Μ (e.g. $4 kilobits), therefore, the third feasible embodiment is the most favorable one both from the point of view of the integration density cb and from the point of view the reduction of leakage or leakage currents. In the drawings: Figure 1 illustrates a block diagram of an EPROM according to the present invention; FIGS. 2A and 2B illustrate a circuit diagram of the essential portions of FIG. 1; Figure 3 illustrates a circuit diagram of a sense amplifier included in the EPROK according to the present invention; Figures 4 and 5 are circuit diagrams illustrating modified embodiments of a write circuit; Figure 6A illustrates a plan view of a non-volatile memory element included in the EPROK according to the present invention, Figure 6B illustrates a sectional view of Figure 6A and Figure 6C illustrates a view of another section of Figure 6A ; Figures 7a to 7f are process sectional views for illustrating a process for manufacturing the EPROM according to the present invention; Fig. 8A illustrates a structural sectional view of a Zener diode of the write circuit in the KPROM according to the present invention, Fig. 8B illustrating a plan view corresponding to Fig. 8A ; Fig. 9A illustrates a plan view of a non-volatile memory array which includes switch SPETs, Fig. $Pￂﾷ illustrating a sectional view of Fig. 9Aￂﾻ Hereinafter the present invention will be described in detail with reference to embodiments thereof. From figure 1 is a block diagram of an EEROM according to an embodiment of the present invention. In this figure, the part enclosed within the dotted line IC is formed within a single silicon wafer by a semiconductor integrated circuit manufacturing method to be described later and includes well-known semiconductor manufacturing methods. ba EEROM has input terminals which are supplied with address signals óaA, aA,., input terminals which are supplied with control signals PGM, CE and OE, input / output terminals from l / θθ a ΐ / θγ» terminal or terminal of the power or electric energy generator which is supplied with voltage V of the generator, for example Ι / L· of 5 volts, another terminal of the energy generator which is supplied with a reference voltage GND such as circuitry ground voltage, and a power source terminal. write which is supplied with a write voltage which is made of for example a value of 25 volts during an operation. programming mode (ie when writing information). The EEROM is activated by feeding the respective terminals with the appropriate voltages, or signals. While not specifically limited thereto, the EEROM of the embodiment includes memory matrix circuitry Ι'ΆΤΐθ through MAR? (ìhereinafter indicated with from ’ΜΛΕθ to MAR?*) divided into eight groups. Each of the circuits MAR1 through MAR is provided with a memory capacity of 0 7 8192 hits, so that the EEROM comes to have a memory capacity of about 64 Bilobits overall. A memory matrix circuit consists of 256 word lines, 32 lines or bit lines, 256 x 32 memory cells and switching elements to reduce leakage currents as will be described later. The X-address buffer circuit, ABB^ (hereafter simply denoted by 'ABB^ ' ) responds to externally fed address signals A^ - A^ of 8 bits, for example and levels TTb (logic trans?etor- The transceiver provides address signals of a true level and a false level from ar, a, J5 to a^, a^, rendered at appropriate levels, respectively. By receiving the address signals from a^, to a n an X-decoder circuit, indicated by X12' 12' BEO (hereinafter simply referred to as "X-BEC") forms drive signals from to ^nnec of the words intended to be fed to the word lines of the circuits from MRq to MAR?. Only one of the signals from VL to VL·,.,. the driving 1 256 of the word lines, which corresponds to a combination of the address signals from A r to A^_ is brought to a selection level 5 12, while all the others are brought to a non-selection level such as the ground potential of the circuitry. By supplying the X-DE'C with the voltage of the energy generator or electric power, the writing voltage Vpp and a control signal vm from a control circuit CONI which will be described later, the signal selection and drive level of the lynx of words is made substantially equal to the voltage V of the energy receptor vL gene during an information read operation and a level substantially equal to the voltage V. rT, during an information write operation FP An address buffer circuit! zzo-Y, ABB^ (hereafter simply referred to as 'ADB^*), responds to externally fed address signals Αθ - A^ by 5 hits, for example at Ti'h levels, and provides true level and of level 0 do so from to a^ to a , a^, made of appropriate level. Are the address numbers a^ through a^ad *4" used to connect 1 and lines to 3? bit of each of the matrix circuits of. memory from ΚΑΙϊθ to I.1AR?. While this is not specifically limiting, the embodiment is such that the lines of lits of the respective memory matrix circuits Τ,ΆΚθ to BAR are selected by circuits of. column switching from CS A to CS r? and 1 read / write circuits R / Wq to R / W q Therefore, among the address signals from Bq, οθ to a^, the signals from a^ to a^, , are supplied, to a first Y-decoder circuit, Y-IXEC (hereafter called "Y-BEC^ 1), and the remaining signals a^, a^ and a^, a^ are fed to second circuit decedi fi. cator-Y, Y-BEC (hereinafter referred to as'Y-BEC f). Upon receipt of address signals from βθ, to the Y-BEC, forms lynx selection signals 2 2' 1 dl Bit from BS^ to BSg, P revi to be fed to the column switching circuits from Οδθ to CS? Only one of the Bit line select signals BS1 to BSg which corresponds to a combination of the signals of. address from Αθ to A ? is brought to a level of selection, while all the others are brought to a level of non-selection such as for example the mass potential of the circuitry. By supplying the Y-BEC with the voltages V_ n and Vpp c the control signal we in a similar way to those of X-bEC, the select level of the bit line select signal is made substantially equal to the voltage of the power generator during the operation of CC reading of the information is of a level substantially equal to the voltage V^p during the operation of sew the information » Upon receipt of the address signals a^, a. and a,, a., Y-bECL forms selection signals from a 3 3 4 4 ? θ K 3. Only one of the selection signals Κθ a which corresponds to a combination of the address signals A. and A 3 4 is brought to a selection level substantially equal to the voltage V nn of the electrical power generator, while all the others are brought to a non-exjection level such as the ground potential of the circuitry. Y-bEC^ is supplied with a control signal ce from the control circuit CONT. By way of example, the control signal ce is made high during die select and low during die non-select. .selection signals from Κθ to which are provided by the Y-bEC ? are held at the non-select level during chip non-select regardless of the levels of the address signals A^ and A^. 3Following the reception of the previous selection, bit signals, the switching circuits of the columns from 08θ to CS? (hereinafter simply indicated with CS^-CS?) select the lines of the bits of the corresponding circuits ΡΑΚθ - BAR? in numbers of four at the same time. That is, four of the 32 bit lines B^ to B^ of, for example, ΙΆΒθ are coupled with the common bit lines <3&CBq to CB^ through the column switching circuit CS^. As an example, the signals expected to be switched by the circuits from Οδθ to CS? switching mode i of the columns are made high level close to the voltage V„ of the power source or low level close to ground potential during the information read operation, and they are made high level close to the voltage Vpp or low level close to ground potential during the information writing operation. In order to couple the bit lines to be selected and the common bit lines with low voltage loss, the select level of the bit line select signals which are fed to circuits Οδθ to CS? column switching is made substantially equal to Vpp during the action of writing information as previously described, The groups of common bit lines, each group in- bypassing the four lines, they are respectively coupled to the read / write circuits by R / W^ θ R / W ? (hereafter referred to as 'R / W^ a H / W ' ) as shown in the fi gure. Each of the circuits R / W^ to R / W? it consists of four-unit read / write circuits corresponding to the four common bit lines ΟΒθ - CB^, with one-to-one matching. Input / output terminals of the four unit read / write circuits 1 in the respective circuits R / Wq to R / W? are connected in common to the common input / output terminals l / θθ to l / 0 r^. Each unitary read / write circuit is selected by one of the select signals Κθ to IL provided by the Y-UBC,. When it is selected, the corresponding common bitline and the corresponding common input / output terminal are substantially coupled. Each unitary read / write circuit is activated by the power source voltage and the write voltage Vpp supplied during the information write operation. Each unitary read / write circuit has its mode of operation specified by control signals v / e, we, cs and cs supplied by the control circuit CONT. 1 Although this is not particularly restrictive, a control terminals cs and wc. In the read mode, a signal on one of the four common bit lines is fed to the common input / output terminal through the unit read circuitry selected by Y-UBC2. In other words, the common input / output terminal is powered X-DKC, Y-I / EC^ and Y-UKC . A write mode is specified by the high level to of the control signal wc and the low level of the control signal cs. In the writing mode, between circuits a circuit not shown across the common input / output terminals, only the one selected by Y-DBC2 is brought into its operational state. Thus, one of the four common bit lines is rendered substantially ground potential level, i.e., an appropriate write voltage level in response to the data signal that is to be written. P, and the remaining three common bit lines are rendered substantially equal to the ground potential level since the corresponding unitary read / write circuits are not selected. In a platelet non-selection mode, selection signals from Κθ a non-selection level returns as described above. So, do all the 1 read / write circuits read / write in circuits R / V / θ to R / w? eare brought to their inoperative state. While not specifically limited thereto, the read / write circuit is constructed such that its input / output terminals go into the floating state in the chip nonselect mode. control circuit (hereinafter simply called 'CONT') forms the indicated control signal we in the following Table 1, by receiving an external program control signal PGM, chip enable signals CE and output enable signal OE and the write voltage V-. the prey level! I was born, -TX Table 1 Reading v Plan v PGM H li CE L L OE L we Η 1, Using these control signals, selection of write / read operations (in other words, control of various modes of operation such as reading in a high voltage application state) is performed. • ο Ό FIGS. 2A and 2Ύ illustrate a circuit diagram in which this cV / .00 I of a possible embodiment of the FPROM according to the present invention. JóARq includes 256 x 32 cells of nonvolatile memory l·' - which are arranged in 3? rows and 25632 L ?5(> columns. Although its structure is further clarified below, each individual memory element consists of a FAJ.OS (Floating Gate Avalanche Injection Transistor KOS) having a floating gate electrode and a control gate electrode. Among the memory elements, 32 memory elements arranged in the same column have their control gate electrodes connected in common with a corresponding one of the word lines W, 256* The memory matrix circuit KARq is provided with lines of reference potential from R^ to R^g» each of which corresponds to two of the word lines, such as for example the word lines e and the word lines e W » In thus, the source electrodes of the 3? memory elements belonging to one column and those of the 32 memory elements belonging to the next column contiguous to the first mentioned column are connected in common to a reference potential line. Switching MISFETs from S, to S^ rr, which are con1 256 - >1 controlled on or on off or off by the signals fed to the word lines are respectively disposed between lines R^ to ^128 P°^ and Bzi al and di. reference and the ground point of the circui teri a. The. drain electrodes of the 256 memory elements arranged in the same row are connected in common to the corresponding one of the bit lines B^ - ^32* l.e bit lines B^ - B^ ? are divided into four groups by the column switching circuit CS2. Switching MISPBTs are disposed between the respective bit lines and the common bit line. More specifically, the switching rnSl'BT ζ> - Q„ or eb are controlled meli 18 of antes the selection signals formed by Y-IJB'C , are respectively disposed between the lines of the bits Β - Βθ and the bit line common ΟΒθ. Similarly, switching KISBBT - Q^g» - Q- o and Q. - Q, or similar to those previously mentioned so 3o 41 4o - n respectively arranged between the bit lines B o - B^, ^17 ~ ^24 6 ^25 ~ B32 and the bit comm4 CB·) » CBp e CB^. Thus, when a selection signal e.g. BS^ formed by Y-IJB'C is brought to the selection level, the four bit lines B^, B0, B^ and B^ are simultaneously coupled with the common bits CB^, CB^, CB^ and CB^ respectively. The common bit lines ΟΒθ to CB^ are connected (;Q>) with the read / write circuit R / W^. As shown in Figure 2B, the 1. read / write circuit R / w^ ® consists of a write circuit W Q and a read circuit Κθ, The write circuit consists of four single write circuits WA to L, corresponding to the common bit lines CB^ to CBy corresponding to each other, and a single input circuit V / θ^. As shown in the figure, the input circuit ν? ΛΓ_ b consisting of MISPETs Q through C' A. Although not 62 70 is specifically limited to this, MISPBTs such as KISPET Qg and with straight line symbols drawn between their sources and sinks are expected! exhaustion (deplction) or impoverishment mode while the other IUSEETs are foreseen in the filling or enrichment mode (enhancemcnt). Since the input circuit V / θ^ is implemented as shown in the figure, its output terminal (i.e. the drain of the MISERI' Φγθ) supplies a signal which is equal to the logical product between the inverted signal of the signal and write data fed to I / O common input / output terminal and way write control signal. More specifically, when the web write control signal is high, the input circuit W gives a low level signal substantially equal to the mass potential or high level substantially equal ?3 - le to the voltage V of the electric energy or power generator UL, in accordance with the high level or low level of the data signal supplied to the common input / output terminal 1 / θ, When the write control signal we is at the low level, it provides the low level signal substantially equal to the ground potential regardless of the data signal fed to the. common I / O input / use terminal. The unitary write circuit W includes an e PISEET output Q co whose. piece and connected to the x terminal Vpp c whose. - source is connected to the common bit line CEq, a PISELI of. moving of. level Q whose port and drain are connected to the port of the outgoing PJSEET Q and whose source is connected to a Zener diode ZD and a fi £ PJSEET Q r. A click serves to feed a bias current to the level shift PISELI, The circuit of. unitary writing VA, also includes 01 a Kl SI ET Q?^ to control the PISELI output Q , the PISELI in the switching on and off Q and Q?^ constituting a logic gate circuit for controlling the on and off switching of PISELI Q?^ and a load KISEET Q?^, The gate electrode of the PISELI Q?^ is supplied with the selection signal Κθ supplied by Y-LBC , while the gate electrode of the PISEET Q?^ is supplied with a signal for24 MlSPET output Q> drain breakdown with a high voltage nished by the wholesale circuit W . In the circuit illustrated, the must have a breakdown voltage or margin sufficient relative to the order of 425 volts supplied to the Vpp terminal In general, the drain voltage Vpp of a MlSPET is limited relatively strongly in proportion to the degree to which the width of a depletion layer at the drain junction surface is limited by the field strength applied by the drain electrode. door, as is well known. The output SPET Q r.- is therefore rendered a stacked-gate structure 52, although it is not specifically limited to such a structure. The first gate electrode thereof is connected to the gate electrode and drain electrode of the MlSPET Q F^, and the second gate electrode, near the drain region thereof, is connected to terminal Vpp as shown in the figure. If necessary, the output MlSPET Q is implemented in the form of the so-called ring gate structure, wherein the drain region is surrounded by the gate electrode. If necessary, a channel region underlying the first gate electrode of the. The output Q SPET is implemented in the depletion mode in order to increase the appropriateness - V is fed to the common bit line. A channel region below the second gate electrode is made in the enrichment mode. ba channel region of the depletion mode can be formed by the known impurity ion implantation technology. In this case, the amount of impurities to be implanted in the channel region can be determined with much greater accuracy than in the case where impurity diffusion technology is employed. Thus, a threshold voltage which is determined by the first gate electrode of the output PISPKT Q is set to a value which is shifted by an exact predetermined amount by the threshold voltages of the. BlSh'KT Q , etc. by two MISPBTs connected in series. However, just in case stacked as described above, they can advantageously be constructed to relatively small dimensions. In this embodiment, the brc-akdown voltage of the constant voltage diode 71) (hereinafter also referred to as the Zener diode) is made to be substantially 26 equal to the breakdown voltages of the drain junctions of the non-volatile memory elements, and at home it is allowed to have a dispersion substantially equal to that of the breakdown voltages of the drain junctions of the non-volatile memory elements. To this end, the well-known characteristic in the production technology of integrated circuits, constituted by the . fact that a plurality of elements formed simultaneously exhibit comparatively small relative dispersions in their characteristics. As will be better understood from the following description, semiconductor regions for constructing the constant voltage diode Z1) are formed simultaneously with semiconductor regions for constructing the nonvolatile memory elements. the bias current of the diode Zcner at constant voltage ZI) is supplied by the terminal Vpj, through the K3SEET Q cr. and ζ> , by way of example. 51 The level shift MJSFKT Q_„ is constructed 51 such that a voltage substantially equal to its threshold is provided between its drain and its source. Assuming now that A' denotes the dimension ratio W / h (W: channel width, L: channel length) of the M1SFET Q and B denotes the dimension ratio 1 and W / l, de] KISFKT Q ,, ei has B «A. In this ”' oa°> the entity of ερο measurement of level V is evaluated by the following expression (1)27 in which V., ,, indicates the threshold voltage of the MlSPET thD Q rr, and V,. T, indicates the threshold voltage of the MlSPET ζ> : the 51 V 4 V ' V thD thE thE (1) The unitary write circuit or Vg . the Vg_ input circuit 01. and the associated circuits shown in figure 05 2B work as follows: During the information writing operation, the Vpp terminal is supplied with a high voltage Vpp of the order of 4 25 volts, and the electrodes tìi carry MlSPETs, 0 / -. Qz-r, and Q, or of the input circuit are powered 6? 60 05 with the write control signal wc at a level which is substantially equal to the supply electric power generator voltage Vθθ. If, at this moment, the selection signal Κθ provided by Y-DEC is at the selection level or high level substantially equal to the voltage V nn, then the MlSPET Q will thus be brought to the on state. If the data signal fed to the common input / output terminal 1 / O from a circuit not shown is low, then the input circuit MlSPET drain will provide the high level signal by which the MlSPET will be driven in the state on. Since the series-connected MlSPETs are simultaneously turned on, a voltage essentially equal to the GMD ground potential of the circuitry is applied to the gate electrode of the KISFET As a result, KJSFET Q is brought to the off state. Turning off the K1SFET Qf,, results in energizing the gate electrode 74 of the KISFET ζ> with a voltage that is substantial to the rncn5 ? te equal to the sum V„ 4 V,. v between the Zener voltage V 9 Z VrìK Z» of the Zcner diode ZB c the threshold voltage V., 1A of the KISFET thE °51' Output BIISFET KISFET Q c whose threshold voltage 52 is indicated at V.,, maintains its on state until its source electrode potential is raised to (V n 4 V,, ,J-V.,-, i.e. until it is raised K Z thE thD' tato to a potential greater than the Zener voltage V according to the difference of the threshold voltages V., _ - V thE thI). Therefore, the shield voltage having a value close to the Zener voltage is fed from the 1 ' source electrode of the output MISFET Q - to the common bit line ΟΒθ. The write voltage fed to the common bit line ΟΒθ is fed to one of the bit lines from B„ to B or via the switching circuit CS co1 ο v 1women. More specifically, just in case. the memory element to be selected is by way of example V* \ fi / - 29 vo 3' element E. Λ, the tension ài. writing is fed to the bit line B^ In this case, the driving signal of the word lines is brought to the selection level substantially equal to the voltage Vj,p by means of X-DEC. Due to the selection level of the driving signal of the word lines, the memory element 1' and the switching TiISEET which is disposed between the source electrode of this memory element and the GMD ground point of the circuitry are brought, in the states on. As a result, write current is introduced into the memory element F. In this way, the threshold voltage of the memory element 1' is varied by its value which is lower than the selection level (for example the level of 5 volts substantially equal to the voltage Vqq) of the driving signal of the word lines provided by X-DEC during the information reading operation, to its value which is higher than the selection level during the reading. According to this embodiment, voltage drops that develop such that the write current flows through the ON-state resistance between the source and drain of the MISFE'T, for example the T1ISFET Q ^ in circuit 05θ of column switching, which is a resistance existing on the common bit line, the resistance sy * of source output of the output PISELI etc., are substantially annual 1 ate by the difference of the threshold voltages V 1M, - V tM) between the KSFBT Qj, 0 In this case, by forming the PISEET Q r, and ζ> on an identical semiconductor substrate 51 52* substantially simultaneously, the threshold voltages of the respective PISEET Q F1 e undergo dispersions and fluctuations in values ​​substantially equal to each other Furthermore, however, the difference of the threshold voltages V.. ... - V.,„ is substantially not theE thD influenced by the absolute values ​​of the dispersions and by the fluctuations of the threshold voltages of the respective PISELI. Since the amount of voltage variation tìi. threshold of the output PISELI' θ determined by the amount of impurities introduced into the channel region by means of the ion implant technology as previously mentioned, the difference of the threshold voltages at V, thE V J1T, can be determined in a relatively precise way. Therefore, the voltage drops developing across the resistive components can be satisfactorily canceled regardless of the PISEL threshold voltage losses. Therefore, the bit lines can be supplied with the voltage of. writing with a value very close to the Zener voltage V„ of the Zener diode ZIJ regardless of the characteristic dispersion and fluctuations31 tions of the characteristics of the integrated circuit. In other words, the lines of the bits can be supplied with the write voltage with a value very close to the breakdown voltage of the drain junction of the non-volatile memory elements* The write voltage to be supplied to the bit line is sufficiently increased, with the result that sufficient information charges are injected into the floating gate of the memory element. Output MI SEBI 1 Q shown in FIG. 2B can be altered in the enrichment mode. Again, the write voltage at a relatively good level can be fed to the bit line due to the voltage V r supplied by the Zener diode Z1). In this case, however, it must be taken into account that the voltage tìi writing is somewhat reduced compared to that which occurs in the case in which. the output MISEBT is implemented in the depletion (after eti on) mode, whereby the charges tìi information to be injected into the floating gate of the element tìi memory decrease. In the circuit of the figure. 2A, in the case in which the bit line B has been supplied with the write voltage as previously stated, the potentials of the floating gates of the memory elements E' to l ' are increased 2561 - 3? - at non-negligible levels through the parasitic capacitances between the respective fluctuating gates and the respective drain electrodes, since the write voltage is of relatively large value. Accordingly, if the S1 to S<ir- switching M1SFLTs are omitted, then the unselected memory elements F1 through parann0 are essentially turned ON regardless of the unselected level of the signals from W? a 6i piloting the lynxes of words. Between the source and drain of the ON-state KISFLT, write current is injected through the selected memory element Fc then a voltage appears. The memory element F^^ has its source electrode supplied with the drain voltage of the switching M3SFFT, whereby this results in a relatively small leakage current, or is substantially held in the off state. In this embodiment, the to-switching K1SFLTs disposed between the source electrodes of the memory elements F^^^ and the ground point GNU of the circuitry are held in the off states since the signals YL to ν / ΛΓ .< for driving the lines of. paro 3 256 ~* le are at the non-selection level. Therefore, despite the fact that the memory elements F-^ through F' , are substantially brought into the states 31 256 ON as described above, at the current of Channel leakage can be prevented in a substantially perfect manner from flowing between the bit line B1 and the ground point GND of the circuitry. In the event that the channel leakage or leakage currents are injected by the respective memory elements from Ig, to 1' due to the omission of the switching BlSl'BT31 256 tion from S a a leakage or leakage current flows 256' which is large overall, even when the respective channel currents are small. Conversely, according to this embodiment, the leakage current can be reduced to a substantially negligible value. Since the leakage currents which must flow through the memory arrays are reduced to substantially negligible 1e, the current drive capability of the write circuit may be reduced. In other words, the size of the output JilSPBT ζ> eoe. can be re5< if small. In addition, the write current to be supplied to the write circuit can be set without considering leakage and leakage current fluctuation, and the design of the circuitry as well as the elements can be facilitated. Therefore, an improvement in the production yield can be obtained. Instead of arranging the lines of reference potential corresponding to the lynxes of the words as in figure 2 (A), it is permissible by way of example that they sort them" 34 '1 / A u\ Or, people of a plurality of memory elements belonging to the one bit line are connected to the ground point of the ci. rcuiteria through a common resistance. In this case, a voltage is formed on the common resistance by means of a write current to be injected into an e-election memory element * The voltage developing on the common resistance is fed to the sources of the unselected memory elements. The unselected memory elements have their source potentials increased, and they are thereby driven into the off states. Even with this provision, the occurrence of leakage currents can be prevented (refer to U.S. Patent Application Serial No. 193411 filed October 3, 19θ0 in the name of T. Kihara et al. entitled Programmable Read Only Memory; German published patent application 3 037 315) In this case, however, the following fact must be observed. In order to prevent leakage currents into the unselected memory elements, the ohmic value of the common resistor must be made relatively large. A relatively large voltage drop is developed across the common resistor having a high ohmic value from the current of writing. This voltage is also supplied to the source of the memory element to be selected. Therefore, the writing current of the selected * emen- 35 sacred element is reduced, c a of information results in the memory that must e 'effà ci en:-a of writable fi. The switching PISEETs illustrated in Figure 2Λ can be implemented in a structure having a sufficiently low on-state ohmic value. Therefore, the efficiency of writing information into the memory to be selected is not substantially limited by the PISEET dl. switching. In the circuit shown in Fig. 2B , in the case where the common input / output terminal 1 / θ is supplied with the high level data segase c, the output signal of the input circuit \Υθ Γ (drain output of the PISEET Ογθ) is brought down to a level substantially equal to the ground potential, and the PISEET Q?^ is brought into the off state. In accordance with the off state of the PISEET Q?^, i^ PISEET is brought to the on state. The gate electrode of the PISEET Q__ is substantially brought to the ground potential GNI) by means of the PISEET Q In this case, the common bitline ΟΒθ is fed with only a relatively small voltage across the PISEET Q co. Therefore, no charge is injected into the port floating of the selected memory item l ' In case the tìi selection signal Κθ supplied by Y-DEC is at the non-selection level, and in the case in which the write control signal we is at a low level, at least one of the MlSPETs responds to it to fall in the off state, whereby the MlSPET ζ> ca74 de similarly in the on state of ignition The circuits of. unit writing from Υτθ? a V / θ^ have the same arrangement as that of the unitary write circuit hP„ shown in the figure. While no limitation is specifically provided, the single Zener diode ZD which is common to the unitary write circuits V / θ^ through V / θ^ is contemplated in this embodiment. According to the arrangement illustrated in FIGS. 2A and 2B, the bias current of the Zener diode ZD is fed through one of the unitary write circuits VL, to VP,. By way of example, bias current O1 04 is fed through the MlSPET and when the MlSPET is turned off. In this case, the well electrodes of the MlSPETs Q^, Q , are respectively brought to the ground potential of the circuit by the MlSPETs Q ?g, Q g? and Q gg and essentially function as the source electrodes. Therefore the MlSPET Q^, Q _ and are taken to the off states. Since i MlSPET Q ,, >7 ou - 37Qr? c Q^-q are brought into the off states, the normal bias current is fed to the Zcner diode ZI)* In this embodiment, the sense circuit Γίθ consists of the sense amplifiers $ￎﾑￎﾸ to SA^ ￃﾬ which correspond to the common bit lines CBq to CBy with co:r:r^ one-to-one correspondence, and from a circuit to output buffer OUT» The sense amplifiers 8Αθ to SA^ are selectively activated by the selection signals Κθ to which are provided by Y-BBC^. The output buffer circuit OUT supplies the I / O common output input terminal with a signal having a level corresponding to an output signal of a selected sense amplifier. output terminal e of the output buffer circuit OUT is brought into the floating state such that the control signal cs is made low as during chip non-selection. FIG. 3 illustrates one possible circuit arrangement of the sense amplifier SA2 and the circuitry associated therewith. In figure 3, the common bit line ΟΒθ is connected with the source electrode of a KISFBT amplifier and with the gate electrode of a constant current MISFET ε Q.a The MISBBT port is connected to connection 101 99 / Ρ - 38 common of the ElSFBT Q' , and which are connected in series between the power supply terminal and the ground point of the circuitry so as to form a predetermined bias voltage. The common bit line CB^ is also connected to the *e~ source electrode of an I.'ISFbT Q θ whose port is connected to the common connection of the EISPBT and Q o? and the well outlet is connected to the feeder terminal. Therefore, during the information read operation, the bias voltage is applied through the El'SFBT or in the SA- sense circuit to a yo ' or memory element selected by X-DEC and ,Ύ-DKC According to the above-described information, the selected memory element has the threshold voltage higher or lower than the word line drive signal selection level as previously stated. In the case of. the selected memory element is kept in the off state regardless of the level of selection of the dream and of the driving of the word lines, the line of. common bit ΟΒθ is raised to a relatively high level by MISFET Q 98' In the event that the memory element is selected and held in the on state by the select level of the dream and drive the lines of. words, the common bit line ΟΒθ is driven to a relatively low level. In this case, the high level of the common bit line ΟΒθ is brought down to a relatively low level since the PISEET gate voltage Q^g is kept relatively low. low level of the common bit line ΟΒθ is made relatively high level by properly setting the size ratios of the PISEETs Q^g and Qo^ and of the memory element, etc. When the high level and low level of the common bit line ΟΒθ are limited in this way, the read rate can be made high notwithstanding the fact that capacitances such as signal rate limiting parasitic capacitances exist in the signal line. common bit ΟΒθ, etc. That is, in the case where data is read from a plurality of memory elements, in succession, the period of time in which one level of the common bit line ΟΒθ is changed to the other level can be made short. The PISEET amplifier Q oo has the fixed bias voltage applied to its port, and the read signal from the common bit line ΟΒθ applied to its source. Thus, it constitutes a common-gate amplifier together with a load PISEET Q^qq* Uh amplified output signal supplied at the sink of the PISEET Q is applied to port y y of a differential KISFET The gate of the other differential MISFBT Q n is ali y i ~ mounted with a reference voltage V „ which is forref mated by a reference voltage source circuit in the next stage. reference voltage source circuit includes a dummy memory element F. the gate of the dummy memory element F is connected to the common connection between the MISFETs and Q-jq^ which are connected in series between the power supply terminal and the ground point of the circuitry to form a predetermined average voltage. Connected to the drain electrode of the dummy memory element F there is a MI SEET P for υη of the dummy memory element which corresponds to the MI SFECI' of the column switching circuit. Is the same circuit as that made up of the K1SFETs from Q og to Q 1O1 made up of the MISEE'T Q 1O?» Q lOg θ from to Q11O* As shown in the figure, the dummy memory element F and the MISFET Q lOg ^are connected to the source electrodes of the MISFBTs θ ^08 and P° ?,z or constant current ACISFET Q^q A potential of mean value between the high level il* and the low level of the common bit line CJ-'θ is applied to the source electrode of the MISERI* by the dummy memory element F and the MISERI* Consequently, the reference voltage V „ at the mean level between the high level and the low reading level which are supplied to the drain of the M1SPET Q is supplied in corre spondence, y ΐ-1 the sink of the MISERI' wide i fi ca tore Q^g Since the reference voltage source circuit of this type has a similar arrangement to the circuit consisting of the KISERTs from CL·, a , the switching circuit 101 of the columns and the memory elements, it supplies the reference voltage V _ of a good level regardless of the fluctuations of the threshold voltages of the MISERI*, etc. From common source of the MISERI* of differenzi al i Q e is equipped with a MISERI' Q o? which functions as a constant current element and a MISERI' Q o^ whose gate electrode is supplied with the select signal Κθ from Y-DBC in order to select the sense amplifier. On the other hand,! wells of MISERI di fferenti al i ζ> οθ and Q O1 are respectively equipped with load M1SERT and Q . The amplified output signal of this differential amplifier circuit is transmitted to the output buffer circuit OUT via the RC latch circuit. circuit of. LC latch has selection signal Κθ applied to it and is selected to leave it at am pii fi heat detection SA,. u The latch circuit EC is constructed such that when it is selected by the signal K1 it outputs at its output terminal a signal corresponding to the signal supplied by the differential amplifier circuit. When not selected by the signal and Κθ it puts its output terminal in the floating state. Therefore, the input terminal of the output buffer circuit OUT is supplied only with the output signal of that of the sense amplifiers ΒΑθ to SAg which has been selected by the selection signals Κθ to Kg. Each of Figures 4 and 5 illustrates a writing circuit according to another embodiment capable of replacing the writing output circuit illustrated in Figure 2B. Arranged in each of the circuits of the embodiments is an output circuit consisting of KISFETs to Q„„,. In the previous stage of the output circuit, a suitable logic gate circuit is provided which is supplied with the write control signal we, the write data and the select signal. Signals at a level substantially equal to Vpp are provided at output terminals N. and N ri of the output circuit during the write operation if data fed to the common I n / Out terminal are 0 or low level. A MlSPET Q„ „ < is disposed between the output terminal Np of the output circuit and the corresponding common bit line (e.g. ΟΒθ). A Zenere diode ZI) similar to that of the previous form of rea! i zzasi one is connected to the output terminal N^ through a MlSPET current fixer MlSPET Q. The gate of the MlSPET Q.., is connected 115 Up of the Zener diode Z1) either directly or through a level shifter MlSPET Q,, / · Thus, the common bitline voltage CIP is determined by MlSPET Q --zr. 116 In the circuit according to the embodiment of « e Figure 4, a Zen voltage applied directly to the gate of the fixer MlSPET In response to this, the common bitline voltage ΟΒθ reduces to a component equal to the threshold voltage of the MlSPET yelped, the discharge or avalanche breakdown does not occur in the non-volatile memory element P. According to the circuit of this embodiment, the voltage which is applied to the drain of the memory element P1 during writing becomes relatively low. Therefore, the circuit is not suitable for the case where a relatively high writing speed is required. In the circuit of the embodiment of Fig. 5 , the level shifter MlSPET arranged as in the embodiment of Fig. 2(B). According to the circuit of FIG. 5, therefore, the voltage which is applied to the gate of the fólSPET is increased approximately to the threshold voltage V of the KlSf'BT tnb with respect to the voltage of the Zcner diode ZI) as in the circuit of the embodiment of FIG. b. Accordingly, the common Bitline potential can be set substantially to the Zener voltage as in the circuit of the embodiment of FIG. 2B. Thus, the write voltage to be applied to the bit line can be precisely set to a value which is necessary to prevent avalanche breakdown in the non-volatile memory element and which is close to the maximum voltage. Thus, the non-volatile memory element is allowed to perform a write operation at high speed. In this way, the circuit which carries out the voltage fixing in the writing circuit can be variously modified. As a constant voltage element for predetermining the clamping voltage, it is convenient to use the semiconductor regions which are formed simultaneously with the formation of the semiconductor regions of the nonvolatile memory element as stated above. However, this is not limiting, and various constant voltage circuits may also be utilized. to etc. In order to obtain a high-speed writing operation, the non-volatile memory elements F , are manufactured according to the structure illustrated in Figs. 6 (A) - 6(C). Fig. 6(A) is a diagram of configuration or drawing, Fig. 6(B) is a sectional view taken along the line B - B 1 of Fig. 6(A) and Fig. 6(C) is a sectional view taken along line A-A' of Fig. 6(A). Referring now to Figures 6(A) to 6(0), the numeral 1 designates a substrate of. semiconductor consisting of a p-type silicon or Si single crystal in which a determining impurity of the conductivity type 5 3 is contained and at a concentration of, for example, 10 atoms / cm. A major or major surface of the substrate 1 is formed with a thick film 2 of field SiO2 (silicon dioxide). A portion surrounded by the SiO2 field film 2 yields an active region. The substrate surface constituting the active region is formed with a thin film of SiO3. The gate 3. Above the SiO3 gate film is a floating gate FG which is made of a first layer of polysilicon. stay as a conductor. Above the floating gate electrode FG is arranged, through an intermediate insulating film 5a, a control gate electrode CG which consists of a second; polycrystal 3 inoconducting silicon layer substantially forming a line of words. ^OS^' Z fr o Bcnchfe not. if this is specifically limited, the floating gate FG has a width equal to that of the control gate CG and extends over the field SiO2 film 2. In Fig. 6(A), the end portions of the floating gate FG are indicated by dotted lines a and E^ c w In that surface of the semiconductor substrate 1 which is not surrounded by the SiO2 film? of field 2 and the gate electrodes, semiconductor regions of the η type are formed, indicated by .R , 4 C;., 4.,, 4 CO and R , the 1 Ol JJ br <s which are formed by introducing an n-type impurity with a relatively high concentration. The n-type semiconductor region 4 Q 4 is used as the source region of a non-volatile memory element. has the n* type semiconductor region R2 which extends in the lateral direction in the drawing as shown in FIG. 6(A) is employed as a region constituting a reference potential line. I.a source region 4 Ο. θ the connection or wiring region R^ are integrally formed as fe illustrated in the drawings. I.a region of. n-type semiconductor 4g^ 4fe similarly employed as the source region of another nonvolatile memory element, and the semiconductor region R? The n-type is employed as a region ói with the 1 bondOiOsS'*'' has region 4 T. The n-type semiconductor* is employed as the common well regions of the pair of non-volatile memory c1 emeritus. Above the control gate electrode OG, a connecting layer 6 is formed which forms a bit line (consisting, for example, of a layer of evaporated aluminum) through an intermediate insulating film 5b so as to perpendicularly intersect the control or command gate electrode. The link layer 6 is maintained in olimic contact with the region of. well 4^ in a contact portion CN?. As shown in Fig. 6(C), in the surface of the semiconductor substrate 1 below the SiO film? In field 2, a p-type region 7 is formed which has the same conductivity type as the substrate and a higher impurity concentration than that of the substrate, acting as a channel stopper. Moreover, 4 if necessary, a p-type region 7a having an even greater impurity concentration is formed in that part of the channel portion of the semiconductor nonvolatile memory element which is close to the field SiO2 film. Therefore, the non-volatile memory element having this structure, when, by way of example, the write voltage is applied to the drain region 4., * JJ and the signal of. piloting of the lines. word having the selection level is applied to the control gate CG^, the widening of the susceptibility depletion layer 1 and to widen up to the region 7& of type p* -* from the junction portion between the drain region 4 ^ and the region of type ρ, 7a, is limited, and accordingly the intensity of the drain field is intensified. The electrons forming a channel current are accelerated more by the high strength of the drain field. Therefore, high energy a is imparted to the electron-hole pairs which are created when the electrons collide against the crystal lattices of the semiconductor. In other words, the efficiency or efficiency of generating the hot electrons is improved, and the re-reading speed is sharply increased. The non-volatile memory element, in which electrons are injected into the floating gate PG through the film 3 of. YesO? As is well known, this floating gate PG goes negative in potential, whereby the threshold voltage for the control gate CG is made relatively large, such as about 7 volts. Conversely, in the case where electrons are not injected into the fluctuating gate PG, the threshold voltage for a voltage from < apply to the control gate CG c output of a relatively low value such as about 2 volts. Thus, when the word line drive signal selection level, i.e., the level of the signal c to be applied to control gate CG, is set to the mean value between the high and low threshold voltages of the memory element, e.g. 5 volts into the 1st read operation, the memory element drops into the on state or the off state depending on whether or not electrons are injected into the floating PG anti-chatter gate. Therefore, reading can be implemented. While not particularly limiting, the nonvolatile memory element, as stated above, can be fabricated by a manufacturing method to be described hereinafter. B and Figures 7(&) 7(f) illustrate sectional views of a semiconductor substrate in respective manufacturing steps. Thus, the method of manufacturing an embodiment will be described with reference to Figs. 7a to 7f. B and left portions I of Figures 7(a)-7(f) illustrate a non-volatile memory element, while right portions II illustrate a KISFBT for constructing a peripheral circuit. (a) A semiconductor substrate 1 made of p-type monocrystalline silicon is first prepared, the one parallel to the ( 100) plane which has microns and a resistivity of about Si 0, thermally thin, whereby surfaces are greater ò a thickness of about 200 ca 20 ohm x cm A 3* coated film having a thickness of, for example, several hundred o A is formed on the surface of the substrate 1 by the known thermal oxidation technology in order to prevent the induction of crystalline defects in the surface of the substrate 1 due to the subsequent formation of a silicon nitride film. Next, the silicon nitride (S12 N2) film 8 having a thickness of about 1400 A is formed on the SiO2 film 3' by known chemical vapor deposition technology employing silane and ammonia. ca gas.so yes. A photoresist film (not shown) for an etch mask is formed on the film 8 whereupon the photoresist film is selectively moved to light and developed. As a consequence, the photoresist film is left on parts of the substrate 1 which are to be made active regions. Subsequently, by supplying the remaining photoservic film as an etching mask, the Si JC film is etched and removed. For the chemical content of the Si 3 N 8 film 8, it can be used for the plasma etching process using freon gas as the reaction gas. After removing the aforementioned tori film, a tori film is again formed on the substrate 1. photorescrip 9 fo O -> ' Da photoresist film 9 is scientifically exposed to light and is developed so that a window can be formed to form the ρ-type region 7a, as b illustrated in Figs. 6(A) to 6(C), midi before combining Si2 N2 film 8 with photoresist film 9. Using the remaining photoresist film 9 and Si2H2 film 8 as an ion implant mask, a p-type impurity is introduced into the surface of substrate 1 through SiO2 film 3* by ion implant technology , as b illustrated in Fig. 7(a). In this case, BE^* (boron fluoride) is used as the impurity ion, although no specific restrictions are intended. The impurity ions b are imparted energy of e.g. 75 BeV, and they are implanted into the surface of the substrate 1 with a concentration of e.g. about 10 atoms / cm2, Since BE^ as an impurity ion has a greater mass than that of impurities such as B ions 5? - (boron) (the mass of BF is 4 9 and the mass B is 11 ), there is difficulty in penetrating through the Si^N^ film 8 and the underlying SiO^ film 3*. Therefore, even when the Si-IL film 8 is made relatively thin as described above, the impurity is not introduced into the substrate surface 1 below the Si-.N. skin 8. 4(b) Subsequently, after having removed the photoresist film 9, the substrate 1 is annealed at a temperature of for example 1100°C in an inert gaseous atmosphere such as for example gaseous nitrogen. Based on the annealing treatment, the impurity introduced into the surface of the substrate 1 is diffused by insertion diffusion. As a result, the ρ-type region 7(&) is formed, extending into the substrate surface below the Si2 N2 film 8. After the annealing treatment, using the Si2 N2 film 8 as a mask, BF ? are implanted for the second time in the entire surface of the substrate 1 under the conditions in which, for example, 75 BeV and 2 x 10 atoms / cm are established. The impurity for forming the p-type layer 7 4 as a channel stopper is introduced into the substrate surface 1 by the second ion implantation. The impurity ion implantation operations can also be altered as follows. First, the Si2 N2 film 8 formed on the SiO film 3' is coated with a photoresist film. The photoresist film on the part where. is to be formed layer 7(&) of t / *11 p or p is removed by exposure and development. Yes^. Using the remaining Si film 8 and the overlying photoresist film as an ion implantation mask, p-type impurity ions are first implanted into the surface of substrate 1. After removing the photoresist film, the substrate 1 is annealed as above. The entire surface of the substrate is again covered with a photoresist film 9. The photoresist film 9 is selectively exposed to light and is developed to remain on the part to be made the active region. Using the remaining photoresist film 9 as an etch mask, the Si2 N2 film 8 is selectively etched and removed. Using the remaining photoresist film 9 and Si2 N2 film 8 as an ion implantation mask p-type impurity ions are implanted for the second time into the surface of substrate 1. In such an altered procedure, in the first ion implantation step, that surface of the substrate 1 which is not to be ion implanted is covered with the Si-2N2 film 8 and the Si-2N2 film 8. stacked stock. In the second ion implantation step, that surface of the substrate 1 which is not to be implanted with ions, in particular the surface which is ultimately to be made the channel region of the 1 * el omentum ε field effect, is similarly covered with the ^3^4 film 8 and photographic film 9 stacked or superimposed. Accordingly, it can be satisfactorily prevented that impurity ions are undesirably introduced into the surface part of the substrate 1 intended to ultimately be made the channel region of the field effect element. (c) After the second operation tìi. implantation of the impurity ions, the substrate 1 is heated to about 1000°C, for example in an oxygen atmosphere containing water vapour. Thereby, a relatively thick field oxide film 2 having a thickness of, for example, about 1 micron is formed on the surface of the substrate 1. Thus, in this case, the Si2 N2 film 8 behaves as an oxidation mask, the surface of the substrate 1 co bears with the film 8 of is not formed with the field oxide film 2 as seen in Fig. 7(c). In this oxidation treatment, the p-type impurity which was introduced to the substrate surface by ion implantation in advance is diffused into the substrate. Thus, the p-type region 7(a) 14 is caused to extend deeply beneath the field oxide film 2 proximate the region forming the memory element. A part of the p-type region 7(a) lies outside the active region (below the film), At the same time, the p-type region 7 having the same concentration as the channel stopper is formed under the field oxide film 2. Since the p-type impurity which is introduced by the second impurity ion implantation step has a relatively low concentration as described above, the p-type region 7 4 is hardly extended to the active region. According to the manufacturing process described above, it is possible to self-align between the field SiO2 film 2 and the field SiO2 region 7a. The type p , c can be manufactured very precise and small size memory cells with a good yield. In addition, the core portion and the Si^N^ film in the peripheral portion can be processed in one step, so the bias need not be taken into account. MOnc of mask alignment. (d) After field oxidation, the Si,N. it is etched and removed by the known etching process which employs heated phosphoric acid. If necessary, the 3' film of SiO? is removed by a process such as a washing process, after which. the exposed surface of substrate 1 is formed with a thin film of BiO2 (not O shown) having a thickness of for example about 400 A, by the thermal oxidation process. The entire surface of the substrate 1 is recoated with a photoresist film. The photoresist film is selectively exposed to light and developed so that the portion to be rendered can be exposed to the channel region of the field effect transistor. By using the photoresist film and field oxide film 2 as an ion implantation mask, As (arsenic) ions as an n-type impurity are implanted into the surface of the substrate 1 under stable conditions 1 e.g., 1 50 keV and 3 x 10 atoms / cm * After removing the photoresist film, the thin SiO2 film is removed. The substrate 1 is heated, for example, to 1000°C in an atmosphere of oxygen, thus forming a film 0 ói Si 0? The gate is about 500 A thick on the exposed surface of the substrate 1. In the case where insulated gate field effect transistors having voltages of. Relatively high thresholds are required in peripheral circuits, e.g. of the 25 volt type, a relatively thick SiO2 gate film, e.g. 800 A thick is formed by thermal oxidation prior to film formation of SiO2 gate, and is subsequently effectively removed from the surface of the substrate 1. Subsequently, the SiO2 gate film can be formed. reactively thin* After formation of the SiO2 gate film, boron ions having an energy of, for example, 70 keV can be introduced into the substrate surface through the SiO2 film 3 if it is necessary to control the threshold voltage of a high-mode transistor. enrichment to a desired value, for example. After forming the SiO2 gate film 3, a Si polycrystal 1 in 10 layer having a thickness of about 3500 A is formed on the surface of the substrate 1 by the CVD (Chemical Vapor Deposition) process. vapor deposition) in order to form the floating gate electrode of the memory transistor, the gate electrode of the peripheral transistor and the required connection layer. Thereafter, a photoresist film 9' is formed on the Si polycrystalline layer 10, and the photoresist film 9' is selectively exposed to light and developed. Using the remaining photoresist film 9' as a mask, the polycrystalline Si layer 10 is selectively etched (patterned or patterned) as shown in Fig. 7(d) so as to form the floating gate PG of the memory transistor, the electrode of gate G of the peripheral transistor and the necessary connection. (e) After removing the photoresist film 9', P (phosphorus) ions are implanted into the Si polycrystalline 1 ino state by the ion implantation method. Thus, the polycrystalline Si layer to be made between the gate electrodes PG and G and the bonding layer is made to be n-type and is imparted the low resistance characteristic. Subsequently, the substrate 1 is heated in an oxidizing atmosphere to form a SiO film 5a of about 800 A thickness on the surface of each of the PG and G gate electrodes and the bonding layer as illustrated in Fig. 7 (e ). The SiO2 films function as an intermediate insulating film (ί) On the surface of the substrate subjected to step (6) is formed by the method CVD the second layer of polycrystalline silicon, layer 0 CG having a thickness of about 35θθ A. Next, phosphorus is introduced into the surface of the second layer of the polycrystalline silicon CG layer, as a conductivity type determining impurity, by an appropriate impurity deposition method. Subsequently, a photoresist film is formed on the surface of the substrate 1. While no specific limitation is intended, the width of the floating gate BG in the memory element is made equal to that of the control gate CG, in this embodiment. To such. Finally, the photoresist film is selectively exposed to light and developed to determine the patterns of the control gates and lines of words in the portion of the memory array. Thus, except for the portion to be rendered the memory array, the photoresist film is left substantially intact from exposure and evi 3 affixing. After exposure and development, using the remaining photoresist film as an etch mask, the second layer of the polycrystalline silicon layer is selectively etched and removed. :"And Using the remaining polycrystalline silicon layer CG as a mask, the SiO2 films 5a the surface of the first layer of the polycrystalline silicon layer FG 1ino are etched and removed. Next, using the second layer of the polycrystalline silicon CG layer and the SiO2 films, 5a, in masking action, the first layer of the polycrystalline silicon FG layer is etched and removed. By such etching, the width of the first layer of the polycrystalline silicon FG layer is determined by the width of the second layer of the polycrystalline silicon CG layer. After removing the photoresist film, a photoresist film is re-formed on the surface of the substrate 1. This newly formed photoelectric film is selectively exposed to light and is developed in a pattern in which the unnecessary portions of the second layer of the silicon layer then crystallize up to the top of the gate electrodes of the effect transistor. isolated port field devices constituting the peripheral circuits are removed. The second layer of the polycrystalline silicon layer is also utilized as the second gate electrodes in stacked gate type transistors constituting the peripheral circuits. Therefore, the new photoresist film is pu61 re left on portions intended to be made second gate electrodes of stacked gate type transistors. Using the photoresist film as an etching mask, the second layer of the silicon layer then the crystals is selectively etched and removed. The photoresist film is then removed. In the stage after the removal of the photoresist film, only the relatively thin SiO2 film is left on the surface parts of the substrate 1 not covered by the field oxide film 2 and the first and second layers of the polycrystalline silicon layers. that is, the surface portions provided to form the source and drain regions of the transistors and the surface portions provided to form the semiconductor connection regions. If necessary, the relatively thin SiO2 film is removed by a chemical etching process such as the washing process. Subsequently, a SiO2 film approximately 35θ A thick is formed on the exposed surface of the substrate 1 by the thermal oxidation process. The SiO2 film is also formed on the exposed surfaces of the first and second layers of the polycrystalline silicon layers by thermal oxidation. Next, using the field oxide film 2 and the silicon polycrystalline layers as an ion implantation mask, phosphorus ions are introduced into the surface of the substrate 1 so as to establish, for example, a depth of 1 micron and a concentration of 10 atoms / cm . As a result, the n-type source and drain regions of the transistors and semiconductor bonding regions are formed in the surface of the substrate 1. In the next step, if necessary, the substrate is heated to. a relatively low temperature of, for example, 800°C, for example, in an oxidizing atmosphere so as to form the insulating films 5b on the exposed surfaces of the polycrystalline silicon layers. The structure obtained so far is: illustrated in figure 7f Subsequently, using a photoresist film as a mask to lead out electrodes, the SiO? on the drain source regions it is selectively etched and removed. After removing the photoresist film, a photoresist film is then formed on the surface of the substrate. PSG (phosphosilicate glass), such as about 800 A thickness * Using a photoresist film as a mask, the PSG film is selectively etched to form contact holes. - 63Λ After removing the photoresist film, Al (aluminum) is evaporated on the substrate, and the aluminum reservoir is patterned to form a bonding layer. The aluminum bonding layer 6 is illustrated for example in figures 6B and 60. In the non-volatile memory element having the In the above structure, the p-type region 7a is in contact with the drain region 44, whereby the discharge or breakdown of the pn junction takes place with a relatively low write voltage. Therefore, the write voltage to be applied to the bit line must be limited to a relatively low value. When a selected bit line, for example bit line B of Fig ur fi ?A is supplied with a write voltage exceeding the drain breakpoint voltage of the memory element, the drain junctions of the plurality of memory elements memory F^ - F^ belonging to the bit line undergo respectively the avalanche discharge. In the event that the avalanche discharge has occurred in this way, holes generated by the avalanche discharge are injected into the floating gates of the memory elements, and the rewriting efficiency deteriorates. According to the present invention, the write voltage to be applied to the well of the memo element ria is formed by diode a. constant voltage having a breakdown voltage substantially equal to the breakdown voltage of the drain junction of the memory element. The constant voltage diode is formed on a single semiconductor substrate by integrated circuit manufacturing technology together with transistors to build a plurality of memory elements and peripheral circuits and the constant voltage diode is formed in a appropriate part of the peripheral portion of the semiconductor chip unless carriers injected into the substrate due to its junction discharge have adversely affected the memory elements. According to the present invention, a constant voltage diode of appropriate structure can be obtained which can be formed on the semiconductor substrate together with the memory elements. FIG. 8A illustrates a sectional view of such a constant voltage diode while FIG. 8B illustrates a plan view. As fe illustrated in the figures, the constant voltage diode fe consists of a semiconductor region of the η* type, 4a and has a p-type region 7a tìi 44. An electrode and a bonding layer K such as an evaporated aluminum layer are kept in non-rectifying contact with the region 4a of an n-type conductor air as the cathode of the diode through a hole-aperture portion provided in a SiOp film 3. Although not illustrated, the bonding layer K is extended over a field oxide film 2 and is connected to the sources of the echo transistors. as illustrated in FIG. 2B. While no specific limitation is provided, a BE electrode, such as of gold is disposed on the lower surface side of the semiconductor substrate 1. 3, the anode electrode of the constant voltage diode is all made up of the BE electrode. The semiconductor region 7& is formed simultaneously with the p-type region 7a of FIGS. 6A to 6C of FIG. 7, while the semiconductor region 4a is similarly formed simultaneously with the well source regions 4 C.,, 4 CO c 4 Tì àegli. non-volatile memory items 1 s ? u le. In FIGS. 8A and 8B, an n*-type region 4b is formed to surround the r / -type region 4a unless the carriers injected into the substrate 1 due to constant voltage diode operation have to exert some detrimental effect on non-voile memory elements. Carriers injected into substrate 1 can dif66 tf) fi ei 3 mind pass outside the N-type region 4b » In the drawings, the n* type region 4b is shown as being held at a predetermined circuitry potential. The n-type 1 region 4b, however, may also be maintained at the level of the circuit power supply voltage Vc. According to this embodiment, the junction Η I H nc ρ -n in the nonvolatile memory element and the junction -J 4 ne p -n of the Zener diode ZI) are formed by the same manufacturing step, whereby the breakdown voltages of both junctions are equal despite the dispersion of the manufacturing process. It is therefore possible to obtain a clamping voltage such as to accurately prevent snowballing into the nonvolatile memory element. As shown in FIG. 2B the write circuit is of the type where the output M1SFET Q, etc., 5? placed on the high voltage side, it is controlled by the logic circuit operating at the low voltage Therefore, the write circuit can also be made simple as far as the regards the circuit arrangement and low power dissipation, FIG. 9A illustrates a configuration diagram of a memory array while FIG. 9B illustrates a structural sectional view taken along line A-A* of the <ov6> figure 9A Referring to Fig. 9A , a field oxide film ? with a configuration indicated by the combination of the oblique lines ascending to the right and the solid lines is formed on the surface of a p-type semiconductor substrate 1. Word lines VL to VL formed by layers of ei 15 li what then i were 1 ino are also extended over the surface of the substrate 1 in the lateral direction of the drawing. Make you predetermined lines of words from to form the control gates of memory-to-unflown elements! and solid state Óa F Ί a F , r . from F o & F , and from F to F rinl n-1 21' n2 n+22 nj n-f23 respectively. Floaters, as evident from FIGS. 6A through 6C and FIGS. 2a through 7f, are located below the control gates. In FIG. 9A, the configuration of the floating gate is indicated by the combination of dashed Ir ncc and oblique lines descending to the right. In that surface of the substrate 1 which is not covered by the field oxide film 2 and the word lines a are formed n-type semiconductor regions 1 to be used as the drain source regions of the non-volatile memory elements a semiconductor and semiconductor connection regi onl. A semiconductor region R1 which is disposed between t Ik the lines of words W c which is extended in parallel with these lines of words W c W is used as the region of l F- k, common source of memory elements which P - to E and n1 n+21 from P „ a P r the semiconductor region R. constitutes n? rH2? 1 the R line of the reference potential as shown in the figure. 2A. Arranged on the semiconductor substrate 1 are a plurality of conductive layers B1 to c1 and are constituted. for example from aluminum layers which are extended in the vertical direction in the drawing. These conductive layers constitute bit lines respectively. The respective conductive layers are connected to the drain regions of the memory elements via contact holes. By way of example, the conductive layer B is bonded with the drain regions of the elements d. memory Ρ η, Ρ,. Ρ -, P P etc* through the contact holes ni’ n?’ n3 n4’ n5’ CH CH n and CH n1' n? n3 In the memory array of Fig. 9A , a plurality of switching MTSPBTs of 6 are constructed together with the plurality of memory elements. By way of example, the switching TiISPPT S. consists of a region of. source 10 C„, the word line W and the semiconductor region R^, the switching MISERI' consists of the semi-conductor region 69 ΓΑ, the word line VL· and the source rcgion 1 2 ZO 10 . Furthermore, the switching element S- is co 5? j ** established by the region of. source 10^ from the word line and the semiconductor region R^. I IJSEET switching, eg S ? and S^ belonging to a group of word lines and TV have their source regions realized in common. wells of the switching PISEETs consist of the semiconductor regions R1, R1, R1, etc. Ee sources of the switching PJSEETs are connected to the GNU ground line through contact holes. The ground line GO may be formed in parallel with the bit lines, and may be formed of aluminum bonding layers in a similar manner to the bit lines. Therefore, the gates of the switching PISEETs can be formed by the step of shaping the word lines, and the ground line for the switching PISEETs can be formed by the step of shaping the bit lines, The semiconductor regions constituting the switching PISEET can be formed without compromising the regularity of the memory array configuration. Thus this embodiment has the advantage that the switching PISEETs can be inserted into any desired part of the matrix portion of the memory. In ϋ) added, the integration density is not compromised These semiconductor devices can be formed by the semiconductor manufacturing method which has been described above, the reason why these switching MI SEBI's are arranged in the memory matrix portion is to prevent channel leakage currents as mentioned previously. Therefore, the switching MISFETs of this embodiment are not provided with regions such as the p-type region for high-speed writing that are provided in the substrate surface in the direction of the element channel. memory. Switching MISFETs designed to prevent channel leakage currents, as mentioned above, can also be widely applied to EPROMs employing memory elements not provided with any p-type regions

Claims

1. CLAIMS. A read-only memory program 1 and electrically comprising: a plurality of non-volatile memory elements whose command control gates are combined to a first line of words, characterized in that it comprises: a first switching M1SFET, at least one source electrode of the source electrodes of said plurality 71 or of said non-volatile memory elements being connected to. a reference potential through the source path of said first switching MlSPET, the gate electrode of said first switching MlSPET being connected to said first word line,?. Electrically programmed read-only memories 1 according to claim 1, wherein said electrodes are electrically programmed. source of said plurality of said non-volatile memory elements are connected in common to said reference potential through said drain-source path of said point or MlSPET of. switching * 3. Read-only memory programmed! and electrically according to claim 2 further comprising: another plurality of memory elements, not flying 1 and whose control or command gates are connected in common to a second line of words; and a second switching MISPET, wherein source electrodes of said other plurality of said non-volatile memory elements are connected in common to said reference potential through the drain source path, of said second switching MISPET, the electrode gate of said second switching M1SPET being connected to said second word line, and said source electrodes of the first and second plurality of non-volatile memory elements and drain electrodes. said first and second 72 switching MJSPKTs being connected in common. * 4. Electrically programmable read-only memories according to claim 3, wherein said reference potential is the ground potential of the Circuits. The Agent: Dr. Ing. G.MODI ANO -