Scalable high-voltage control circuits using thin film electronics

Abstract

To provide scalable high-voltage control circuits.SOLUTION: A high-voltage switching device for driving an EMS actuator includes first transistors 120A-120J each having a first source, a first gate, a first drain, and one or more electrodes. The first transistors serve as an inverter. The device also includes second transistors 140A-140J each having a second source, a second gate, and a second drain. The first and second sources are connected together. The first and second drains are connected together. The second transistors serve as an output, a driver, or both. The one or more electrodes, the second gates, or combinations thereof serve as tapped drains that are configured to sample a stepped voltage of the second transistors.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure generally relates to microelectromechanical systems (MEMS), and more specifically to high-voltage switching devices for driving MEMS actuators.

Background Art

[0002] MEMS are small (e.g., microscopic) systems, especially those having movable parts. MEMS are fabricated from components sized from 1 to 100 micrometers (μm), and MEMS generally range in size from 20 micrometers to 1 millimeter (mm). MEMS typically include a central unit for processing data (e.g., a microprocessor) and several components that interact with the environment (e.g., microsensors). Due to the large surface area to volume ratio of MEMS, forces generated by the surrounding electromagnetic (e.g., electrostatic charge and magnetic moment) and hydrodynamic (e.g., surface tension and viscosity) are more important design considerations than those of larger-scale mechanical devices.

[0003] MEMS typically use electrostatic actuation, piezoelectric actuation, or thermal actuation. Electrostatic actuation scales down better to smaller sizes than electromagnetic and thermal actuation. However, electrostatic actuation typically relies on higher voltages (e.g., several kV) than electromagnetic and thermal actuation to generate sufficient output. Both generating and controlling such high voltages in microelectronic components having actuators of comparable size and weight are difficult.

Summary of the Invention

[0004] The following is a simplified overview to provide a basic understanding of some aspects of one or more embodiments of this teaching. This overview is not a broad summary and is not intended to identify the main or important elements of this teaching or to specify the scope of this disclosure. Rather, its primary purpose is simply to present one or more concepts in a simplified form as a prelude to the detailed explanations that will be presented later.

[0005] A device is disclosed. The device includes a first transistor having a first source, a first gate, a first drain, and one or more electrodes. The first transistor acts as an inverter. The device also includes a second transistor having a second source, a second gate, and a second drain. The first and second sources are connected together. The first and second drains are connected together. The second transistor acts as an output, a driver, or both. One or more electrodes, the second gate, or a combination thereof acts as a tapped drain, configured to sample the step voltage of the second transistor.

[0006] A switching device for driving an actuator is also disclosed. The switching device includes a first transistor configured to act as an inverter. The first transistor includes a first source, a first gate, a first drain, and a plurality of electrodes spaced apart from each other. The electrodes are at least partially located between the first gate and the first drain. The switching device also includes a second transistor configured to act as an output, a driver, or both. The second transistor includes a second source. The first and second sources are connected together. The second transistor also includes a second gate. The second transistor also includes a second drain. The first and second drains are connected together. The second transistor also includes a plurality of field plates spaced apart from each other. The field plates are at least partially located between the second source and the second drain. Each field plate is connected to one of the electrodes. The electrodes, second gate, or combination thereof act as a tapped drain configured to sample the step voltage of the second transistor to provide the field plate voltage of the second transistor.

[0007] Also disclosed is a high-voltage switching device for driving a micro-electromechanical system (MEMS) actuator. The switching device includes a first transistor configured to act as an inverter. The first transistor includes a first source, a first gate, a first drain, and a plurality of electrodes spaced apart from each other across the high-voltage drift region of the non-gate channel of the first transistor. The electrodes and non-gate channel of the first transistor are at least partially located between the first gate and the first drain. The switching device also includes a second transistor configured to act as an output, a driver, or both. The second transistor includes a second source. The first and second sources are connected together. The second transistor also includes a second gate. The gate of the second gate is connected to one of the electrodes. The second transistor also includes a second drain. The first and second drains are connected together. The second transistor also includes a plurality of field plates spaced apart from each other across the non-gate channel of the second transistor. The field plate is configured to distribute a high voltage substantially uniformly across the non-gate channel of the second transistor. The field plate and the non-gate channel of the second transistor are at least partially located between the second source and the second drain. Each field plate is connected to one of the electrodes. The electrode, the second gate, or a combination thereof acts as a tapped drain that distributes between the first gate and the first drain. The tapped drain is configured to sample the step voltage of the second transistor to provide the voltage at the field plate of the second transistor. [Brief explanation of the drawing]

[0008] The accompanying drawings, which are incorporated into and constitute part of this specification, illustrate embodiments of this teaching and serve to illustrate the principles of this disclosure together with this specification.

[0009] [Figure 1]This diagram shows a schematic representation of a high-voltage switching device for driving a MEMS actuator, according to one embodiment.

[0010] [Figure 2] This shows an enlarged view of a portion of Figure 1 according to one embodiment.

[0011] [Figure 3] This shows a circuit diagram of the first stage of the device according to one embodiment.

[0012] [Figure 4] This diagram shows a circuit diagram of multiple (e.g., four) stages of devices stacked together according to one embodiment.

[0013] [Figure 5] This shows a schematic side cross-sectional view of a portion of the first stage of the device according to one embodiment.

[0014] [Figure 6] This graph shows the current-voltage characteristics of the first stage of the device according to one embodiment.

[0015] [Figure 7] This graph shows the current-voltage characteristics of multiple stacked and / or cascaded device stages (e.g., four stages) according to one embodiment.

[0016] [Figure 8] This shows a schematic side cross-sectional view of a portion of the first stage of the device according to one embodiment.

[0017] [Figure 9] This graph shows the current-voltage characteristics of the optical switch of the device, in one embodiment where an n+-doped a-Si:H layer is at least partially positioned between the S / D metal layer and the channel.

[0018] [Figure 10]A graph showing the current-voltage characteristics of an optical switch when, according to one embodiment, the S / D metal layer is positioned at least partially (i.e., in direct contact) over the channel (shown on the right side of FIG. 8).

[0019] [Figure 11] Schematic diagram of another high-voltage switching device for driving a MEMS actuator according to one embodiment.

[0020] [Figure 12] Represents an enlarged portion of FIG. 11 according to one embodiment.

[0021] [Figure 13] Schematic side cross-sectional view of a portion of the device shown in FIG. 11 according to one embodiment.

[0022] [Figure 14] A graph showing the conversion characteristics of the device of FIG. 11 according to one embodiment.

Mode for Carrying Out the Invention

[0023] Here, exemplary embodiments of the present teachings are referred to in detail, and this example is shown in the accompanying drawings. As far as possible, the same reference numerals are used throughout the drawings to refer to the same, similar, or like parts.

[0024] This disclosure relates to micro-electromechanical systems (MEMS). A first embodiment of the MEMS may be or may include an optical coupler (also known as an optocoupler). The optical coupler technique simplifies the interface and isolation to low-voltage control circuits. The optical coupler technique can also increase voltage ratings by cascading (e.g., stacking) multiple stages. The optical coupler technique may have reduced energy efficiency because a light source is required to turn the device on and off. A second embodiment of the MEMS may be or may include a two-stage inverter / buffer transistor structure in which an inverter thin-film transistor (TFT) and a buffer TFT are densely integrated at the subdevice level. Such dense integration helps to uniformly distribute the high voltage across the drain region of the buffer TFT so that high voltage ratings can be achieved.

[0025] High-voltage (HiV) TFTs based on hydrogenated amorphous silicon (a-Si:H), particularly "offset-gate" TFT architectures, can provide operating voltages of 200V to 500V or 300V to 400V. The offset-gate TFT architecture may have a non-gate drift channel region, which provides a section of semiconductor for distributing the high voltage across the entire non-gate region to prevent any outflow processes caused by the high electric field. The non-gate region can be scaled in length to maintain the same electric field with any voltage (e.g., E=V / L). In one embodiment, an 800V HiV TFT can be constructed based on this design.

[0026] However, this method becomes increasingly ineffective when scaling voltages above 800V. It is difficult to maintain a uniform distribution of high voltage across the entire non-gate region to prevent localized concentration of high voltage that could cause a runaway failure process. In addition, having longer non-gate regions can have adverse effects on the on-current. Non-gate channels are inherently "resistive." The on-current of a TFT with a long non-gate channel may be small for the same channel width. Increasing the length of the non-gate channel can drastically reduce the on / off ratio. An 800V HiV-TFT can have an on / off ratio of about 3-4 orders of magnitude. A fundamental challenge for scalable high-voltage drivers with reliable methods for implementing desired voltages over a wide range is preventing runaway failure processes from occurring due to high voltage concentration in a small area of ​​the channel material or device.

[0027] Multiple separate transistors can be cascaded to extend the operating voltage range. However, implementing this in a TFT circuit is difficult and has not been done until now. Several differences exist between using separate devices and TFT processes. Only N-type metal-oxide-semiconductor (NMOS) active devices are available in the a-Si:H TFT process. No P-type metal-oxide-semiconductor (PMOS) or bipolar devices are available. Resistors limit the range of the a-Si:H TFT process and are generally considered an inefficient use of layout space. Subcircuits are typically complex DC-DC converters that exceed the capabilities of the TFT circuit, so providing multiple voltage rails to support subcircuits in controlling the gates of a cascaded transistor array is generally not feasible.

[0028] Figure 1 shows a schematic diagram of a high-voltage switching device 100 for driving a MEMS actuator according to one embodiment, and Figure 2 shows an enlarged view of a portion of Figure 1 according to one embodiment. The device 100 may include one or more optical switches (10 are shown: 110A to 110J). The optical switches 110A to 110J may be or include photodiodes (e.g., semiconductor diodes) that convert light into electric current. In one embodiment, the semiconductor may be or include a-Si:H. Each semiconductor may include two terminal contacts. The terminal contacts may form a Schottky barrier against the semiconductor. The terminal contact material may be or include TiW, MoCr, Mo, Ito, or a combination thereof.

[0029] Device 100 may also include one or more first transistors (10 are shown: 120A to 120J). The first transistors 120A to 120J may be or include TFTs. The first transistors 120A to 120J may be long and narrow to provide a discharge path for the gate of the second transistor (introduced and described below). For example, the first transistors 120A to 120J may have a length of about 20um to about 500um and a width of about 3um to about 10um.

[0030] Each of the first transistors 120A to 120J may include a source 122A, a gate 124A, and a drain 124A. As will be described in more detail below, each of the first transistors 120A to 120J may be connected to one of the optical switches 110A to 110J. For example, the first transistor 120A may be connected to optical switch 110A, and the first transistor 120B may be connected to optical switch 110B, and so on. The first transistors 120A to 120J may have a W / L ratio of less than 1. For example, the W / L ratio may be about 0.1 to about 0.01.

[0031] Device 100 may also include one or more second transistors (10 are shown: 140A-140J). The second transistors 140A-140J may be or include HiV-TFTs. More specifically, the second transistors 140A-140J may be configured to operate at higher voltages than the first transistors 120A-120J. For example, the first transistors 120A-120J may be rated to voltages of about 10V-100V (e.g., 20V), while the second transistors 140A-140J may be rated to voltages of about 200V-1000V (e.g., 400V). The second transistors 140A-140J may be shorter and wider / thicker than the first transistors 120A-120J. For example, the second transistor 140A~140J may have a length of approximately 3um to approximately 10um and a width of approximately 10um to approximately 1000um.

[0032] Each of the second transistors 140A to 140J may include a source 142A, a gate 144A, and a drain 144A. Each of the second transistors 140A to 140J may be connected to one of each of the optical switches 110A to 110J and one of each of the first transistors 120A to 120J. For example, the second transistor 140A may be connected to optical switch 110A and the first transistor 120A, and the second transistor 140B may be connected to optical switch 110B and the first transistor 120B, and so on. The gates 144A to 144J of the second transistors 140A to 140B may be controlled by the optical switches 110A to 110J. For example, each of the second transistors (e.g., 140A) may be controlled using each of the optical switches (e.g., 110A) and / or each of the first transistors (e.g., 120A) to bring the gate (e.g., 144A) of the second transistor (e.g., 140A) to the same potential as the source (e.g., 142A) of the second transistor (e.g., 140A). This may cause the second transistor (e.g., 140A) to be turned off when the optical switch 110A is not lit.

[0033] The optical switch 110A, the first transistor 120A, and the second transistor 120A may form the first stage of device 100, the optical switch 110B, and the first transistor 120B, and the second transistor 120B may form the second stage of device 100, and so on. Thus, device 100 may include multiple (e.g., 10) stages that are stacked and / or cascaded, which may help device 100 achieve an operating voltage range higher (e.g., 10 times) than that a single TFT can handle / withstand. For example, the optical switches 110A to 110J and the second transistors 140A to 140J may be cascaded in series to extend the operating voltage range of device 100.

[0034] Device 100 may also include one or more pads (two are shown: 150A, 150B). Pads 150A, 150B may be metal pads configured for use with a probe station for probing. The first pad 150A may be connected to a first stage (e.g., to a first transistor 120A and / or a second transistor 140A). The second pad 150B may be connected to a last (e.g., tenth) stage (e.g., to a first transistor 120J and / or a second transistor 140J).

[0035] Device 100 may also include one or more pads (10 are shown: 160A to 160J). For example, a first pad 160A may be connected to a first stage (e.g., a first transistor 120A and / or a second transistor 140A), and a second pad 160B may be connected to a second stage (e.g., a first transistor 120B and / or a second transistor 140B), and so on.

[0036] To turn on device 100, a light source (e.g., an LED controlled by a low-voltage control circuit) illuminates the photoswitch 110A-110J, which induces a photocurrent that biases the gate potential of the second transistor 140A-140J toward the drain voltage. This turns on the second transistor 140A-140J. The first transistor 120A-120J may act as a load for the photoswitch 110A-110J. A certain resistor is required to induce a gate voltage sufficient by the photocurrent to operate the second transistor 140A-140J in the ON state.

[0037] Figure 3 shows a circuit diagram of the first stage of device 100 according to one embodiment. As described above, the first transistor 120A may include a source 122A, a gate 124A, and a drain 126A, and the second transistor 140A may include a source 142A, a gate 144A, and a drain 146A. The drain 126A of the first transistor 120A may be connected to the first side of the optical switch 110A and the gate 144A of the second transistor 140A. The source 122A of the first transistor 120A may be connected to the gate 124A of the first transistor 120A and the source 142A of the second transistor 140A (for example, at the common node 170A). The drain 146A of the second transistor 140A may be connected to the second side of the optical switch 110A.

[0038] Figure 4 shows a circuit diagram 400 of multiple (e.g., four) stages of stacked devices 100 according to one embodiment. As shown, the drain 146A of the optical switch 110A and the second transistor 140A of the first stage may be connected to a common node 170B of the second stage, the drain 146B of the optical switch 110B and the second transistor 140B of the second stage may be connected to a common node 170C of the third stage, and the drain 146C of the optical switch 110C and the second transistor 140C of the third stage may be connected to a common node 170D of the fourth stage. The optical switches 110A to 110D may be positioned close together in the illumination area to ensure light utilization and uniformity of illumination. The optical switches 110A to 110D may be grouped together and controlled by one (or more) light sources actuated by low-voltage electronic components.

[0039] Figure 5 shows a schematic side cross-sectional view of a portion of the first stage of device 100 according to one embodiment. The first stage may be formed using a back-channel etch-stop a-Si:H TFT process. The first stage may include a gate dielectric layer (also referred to as a bottom nitride layer) 510, an interlevel dielectric (ILD) layer 512 located on the gate dielectric layer 510, and a (top) passivation layer 514 located on the ILD layer 512.

[0040] The first stage may also include an optical switch 110A, a first transistor 120A (not shown in Figure 5), and a second transistor 140A. The optical switch 110A may be at least partially located within the ILD layer 512 and / or passivation layer 514. The optical switch 110A may be mounted on the S / D metal layer (six portions 120A to 120F are shown). As shown, the first surface of the optical switch 110A may be mounted on the first portion 520A of the S / D metal layer, and the second surface of the optical switch 110A may be mounted on the second portion 520B of the S / D metal layer. The first portion 520A and the second portion 520B of the S / D metal layer may be located within the ILD layer 512. The first portion 520A and the second portion 520B of the S / D metal layer may be separated from each other (i.e., a portion of the ILD layer 512 may be located between them). A second portion 520B of the S / D metal layer may be connected to a third portion 520C of the S / D metal layer, which may be at least partially located within the gate dielectric layer 510. The third portion 520C of the S / D metal layer may be located on and / or connected to a field plate 522 located within the gate dielectric layer 510. The third portion 520C of the S / D metal layer may be connected to a fourth portion of the S / D metal layer 520D, which may be located within the ILD layer 512.

[0041] The n+-doped a-Si:H layer (five portions shown: 524A to 524E) can be at least partially located within the ILD layer 512. As shown, the first portion 520A of the S / D metal layer can be at least partially located within the first portion 524A of the n+-doped a-Si:H layer, the second portion 520B of the S / D metal layer can be at least partially located within the second portion 524B of the n+-doped a-Si:H layer, and the fourth portion 520D of the S / D metal layer can be at least partially located within the third portion 524C of the n+-doped a-Si:H layer.

[0042] The second transistor 140A may include a source 142A, a gate 144A, and a drain 146A. The second transistor 140A may also include a field plate 530 offset from the gate 144A within the gate dielectric layer 510. The field plate 530 may be located between the gate 144A and the drain 146A. A non-gate channel (e.g., an offset region) 532 may be located within the gate dielectric layer 510. The non-gate channel 532 may be located between the gate 144A and the field plate 530. The non-gate channel 532 may also, or instead, be located between the gate 144A and the drain 146A. The field plate 530 and / or the non-gate channel region 532 may be located near the drain 146A to extend the S / D operating range from approximately tens of volts to several hundred volts. This is specific to the offset-gate HiV-TFT architecture.

[0043] The second transistor 140A may also include a fifth portion 520E and a sixth portion 520F of the S / D metal layer. The fifth portion 520E and the sixth portion 520F of the S / D metal layer may be located within the ILD layer 512. The fifth portion 520E and the sixth portion 520F of the S / D metal layer may be separated from each other (i.e., a portion of the ILD layer 512 may be located between them). The fifth portion 520E and the sixth portion 520F of the S / D metal layer may have stepped profiles such that each advances closer to the passivation layer 514 as they move closer to each other.

[0044] The second transistor 140A may also include a fourth portion 524D and a fifth portion 524E of the n+-doped a-Si:H layer. The fourth portion 524D and the fifth portion 524E of the n+-doped a-Si:H layer may be located within the ILD layer 512. The fourth portion 524D and the fifth portion 524E of the n+-doped a-Si:H layer may be separated from each other (i.e., a portion of the ILD layer 512 may be located between them). The fourth portion 524D and the fifth portion 524E of the n+-doped a-Si:H layer may have stepped profiles such that each advances closer to the passivation layer 514 as they move closer to each other.

[0045] The second transistor 140A may also include a channel 540 (e.g., containing a-Si:H) and a top nitride (T.Nit.) layer 542. The channel 540 may be located on and / or within the gate dielectric layer 510. The channel 540 may be located at least partially between the fourth portion 524D and the fifth portion 524E of the n+-doped a-Si:H layer. The top nitride layer 542 may be located on the channel 540. The top nitride layer 542 may be located at least partially between the fourth portion 524D and the fifth portion 524E of the n+-doped a-Si:H layer. The channel 540 may have a wider width than the top nitride layer 542.

[0046] Source 142A may include a sixth portion 520F of the S / D metal layer, a fifth portion 524E of the n+-doped a-Si:H layer, a channel 540, and at least a portion of the top nitride layer 542. Drain 146A may include a fifth portion 520E of the S / D metal layer, a fourth portion 524D of the n+-doped a-Si:H layer, a channel 540, and at least a portion of the top nitride layer 542. The channel 540 and the top nitride layer 542 may be at least partially positioned between source 142A and drain 146.

[0047] In one embodiment, the isolated a-Si:H layer 520 of the optical switch 110A can be implemented with the same a-Si:H channel material. However, process modifications are necessary to ensure that the optical switch 110A has a predetermined on / off ratio. This alternative injection will be discussed later.

[0048] Figure 6 shows graph 600 illustrating the current-voltage characteristics of the first stage of device 100 according to one embodiment, and Figure 7 shows graph 700 illustrating the current-voltage characteristics of multiple stacked and / or cascaded stages (e.g., four stages) of device 100 according to one embodiment. Both graphs 600 and 700 show one curve for the first (e.g., on) state of device 100 and another curve for the second (e.g., off) state of device 100. As can be seen from the graphs, when device 100 has four stages, device 100 can generate four times the voltage compared to when device 100 has a single stage. For example, the single-stage embodiment operates at a maximum of approximately 300V, and the multi-stage embodiment operates at a maximum of approximately 1200V. The current limit for the single-stage embodiment is set to 20μA, and the current limit for the multi-stage embodiment is set to 50μA. On / off ratios exceeding six orders of magnitude are shown for both the single-stage and multi-stage embodiments.

[0049] Figure 8 shows a schematic side cross-sectional view of a portion of the first stage of device 100 according to one embodiment. The embodiment in Figure 8 is an alternative example of the embodiment in Figure 5. In this embodiment, the first stage may include a gate dielectric layer 510 and an interlevel dielectric (ILD) layer 512 positioned on the gate dielectric layer 510. The (top) passivation layer 514 may be optionally omitted.

[0050] The optical switch 110A may include two portions 820A and 820B of the S / D metal layer. The portions 820A and 820B of the S / D metal layer may have stepped profiles such that each advances further away from the gate dielectric layer 510 as they move closer to each other. The optical switch 110A may also include a channel 840 (e.g., containing a-Si:H) and a top nitride layer 842. The channel 840 may be located on and / or within the gate dielectric layer 510. The channel 840 may be located at least partially between the portions 820A and 820B of the S / D metal layer. The top nitride layer 842 may be located on the channel 840. The top nitride layer 842 may be located at least partially between the portions 820A and 820B of the S / D metal layer.

[0051] As described above, the optical switch 110A and the second transistor 140A may share the same a-Si:H material layer, which can simplify the layer structure and process. As shown, the second transistor 140A (illustrated on the left) and the optical switch 110A (illustrated on the right) share almost identical structures, except that the optical switch 110A does not include a gate because it is a two-terminal device. In addition, there is no n+-doped a-Si:H layer between the S / D metal layers 820A, 820B and the channel 840. This structure may require additional steps in construction compared to conventional a-Si:H TFT processes that assume the S / D metal and n+, a-Si:H are patterned in one step and share the same mask pattern.

[0052] However, Figures 9 and 10 illustrate the importance of using different contact structures separately for the optical switch 110A and the second transistor 140A.

[0053] Figure 9 shows graph 900 illustrating the current-voltage characteristics of optical switch 110A in one embodiment, where the n+-doped a-Si:H layer is at least partially positioned between the S / D metal layer and the channel. More specifically, Figure 9 shows the current-voltage characteristics of an optical switch having a similar structure to optical switch 110A shown on the right side of Figure 8, except that the n+-doped a-Si:H layer is positioned between the S / D metal layer and the channel, similar to the second transistor 140A shown on the left side of Figure 8. The on / off ratio of this device is less than 10, which is insufficient.

[0054] Figure 10 shows graph 1000 illustrating the current-voltage characteristics of the optical switch 110A when the S / D metal layers 820A and 820B are at least partially positioned on (i.e., in direct contact with) the channel 840 (shown on the right side of Figure 8) according to one embodiment. The on / off ratio is improved from approximately two orders of magnitude to over 1000. Similarly, without the n+-doped a-Si:H layer of the second transistor 140A, the second transistor 140A can have a very small on-current.

[0055] Figure 11 shows a schematic diagram of another high-voltage switching device 1100 for driving a MEMS actuator according to one embodiment, and Figure 12 shows an enlarged portion of Figure 11 according to one embodiment. Device 1100 may or may include total electroinjection. One difference between device 1100 shown in Figure 11 and device 100 described with reference to Figures 1 to 10 is that device 1100 in Figure 11 is directly scalable to multiple kV ranges.

[0056] Device 1100 may be or include a composite device. Device 1100 may include one or more transistors (two are shown: 1120, 1140). The first (e.g., upper) transistor 1120 may be or include a TFT. For example, the first transistor 1120 may be or include a HiV-TFT having a source 1122, a gate 1124, and a drain 1126. The first transistor 1120 may be long and narrow. For example, the first transistor 1120 may have a length of about 20 μm to about 1000 μm and a width / thickness of about 3 μm to about 20 μm. The first transistor 1120 may function as an inverter (e.g., a first stage inverter). In the shown embodiment, unlike conventional inverter circuits, there is no load resistor for the first transistor 1120.

[0057] Device 1100 may be operable between a first (e.g., off) state and a second (e.g., on) state. Device 1100 may be in an off state (e.g., low current) when gate 1124 turns off the first transistor 1120. Device 1100 may be in an on state (e.g., higher current) when gate 1124 turns on the first transistor 1120.

[0058] The second (e.g., lower) transistor 1140 may also be or include a TFT. For example, the second transistor 1140 may be or include a HiV-TFT having a source 1242, a gate 1144, and a drain 1146. The second transistor 1140 may be wider than the first transistor 1120. For example, the second transistor 1140 may have a width of about 20 μm to about 1000 mm. The second transistor 1140 may function as a drive and / or output transistor.

[0059] Sources 1122 and 1142 can be connected (e.g., by metal), but sources 1122 and 1142 cannot be shared (e.g., their semiconductor channels can be isolated). Similarly, drains 1126 and 1146 can be connected (e.g., by metal), but drains 1126 and 1146 cannot be shared (e.g., their semiconductor channels can be isolated). The subcomponents of transistors 1120 and 1140 are tightly coupled so that device 1100 is not a conventional inverter + output transistor. Rather, device 1100 is a composite three-terminal device having a source, a gate, and a drain.

[0060] The first transistor 1120 may include one or more tap electrodes (five are shown: 1130A to 1130E). Electrodes 1130A to 1130E may be distributed across the entire high-voltage drift region of the non-gate channel (also referred to as the non-gate drift region) 1132 of the first transistor 1120. Electrodes 1130A to 1130E of the first transistor 1120 may be at least partially positioned between the gate 1124 and the drain 1126. One of the electrodes 1130A may be connected to the gate 1144 of the second transistor 1140.

[0061] The second transistor 1140 may include one or more field plates (five are shown: 1148A-1148E). The gate 1144 and field plates 1148A-1148E of the second transistor 1140 may be connected (e.g., directly) to the electrodes 1130A-1130E of the first transistor 1120. The field plates 1148A-1148E may be at least partially located between the gate 1144 and the drains 1126, 1146. The field plates 1148A-1148E may distribute the high voltage substantially uniformly throughout the non-gate channel (also referred to as the non-gate drift region) 1152 of the second transistor 1140, which may reduce and / or prevent premature failure. As shown, the non-gate channels 1132, 1152 may be at least partially located between the gates 1124, 1144 and the drains 1126, 1146. The operating voltage range of device 1100 can be extended by increasing the number of electrodes 1130A to 1130E of the first transistor 1120 and / or by increasing the number of field plates 1148A to 1148E of the second transistor 1140.

[0062] Sources 1122, 1142, gate 1144, drains 1126, 1146, electrodes 1130A-1130E, or combinations thereof, may be made from a first material (e.g., S / D metal). Gate 1124, field plates 1148A-1148E, or combinations thereof, may be made from a second material different from the first material (e.g., gate metal). Channels 1132, 1152 may be made from a third material different from the first and second materials (e.g., a:Si:H).

[0063] As shown in Figure 11, device 1100 may be connected to one or more pads (four are shown: 1160A to 1160D). Pads 1160A to 1160D may be metal pads configured for use in probes using a probe station. As shown, pad 1160A may be connected to sources 1122 and 1142, pad 1160B may be connected to gate 1144, and pad 1160D may be connected to drains 1126 and 1146.

[0064] The first transistor 1120 may have a modified (e.g., unconventional) structure. More specifically, in addition to the source 1122, gate 1124, and drain 1126, the first transistor 1120 may also include one or more tapped drains distributed along a non-gate drift region 1132 between the gate 1124 and the drain 1126. The tapped drains may be or include the gate 1144 and / or electrodes 1130A-1130E. The tapped drains may be configured to sample the step voltage of the second transistor 1140. The tapped drains may also, or instead, be configured to provide the fieldplate voltage of the second transistor 1140. In one embodiment, the tapped drains may be the fieldplate of the first transistor 1120. In another embodiment, the tapped drains may not be the fieldplate of the first transistor 1120.

[0065] In one embodiment, electrode 1130 may serve as the field plate and / or drain of the first transistor 1120. In one embodiment, gate 1144 may serve as the field plate and / or drain of the first transistor 1120. In one embodiment, electrode 1130 may serve as the field plate of the second transistor 1140.

[0066] Figure 13 shows a schematic side cross-sectional view of a portion of device 1100 cut along line 13-13 in Figure 11, according to one embodiment. Although the cross-section is shown as passing through gate 1144 in Figure 11, the cross-section may also, or instead, be cut through any one of electrodes 1130A-1130E.

[0067] The device 1100 may include a first (e.g., lower) metal layer 1310. The first metal layer 1310 may be made of the same type of metal as the gate 1124. The gate dielectric layer 1120 may be at least partially located on the first metal layer 1310. A second (e.g., upper) metal layer 1330 may be at least partially located on the gate dielectric layer 1120. The second metal layer 1330 may be made of the same type of metal as the drain 1126. In at least one embodiment, the metal layers 1310, 1330 may be made of the same type of metal. In another embodiment, the metal layers 1310, 1330 may be made of different types of metal. The second metal layer 1330 may include one or more legs (two are shown: 1332, 1334) that extend at least partially through the gate dielectric layer 1120 toward the first metal layer 1310. In at least one embodiment, the legs 1332, 1334 are positioned on and / or in contact with the first metal layer 1310.

[0068] The channel 1340 may be at least partially located within the second metal layer 1330. The channel 1340 may be made of a:Si:H. The n+ layer 1350 may be at least partially located within the second metal layer 1330. The n+ layer 1350 may be at least partially located on and / or above the channel 1340. The n+ layer 1350 may be or contain an n+-doped a-Si:H layer. The top nitride layer 1360 may be at least partially located within the second metal layer 1330. The top nitride layer 1360 may be at least partially located between the channel 1340 and the n+ layer 1350. For example, the top nitride layer 1360 may be located above the channel 1340 and below the top nitride layer 1360.

[0069] The third metal layer 1370 may be at least partially located on and / or above the second metal layer 1330 and / or the n+ layer 1350. The third metal layer 1370 may be made of the same type of metal as the second metal layer 1330. In at least one embodiment, layers 1330 and 1370 may be the same layer.

[0070] Figure 14 shows a graph 1400 illustrating the conversion characteristics of the device 1100 according to one embodiment. Low input gate voltage (V g At a high gate input voltage (V) <2V, device 1100 is in an "on" state with an on current exceeding 10uA (e.g., the device compliance setting). g When >2.5V, device 1100 is in the off state, and the leakage current can be several hundred pA at 1100V. In one embodiment, 1100V may be the highest voltage that device 1100 can provide. The input voltage may be swept from -5V to +10V, and the S / D drain may be set to the maximum voltage range of the measurement setting (e.g., 1100V). The current correspondence is set to 10μA. Device 1100 may achieve 4-5 order of magnitude on / off.

[0071] Although the numerical ranges and parameters described in the broad scope of this instruction are approximations, the numerical values ​​described in specific examples are reported as accurately as possible. However, any numerical value inherently contains certain errors that inevitably arise from the standard deviation observed in each test measurement. Furthermore, all ranges disclosed herein should be understood to encompass all subranges contained within them. For example, the range "less than 10" may include all subranges between a minimum value of 0 and a maximum value of 10 (including the minimum value of 0 and the maximum value of 10), i.e., all subranges having a minimum value greater than or equal to 0 and a maximum value less than or equal to 10, e.g., 1 to 5.

[0072] While this instruction is provided for one or more implementations, modifications and / or alterations may be made to the examples provided without departing from the spirit and scope of the appended claims. For example, while a process is described as a series of actions or events, it should be understood that this instruction is not limited by the order of such actions or events. Some actions may occur in a different order and / or concurrently with other actions or events not described herein. Also, not all process steps may be required to implement a methodology according to one or more aspects or embodiments of this instruction. Structural objects and / or processing steps may be added, or existing structural objects and / or processing steps may be removed or modified. Furthermore, one or more of the actions described herein may be performed in one or more separate actions and / or steps. Furthermore, to the extent that the terms “including,” “includes,” “having,” “has,” and “with,” or their variations thereof, are used in any form for carrying out the invention or in the claims, such terms are intended to be comprehensive in a similar manner to the term “comprising.” The term “at least one” is used to mean that one or more of the enumerated items may be selected. Furthermore, in the discussion and claims herein, the term “on” used for two materials, one of “on” means at least some contact between the materials, and the other means that the materials are in proximity to one or more additional intervening materials, to the extent that contact may be possible but not required. Neither “on” nor “over” implies any directionality when used herein. The term “conformal” describes a coating material in which the angle of the underlying material is maintained by the conformal material. The term “about” indicates that the enumerated values ​​may be slightly modified, provided that the modification does not result in a process or structural incompatibility with the indicated embodiment.The terms “join,” “be joined,” “connect,” “connect,” “be connected,” “connected to,” and “connected” mean “to connect directly to” or “to connect via one or more intermediate elements or members.” Finally, the terms “exemplary” or “exemplary” indicate that the description is used as an example and not that it is ideal. Other embodiments of this teaching may be apparent to those skilled in the art with respect to this specification and the practices of the disclosure herein. This specification and the examples are intended to be illustrative only, and the true scope and spirit of this teaching are set forth by the following claims.

Claims

1. A device, comprising: an optical switch configured to convert light into electrical current; a first transistor having a first source, a first gate, a first drain, and one or more electrodes, the first transistor acting as an inverter; a second transistor comprising a second source, a second gate, and a second drain, wherein the first and second sources are connected together and the first and second drains are connected together, the second transistor acting as an output, a driver, or both, and the one or more electrodes, the second gate, or a combination thereof acting as a tapped drain configured to sample a step voltage of the second transistor; an interlevel dielectric; a source-drain (S / D) metal layer located at least partially within the interlevel dielectric; the optical switch is located over a first portion and a second portion of the S / D metal layer, the first portion and the second portion being separated from one another by a portion of the interlevel dielectric.

2. 2. The device of claim 1 , wherein the one or more electrodes comprise a plurality of electrodes spaced apart from one another between the first gate and the first drain, the electrodes being positioned within a drift region of an ungated channel of the first transistor.

3. The device of claim 1 , wherein the first transistor is narrower than the second transistor.

4. 10. The device of claim 1, wherein the semiconductor channels of the first and second sources are separated such that the first and second sources are not shared.

5. 2. The device of claim 1, wherein the semiconductor channels of the first and second drains are separated such that the first and second drains are not shared.

6. 2. The device of claim 1 , wherein the first transistor comprises a first electrode and a second electrode spaced apart from each other, the second transistor comprises a first field plate and a second field plate spaced apart from each other, the first electrode connected to the first field plate and the second electrode connected to the second field plate.

7. The device of claim 6 , wherein the gate of the second transistor is connected to the first electrode.

8. 7. The device of claim 6, wherein the first and second field plates are positioned at least partially between the gate of the second transistor and the drain of the second transistor.

9. The device of claim 6 , wherein the first and second electrodes are distributed across a high-voltage drift region of an ungated channel of the first transistor.

10. The device of claim 9 , wherein the first and second electrodes are positioned between the gate and the drain of the first transistor.

11. A switching device for driving an actuator, comprising: an optical switch configured to convert light into electrical current; a first transistor coupled to the optical switch configured to act as an inverter, A first source; A first gate; A first drain; a first transistor comprising a plurality of electrodes spaced apart from one another, the plurality of electrodes being positioned at least partially between the first gate and the first drain; a second transistor configured to act as an output, a driver, or both; a second source, the first and second sources being connected together; and A second gate; a second drain, the first and second drains being connected together; and a second transistor comprising: a plurality of field plates spaced apart from one another, the field plates positioned at least partially between the second source and the second drain, each field plate connected to one of the electrodes, the electrode, the second gate, or a combination thereof acting as a tapped drain configured to sample a step voltage of the second transistor to provide a voltage for the field plate of the second transistor; a gate dielectric layer; an interlevel dielectric overlying the gate dielectric layer; a passivation layer located on the interlevel dielectric, the optical switch being at least partially located within the interlevel dielectric, within the passivation layer, or both; a source-drain (S / D) metal layer located at least partially within the interlevel dielectric; a switching device, the optical switch being located over the S / D metal layer, the optical switch being located over a first portion and a second portion of the S / D metal layer, the first portion and the second portion being separated from one another by a portion of the interlevel dielectric.

12. The switching device of claim 11 , wherein the gate of the second gate is connected to one of the electrodes.

13. The switching device of claim 11 , wherein the electrode is distributed throughout a high-voltage drift region of an ungated channel of the first transistor.

14. 12. The switching device of claim 11, wherein the field plate is configured to distribute a high voltage substantially uniformly across the non-gated channel of the second transistor.

15. 12. The switching device of claim 11, wherein an ungated channel of the first transistor is positioned at least partially between the gate of the first transistor and the drain of the first transistor, and an ungated channel of the second transistor is positioned at least partially between the source of the second transistor and the drain of the second transistor.

16. 1. A high voltage switching device for driving a microelectromechanical system (MEMS) actuator, comprising: an optical switch configured to convert light into electrical current; a first transistor coupled to the optical switch configured to act as an inverter, A first source; A first gate; A first drain; a first transistor comprising: a plurality of electrodes spaced apart across a high-voltage drift region of an ungated channel of the first transistor, the electrodes and the ungated channel of the first transistor being positioned at least partially between the first gate and the first drain; a second transistor configured to act as an output, a driver, or both; a second source, the first and second sources being connected together; and a second gate, the gate of the second gate being connected to one of the electrodes; and a second drain, the first and second drains being connected together; and a second transistor comprising: a plurality of field plates spaced apart from one another across an ungated channel of the second transistor, the field plates configured to distribute a high voltage substantially uniformly across the ungated channel of the second transistor, the field plates and the ungated channel of the second transistor being positioned at least partially between the second source and the second drain, each field plate being connected to one of the electrodes, the electrode, the second gate, or a combination thereof acting as a tapped drain distributed between the first gate and the first drain, the tapped drain being configured to sample a step voltage of the second transistor to provide a voltage for the field plate of the second transistor; a gate dielectric layer; an interlevel dielectric overlying the gate dielectric layer; a passivation layer located on the interlevel dielectric, the optical switch being at least partially located within the interlevel dielectric, within the passivation layer, or both; a source-drain (S / D) metal layer located at least partially within the interlevel dielectric; a high voltage switching device, the high voltage switching device being located above the S / D metal layer, the high voltage switching device being located above a first portion and a second portion of the S / D metal layer, the first portion and the second portion being separated from each other by a portion of the interlevel dielectric.

17. 17. The switching device of claim 16, wherein the first source, the second source, the second gate, the first drain, the second drain, and the field plate are made of a first material.

18. 20. The switching device of claim 17, wherein the first gate and the field plate are made of a second material different from the first material.

19. 20. The switching device of claim 18, wherein the non-gated channel of the first transistor and the non-gated channel of the second transistor are made of a third material different from the first and second materials.

20. 20. The switching device of claim 19, wherein the first material comprises a first metal, the second material comprises a second metal, and the third material comprises hydrogenated amorphous silicon (a-Si:H).

21. A gate dielectric layer, the interlevel dielectric being disposed on the gate dielectric layer; and 10. The device of claim 1, further comprising: a passivation layer located on the interlevel dielectric, the optical switch being at least partially located within the interlevel dielectric, within the passivation layer, or both.

22. The device described in claim 21, wherein the S / D metal layer also includes a third portion coupled to the second portion, the third portion being located within the gate dielectric layer.

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