Radio frequency switch biasing topology

Abstract

To provide a switching circuit for radio frequency applications.SOLUTION: A switching circuit 500 includes a first series switch 502, a second series switch 504, a first shunt switch 503 and / or a second shunt switch 505. The first series switch 502 and / or the first shunt switch 503 are coupled to a first port (that is, output) 506 via a coupling circuit. The second series switch 504 and / or the second shunt switch 505 are coupled to a second port (that is, output) 508 via a coupling circuit. The circuit 500 includes an input 501 (that is, single input) coupled to first series switch 502 and / or the second series switch 504 via a coupling circuit. One or more of the switches include a plurality of switches, gates of each of the four switches being coupled to a first gate voltage 511.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] Cross-reference with related applications This application claims priority to U.S. Provisional Application No. 63 / 169,053, entitled “Radio Frequency Switch Biasing Topologies,” filed on 31 March 2021. The disclosures of said Provisional Application are expressly incorporated herein by reference, each in its entirety.

[0002] background field This disclosure relates to switching circuits, related devices, and related methods for radio-frequency (RF) applications. [Background technology]

[0003] Explanation of related technologies Switches, including RF and / or Single Pole Double Throw (SPDT) switches, can be critical components in RF and / or other circuit applications. When a switch is turned on (i.e., enters the on state), the switch has an on-resistance (R) ON To minimize the positive gate-source voltage (V) GS ) is required. When the switch is turned off (i.e., enters the off state), the switch requires an off capacitance (C). OFF ) and / or negative V to minimize nonlinearity GS It requires. [Overview of the project] [Means for solving the problem]

[0004] overview According to several implementation examples, the present disclosure relates to a switching circuit comprising a first series switch coupled to a first output port. The first series switch includes a first field-effect transistor (FET), a second FET, a third FET, a fourth FET, a fifth FET, and a sixth FET. The switching circuit further comprises a second series switch coupled to a second output port and a coupling circuit, the coupling circuit configured to couple the gate of the fifth FET and the gate of the sixth FET to a first node, the source of the fifth FET and the drain of the sixth FET to a second node, the source of the first FET and the drain of the second FET to a third node, the gate of the first FET and the drain of the fifth FET to a fourth node, the gate of the second FET and the source of the sixth FET to a fifth node, the fourth node and the fifth node to a first gate voltage, and the first node to a second gate voltage different from the first gate voltage.

[0005] In some embodiments, the switching circuit further comprises a first shunt switch. The coupling circuit may further be configured to couple a first output port between a first series switch and a first shunt switch.

[0006] The switching circuit may further include a second shunt switch. In some embodiments, the coupling circuit is further configured to couple a second output port between a second series switch and a second shunt switch.

[0007] In some embodiments, the first shunt switch comprises four FETs connected in series. The second shunt switch may also comprise four FETs connected in series.

[0008] The second series switch may comprise four FETs connected in series. In some embodiments, the first series switch further comprises a seventh FET and an eighth FET.

[0009] In some embodiments, the first gate voltage is configured to be approximately 0V while the second gate voltage is positive. The second gate voltage may be configured to be approximately 0V while the first gate voltage is positive.

[0010] Some implementations of the present disclosure relate to a wireless device comprising a first series switch coupled to a first output port. The first series switch includes a first field-effect transistor (FET), a second FET, a third FET, a fourth FET, a fifth FET, and a sixth FET. The wireless device further comprises a second series switch coupled to a second output port and a coupling circuit, the coupling circuit configured to couple the fifth FET to the first FET, couple the fifth FET to the sixth FET, couple the first FET to the second FET, couple the first FET and the second FET to a first gate voltage, and couple the fifth FET and the sixth FET to a second gate voltage different from the first gate voltage.

[0011] The wireless device may further include a first shunt switch. The coupling circuit may further be configured to couple a first output port between a first series switch and a first shunt switch.

[0012] In some embodiments, the wireless device further comprises a second shunt switch. The coupling circuit may further be configured to couple a second output port between a second series switch and a second shunt switch.

[0013] The first shunt switch may comprise four FETs connected in series. The second shunt switch may comprise four FETs connected in series. In some embodiments, the second series switch comprises four FETs connected in series.

[0014] According to some realizations of the present disclosure, a semiconductor die comprises a first series switch coupled to a first output port. The first series switch includes a first field-effect transistor (FET), a second FET, a third FET, a fourth FET, a fifth FET, and a sixth FET. The semiconductor die further comprises a second series switch coupled to a second output port and a coupling circuit, the coupling circuit configured to couple the fifth FET to the first FET, couple the fifth FET to the sixth FET, couple the first FET to the second FET, couple the first FET and the second FET to a first gate voltage, and couple the fifth FET and the sixth FET to a second gate voltage different from the first gate voltage.

[0015] In some embodiments, the semiconductor die further comprises a first shunt switch. The coupling circuit may further couple a first output port between a first series switch and a first shunt switch.

[0016] The semiconductor die may further include a second shunt switch. The coupling circuit may further configure a second output port to couple between a second series switch and a second shunt switch.

[0017] In some embodiments, the first shunt switch comprises four FETs connected in series. The second shunt switch may also comprise four FETs connected in series.

[0018] For the purpose of summarizing this disclosure, certain aspects, advantages, and novel features of the invention are described herein. It should be understood that not all such advantages are achieved according to any particular embodiment of the invention. For this reason, the invention may be embodied or practiced in a manner that achieves or optimizes one or a group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein. [Brief explanation of the drawing]

[0019] [Figure 1] FIG. is a diagram showing an exemplary circuit that utilizes an NVG to create a negative voltage for one or more switches (e.g., a field effect transistor (FET)) of a circuit. [Figure 2] FIG. is a diagram showing another exemplary circuit that uses one or more capacitors to create a cross bias with one or more switches of a circuit. [Figure 3] FIG. is a diagram showing a network of multiple switches that can be utilized in the circuits described herein. [Figure 4] FIG. is a diagram showing an exemplary back diode according to one or more embodiments. [Figure 5] FIG. is a diagram showing an exemplary circuit having one or more features as described herein. [Figure 6] FIG. is a diagram showing an exemplary packaged module having one or more features as described herein. [Figure 7] FIG. is a diagram showing an exemplary wireless device having one or more advantages as described herein.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Description If headings are provided herein, they are for convenience only and do not necessarily affect the scope or meaning of the claimed invention.

[0021] Switches, including radio frequency (RF) and / or single pole double throw (SPDT) switches, can be important components for RF and / or other circuit applications. When the switch is turned on (i.e., in the on state), the switch requires a positive gate-source voltage (V ON ) to minimize the on-resistance (R GS ) of the switch. When the switch is turned off (i.e., in the off state), the switch requires a negative V OFF ) to minimize the off capacitance (C GS ) and / or non-linearity of the switch.

[0022] Various methods can be used to bias a switch to the on and / or off state. Some applications can utilize a negative voltage generator (NVG) to provide a negative voltage to the switch in the off state. Figure 1 shows an exemplary circuit 100 that utilizes an NVG to create a negative voltage for one or more switches (e.g., field-effect transistors (FETs)) in the circuit 100. The circuit 100 may comprise a first series switch 102, a second series switch 104, a first shunt switch 103, and / or a second shunt switch 105. The first series switch 102 and / or the first shunt switch 103 may be coupled to a first port (i.e., output) 106 via a coupling circuit. The second series switch 104 and / or the second shunt switch 105 may be coupled to a second port (i.e., output) 108 via a coupling circuit. Circuit 100 may include an input 101 (e.g., a single input) coupled to a first series switch 102 and / or a second series switch 104 via a coupling circuit. The coupling circuit may be configured to couple various components, as described herein, together and / or to various nodes, as described in Figure 1 and / or other figures.

[0023] The signal received via input 101 in circuit 100 can proceed to the first port 106 or the second port 108. For the signal to proceed from input 101 to the first port 106, the first series switch 102 is in the on state, the second series switch 104 is in the off state, the first shunt switch 103 is in the off state, and / or the second shunt switch 105 can be in the on state. Similarly, for the signal to proceed from input 101 to the second port 108, the first series switch 102 is in the off state, the second series switch 104 is in the on state, the first shunt switch 103 is in the on state, and / or the second shunt switch 105 can be in the off state. Although shunt switches may not be necessary for circuit 100 to operate, shunt switches (e.g., the first shunt switch 103 and / or the second shunt switch 105) can improve impedance matching and / or isolation of circuit 100.

[0024] Each of the switches in circuit 100 may be biasable to turn on and / or off each respective switch. To turn on a switch, a positive bias voltage (e.g., 2.5V) exceeding a threshold voltage can be applied to the switch. Similarly, to turn off a switch, a negative V GS (e.g., -2.5V) can be applied to the switch. Each switch may include a gate, a drain, and a source.

[0025] If a negative voltage is not available outside circuit 100, an NVG can be used to generate a negative voltage with one or more switches in circuit 100 to control the signal path of circuit 100. Applying a negative voltage can enable circuit 100 to handle larger voltage amplitudes without an off switch turning on due to the applied voltage.

[0026] In the example shown in Figure 1, a negative voltage (e.g., 2.5V) may be applied to the second series switch 104 and / or the first shunt switch 103 to facilitate the signal path to the first port 106. Alternatively, a negative voltage (e.g., 2.5V) may be applied to the first series switch 102 and / or the second shunt switch 105 to facilitate the signal path to the second port 108.

[0027] Circuit 100 can advantageously provide good RF and / or electrostatic discharge performance without requiring blocking capacitors. However, circuit 100 may require an NVG, which may require a larger controller die size and / or result in relatively high standby current.

[0028] Another method for biasing circuit switches is shown in Figure 2. Figure 2 shows another exemplary circuit 200 that uses one or more capacitors 210 to create a cross bias on one or more switches of circuit 200. One or more capacitors 210 may be used instead of an NVG and / or apply a negative voltage in other ways. To allow a signal to proceed to the first port 206 of circuit 200, the gates of the second series switch 204 and / or the first shunt switch 203 may be set to 0V. One or more capacitors 210 may be configured to block a voltage so that the gates of these switches have a different voltage from the drains and / or sources of these switches. Thus, by applying 0V to the gates of the second series switch 204 and / or the first shunt switch 203, the drains and sources of the second series switch 204 and / or the first shunt switch 203 may have a positive voltage (e.g., 2.5V). The voltages at the drain and / or source of the second series switch 204 and / or the first shunt switch 203 may be equivalent to the positive voltage applied to the gates of the first series switch 202 and / or the second shunt switch 205. The first series switch 202 and / or the second series switch 204 may be coupled to the antenna / input port 201. When the second series switch 204 is ON, it may be configured to draw a signal toward the second port 208.

[0029] Circuit 200 may have the advantage of not requiring an NVG, which could allow for a relatively small controller die size and / or result in relatively low standby current. However, circuit 200 may require additional electrostatic discharge protection and / or result in degraded RF performance.

[0030] The switch topologies described herein do not require NVGs and / or cross-bias capacitors. Some embodiments described herein may be configured to achieve RF and / or electrostatic discharge performance similar to circuits utilizing NVGs and / or cross-bias capacitors. Some embodiments may involve the use of one or more short-circuit switches (e.g., FETs) to effectively create back-to-back diode configuration performance to maintain the off state with a switch set to the off state. Such configurations can provide relatively low voltage clipping and / or relatively low compression.

[0031] Some embodiments may be used in silicon-on-insulator (SOI) processes. In some cases, the embodiments described herein may have significant effects on various processes. For example, complementary metal-oxide-semiconductor (CMOS) and / or bipolar CMOS processes may not be compatible with negative voltages due to the grounded substrate.

[0032] Figure 3 shows a network of multiple switches that may be used in the circuit described herein. The network of switches includes a first switch 302, a second switch 304, a third switch 306, and / or a fourth switch 308. The gate of the first switch 302 may be coupled (via a coupling circuit) to the drain or source of the third switch 306, and the gate of the second switch 304 may be coupled to the drain or source of the fourth switch 308. Also, the gate of the third switch 306 may be coupled to the gate of the fourth switch 308, and / or the drain or source of the third switch 306 may be coupled to the drain or source of the fourth switch 308. For example, the drain of the first switch 302 and the source of the second switch 304 may be connected to the first node 310, the drain of the third switch 306 and the source of the fourth switch 308 may be connected to the second node 312, the gate of the third switch 306 and the gate of the fourth switch 308 may be connected to the third node 314, the drain of the fourth switch 308 and the gate of the second switch 304 may be connected to the fourth node 316, and / or the source of the third switch 306 and the gate of the first switch 302 may be connected to the fifth node 318. The first node 310 and the second node 312 may be connected together.

[0033] This coupling of the first switch 302, the second switch 304, the third switch 306, and / or the fourth switch 308 can operate similarly to a back-to-back diode. Figure 4 shows an exemplary back-to-back diode 400. Although some circuits described herein may not include diodes and / or back-to-back diodes, the switch topology in some circuits described herein can be configured to operate as a back-to-back diode 400. An exemplary back-to-back diode 400 may include a first diode 402 coupled back-to-back with a second diode 404, and / or a third diode 406 coupled back-to-back with a fourth diode 408. The back-to-back diode 400 can operate in a complementary manner in which the first diode 402, which is on, can ensure that the second diode 404 is off. The back-to-back diode 400 can therefore effectively block a signal in the off state without requiring a negative voltage. The third switch 306 and the fourth switch 308 in the network shown in Figure 3 can similarly effectively block signals in the off state.

[0034] Figure 5 shows an exemplary circuit 500. The circuit 500 may comprise a first series switch 502, a second series switch 504, a first shunt switch 503, and / or a second shunt switch 505. The first series switch 502 and / or the first shunt switch 503 may be coupled to a first port (i.e., output) 506 via a coupling circuit. The second series switch 504 and / or the second shunt switch 505 may be coupled to a second port (i.e., output) 508 via a coupling circuit. The circuit 500 may comprise an input 501 (e.g., a single input) coupled to the first series switch 502 and / or the second series switch 504 via a coupling circuit.

[0035] One or more of the switches may comprise multiple switches. For example, the first series switch 502 may comprise four switches, the gate of each of the four switches being coupled to the first gate voltage 511. The sources and / or drains of the four switches may also be coupled to a common source voltage 513. The first series switch 502 may comprise a first switch 512, a second switch 514, a third switch 516, and / or a fourth switch 518. The gates of the first switch 512, the second switch 514, the third switch 516, and / or the fourth switch 518 may be coupled to the first gate voltage 511. The second series switch 504, the first shunt switch 503, and / or the second shunt switch 505 may also comprise multiple switches.

[0036] In some embodiments, the gate of the first switch 512 may be coupled to the fifth switch (see Figure 3 for a closer view of additional switches, including the fifth switch corresponding to the fourth switch 308 in Figure 3). The gate of the second switch 514 may be coupled to the sixth switch. The source or drain of the fifth switch and the source or drain of the sixth switch may be coupled to the first node. The gate of the fifth switch and the gate of the sixth switch may be coupled to the second node. The first node may be coupled to the second gate voltage 515.

[0037] Furthermore, the gate of the third switch 516 may be coupled to the seventh switch. The gate of the fourth switch 518 may be coupled to the eighth switch. The source or drain of the seventh switch and the source or drain of the eighth switch may be coupled to the third node. The gate of the seventh switch and the gate of the eighth switch may be coupled to the fourth node. The third node may be coupled to the second gate voltage 515.

[0038] The fifth and sixth switches (and the seventh and eighth switches) may be configured to block voltages and / or signals, similar to back-facing diodes. Thus, the various switches constituting the first series switch 502 may be configured to receive a second positive gate voltage (e.g., 2.5V) while maintaining a source voltage 513 of 0V.

[0039] The second series switch 504 may be coupled to the second port (i.e., output) 508 via a coupling circuit. In some embodiments, the second series switch 504 may comprise four switches, the gate of each of the four switches being coupled to the first gate voltage 517. The sources and / or drains of the four switches may also be coupled to a common source voltage 519. The second series switch 504 may comprise a first switch 542, a second switch 544, a third switch 546, and / or a fourth switch 548. The gates of the first switch 542, the second switch 544, the third switch 546, and / or the fourth switch 548 may be coupled to the first gate voltage 517.

[0040] In some embodiments, the gate of the first switch 542 may be coupled to the fifth switch. The gate of the second switch 544 may be coupled to the sixth switch. The source or drain of the fifth switch and the source or drain of the sixth switch may be coupled to the first node. The gate of the fifth switch and the gate of the sixth switch may be coupled to the second node. The first node may be coupled to the second gate voltage 521.

[0041] Furthermore, the gate of the third switch may be coupled to the seventh switch. The gate of the fourth switch may be coupled to the eighth switch. The source or drain of the seventh switch and the source or drain of the eighth switch may be coupled to the third node. The gate of the seventh switch and the gate of the eighth switch may be coupled to the fourth node. The third node may be coupled to the second gate voltage 521.

[0042] The fifth and sixth switches (and the seventh and eighth switches) may be configured to block voltages and / or signals, similar to back-facing diodes. Thus, the various switches constituting the first series switch 502 may be configured to receive a second positive gate voltage 521 (for example, 2.5V) while maintaining a source voltage 519 of 0V.

[0043] In some embodiments, the first series switch 502 may be configured to be ON when the second series switch 504 is OFF. Similarly, the second series switch 504 may be configured to be ON when the first series switch 502 is OFF. For example, the first gate voltage 511 at the first series switch 502 and / or the second gate voltage 521 at the second series switch 504 may be positive (e.g., 2.5V) while the second gate voltage 515 at the first series switch 502 and / or the first gate voltage 517 at the second series switch 504 may be approximately 0V. Similarly, while the second gate voltage 515 at the first series switch 502 and / or the first gate voltage 517 at the second series switch 504 may be positive (e.g., 2.5V), the first gate voltage 511 at the first series switch 502 and / or the second gate voltage 521 at the second series switch 504 may be approximately 0V. The first source voltages 513, 519 at the first series switch 502 and / or the second series switch 504 may be approximately 0V in both the on and off states.

[0044] The first shunt switch 503 may have a network of switches and / or voltage sources similar to that of the first series switch 502. Similarly, the second shunt switch 505 may have a network of switches and / or voltage sources similar to that of the second series switch 502. Therefore, when the first series switch 502 is ON, the first shunt switch 503 may be configured to be ON, and / or when the first series switch 502 is OFF, the first shunt switch 503 may be configured to be OFF. Likewise, when the second series switch 504 is ON, the second shunt switch 505 may be configured to be ON, and / or when the second series switch 504 is OFF, the second shunt switch 505 may be configured to be OFF.

[0045] In the example of Figure 6, the switching circuit 500 of Figure 5 may be included in the packaged module 600. The switching circuit 500 may comprise a semiconductor die 602 which may include various switches and / or coupling circuits as described herein with respect to Figure 5 and / or other figures.

[0046] The packaged module 600 may further include a controller 610. Such a controller may be configured to provide logic functionality, such as described herein, for example, to selectively bias various switches of the switching circuit 500. In some embodiments, such a controller may be configured to operate in a control standard such as the mobile industry processor interface (MIPI) standard.

[0047] In some implementations, architectures, devices, and / or circuits having one or more of the features described herein may be included in RF devices such as wireless devices. Such architectures, devices, and / or circuits may be implemented directly in wireless devices, in one or more modular forms as described herein, or in any combination thereof. In some embodiments, such wireless devices may include, for example, mobile phones, smartphones, portable wireless devices with or without telephone functionality, wireless tablets, wireless routers, wireless access points, wireless base stations, and the like. Although the disclosure has been described in the context of wireless devices, it will be understood that one or more of the features of this disclosure may also be implemented in other RF systems such as base stations.

[0048] Figure 7 shows an exemplary wireless device 700 having one or more of the advantageous features described herein. As described herein, one or more switching circuits having one or more of the features described herein can be implemented in many places in such wireless devices. For example, in some embodiments, a switching circuit 500 having one or more of the features described herein can be implemented in a module such as a diversity receiver (DRx) module 701 having one or more low-noise amplifiers (LNAs).

[0049] In some embodiments, a switching circuit 500 having one or more of the features described herein can be implemented in a transceiver. Such a switching circuit can be implemented as a separate module within the transceiver or as part of a transceiver module.

[0050] In some embodiments, a switching circuit 500 having one or more of the features described herein can be implemented between a front-end module (e.g., a DRx module) and a transceiver. Such a switching circuit 500 can be implemented as a separate module, as an assembly of circuit elements, or as any combination thereof.

[0051] In the example in Figure 7, a power amplifier (PA) in a PA module 712 can receive RF signals from a transceiver 710, which is configured and can operate to generate amplified and transmitted RF signals and process received signals. The transceiver 710 is illustrated to interact with a baseband subsystem 708 configured to provide conversion between user-friendly data and / or voice signals and RF signals suitable for the transceiver 710. The transceiver 710 is also illustrated to be connected to a power management component 706 configured to manage power for the operation of the radio device 700. Such power management can also control the operation of the baseband subsystem 708 and other components of the radio device 700.

[0052] The baseband subsystem 708 is illustrated to be connected to a user interface 702 to facilitate various inputs and outputs of voice and / or data provided to and received from the user. The baseband subsystem 708 may also be connected to a memory 704 configured to store data and / or instructions to facilitate the operation of the wireless device and / or to provide storage for information about the user.

[0053] In the example in Figure 7, the DRx module 701 may be implemented between one or more diversity antennas (e.g., diversity antenna 730) and the ASM 714. Such a configuration may allow the RF signal received through the diversity antenna 730 to be processed (including amplification by an LNA in some embodiments) with little or no loss and / or with little or no noise added to the RF signal from the diversity antenna 730. Such processed signal from the DRx module 70100 can then be routed to the ASM through one or more signal paths.

[0054] In the example shown in Figure 7, the main antenna 720 may be configured to facilitate the transmission of RF signals from, for example, the PA module 712. In some embodiments, receiving operations may also be achieved through the main antenna.

[0055] Many other wireless device configurations can utilize one or more of the features described herein. For example, a wireless device does not have to be a multiband device. In another example, a wireless device may include additional antennas, such as diversity antennas, and additional connectivity features, such as Wi-Fi, Bluetooth®, and GPS.

[0056] One or more features of this disclosure may be realized in various cellular frequency bands as described herein. Examples of such bands are listed in Table 1. It will be understood that at least some of these bands may be divided into subbands. It will also be understood that one or more features of this disclosure may be realized in frequency ranges that do not have names like those in the examples in Table 1.

[0057] [Table 1]

[0058] This disclosure describes various features, but no single feature is solely responsible for the benefits described herein. As will be apparent to those skilled in the art, the various features described herein may be combined, modified, or omitted. Combinations and partial combinations other than those specifically described herein will be apparent to those skilled in the art and are intended to constitute part of this disclosure. Various methods are described herein in relation to various flowchart steps and / or stages. In many cases, it should be understood that certain steps and / or stages may be combined together so that multiple steps and / or stages shown in a flowchart can be performed as a single step and / or stage. Also, certain steps and / or stages may be divided into additional sub-elements that are performed separately. In some cases, the order of steps and / or stages may be rearranged, and certain steps and / or stages may be omitted entirely. Furthermore, the methods described herein should be understood as open-ended so that additional steps and / or stages beyond those shown and described herein may also be performed.

[0059] Some aspects of the systems and methods described herein can be advantageously implemented, for example, using computer software, hardware, firmware, or any combination of computer software, hardware, and firmware. Computer software may include computer executable code stored on a computer-readable medium (e.g., a non-temporary computer-readable medium) that, when executed, performs the functions described herein. In some embodiments, the computer executable code is executed by one or more general-purpose computer processors. Those skilled in the art will recognize in light of this disclosure that any feature or function that can be implemented using software running on a general-purpose computer can also be implemented using different combinations of hardware, software, or firmware. For example, such a module can be fully implemented in hardware using a combination of integrated circuits. Alternatively, or in addition to this, such features or functions can be fully or partially implemented using a dedicated computer designed to perform the specific functions described herein, rather than a general-purpose computer.

[0060] Multiple distributed computing devices can be replaced by any one of the computing devices described herein. In such a distributed embodiment, the functions of the single computing device are distributed (for example, over a network) so that some functions are performed on each of the distributed computing devices.

[0061] Some embodiments may be described with reference to equations, algorithms, and / or flowcharts. These methods may be implemented using computer program instructions executable on one or more computers. These methods may also be implemented separately as computer program products, or as components of a device or system. In this regard, each equation, algorithm, block or step in a flowchart, and combinations thereof, may be implemented by hardware, firmware, and / or software, including one or more computer program instructions embodied in computer-readable program code logic. It will be understood that any such computer program instructions may be loaded onto one or more computers, which are not limited to general-purpose computers or dedicated computers, or other programmable processing units that manufacture machines, such that computer program instructions executed on such computers or other programmable processing units implement the functions specified in the equations, algorithms, and / or flowcharts. It will also be understood that each equation, algorithm, and / or block in a flowchart, and combinations thereof, may be implemented by a dedicated hardware-based computer system that performs the specified function or step, or by a combination of dedicated hardware and computer-readable program code logic means.

[0062] Furthermore, computer program instructions, as embodied in computer-readable program code logic, may also be stored in computer-readable memory (e.g., non-temporary computer-readable media), which can instruct one or more computers or other programmable processing units to function in a particular manner such that the instructions stored in computer-readable memory realize the functions identified in the blocks of a flowchart. Computer program instructions may also be loaded onto one or more computers or other programmable computing devices, causing a series of work steps to be performed on those computers or other programmable computing devices to generate a process realized by the computer such that the instructions executed on those computers or other programmable processing units provide steps for realizing the functions identified in the equations, algorithms, and / or blocks of a flowchart.

[0063] Some or all of the methods and tasks described herein may be performed by a computer system and may be fully automated. The computer system may, in some cases, include multiple different computers or computing devices (e.g., physical servers, workstations, storage arrays, etc.) that communicate and interoperate over a network to perform the functions described. Each such computing device typically includes a processor (or more processors) that executes program instructions or modules stored in memory or other non-temporary computer-readable storage media or devices. While the various functions disclosed herein may be embodied in such program instructions, some or all of the disclosed functions may instead be implemented in application-specific circuitry (e.g., ASICs or FPGAs) of the computer system. If the computer system includes multiple computing devices, these devices may or do not need to be located in the same place. The results of the disclosed methods and tasks may be permanently stored by converting physical storage devices, such as solid-state memory chips and / or magnetic disks, into different states.

[0064] Throughout this specification and the claims, words such as “comprise,” “comprising,” etc., should be interpreted in a comprehensive sense, the opposite of an exclusive or exhaustive sense, i.e., “including but not limited to,” unless the context clearly requires a different meaning. The word “coupled,” as commonly used herein, means that two or more elements can be connected directly or through one or more intermediate elements. In addition, the words “in this specification,” “above,” “below,” and words of similar intent, when used in this application, refer to the application as a whole and not to any particular part of it. Where the context allows, words used singular or plural in the “detailed description” above may also be plural or singular. The word “or” in relation to a list of two or more items encompasses all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. The word “exemplary” is used exclusively herein to mean “to serve as an example, case, or illustration.” None of the examples described herein as “exemplary” should necessarily be construed as being preferable or more advantageous than other examples.

[0065] This disclosure is not intended to be limited to the realizations shown herein. Various modifications to the realizations described herein will be readily apparent to those skilled in the art. Furthermore, the comprehensive principles defined herein may be applied to other realizations without departing from the spirit or scope of this disclosure. The teachings of the present invention provided herein are applicable to other methods and systems, and are not limited to those described herein, and further embodiments may be provided by combining elements and operations of the various embodiments described herein. Thus, the novel methods and systems described herein may be embodied in various other forms. Furthermore, various omissions, substitutions, and modifications in the forms of methods and systems described herein may be made without departing from the spirit of this disclosure. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of this disclosure.

Claims

1. A switching circuit comprising: a first series switch coupled to a first output port, the first series switch including a first field effect transistor (FET), a second FET, a third FET, a fourth FET, a fifth FET, and a sixth FET, the switching circuit further comprising: a second series switch coupled to the second output port; a gate of the fifth FET is directly coupled to a gate of the sixth FET at a first node, a source of the fifth FET is coupled to a drain of the sixth FET at a second node, a source of the first FET is coupled to a drain of the second FET at a third node, a gate of the first FET is coupled to a drain of the fifth FET at a fourth node, a gate of the second FET is coupled to a source of the sixth FET at a fifth node, the fourth node and the fifth node are coupled to a first gate voltage, and the first node is coupled to a second gate voltage different from the first gate voltage.

2. Further comprising a first shunt switch; The switching circuit of claim 1 , wherein the first output port is coupled between the first series switch and the first shunt switch.

3. Further comprising a second shunt switch; The switching circuit of claim 2 , wherein the second output port is coupled between the second series switch and the second shunt switch.

4. The switching circuit of claim 3 , wherein the first shunt switch comprises four FETs connected in series.

5. The switching circuit of claim 3 , wherein the second shunt switch comprises four FETs connected in series.

6. 2. The switching circuit of claim 1, wherein the second series switch comprises four FETs connected in series.

7. The switching circuit of claim 1 , wherein the first series switch further comprises a seventh FET and an eighth FET.

8. 2. The switching circuit of claim 1, wherein the first gate voltage is configured to be approximately 0V while the second gate voltage is positive.

9. 2. The switching circuit of claim 1, wherein the second gate voltage is configured to be approximately 0V while the first gate voltage is positive.

10. 1. A wireless device, comprising: a first series switch coupled to a first output port, the first series switch including a first field effect transistor (FET), a second FET, a third FET, a fourth FET, a fifth FET, and a sixth FET, the wireless device further comprising: a second series switch coupled to the second output port; the fifth FET is coupled to the first FET, a gate of the fifth FET is directly coupled to a gate of the sixth FET, the first FET is coupled to the second FET, the first FET and the second FET are coupled to a first gate voltage, and the fifth FET and the sixth FET are coupled to a second gate voltage that is different from the first gate voltage.

11. Further comprising a first shunt switch; The wireless device of claim 10 , wherein the first output port is coupled between the first series switch and the first shunt switch.

12. Further comprising a second shunt switch; The wireless device of claim 11 , wherein the second output port is coupled between the second series switch and the second shunt switch.

13. The wireless device of claim 12 , wherein the first shunt switch comprises four FETs connected in series.

14. The wireless device of claim 12 , wherein the second shunt switch comprises four FETs connected in series.

15. The wireless device of claim 10 , wherein the second series switch comprises four FETs connected in series.

16. 1. A semiconductor die comprising: a first series switch coupled to a first output port, the first series switch including a first field effect transistor (FET), a second FET, a third FET, a fourth FET, a fifth FET, and a sixth FET, the semiconductor die further comprising: a second series switch coupled to the second output port; the fifth FET is coupled to the first FET, a gate of the fifth FET is coupled to a gate of the sixth FET, the first FET is coupled to the second FET, the first FET and the second FET are coupled to a first gate voltage, and the fifth FET and the sixth FET are coupled to a second gate voltage, different from the first gate voltage.

17. Further comprising a first shunt switch; The semiconductor die of claim 16 , wherein the first output port is coupled between the first series switch and the first shunt switch.

18. Further comprising a second shunt switch; The semiconductor die of claim 17 , wherein the second output port is coupled between the second series switch and the second shunt switch.

19. 20. The semiconductor die of claim 18, wherein the first shunt switch comprises four FETs connected in series.

20. 20. The semiconductor die of claim 18, wherein the second shunt switch comprises four FETs connected in series.

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