Image sensor and analog-to-digital converter

Abstract

To provide an image sensor that does not include a separate power-down switch by separately applying a bias voltage depending on an operation mode.SOLUTION: An image sensor supporting a full resolution mode and a crop mode includes: a pixel array including a plurality of pixels configured to generate a pixel signal by sensing an object; an analog-to-digital converter configured to convert the pixel signal into a digital signal and including a plurality of metal lines; a bias generator configured to apply a bias voltage to the plurality of metal lines; and a bias controller configured to determine a path of the bias voltage applied to the metal lines. The bias controller includes: a first transistor configured to determine activation of all of the plurality of metal lines on the basis of, a first control signal; and a second transistor configured to determine activation of a first metal line for the crop mode among the plurality of metal lines on the basis of, a second control signal.SELECTED DRAWING: Figure 5A

Description

[Technical field]

[0001] The present invention relates to a complementary metal-oxide semiconductor (CMOS) image sensor, and more particularly to an analog-to-digital converter that applies bias voltages separately depending on an operation mode, and an image sensor including the same. [Background technology]

[0002] CMOS (complementary metal-oxide semiconductor) image sensors are widely used as devices for capturing two-dimensional or three-dimensional images of objects. In CMOS image sensors, correlated double sampling (CDS) technology is used to eliminate pixel reset noise. In order to improve the performance of image sensors, improving the efficiency of analog-digital converters (ADCs) that use CDS technology is an important topic. The analog-to-digital converter can be made more power efficient by including a power-down switch to minimize power supply when not being used for sensing.

[0003] However, increasing the number of physical switches induces an on-resistance itself, which causes a problem of varying the input range of the amplifier. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 10-55403 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the problems in the conventional image sensors described above, and an object of the present invention is to provide an image sensor that does not include a separate power-down switch by applying a bias voltage separately depending on the operation mode. [Means for solving the problem]

[0006] In order to achieve the above object, an image sensor according to the present invention is an image sensor that supports a full resolution mode and a crop mode, comprising: a pixel array including a plurality of pixels configured to generate a pixel signal by sensing an object; an analog-to-digital converter configured to convert the pixel signal into a digital signal and including a plurality of metal lines; a bias generator configured to apply a bias voltage to the plurality of metal lines; and a bias controller configured to determine a path along which the bias voltage is applied to the metal lines, wherein the bias controller includes a first transistor that determines activation of the entire plurality of metal lines based on a first control signal, and a second transistor that determines activation of the first metal line among the plurality of metal lines for the crop mode based on a second control signal.

[0007] In order to achieve the above object, an analog-to-digital converter according to the present invention is configured to convert a pixel signal sensed in a pixel into a digital signal, and is characterized in that it comprises a first metal line and a second metal line activated by a bias voltage provided from an external source, a comparator configured to generate a comparison signal by comparing the pixel signal with a ramp signal provided from an external source based on the bias voltage, a counter configured to generate a digital signal by counting the comparison signal based on a clock signal provided from an external source, and a plurality of transistors including a first transistor and a second transistor configured to determine a path of the bias voltage applied to the first metal line and the second metal line. Effect of the Invention

[0008] The image sensor and analog-to-digital converter according to the present invention can reduce the number of physical switches by applying separate bias voltages depending on the operation mode. This allows the image sensor and analog-to-digital converter to reduce noise induced by physical switches, minimize resistance increases, and stabilize the input range of the amplifier. In addition, the image sensor and analog-to-digital converter according to the present invention have robustness against a decrease in input voltage by reducing the number of physical switches, and can easily achieve low-power circuit design. [Brief description of the drawings]

[0009] [Figure 1] 1 is a block diagram showing a schematic configuration of an image sensor according to an embodiment of the present invention. [Diagram 2] FIG. 1 is a circuit diagram showing a schematic configuration of a pixel according to an embodiment of the present invention. [Diagram 3] 1 is a block diagram showing a schematic configuration of an analog-to-digital converting array according to an embodiment of the present invention. [Figure 4A] FIG. 1 is a circuit diagram showing a schematic configuration of an exemplary amplifier as a comparative example. [Figure 4B] 1 is a circuit diagram showing a schematic configuration of an amplifier according to an embodiment of the present invention. [Figure 5A] FIG. 2 shows a schematic configuration of metal lines, a bias generator, and transistors according to an embodiment of the present invention. [Figure 5B] FIG. 2 shows a schematic configuration of metal lines, a bias generator, and transistors according to an embodiment of the present invention. [Figure 5C] 2 is a schematic diagram of metal lines, a bias generator, and transistors according to an embodiment of the invention. [Figure 6A]FIG. 2 is a circuit diagram illustrating the operation of a plurality of metal lines, a bias generator, and a plurality of transistors according to an embodiment of the present invention. [Figure 6B] FIG. 2 is a circuit diagram illustrating the operation of a plurality of metal lines, a bias generator, and a plurality of transistors according to an embodiment of the present invention. [Figure 6C] FIG. 2 is a circuit diagram illustrating the operation of a plurality of metal lines, a bias generator, and a plurality of transistors according to an embodiment of the present invention. [Figure 6D] 4 is a table showing signal levels according to operation modes of an analog-to-digital converter according to an embodiment of the present invention. [Figure 7A] FIG. 2 illustrates a pixel array in crop mode according to an embodiment of the present invention. [Figure 7B] 1 is a diagram illustrating image processing according to an embodiment of the present invention; [Figure 8] 1 is a block diagram showing a schematic configuration of an electronic device including a multi-camera module according to an embodiment. [Figure 9] FIG. 9 is a block diagram showing a detailed configuration of the camera module of FIG. 8 according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Next, specific examples of embodiments for carrying out the image sensor and analog-to-digital converter according to the present invention will be described with reference to the drawings.

[0011] FIG. 1 is a block diagram showing a schematic configuration of an image sensor 100 according to an embodiment of the present invention. Referring to FIG. 1, an image sensor 100 is mounted in an electronic device having an image or light sensing function. For example, the image sensor 100 can be installed in electronic devices such as cameras, smartphones, wearable devices, Internet of Things (IoT), tablet PCs (Personal Computers), PDAs (Personal Digital Assistants), PMPs (Portable Multimedia Players), and navigation devices. The image sensor 100 can also be mounted on electronic devices that are provided as components in vehicles, furniture, manufacturing equipment, doors, various measuring instruments, and the like.

[0012] The image sensor 100 converts an optical signal of an object incident through an optical lens into an electrical signal, and converts the converted electrical signal into image data IDTA. The image sensor 100 includes, for example, a pixel array 110 including a plurality of pixels arranged two-dimensionally and various electrical circuits for sensing, and the image sensor 100 is realized as a semiconductor chip including the pixel array and the sensing circuits. The image sensor 100 includes a pixel array 110, a row driver 120, an analog-to-digital converting array (ADC array) 130 including an analog-to-digital converter (ADC) 131, a bias generator 140, a bias controller 150, a ramp generator 160, a clock generator 170, a column decoder 180, an output buffer 190, and a control logic 195.

[0013] The pixel array 110 converts the received optical signals into electrical signals. The pixel array 110 includes a plurality of pixels 111 arranged in a matrix, each of which is connected to a plurality of row lines and a plurality of column lines COL. Each of the multiple pixels 111 includes a photoelectric conversion element. For example, the pixel 111 may be implemented by a photoelectric conversion element such as a charge coupled device (CCD) or a complementary metal-oxide semiconductor (CMOS), or may be implemented by various other types of photoelectric conversion elements.

[0014] For example, the photoelectric conversion element may include a photodiode, a phototransistor, a photogate, or a pinned photodiode. Each of the multiple pixels 111 includes at least one photoelectric conversion element, and the multiple photoelectric conversion elements may be stacked on one another. The pixels 111 each sense light using a photoelectric conversion element and convert it into a pixel signal PS, which is an electrical signal. The pixel signal PS includes a reset signal generated by a reset operation of each of the plurality of pixels 111 and an image signal generated by a light sensing operation of each of the plurality of pixels 111 .

[0015] Each of the plurality of pixels 111 is sensitive to light in a particular spectral region. For example, the plurality of pixels 111 includes a red pixel for converting light in the red spectral region into an electrical signal, a green pixel for converting light in the green spectral region into an electrical signal, and a blue pixel for converting light in the blue spectral region into an electrical signal. A color filter for transmitting light in a specific spectral region is disposed above each of the plurality of pixels 111 . As another example, the plurality of pixels 111 may include cyan pixels, yellow pixels, magenta pixels, or white pixels.

[0016] A microlens and a color filter are laminated on each of the pixels 111, and the color filters of the pixels 111 constitute a color filter array. The color filter transmits light of a specific hue, that is, wavelengths in a specific hue range, among the light incident via the microlens. The color that the pixel 111 can sense is determined by the color filter provided in the pixel 111 . However, without being limited thereto, in an embodiment, the photoelectric conversion element provided in pixel 111 converts light corresponding to a wavelength in the hue region into an electrical signal depending on the level of the applied electrical signal, e.g., voltage level, thereby allowing the hue that pixel 111 can sense to be determined depending on the level of the electrical signal applied to the photoelectric conversion element.

[0017] In one embodiment, each of the pixels 111 senses an object using at least two photoelectric conversion elements. For example, each of the multiple pixels 111 includes at least one first photoelectric conversion element arranged to the left (or upward) side about the optical axis of the microlens and at least one second photoelectric conversion element arranged to the right (or downward) side about the optical axis of the lens. Each of the plurality of pixels 111 outputs a first image signal generated from a first photoelectric conversion element or a second image signal generated from a second photoelectric conversion element.

[0018] Of two pixels 111 arranged in adjacent different rows and the same column, one pixel 111 outputs a first image signal generated from a first photoelectric conversion element, and the other pixel 111 outputs a second image signal generated from a second photoelectric conversion element. At this time, the two pixels 111 sense the same hue. Based on the first and second image signals output from the two pixels 111, autofocusing data used in phase difference calculation for the AF function, for example, a phase detection signal pair, is generated. Moreover, the pixel 111 outputs a combined image signal generated from at least one first photoelectric conversion element and at least one second photoelectric conversion element as a pixel signal PS. The summed image signal is used to generate a frame-by-frame image.

[0019] The row driver 120 drives the pixel array 110 on a row-by-row basis. The row driver 120 decodes a row control signal (CTR_R) generated by the control logic 195, and selects at least one of the row lines constituting the pixel array 110 in response to the decoded row control signal. For example, the row control signal (CTR_R) includes an address signal or a command indicating address information. In one embodiment, the row driver 120 generates the row select signal. The pixel array 110 outputs a pixel signal PS from a row selected by a row selection signal provided by a row driver 120 through a column line COL. That is, the pixels 111 of the pixel array 110 sequentially output pixel signals row by row.

[0020] The analog-to-digital converting array 130 converts the pixel signal PS, which is an analog signal input from the pixel array 110, into a digital value. The analog-to-digital converting array 130 includes a plurality of ADCs 131 arranged in a column direction for processing pixel signals PS provided via column lines COL. In one embodiment, analog-to-digital converting array 130 may be referred to as a Correlated Double Sampling circuit. The pixel signals PS output from the multiple pixels 111 have deviations due to pixel-specific characteristics (e.g., CFPN (Column Fixed Pattern Noise)) that each pixel has and / or deviations due to differences in the characteristics of the logic for outputting pixel signals from the pixels 111. In order to compensate for such deviations between pixel signals, a reset component (or reset signal) and an image component (or image signal) are obtained for each pixel signal PS, and the difference is extracted as the effective signal component. This is called correlated double sampling.

[0021] The analog-to-digital converting array 130 is provided with a bias control signal BCS generated by a bias controller 150 , a ramp signal RS generated by a ramp generator 160 , and a counter clock signal CLK generated by a clock generator 170 . The ADC 131 converts the pixel signal PS, which is an analog signal, into a digital value based on the bias control signal BCS, the ramp signal RS, and the counter clock signal CLK. According to one embodiment, the ADC 131 activates at least a portion of the column lines COL based on a bias control signal BCS, compares pixel signals PS output from pixels connected to the activated column lines COL with a ramp signal RS, and amplifies the comparison result to generate a comparison signal. According to one embodiment, the ADC 131 converts the comparison signal into a digital signal based on a counter clock signal CLK. ADC 131 is described in further detail in FIG.

[0022] The bias generator 140 operates based on a bias control signal (CTR_B) provided by the control logic 195 . The bias generator 140 generates the bias voltage required to amplify the pixel signal PS and provides it to the analog-to-digital converting array 130 . The bias controller 150 determines the path of the bias voltage provided to the analog to digital converting array 130 . A bias voltage is required in common to multiple ADCs 131 depending on the operating mode, and the bias controller 150 activates at least some of the multiple column lines COL by determining a path so that a bias voltage is provided in common to multiple ADCs 131 arranged in parallel.

[0023] The ramp generator 160 operates based on a ramp control signal (CTR_RP) provided by the control logic 195 . The lamp control signal (CTR_RP) includes a lamp enable signal. The ramp generator 160 generates a ramp signal RS having a slope when the ramp enable signal is activated. The ramp signal RS is a signal that gradually rises or falls to a constant size. The ramp signal RS includes a reset ramping section for resetting and a signal ramping section for sensing a signal. For example, when the ramp signal RS is used for correlated double sampling CDS, the ramp signal RS sequentially has a reset ramping section and a signal ramping section. According to one embodiment, the ramp generator 160 generates a ramp signal RS having a particular slope, ramping time, ramping start voltage level, and / or ramping end voltage level in response to a ramp control signal (CTR_RP). For example, the ramp generator 160 generates a ramp signal RAMP that decreases with a constant slope, or generates a reverse ramp signal RAMP that increases with a constant slope.

[0024] The clock generator 170 operates based on a clock control signal (CTR_CK) provided by the control logic 195 . The clock generator 170 generates a counting clock signal CLK that is provided to the analog-to-digital converting array 130 . The generation timing and frequency of the counting clock signal CLK are controlled by the control logic 195. Although not shown in the figure, the clock generator 170 may be embodied by a Gray code generator. The clock generator 170 generates a number of code values ​​having a resolution according to a set number of bits as a counting clock signal CLK. For example, when a 10-bit code is set, the clock generator 170 generates a counting clock signal CLK that includes 1024 code values, and when an 11-bit code is set, the clock generator 170 generates a counting clock signal CLK that includes 2048 code values.

[0025] The output buffer 190 temporarily stores the digital signal output from the analog-to-digital converting array 130, senses it, amplifies it, and outputs it. The output buffer 190 may further include a column memory (not shown), and a sense amplifier (not shown). The column memory temporarily stores the digital signals output from each of the plurality of ADCs 131 and then outputs the digital signals to a sense amplifier, which senses and amplifies the digital signals output from the column memory. The sense amplifier outputs the amplified digital signal as image data IDTA. In FIG. 1, for convenience of explanation, the column memory is shown as being included in the output buffer 190, but the technical idea of ​​the present invention is not limited thereto. For example, it is understood that column memories may be included in the analog-to-digital converting array 130 in latches, and this is a matter of choice. In addition, the column memory may be implemented by, but is not limited to, a static random access memory (SRAM), a latch, a flip-flop, or a combination thereof.

[0026] The column decoder 180 operates based on a column control signal (CTR_C) provided by the control logic 195 . The column decoder 180 controls the output timing of the pixel values ​​stored in the output buffer 190 according to a column control signal (CTR_C). The column decoder 180 selects a particular column line from among a plurality of column lines COL by decoding a column control signal CTR_C. The column decoder 180 provides the image data IDTA temporarily stored in the memory of the output buffer 190 corresponding to the selected column line COL to the outside.

[0027] The control logic 195 provides overall control of the image sensor 100 by generating various control signals. According to one embodiment, the control logic 195 generates a row control signal (CTR_R) to control the row driver 120, a bias control signal (CTR_B) to control the bias generator 140, a ramp control signal (CTR_RP) to control the ramp generator 160, a clock generation signal (CLK_CK) to control the clock generator 170, and a column control signal (CTR_C) to control the column decoder 180. For example, the control logic 195 determines the timing, level, amplitude, duty ratio, and application time of the row control signal (CTR_R), bias control signal (CTR_B), ramp control signal (CTR_RP), clock generation signal (CLK_CK), and / or column control signal (CTR_C) to adjust the application time, application speed, slope, start voltage level, and / or end voltage level of the bias signal BS, ramp signal RS, and counter clock signal CLK.

[0028] The control logic 195 decodes commands provided from the outside and adjusts various control signals (e.g., row control signals (CTR_R), bias control signals (CTR_B), lamp control signals (CTR_RP), clock generation signals (CLK_CK), and / or column control signals (CTR_C)) to correspond to the commands. According to one embodiment, when a central processing unit (e.g., an application processor) of an electronic device including image sensor 100 determines an operational mode of image sensor 100, control logic 195 controls functional units of image sensor 100 to correspond to that operational mode. For example, the image sensor 100 supports a full resolution mode and a crop mode, and when the application processor commands a change in operating mode to the crop mode, the control logic 195 adjusts the row control signal (CTR_R), the bias control signal (CTR_B), the lamp control signal (CTR_RP), the clock generation signal (CLK_CK), and / or the column control signal (CTR_C) to correspond to the crop mode.

[0029] It will be understood that the control logic 195 may be embodied by a Central Processing Unit (CPU), an Arithmetic Logic Unit (ALU) that performs arithmetic and logical operations, bit shifting, etc., a Digital Signal Processor (DSP), a microprocessor, an Application Specific Integrated Circuit (ASIC), control logic, etc., but is not limited to these. In one embodiment, control logic 195 includes a state machine made up of a number of logic gates and may include a processor and a memory for storing instructions executed by the processor.

[0030] FIG. 2 is a circuit diagram showing a schematic configuration of a pixel 111 according to an embodiment of the present invention. Please also refer to FIG. Referring to FIG. 2, the pixel 111 includes a photodiode PD, a transfer transistor TX, a floating diffusion node FD, a reset transistor RX, a drive transistor DX, and a selection transistor SX. However, the present invention is not limited thereto, and the photodiode PD can be replaced with another photoelectric conversion element.

[0031] A reset control signal RS provided to the gate electrode of the reset transistor RX, a transmission control signal TS provided to the gate electrode of the transmission transistor TX, and a selection control signal SEL provided to the gate electrode of the selection transistor SX are each provided by the row driver 120 in response to a row control signal (CTR_R) generated by the control logic (FIG. 1) 195. The photodiode PD generates a photocharge that varies depending on the intensity of incident light. For example, a photodiode PD is a PN junction diode that generates electric charges, that is, negatively charged electrons and positively charged holes, in proportion to the amount of incident light. The photodiode PD is at least one of a phototransistor, a photogate, a pinned photodiode (PPD), and a combination thereof, as examples of a photoelectric conversion element.

[0032] A floating diffusion node FD (also called a floating diffusion region) is formed between the transfer transistor TX, the reset transistor RX, and the drive transistor DX. The transmission transistor TX transmits the photocharges to the floating diffusion node FD in response to a transmission control signal TS output from the row driver 120 (FIG. 1). According to one embodiment, the floating diffusion node FD acts as a capacitor. When the transmission transistor TX is turned on in response to a transmission control signal TS applied to the gate terminal of the transmission transistor TX, charges (e.g., photocharges) generated in the photodiode PD are transferred to the floating diffusion node FD and stored in the floating diffusion node FD.

[0033] The driving transistor DX amplifies the photocharges by a potential corresponding to the amount of photocharges stored in the floating diffusion node FD, and transmits the amplified photocharges to the selection transistor SX. The drain electrode of the selection transistor SX is connected to the source of the drive transistor DX, and outputs a pixel signal PS to a column line COL connected to the pixel 111 in response to a selection signal SEL output from the row driver 120 . The reset transistor RX resets the floating diffusion node FD to the power supply voltage VDD level in response to a reset control signal RS provided from the row driver 120.

[0034] The reset transistor RX periodically resets the charge stored in the floating diffusion node FD. The source electrode of the reset transistor RX is connected to the floating diffusion node FD, and the drain electrode is connected to the power supply voltage VDD. When the reset transistor RX is turned on in response to a reset control signal RS applied to the gate electrode thereof, the power supply voltage VDD connected to the drain electrode of the reset transistor RX is transferred to the floating diffusion node FD. When the reset transistor RX is turned on, the charge stored in the floating diffusion node FD is discharged and the floating diffusion node FD is reset.

[0035] The drive transistor DX operates as a source follower. The driving transistor DX receives a signal according to the charge amount of the floating diffusion node FD, that is, the potential of the floating diffusion node FD, at its gate electrode, and buffers and outputs the received signal. The selection transistor SX is turned on in response to a selection signal SEL applied to the gate electrode. When the selection transistor SX is turned on, the buffered signal output from the driving transistor DX is output as a pixel signal PS through the column line COL.

[0036] In FIG. 2, pixel 111 is illustrated as having a 4T (4-transistor) structure including one photodiode PD and four transistors (TX, RX, DX, SX), but each of the multiple pixels 111 included in the image sensor according to the present invention is not limited to the structure of FIG. 2. The pixel 111 may be a three-transistor 3T structure pixel, and may include a photodiode PD and three selected transistors among a transmission transistor TX, a reset transistor RX, a drive transistor DX, and a selection transistor SX.

[0037] FIG. 3 is a block diagram showing a schematic configuration of an analog-to-digital converting array 130 according to an embodiment of the present invention. Please also refer to FIG. Referring to FIG. 3, an analog-to-digital converting array 130 includes a plurality of ADCs 131, and converts a bias voltage V included in a bias signal (BS in FIG. 1) into a digital signal V . BIAS , the ramp voltage V contained in the ramp signal (RS in Figure 1) RAMP , and the counter clock signal CLK are provided in common to each of the multiple ADCs 131.

[0038] According to one embodiment, the ADC 131 includes a comparator 210 and a counter 230 . The comparator 210 is electrically connected to the bias generator 140 and the bias controller 150 . For convenience of explanation, the present invention is illustrated in the figure as the comparator 210 comparing the pixel signal PS with a ramp signal (RS in FIG. 1) and amplifying the comparison result to generate the comparison signal COMP, but the technical idea of ​​the present invention is not limited thereto. For example, it will be appreciated that the ADC 131 according to the present invention may include a separate comparator for generating a comparison signal as a result of the comparator 210 receiving the pixel signal PS, and an amplifier for amplifying the comparison signal.

[0039] According to one embodiment, the comparator 210 includes multiple metal lines. A number of metal lines are provided separately for various operation modes supported by the image sensor (reference numeral 100 in FIG. 1). For example, the comparator 210 may include a first metal line for imaging an object in a full resolution mode and a second metal line for imaging an object in a crop mode. In the present invention, the crop mode is an operating mode for capturing only a portion of an imageable area of ​​an object rather than the entire imageable area. At least one of the metal lines is activated (i.e., the bias voltage V BIAS The operation of the comparator 210 according to the operation mode of the image sensor 100 is determined by the application of the voltage Vcc (voltage Vcc).

[0040] In one embodiment, a number of metal lines are disposed below or above the analog-to-digital converting array 130 . In one embodiment, a plurality of metal lines are disposed under the comparators 210, and a bias voltage V is commonly applied to the plurality of comparators 210 included in the analog-to-digital converting array 130 via the plurality of metal lines. BIAS is provided. In the present invention, the bias voltage V BIAS A comparator 210 connected to a metal line to which a signal is applied is considered to be activated. According to one embodiment, a bias voltage V BIAS is applied to the pixel signal PS, activating the comparator 210 connected to the metal line to which the voltage is applied, thereby comparing, amplifying or inverting the pixel signal PS. The bias controller 150 controls the bias voltage V BIAS By determining the path, it controls whether the comparator 210 is activated or not. Activation of comparator 210 will be described with reference to FIGS. 5A-5C and 6A-6C.

[0041] The comparator 210 converts the pixel signal PS into a ramp voltage V RAMP and amplifying or inverting the comparison result. The comparator 210 detects the bias voltage V BIAS Based on this, the pixel signal PS output from the pixel (111 in FIG. 1) connected to any one of the column lines (COL in FIG. 1) is amplified to a voltage level suitable for analog-to-digital conversion. The comparator 210 detects the lamp voltage V RAMP When the level of the amplified signal VPIX is the same as the level of the amplified signal VPIX, the comparison circuit 10 outputs a comparison signal COMP that transitions from a first logic level (eg, logic high) to a second logic level (eg, logic low). The point in time when the level of the comparison signal COMP transitions is determined by the level of the pixel signal PS.

[0042] The comparator 210 includes a differential amplifier, which may be implemented by an OTA (Operational Transconductance Amplifier), an operational amplifier, or the like. The input terminal of the comparator 210 receives the ramp voltage V RAMP and a pixel signal PS is received. For example, the negative input of the comparator 210 receives the pixel signal PS and the positive input of the comparator 210 receives the ramp voltage V RAMP are entered respectively. The comparator 210 is connected to the pixel signal PS and the ramp voltage V RAMP and outputs the comparison result as a comparison signal COMP through the output terminal.

[0043] Although not shown, ADC 131 may include a limiting circuit (not shown). The limiting circuit is connected to the output terminal of the comparator 210 and limits the voltage at the output terminal, that is, the level of the comparison signal COMP. The limiting circuit provides a current to the output terminal to limit the level of the comparison signal COMP from decreasing below a particular level. Therefore, the comparator 210 can prevent the drain / source voltage of the transistor to which the pixel signal PS is input from decreasing below a certain level, and can prevent column fixed pattern noise (CFPN) caused by trapped charges.

[0044] Each of the plurality of counters 230 is connected to the output terminal of the comparator 210 and starts counting after the generation of each comparison signal COMP is completed. For example, the control logic (reference numeral 195 in FIG. 1) generates counter control signals including a counter clock signal, a counter reset signal that controls the reset operation of the multiple counters 230, and an inversion signal that inverts the internal bits of each of the multiple counters 230. Each of the counters 230 counts the level transition points of the comparison signal output from the comparator 210 corresponding to the same column based on the counting clock signal CLK, and outputs the count value as a digital signal DS. The counter 230 transmits the digital signal DS to the output buffer (190 in FIG. 1) (TO 190).

[0045] In one embodiment, the counter 230 includes a latch circuit and an arithmetic circuit. The latch circuit latches the code value received as the counting clock signal CLK at the time when the level of the comparison signal received from the comparator 210 transitions. The latch circuitry latches a code value corresponding to the reset signal, for example a reset value, and a code value corresponding to the image signal, for example an image signal value, respectively. The arithmetic circuit performs an operation on the reset value and the image signal value to generate an image signal value from which the reset level of the pixel 111 has been removed. The counter 230 outputs the image signal value from which the reset level has been removed as the pixel value.

[0046] However, without being limited thereto, the counter 230 may also be embodied as an up counter and an arithmetic circuit whose count value increases sequentially based on the counting clock signal CLK, or an up / down counter, or a bit-wise inversion counter. In this case, the bit-wise counter performs an operation similar to that of an up / down counter. For example, a bit-wise counter has a function of performing only up-counting and a function of inverting all bits in the counter to make them 1's complement when a specific signal is input. The bitwise counter performs a reset count and then inverts it to convert it to a one's complement, i.e., a negative value.

[0047] However, the image sensor 100 according to the present invention is not limited thereto. The image sensor 100 may further include a counting code generator that generates counting codes under the control of the control logic 195 . The counting code generator is implemented by a Gray code generator and generates a number of code values ​​having a resolution according to a set number of bits as counting codes. For example, the multiple counters 230 include a latch circuit and an arithmetic circuit, and the latch circuit receives the counting code from the counting code generator and the output signal from the comparator, and latches the code value of the counting code when the level of the comparison signal transitions. The arithmetic circuit performs an operation on the reset value and the image signal value to generate an image signal value from which the reset level of the pixel 111 has been removed.

[0048] FIG. 4A is a circuit diagram showing a schematic configuration of an exemplary comparator 210a as a comparative example, and FIG. 4B is a circuit diagram showing a schematic configuration of a comparator 210b according to an embodiment of the present invention. Referring to FIG. 4A, comparator 210a includes a plurality of transistors (MP11, MP12, MN11, MN12, MN21a, MN22a, MN23a), and some of the plurality of transistors (MN21a, MN22a, MN23a) are equivalently represented as a current source CSa.

[0049] In one embodiment, the comparator 210a includes a first P-type transistor MP11, a second P-type transistor MP12, a first N-type transistor MN11, and a second N-type transistor MN12. The comparator 210a also includes a third N-type transistor MN21a, a fourth N-type transistor MN22a, and a fifth N-type transistor MN23a between the first node NN and the ground voltage. For example, the third N-type transistor MN21a, the fourth N-type transistor MN22a, and the fifth N-type transistor MN23a are embodied as a current source CSa. The current source CSa is implemented by an NMOS transistor, i.e., an N-type metal oxide semiconductor field effect transistor (MOSFET), and has one end connected to a ground voltage and the other end connected to a first node NN to generate a bias current.

[0050] The first N-type transistor MN11 and the second N-type transistor MN12 receive a differential input, for example, a first input signal INP and a second input signal INN, respectively, and generate a differential current according to the level difference between the first input signal INP and the second input signal INN. For example, the first input signal INP is a lamp voltage V RAMP is received as a first input signal INN, and a pixel signal PS is received as a second input signal INN. If the first input signal INP and the second input signal INN are the same, the same current flows through the first N-type transistor MN11 and the second N-type transistor MN12, and if the first input signal INP and the second input signal INN are different from each other, different currents flow through the first N-type transistor MN11 and the second N-type transistor MN12. The sum of the currents flowing through the first N-type transistor MN11 and the second N-type transistor MN12 is equal to the bias current.

[0051] A power supply voltage VDD is applied to one end of the first P-type transistor MP11, and the other end is connected to a second output terminal that outputs a second output signal OUTN. A power supply voltage VDD is applied to one end of the second P-type transistor MP12, and the other end forms a first output terminal that outputs a first output signal OUTP. A first output signal OUTP and a second output signal OUTN are determined by current mirroring of a first P-type transistor MP11 and a second P-type transistor MP12. The first output signal OUTP and the second output signal OUTN are determined based on the amount of current flowing through the first N-type transistor MN11 and the second N-type transistor MN12. If the level of the first input signal INP is higher than the level of the second input signal INN, a relatively larger amount of current flows through the first N-type transistor MN11 than through the second N-type transistor MN12, thereby causing the level of the first output signal OUTP to increase and the level of the second output signal OUTP to decrease.

[0052] The gate electrode of the third N-type transistor MN21a is supplied with a first bias voltage V BIAS1 is applied to the gate electrode of the fourth N-type transistor MN22a, and the second bias voltage V BIAS2 is applied to the gate electrode of the fifth N-type transistor MN23a, and a power-down signal PDB is applied to the gate electrode of the fifth N-type transistor MN23a. First bias voltage V BIAS1 and / or a second bias voltage V BIAS2When this signal is applied, the comparator 210a amplifies the pixel signal PS. First bias voltage V BIAS1 and the second bias voltage V BIAS2 is not supplied to only one comparator 210a, but is simultaneously supplied to multiple comparators included in the analog-to-digital converting array (reference numeral 130 in FIG. 1).

[0053] The power-down signal PDB is a signal for cutting off the power supply to minimize the power supply when a part of the analog-to-digital converting array (reference numeral 130 in FIG. 1) is not used for sensing. In that case, the fifth N-type transistor MN23a to which the power-down signal PDB is provided functions as a physical power-down switch. Each additional physical switch added to the analog-to-digital converting array 130 induces its own on-resistance, which may vary the input range and bias current of the amplifier. For example, the comparator 210a of FIG. 4A adopts a three-series connected transistor structure, which results in problems such as a limited input range of the minimum operating voltage and degradation of the on-resistance distribution induced by the power-down switch.

[0054] Referring to FIG. 4B, a comparator 210b according to an embodiment of the present invention includes a third N-type transistor MN21b and a fourth N-type transistor MN22b that function as switches receiving a bias voltage, but does not include a fifth N-type transistor (MN23a in FIG. 4A) that functions as a physical power-down switch. The third N-type transistor MN21b and the fourth N-type transistor MN22b are equivalent to a current source CSb. The comparator 210b according to an embodiment of the present invention applies separate bias voltages depending on the operating mode, so that power supply can be cut off when a portion of the analog-to-digital converting array 130 is not being used for sensing, without the need for a physical power-down switch (i.e., the fifth N-type transistor MN23a). The method of applying the bias voltages separately depending on the operating mode will be described in more detail in FIG. 5A and subsequent figures.

[0055] 5A to 5C are diagrams showing schematic configurations of a plurality of metal lines (211, 212, 213), a bias generator 140, bias controllers (151, 152, 153), and a plurality of transistors (TR1, TR2, TR3) according to an embodiment of the present invention. 5A in conjunction with FIGS. 1 and 3, a first metal line ML1 and a second metal line ML2 included in the ADC 131 are defined as a plurality of metal lines 211. According to one embodiment, a number of metal lines 211 are placed under or over the amplifier (FIG. 3, 210) and are connected to a bias voltage V BIAS is provided. For example, the bias voltage V BIAS are first bias voltages V BIAS1 , and the second bias voltage V BIAS2 Includes.

[0056] According to one embodiment, a number of metal lines 211 are provided for the operational modes that the image sensor (100 in FIG. 1) supports. The operating modes of the image sensor 100 may vary depending on the imaging scenario, including full resolution mode, crop mode, binning mode, power saving mode (power down), etc. For example, for the crop mode, the first metal line ML1 supplies a bias voltage V BIAS to provide.

[0057] In addition, the second metal line ML2 supplies a bias voltage V BIAS does not provide. Bias voltage V BIASThe remaining part of the multiple comparators 210 for which no comparators are provided is included in the ADC 131 corresponding to the column lines (COL in FIG. 1) of the pixel array (110 in FIG. 1) that are not sensed in the crop mode. The comparator 210 corresponding to the non-sensing region is supplied with a bias voltage V BIAS is not applied, minimizing power consumption of the image sensor 100.

[0058] According to an embodiment of the present invention, the bias controller 151 further includes a first transistor TR1a, a second transistor TR2a, and a first switch SW1a. The first transistor TR1a and the second transistor TR2a are connected to a bias voltage V BIAS Determine the route. According to the embodiment, whether the first metal line ML1 and / or the second metal line ML2 are activated is determined by turning on / off the first transistor TR1a and / or the second transistor TR2a. For example, when the first transistor TR1a is turned on, the ground voltage is provided to the first metal line ML1, and no voltage is provided to the first metal line ML1, so that the first metal line ML1 is deactivated. For example, when the second transistor TR2a is turned on, the ground voltage is provided to the second metal line ML2, and no voltage is provided to the second metal line ML2, so that the second metal line ML2 is deactivated.

[0059] According to an embodiment of the present invention, a gate electrode of the first transistor TR1a is provided with a first control signal CS1, and a gate electrode of the second transistor TR2a is provided with a second control signal CS2. Whether the first transistor TR1a and the second transistor TR2a are activated is determined according to the logic levels (logic high or logic low) of the first control signal CS1 and the second control signal CS2. The activation of the first and second transistors (TR1a, TR2a) means turning the first and second transistors (TR1a, TR2a) on / off.

[0060] According to one embodiment of the present invention, the first transistor TR1a applies a bias voltage V across the plurality of metal lines 211. BIAS Determine whether to apply The second transistor TR2a supplies a bias voltage V BIAS Determine whether to apply According to an embodiment of the present invention, a first switch SW1a is included between the first transistor TR1a and the second transistor TR2a. The first switch SW1a is controlled by a first switch signal SS1a. The first switch SW1a blocks the ground voltage, which is applied when the first transistor TR1a is turned on, from being applied to the second metal line ML2, or blocks the ground voltage, which is applied when the second transistor TR2a is turned on, from being applied to the first metal line ML1.

[0061] In the present invention, for various operations of the image sensor (reference numeral 100 in FIG. 1), a first bias voltage V is applied as a bias signal (reference numeral BS in FIG. 1). BIAS1 and the second bias voltage V BIAS2 are shown as being applied to comparator 210a, the technical concepts of the present invention are not so limited. The comparator 210a receives one bias voltage V through one transistor (for example, a third N-type transistor MN21a). BIAS1 or three or more bias voltages may be applied through three or more transistors.

[0062] The analog-to-digital converting array 130 and / or the image sensor 100 including the analog-to-digital converting array 130 according to an embodiment of the present invention reduces physical switches by applying bias voltages separately depending on the operation mode. This allows the analog-to-digital converter and image sensor to reduce noise (column fixed pattern noise (CFPN) or thermal noise) induced by physical switches, minimize resistance increases, and stabilize the input range of the comparator 210.

[0063] In addition, the analog-to-digital converting array 130 and / or the image sensor 100 including the analog-to-digital converting array 130 according to an embodiment of the present invention reduces noise by reducing physical switches, so that a low-power circuit design can be easily achieved even though the input voltage gradually decreases to realize power. In addition, the analog-to-digital converting array 130 and / or the image sensor 100 including the analog-to-digital converting array 130 according to an embodiment of the present invention may increase space efficiency in terms of circuit layout design by reducing physical switches.

[0064] 5B in conjunction with FIGS. 1 and 3, the bias controller 152 further includes a first transistor TR1b, a second transistor TR2b, and a second switch SW2b and a third switch SW3b. In addition, since the image sensor 100 supports various modes such as a binning mode, the plurality of metal lines 212 may further include a third metal line ML3 in addition to the first metal line ML1 and the second metal line ML2. In Figures 5A and 5B, for the sake of simplicity, the multiple metal lines (211, 212) are shown to include two or three metal lines (ML1, ML2, ML3), but the technical idea of ​​the present invention is not limited thereto and various numbers of metal lines can be combined and used to deactivate metal lines that are not sensed or processed for various operating modes.

[0065] In FIG. 5B, the plurality of metal lines 212 includes three metal lines (ML1 to ML3), so that one more transistor is added compared to FIG. 5A. According to the embodiment, the first transistor TR1b is connected to the first metal line ML1 and the common node of the bias generator 140, and is controlled by a first control signal CS1. The second transistor TR2b is connected to the second metal line ML2 and is controlled by a second control signal CS2. The third transistor TR3b is connected to a third metal line ML3 and is controlled by a third control signal CS3. The second switch SW2b is connected between the common node of the first metal line ML1 and the bias generator 140 and the common node of the second transistor TR2b and the second metal line ML2, and is controlled by a second switch signal SS2b. The third switch SW3b is connected between the common node of the first metal line ML1 and the bias generator 140 and the common node of the third transistor TR3b and the third metal line ML3, and is controlled by a third switch signal SS3b.

[0066] According to one embodiment of the present invention, the first transistor TR1b applies a bias voltage V across the plurality of metal lines 212. BIAS Determine whether to apply The second transistor TR2b supplies a bias voltage V BIAS Determine whether to apply The third transistor TR3b supplies a bias voltage V BIAS Determine whether to apply The second switch SW2b blocks the ground voltage from being applied to the second metal line ML2 when the first transistor TR1b is turned on, or blocks the ground voltage from being applied to the first metal line ML1 or the third metal line ML3 when the second transistor TR2b is turned on. The third switch SW3b blocks the ground voltage caused by the first transistor TR1b being turned on from being applied to the third metal line ML3, or blocks the ground voltage caused by the third transistor TR3b being turned on from being applied to the first metal line ML1 or the second metal line ML2.

[0067] 5C together with FIGS. 1 and 3, the bias controller 153 further includes a first transistor TR1c, a second transistor TR2c, a third transistor TR3c, a fourth switch SW1c, and a fifth switch SW3c. The multiple metal lines 213 include a first metal line ML1 and a second metal line ML2.

[0068] According to one embodiment, the first transistor TR1c is connected to the first metal line ML1 and a common node of the bias generator 140, and is controlled by a first control signal CS1. The second transistor TR2c is connected to the second metal line ML2 and is controlled by a second control signal CS2. The third transistor TR3c is connected to the first metal line ML1 and is controlled by a third control signal CS3. The fourth switch SW1c is connected between the common node of the first metal line ML1 and the bias generator 140 and the common node of the second transistor TR2c and the second metal line ML2, and is controlled by a fourth switch signal SS1c. The fifth switch SW3c is connected between the common node of the first metal line ML1 and the bias generator 140 and the common node of the third transistor TR3c and the first metal line ML1, and is controlled by a fifth switch signal SS3c.

[0069] According to one embodiment of the present invention, the first transistor TR1c applies a bias voltage V across the plurality of metal lines 212. BIAS Determine whether to apply The second transistor TR2c supplies a bias voltage V BIASDetermine whether to apply The third transistor TR3c supplies a bias voltage V BIAS Determine whether to apply The fourth switch SW1c cuts off the application of the ground voltage to the second metal line ML2 when the first transistor TR1c is turned on, or cuts off the application of the ground voltage to the first metal line ML1 when the second transistor TR2c is turned on. The fifth switch SW3c blocks the ground voltage, which is applied when the first transistor TR1c is turned on, from being applied to the first metal line ML1, or blocks the ground voltage, which is applied when the third transistor TR3c is turned on, from being applied to the second metal line ML2.

[0070] According to an embodiment of the present invention, at least two metal lines (e.g., a first metal line ML1 and a second metal line ML2) included in the plurality of metal lines 213 each include a transistor (e.g., a second transistor TR2c and a third transistor TR3c) and a switch (a fourth switch SW1c and a fifth switch SW3c). Thus, an image sensor (FIG. 1, 100) operating in crop mode selectively activates the comparators (FIG. 3, 210) required for the crop.

[0071] 6A to 6C are circuit diagrams illustrating the operation of a plurality of metal lines 211, a bias generator 140, and a plurality of transistors (TR1, TR2) according to an embodiment of the present invention. Please refer to both Figure 1 and Figure 5A. In the present invention, for convenience of explanation, it is assumed that the first transistor TR1 and the second transistor TR2 are both N-type MOSFETs, and the control signals (CS1, CS2) of the transistors are also explained based on N-type MOSFETs. However, the technical idea of ​​the present invention is not limited thereto, and the technical idea of ​​the present invention does not exclude the case where the first transistor TR1 and the second transistor TR2 are P-type MOSFETs. In that case, the logic levels of the transistor control signals (CS1, CS2) are in opposite phase.

[0072] Referring to FIG. 6A, the first control signal CS1 is applied to a logic low level. At this time, it is understood that the channel of the first transistor TR1 is not formed and the first transistor TR1 is inactivated. As a result, the ground voltage connected to one end of the first transistor TR1 is not provided to the other end. The second control signal CS2 is applied to a logic low level. At this time, the channel of the first transistor TR1 is not formed, and the second transistor TR2 is inactivated. Therefore, the ground voltage connected to one end of the second transistor TR2 is not provided to the other end. The first switch signal SS1 is applied to a logic high level H, and the first switch SW1 is shorted.

[0073] As a result, the bias voltage V generated by the bias generator 140 BIAS is provided to both the first metal line ML1 and the second metal line ML2. The first metal line ML1 supplies a bias voltage V BIAS , and the second metal line ML2 provides a bias voltage V BIAS , resulting in all comparators 210 being provided with a bias voltage (activated). Bias voltage V BIAS If V is applied to all comparators 210, then full resolution mode applies.

[0074] Referring to FIG. 6B, the first control signal CS1 is applied to a logic low level. At this time, it is understood that the channel of the first transistor TR1 is not formed, the first transistor TR1 is inactivated, and the ground voltage connected to one end of the first transistor TR1 is not provided to the other end. The second control signal CS2 is applied to a logic high level. At this time, it is understood that the channel of the first transistor TR1 is formed and the second transistor TR2 is turned on. Therefore, the ground voltage connected to one end of the second transistor TR2 is provided to the other end. In that case, the ground voltage is provided to the second metal line ML2, thereby deactivating the second metal line ML2. The first switch signal SS1 is applied to a logic low level L, and the first switch SW1 is opened to block the ground voltage from being provided to the first metal line ML1.

[0075] As a result, the bias voltage V generated by the bias generator 140 BIAS is provided to the first metal line ML1. The first metal line ML1 supplies a bias voltage V BIAS , and the second metal line ML2 provides a bias voltage V BIAS Therefore, only a part of the multiple comparators 210 performs the analog-to-digital conversion operation. Bias voltage V BIAS When is applied to only some of the comparators 210, this corresponds to the crop mode.

[0076] Referring to FIG. 6C, the first control signal CS1 is applied to a logic high level H, the channel of the first transistor TR1 is formed, and the first transistor TR1 is activated. Therefore, the ground voltage connected to one end of the first transistor TR1 is provided to the other end. The second control signal CS2 is applied to a logic high level. At this time, the channel of the first transistor TR1 is formed, and the second transistor TR2 is activated. Therefore, the ground voltage connected to one end of the second transistor TR2 is provided to the other end. Thus, the ground voltage is provided to the second metal line ML2, thereby deactivating the second metal line ML2.

[0077] In this case, the first switch signal SS1 is applied to a logic high H or a logic low L (D: Don't care). This is because, if the first switch SW1 is open, a ground voltage is provided to the first metal line ML1 via the first transistor TR1, and a ground voltage is provided to the second metal line ML2 via the second transistor TR2; conversely, if the first switch SW1 is shorted, a ground voltage is provided to both the first metal line ML1 and the second metal line ML2 via the first transistor TR1. As a result, when the second control signal CS2 is logic low L, the logic level of the first switch signal SS1 is irrelevant (D).

[0078] By similar logic, when the first control signal CS1 is applied to logic high H, if the first switch signal SS1 is applied to logic high H, the logic level of the second control signal CS2 is irrelevant (D). For example, if the second control signal CS2 is logic low L, the ground voltage resulting from the deactivation of the first transistor TR1 is provided to the second metal line ML2 through the shorted first switch SW1. For example, if the second control signal CS2 is logic high H, the ground voltage due to the deactivation of the first transistor TR1 is provided to the second metal line ML2 via the shorted first switch SW1, or the ground voltage due to the deactivation of the second transistor TR2 is provided directly to the second metal line ML2. A bias voltage V BIAS When all of the comparators 210 are deactivated by applying no voltage and applying a ground voltage to all of the comparators 210, the mode corresponds to a power saving mode.

[0079] FIG. 6D is a table illustrating signal levels according to the operation mode of ADC 131 in accordance with an embodiment of the present invention. Referring to Figure 6D together with Figures 6A to 6C, in order to support the full resolution mode FULL of ADC131, the first control signal CS1, the second control signal CS2, and the first switch signal SS1 must all be applied to logic low L, and the first switch signal SS1 must be applied to logic high H. As a result, the first metal line ML1 and the second metal line ML2 are supplied with a bias voltage V BIAS is applied.

[0080] In order to support the crop mode of the ADC 131, the first control signal CS1 and the first switch signal SS1 must both be applied to a logic low level L, and the second control signal CS2 must be applied to a logic high level H. As a result, the first metal line ML1 is connected to the bias voltage V BIAS is applied to the first metal line ML1, and a ground voltage VSS is applied to the second metal line ML2.

[0081] In order to support the power saving mode POWEROFF of the ADC 131, at least two of the first control signal CS1, the second control signal CS2, and the first switch signal SS1 are required to be logic high H. For example, when the first control signal CS1 and the second control signal CS2 are applied at logic high and low, the first switch signal SS1 is independent of the logic level of the applied voltage (D). For example, when the first control signal CS1 and the first switch signal SS1 are applied to a logic high, the second control signal CS2 is independent of the logic level of the applied voltage (D). For example, when the second control signal CS2 and the first switch signal SS1 are applied to a logic high, the first control signal CS1 is independent of the logic level of the applied voltage (D).

[0082] As a result, the ground voltage VSS is applied to both the first metal line ML1 and the second metal line ML2. As described above, when the first transistor TR1 and the second transistor TR2 are P-type MOSFETs, the logic levels of the control signals (CS1, CS2) of the transistors (TR1, TR2) are in opposite phase.

[0083] FIG. 7A is a diagram illustrating a pixel array in crop mode according to an embodiment of the present invention. Referring to FIG. 7A, the pixel array 110 sequentially reads a number of rows corresponding to a crop area (CROP AREA) among a number of rows (ROW1 to ROW(N+1)). The operating mode of an image sensor (100 in FIG. 1) according to one embodiment of the present invention is determined by an external controller (eg, an application processor). For example, a crop area is set in the target area by an external application processor.

[0084] The crop area (CROP AREA) includes the Mth row to the Nth row (cropped row area). In one embodiment, the pixel array 110 skips the remaining rows except for the crop area (CROP AREA) and sequentially reads the Mth row ROW(M) to the Nth row ROW(N) along the rows. The pixel signals (PS in FIG. 1) read row by row are output in the column direction of the pixel array 110. The application processor's control over the CROP AREA also provides position information of the pixels 111 relative to the CROP AREA, ie, the position information of the column lines COL.

[0085] For example, under the control of the application processor, the column decoder (reference numeral 180 in FIG. 1) selects only the columns corresponding to the crop area (crop column area), and an analog-to-digital conversion operation is performed only on the columns corresponding to the crop area (crop area). In this case, among the metal lines included in the amplifier (210 in FIG. 3), only the metal lines corresponding to the crop area are activated, and the metal lines not included in the crop area are deactivated.

[0086] FIG. 7B is a diagram illustrating image processing according to an embodiment of the present invention. The pixel to be read is shown in the figure as four sub-pixels in which red, green, and blue are arranged in "RGBG" order clockwise from the top left corner. In all the following figures, the four sub-pixels arranged in a clockwise direction from the upper left corner as "RGBG" represent a hue as a combination of "RGB" light when output to a display unit, but this does not mean that the actual implementation of the pixel array 110 of the image sensor 100 is composed of four sub-pixels.

[0087] The first image IMG1 corresponds to a result of the image sensor 100 capturing an image of an object in a full resolution mode, and the second image IMG2 corresponds to a result of the image sensor 100 capturing an image of an object in a crop mode. According to one embodiment of the present invention, a bias voltage is not provided to the comparators 210 that are not included in the crop region among the multiple comparators 210 included in the analog-to-digital converting array 130, thereby reducing the power consumed by the comparators 210 that are not performing an analog-to-digital converting operation.

[0088] FIG. 8 is a block diagram showing a schematic configuration of an electronic device including a multi-camera module according to an embodiment, and FIG. 9 is a block diagram showing a detailed configuration of the camera module of FIG. 8 according to an embodiment. Referring to FIG. 8, the electronic device 1000 includes a camera module group 1100, an application processor 1200, a PMIC 1300, and an external memory 1400.

[0089] The camera module group 1100 includes multiple camera modules (1100a, 1100b, 1100c). For example, the figures show an embodiment in which three camera modules (1100a, 1100b, 1100c) are arranged, but the embodiment is not so limited. In one embodiment, the camera module group 1100 may be modified and implemented to include only two camera modules. Also, in one embodiment, the camera module group 1100 can be modified and implemented to include N camera modules (n is a natural number equal to or greater than 4).

[0090] The detailed configuration of camera module 1100b will be described in more detail below with reference to FIG. 9, but the following description also applies to other camera modules (1100a, 1100c) depending on the embodiment. Referring to FIG. 9, a camera module 1100b includes a prism 1105, an optical path folding element (hereinafter, “OPFE”) 1110, an actuator 1130, an image sensing device 1140, and a storage unit 1150. The prism 1105 includes a reflecting surface 1107 made of a light reflecting material, and changes the path of light L incident from the outside.

[0091] In one embodiment, the prism 1105 changes the path of light L incident in a first direction X to a second direction Y perpendicular to the first direction X. In addition, the prism 1105 rotates the reflective surface 1107 of the light-reflecting material around the central axis 1106 in the direction A, or rotates the central axis 1106 in the direction B, thereby changing the path of the light L incident in the first direction X to a perpendicular second direction Y. At this time, the OPFE 1110 can also move in a third direction Z perpendicular to the first direction X and the second direction Y.

[0092] In one embodiment, as shown in the figure, the maximum rotation angle of prism 1105 in the A direction is less than or equal to 15 degrees in the plus (+) A direction and greater than 15 degrees in the minus (-) A direction, although the embodiment is not limited thereto. In one embodiment, prism 1105 can move around 20° in the plus (+) or minus (-) B direction, or between 10° to 20° or 15° to 20°, where the angle of movement can be the same angle in the plus (+) or minus (-) B direction, or up to a similar angle in the range of around 1°.

[0093] In one embodiment, the prism 1105 moves the reflective surface 1106 of the light-reflective material in a third direction (eg, Z direction) parallel to the extension direction of the central axis 1106. The OPFE 1110 may include, for example, m groups of optical lenses (where m is a natural number). The m lenses move in a second direction Y to change the optical zoom ratio of the camera module 1100b. For example, when the basic optical zoom magnification of camera module 1100b is Z, when m optical lenses included in OPFE 1110 are moved, the optical zoom magnification of camera module 1100b can be changed to an optical zoom magnification of 3Z or 5Z, or greater than 5Z.

[0094] The actuator 1130 moves the OPFE 1110 or the optical lens (hereinafter referred to as the optical lens) to a particular position. For example, the actuator 1130 adjusts the position of the optical lens so that the image sensor 1142 is located at the focal length of the optical lens for accurate sensing.

[0095] The image sensing device 1140 includes an image sensor 1142 , control logic 1144 , and a memory 1146 . The image sensor 1142 senses an image of a sensing target using light L provided through an optical lens. The control logic 1144 controls the overall operation of the camera module 1100b. For example, control logic 1144 controls the operation of camera module 1100b via control signals provided over control signal line CSLb.

[0096] Memory 1146 stores information necessary for the operation of camera module 1100b, such as calibration data 1147. The calibration data 1147 includes information necessary for the camera module 1100b to generate image data using the light L provided from an external source. The calibration data 1147 includes, for example, the above-mentioned information related to the degree of rotation, information related to the focal length, information related to the optical axis, and the like. If the camera module 1100b is implemented as a multi-state camera in which the focal length changes depending on the position of the optical lens, the calibration data 1147 includes focal length values ​​for each position (or state) of the optical lens and information related to autofocusing.

[0097] The storage unit 1150 stores the image data sensed by the image sensor 1142 . The storage unit 1150 may be disposed outside the image sensing device 1140 and may be implemented in a stacked form with a sensor chip constituting the image sensing device 1140 . In one embodiment, the storage unit 1150 may be embodied by an Electrically Erasable Programmable Read-Only Memory (EEPROM), but the embodiment is not limited thereto.

[0098] 8 and 9, in one embodiment, multiple camera modules (1100a, 1100b, 1100c) each include an actuator 1130. As such, each of the multiple camera modules (1100a, 1100b, 1100c) may include calibration data 1147 that is the same as or different from one another due to the operation of the actuator 1130 contained therein. In one embodiment, one camera module (e.g., 1100b) of the multiple camera modules (1100a, 1100b, 1100c) is a folded lens type camera module including the above-mentioned prism 1105 and OPFE 1110, and the remaining camera modules (e.g., 1100a, 1100b) are vertical type camera modules that do not include the prism 1105 and OPFE 1110, but the embodiment is not limited thereto.

[0099] In one embodiment, one camera module (e.g., 1100c) of the multiple camera modules (1100a, 1100b, 1100c) is a vertical depth camera that extracts depth information using, for example, infrared rays (IR). In that case, the application processor 1200 merges image data provided from such a depth camera with image data provided from a different camera module (e.g., 1100a or 1100b) to generate a 3D depth image.

[0100] In one embodiment, at least two camera modules (eg, 1100a, 1100b) of the multiple camera modules (1100a, 1100b, 1100c) have different fields of view (field of view angles). In that case, for example, but not limited to, the optical lenses of at least two camera modules (eg, 1100a, 1100b) among the multiple camera modules (1100a, 1100b, 1100c) may be different from each other. Also, in one embodiment, the viewing angles of each of the multiple camera modules (1100a, 1100b, 1100c) may be different from each other. In this case, the optical lenses included in each of the multiple camera modules (1100a, 1100b, 1100c) may be different from each other, but are not limited to this. In one embodiment, each of the multiple camera modules (1100a, 1100b, 1100c) is positioned physically separated from one another. In other words, the sensing area of ​​one image sensor 1142 is not divided and used by multiple camera modules (1100a, 1100b, 1100c), but an independent image sensor 1142 is arranged inside each of the multiple camera modules (1100a, 1100b, 1100c).

[0101] 8, the application processor 1200 includes an image processing unit 1210, a memory controller 1220, and an internal memory 1230. The application processor 1200 may be implemented separately from the multiple camera modules (1100a, 1100b, 1100c). For example, the application processor 1200 and the camera modules 1100a, 1100b, and 1100c may be implemented separately from each other on separate semiconductor chips.

[0102] The image processing device 1210 includes multiple sub-image processors (1212a, 1212b, 1212c), an image generator 1214, and a camera module controller 1216. The image processing device 1210 includes a number of sub-image processors (1212a, 1212b, 1212c) corresponding to the number of the camera modules (1100a, 1100b, 1100c).

[0103] Image data generated from each camera module (1100a, 1100b, 1100c) is provided to a corresponding sub-image processor (1212a, 1212b, 1212c) via mutually separated image signal lines (ISLa, ISLb, ISLc). For example, image data generated from camera module 1100a is provided to sub-image processor 1212a via image signal line ISLa, image data generated from camera module 1100b is provided to sub-image processor 1212b via image signal line ISLb, and image data generated from camera module 1100c is provided to sub-image processor 1212c via image signal line ISLc. Such image data transmission may be performed using, for example, a Camera Serial Interface (CSI) based on the Mobile Industry Processor Interface (MIPI), but the embodiment is not limited thereto.

[0104] On the other hand, in one embodiment, one sub-image processor may be arranged to correspond to multiple camera modules. For example, sub-image processor 1212a and sub-image processor 1212c are not implemented separately from each other as shown in the figure, but are integrated into a single sub-image processor, and image data provided from camera module 1100a and camera module 1100c is selected through a selection element (e.g., a multiplexer) and then provided to the integrated sub-image processor.

[0105] The image data provided to each of the sub-image processors (1212a, 1212b, 1212c) is provided to an image generator 1214. The image generator 1214 generates an output image using image data provided from each of the sub-image processors 1212a, 1212b, and 1212c by image generating information or mode signals. Specifically, the image generator 1214 merges at least a portion of the image data generated from the camera modules (1100a, 1100b, 1100c) having different viewing angles according to image generation information or a mode signal to generate an output image. Also, the image generator 1214 selects one of the image data generated from the camera modules 1100a, 1100b, and 1100c having different viewing angles according to image generation information or a mode signal, and generates an output image.

[0106] In one embodiment, the image generation information includes a zoom signal or zoom factor. Also, in one embodiment, the mode signal is a signal based on a mode selected by, for example, a user. When the image generation information is a zoom signal (zoom factor) and each camera module (1100a, 1100b, 1100c) has a different observation field of view (viewing angle), the image generator 1214 performs different operations according to the type of zoom signal.

[0107] For example, when the zoom signal is a first signal, the image data output from camera module 1100a and the image data output from camera module 1100c are merged, and then an output image is generated using the image data output from camera module 1100b that was not used in merging with the merged image signal. If the zoom signal is a second signal different from the first signal, the image generator 1214 does not perform such image data merging, but instead selects one of the image data output from each camera module (1100a, 1100b, 1100c) to generate an output image. However, the embodiment is not limited thereto, and the method of processing image data can be modified in any manner as necessary.

[0108] In one embodiment, the image generator 1214 receives multiple image data having different exposure times from at least one of the multiple sub-image processors (1212a, 1212b, 1212c) and performs HDR (high dynamic range) processing on the multiple image data to generate merged image data with an increased dynamic range.

[0109] The camera module controller 1216 provides control signals to each of the camera modules (1100a, 1100b, 1100c). The control signals generated from the camera module controller 1216 are provided to the corresponding camera modules (1100a, 1100b, 1100c) via mutually isolated control signal lines (CSLa, CSLb, CSLc).

[0110] One of the multiple camera modules (1100a, 1100b, 1100c) is designated as a master camera (e.g., 1100b) by image generation information or a mode signal including a zoom signal, and the remaining camera modules (e.g., 1100a, 1100c) are designated as slave cameras. Such information is included in control signals and provided to the corresponding camera modules (1100a, 1100b, 1100c) via separate control signal lines (CSLa, CSLb, CSLc). The camera modules acting as master and slave can be changed by a zoom factor or an operation mode signal. For example, if the viewing angle of camera module 1100a is wider than that of camera module 1100b and the zoom factor indicates a lower zoom ratio, camera module 1100b acts as the master and camera module 1100a acts as the slave. Conversely, when the zoom factor indicates a high zoom magnification, camera module 1100a acts as the master and camera module 1100b acts as the slave.

[0111] In one embodiment, the control signals provided from the camera module controller 1216 to each camera module (1100a, 1100b, 1100c) include a sync enable signal. For example, if the camera module 1100b is the master camera and the camera modules (1100a, 1100c) are slave cameras, the camera module controller 1216 transmits a sync enable signal to the camera module 1100b. Upon receiving such a sync enable signal, camera module 1100b generates a sync signal based on the provided sync enable signal and provides the generated sync signal to camera modules (1100a, 1100c) via a sync signal line SSL. Camera module 1100b and camera modules 1100a and 1100c transmit image data to application processor 1200 in synchronization with such a sync signal.

[0112] In one embodiment, the control signals provided by the camera module controller 1216 to the multiple camera modules (1100a, 1100b, 1100c) include mode information via a mode signal. Based on such mode information, the camera modules (1100a, 1100b, 1100c) operate in a first operation mode and a second operation mode in relation to the sensing speed. In a first operating mode, multiple camera modules (1100a, 1100b, 1100c) generate image signals at a first rate (e.g., generate image signals at a first frame rate), encode them to a second rate higher than the first rate (e.g., encode image signals at a second frame rate higher than the first frame rate), and transmit the encoded image signals to the application processor 1200. In this case, the second speed may be 30 times or less than the first speed.

[0113] The application processor 1200 stores the received image signal, i.e., the encoded image signal, in an internal memory 1230 or in a storage 1400 external to the application processor 1200, and then reads and decodes the encoded image signal from the memory 1230 or the storage 1400, and displays image data generated based on the decoded image signal. For example, a corresponding sub-processor among a plurality of sub-processors (1212a, 1212b, 1212c) of the image processing device 1210 performs decoding and performs image processing on the decoded image signal.

[0114] In a second operating mode, multiple camera modules (1100a, 1100b, 1100c) generate image signals at a third speed slower than the first speed (e.g., generate image signals at a third frame rate lower than the first frame rate) and transmit the image signals to the application processor 1200. The image signal provided to the application processor 1200 is an unencoded signal. The application processor 1200 performs image processing on the received image signal or stores the image signal in the memory 1230 or storage 1400 .

[0115] The PMIC 1300 supplies power, for example, a power supply voltage, to each of the multiple camera modules (1100a, 1100b, 1100c). For example, under the control of application processor 1200, PMIC 1300 supplies a first power to camera module 1100a via power signal line PSLa, supplies a second power to camera module 1100b via power signal line PSLb, and supplies a third power to camera module 1100c via power signal line PSLc. In response to a power control signal PCON from the application processor 1200, the PMIC 1300 generates power corresponding to each of the multiple camera modules (1100a, 1100b, 1100c) and adjusts the power level.

[0116] The power control signal PCON includes power adjustment signals for each operation mode of the multiple camera modules (1100a, 1100b, 1100c). For example, the operating mode may include a low power mode, where the power control signal PCON includes information related to the camera module operating in the low power mode and the power level to be set. The level of power provided to each of the multiple camera modules (1100a, 1100b, 1100c) may be equal to or different from one another. Additionally, the power level can be changed dynamically.

[0117] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0118] 100 Image Sensor 110 pixel array 111 pixels 120 Row Driver 130 ADC array 131 ADC circuit 140 Bias Generator 150, 151, 152, 153 Bias controller 160 Ramp Generator 170 Clock Generator 180 Column Decoder 190 Output Buffer 195 Control Logic 210, 210a, 210b comparator 211, 212, 213 Metal Line 230 Counter

Claims

1. For image sensors that support full resolution and crop modes, a pixel array including a plurality of pixels configured to generate pixel signals by sensing an object; an analog-to-digital converter configured to convert the pixel signal into a digital signal, the analog-to-digital converter including a plurality of metal lines; a bias generator configured to apply a bias voltage to the plurality of metal lines; a bias controller configured to determine a path along which the bias voltage is applied to the metal line; the bias controller includes a first transistor that determines activation of the entire plurality of metal lines based on a first control signal; a second transistor that determines activation of a first metal line for the crop mode among the plurality of metal lines based on a second control signal.

2. 2. The image sensor according to claim 1, further comprising a first switch between the first transistor and the second transistor.

3. 3. The image sensor of claim 2, wherein the full resolution mode corresponds to the first transistor and the second transistor being in an inactive state and the first switch being in a shorted state.

4. 3. The image sensor of claim 2, wherein the crop mode corresponds to a deactivated state of the first transistor, an activated state of the second transistor, and an open state of the first switch.

5. The image sensor further supports a power saving mode; 3. The image sensor of claim 2, wherein the power saving mode corresponds to one of an active state of the first transistor and an active state of the second transistor, or a short-circuit state of a first switch.

6. The image sensor of claim 1, wherein the first transistor and the second transistor comprise N-type metal oxide semiconductor field effect transistors (MOSFETs).

7. The image sensor of claim 1, wherein the full resolution mode is characterized in that both the first control signal and the second control signal are at a first logic level.

8. In the crop mode, the first control signal is at a first logic level; 2. The image sensor of claim 1, wherein the second control signal is at a second logic level that is opposite in phase to the first logic level.

9. The image sensor of claim 1, wherein in the full resolution mode, the bias voltage is applied to all of the plurality of metal lines.

10. In the crop mode, the bias voltage is provided to the first metal line; 2. The image sensor of claim 1, wherein a ground voltage is provided to the remaining metal lines of the plurality of metal lines except for the first metal line.

11. The image sensor further supporting a power saving mode; 2. The image sensor of claim 1, wherein in the power saving mode, a ground voltage is applied to all of the plurality of metal lines.

12. an analog-to-digital converter configured to convert a pixel signal sensed at a pixel into a digital signal, a first metal line and a second metal line that are activated in response to a bias voltage; a comparator configured to compare the pixel signal with a ramp signal based on the bias voltage to generate a comparison signal; a counter configured to generate a digital signal by counting the comparison signals based on a clock signal; a bias controller including a first transistor and a second transistor and configured to determine whether to apply the bias voltage to at least one of the first metal line and the second metal line.

13. 13. The analog-to-digital converter of claim 12, wherein the first transistor is configured to determine whether the bias voltage is applied to the first metal line and the second metal line.

14. the analog-to-digital converter is configured to support a crop mode that activates at least one of the first metal line and the second metal line; 13. The analog-to-digital converter of claim 12, wherein the first transistor is configured to determine whether the bias voltage is applied to the first metal line for the crop mode.

15. In the crop mode, a first control signal for controlling the first transistor is at a first logic level; 15. The analog to digital converter of claim 14, wherein a second control signal for controlling the second transistor is at a second logic level that is out of phase with the first logic level.

16. The analog-to-digital converter of claim 12, further comprising a first switch between the first transistor and the second transistor.

17. The analog-to-digital converter, comprising: a first metal line and a second metal line; and a second metal line configured to generate a first signal; 17. The analog to digital converter of claim 16, wherein the crop mode corresponds to an inactive state of the first transistor, an active state of the second transistor, and an open state of the first switch.

18. The analog-to-digital converter further supports a power saving mode in which the first metal line and the second metal line are deactivated; 17. The analog-to-digital converter of claim 16, wherein the power saving mode corresponds to any two of the following states: an active state of the first transistor, an active state of the second transistor, and a short-circuit state of the first switch.

19. The analog-to-digital converter supports a crop mode that activates at least one of the first metal line and the second metal line; 13. The analog-to-digital converter of claim 12, wherein in the crop mode, the bias voltage is supplied to the first metal line and the ground voltage is supplied to the second metal line.

20. An image sensor supporting a full resolution mode and a crop mode, comprising: a pixel array including a plurality of pixels configured to generate pixel signals by sensing an object; an analog-to-digital converter array including a plurality of analog-to-digital converters each configured to convert the pixel signals to digital signals; wherein the analog-to-digital converter array includes a plurality of metal lines commonly connected to a plurality of analog-to-digital converters; a bias generator configured to apply a bias voltage to the plurality of metal lines; a bias controller configured to determine a path along which the bias voltage is applied to the metal line; Here, the bias controller is a first transistor configured to activate the entirety of the plurality of metal lines based on a first control signal; a second transistor configured to determine activation of a first metal line of the plurality of metal lines for the crop mode based on a second control signal; and an output buffer configured to output the digital signal.

Images