Storage controller, operation method thereof, and non-volatile memory

Abstract

To provide a storage device including a storage controller capable of detecting command and address communication errors.SOLUTION: A storage device according to the present invention includes a non-volatile memory and a storage controller configured to control the non-volatile memory. The storage controller includes a command and address generator that generates a first command, an address, and a second command, the second command including an error detection signal for detecting a communication error in the first command and the address, an error detection module configured to generate the error detection signal from the first command and the address, and an interface circuit configured to sequentially transmit the first command, the address, and the second command to the non-volatile memory. The first command indicates the type of a memory operation to be executed in the non-volatile memory, and the second command corresponds to a confirm command.SELECTED DRAWING: Figure 2B

Description

[Technical field]

[0001] The present invention relates to a memory device, and more particularly to a storage device including a storage controller having a function for detecting communication errors in commands and addresses. [Background technology]

[0002] The storage controller uses an ECC (Error Correction Code) engine to detect errors that occur during data transmission and reception, and correct the detected errors.

[0003] However, conventional storage controllers do not have a mechanism for detecting errors that occur during the transmission of commands and addresses. As a result, even if an error occurs during the transmission of commands and addresses from the storage controller to the non-volatile memory, it is difficult to detect and correct the error. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2011-164714 ​​A Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the problems with the conventional storage controllers described above, and an object of the present invention is to provide a storage device including a storage controller that can detect communication errors in commands and addresses. [Means for solving the problem]

[0006] In order to achieve the above-mentioned object, a storage device according to the present invention comprises a non-volatile memory and a storage controller configured to control the non-volatile memory, the storage controller including a command and address generator that generates a first command, an address, and a second command, the second command including an error detection signal for detecting a communication error of the first command and the address, an error detection module configured to generate the error detection signal from the first command and the address, and an interface circuit configured to sequentially transmit the first command, the address, and the second command to the non-volatile memory, the first command indicating a type of memory operation to be performed in the non-volatile memory, and the second command corresponding to a confirm command.

[0007] In addition, a storage device according to the present invention, which has been made to achieve the above-mentioned object, comprises a non-volatile memory and a storage controller that controls the non-volatile memory, and the storage controller includes a command and address generator configured to generate a plurality of commands and a plurality of addresses, a machine learning module configured to predict whether or not a communication error will occur in the commands and addresses to be provided to the non-volatile memory based on a communication error rate of the plurality of commands and the plurality of addresses and a decision error rate related to the plurality of commands and the plurality of addresses, an error detection module configured to generate an error detection signal from the command and the address when the occurrence of the communication error is predicted, and an interface circuit configured to transmit the command, the address, and the error detection signal to the non-volatile memory when the occurrence of the communication error is predicted.

[0008] In addition, in order to achieve the above-mentioned object, a storage device according to the present invention has a non-volatile memory and a storage controller that controls the non-volatile memory, wherein the storage controller includes a command and address generator configured to generate a command and an address, an error detection module including a plurality of error detection logics including a first error detection logic and a second error detection logic, and generates an error detection signal related to the command and the address by a selected error detection logic from the plurality of error detection logics, and an interface circuit configured to transmit the command, the address, and the error detection signal to the non-volatile memory, wherein the error detection module applies the first error detection logic to perform an error detection operation related to each of the plurality of commands and addresses, and changes the selected error detection logic from the first error detection logic to the second error detection logic based on a comparison result between a communication error rate of the plurality of commands and addresses and an error rate of the first error detection logic.

[0009] The operating method of the storage controller of the storage device is a method of operating a storage controller that controls a non-volatile memory, and includes the steps of: performing learning by a machine learning module on whether or not a communication error occurs for each first command / address transmitted from the storage controller to the non-volatile memory during a first period; performing learning by the machine learning module on whether or not a communication error occurs for each second command / address transmitted from the storage controller to the non-volatile memory during a second period after the first period; determining whether or not a communication error occurs for each of the second commands / addresses during the second period and collecting determination data based on the determination result on whether or not the communication error occurs; comparing a sum of a communication error rate for the first and second commands / addresses and a determination error rate based on the determination data with a reference value when the second period ends; and predicting a communication error for the command and address by applying a machine learning determination system if the sum of the communication error rate and the determination error rate is smaller than the reference value. Effect of the Invention

[0010] According to a storage device including a storage controller of the present invention, a communication error of a command and an address is predicted, an error detection signal is generated only when a communication error is predicted, and the error detection signal is transmitted to a non-volatile memory. This has the effect that the storage controller can reduce performance degradation due to the generation and transmission of the error detection signal. [Brief description of the drawings]

[0011] [Figure 1] 1 is a block diagram showing a schematic configuration of a storage apparatus according to an embodiment of the present invention. [Figure 2A] FIG. 2 is a timing diagram illustrating communication between a storage controller and a non-volatile memory during a read operation of the non-volatile memory according to an embodiment of the present invention. [Figure 2B]FIG. 2 is a timing diagram illustrating communication between a storage controller and a non-volatile memory during a read operation of the non-volatile memory according to an embodiment of the present invention. [Diagram 3] 1 is a flowchart illustrating a method for performing a read operation between a storage controller and a non-volatile memory according to an embodiment of the present invention. [Figure 4A] FIG. 2 is a timing diagram illustrating communication between a storage controller and a non-volatile memory during a write operation of the non-volatile memory according to an embodiment of the present invention. [Figure 4B] FIG. 2 is a timing diagram illustrating communication between a storage controller and a non-volatile memory during a write operation of the non-volatile memory according to an embodiment of the present invention. [Diagram 5] 1 is a flowchart illustrating a method for performing a write operation between a storage controller and a non-volatile memory according to an embodiment of the present invention. [Figure 6] 2 is a block diagram specifically illustrating the configuration of a storage controller according to an embodiment of the present invention. FIG. [Figure 7] 1 is a block diagram specifically illustrating a configuration of a nonvolatile memory according to an embodiment of the present invention; [Figure 8] 1 is a block diagram showing a storage device according to an embodiment of the present invention; [Figure 9A] FIG. 2 is a timing diagram illustrating communication between a storage controller and a non-volatile memory during a read operation of the non-volatile memory according to an embodiment of the present invention. [Figure 9B] FIG. 2 is a timing diagram illustrating communication between a storage controller and a non-volatile memory during a read operation of the non-volatile memory according to an embodiment of the present invention. [Figure 9C] FIG. 2 is a timing diagram illustrating communication between a storage controller and a non-volatile memory during a read operation of the non-volatile memory according to an embodiment of the present invention. [Figure 10A] FIG. 2 is a timing diagram illustrating communication between a storage controller and a non-volatile memory during a write operation of the non-volatile memory according to an embodiment of the present invention. [Figure 10B]FIG. 2 is a timing diagram illustrating communication between a storage controller and a non-volatile memory during a write operation of the non-volatile memory according to an embodiment of the present invention. [Figure 10C] FIG. 2 is a timing diagram illustrating communication between a storage controller and a non-volatile memory during a write operation of the non-volatile memory according to an embodiment of the present invention. [Figure 11] 2 is a block diagram specifically illustrating the configuration of a storage controller according to an embodiment of the present invention. FIG. [Figure 12] 1 is a flowchart illustrating a method of operating a storage controller according to an embodiment of the present invention. [Figure 13] 1 is a flowchart illustrating an operation method of a storage controller and a non-volatile memory in a first section according to an embodiment of the present invention. [Figure 14] 11 is a flowchart illustrating an operation method of a storage controller and a non-volatile memory in a second section according to an embodiment of the present invention. [Figure 15] 11 is a flowchart illustrating an operation method of a storage controller and a non-volatile memory in a third section according to an embodiment of the present invention. [Figure 16A] FIG. 2 is a timing diagram illustrating communication between a storage controller and a non-volatile memory according to an embodiment of the present invention. [Figure 16B] FIG. 2 is a timing diagram illustrating communication between a storage controller and a non-volatile memory according to an embodiment of the present invention. [Figure 17] 1 is a flowchart illustrating a method of operating a storage controller according to an embodiment of the present invention. [Figure 18] 1 is a block diagram showing a schematic configuration of a storage apparatus according to an embodiment of the present invention. [Figure 19] 1 is a block diagram showing a schematic configuration of a system to which a storage device according to an embodiment of the present invention is applied. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Next, a specific example of an embodiment of a storage device according to the present invention will be described with reference to the drawings.

[0013] FIG. 1 is a block diagram showing a schematic configuration of a storage device 10 according to an embodiment of the present invention. Referring to FIG. 1, the storage device 10 includes a storage controller 100 and a non-volatile memory 200. The storage device 10 includes a recording medium for storing data upon request from a host (HOST).

[0014] As an example, the storage device 10 includes at least one of a solid state drive (SSD), an embedded memory, and a removable external memory. If the storage device 10 is an SSD, the storage device 10 may be a device conforming to the NVMe (non-volatile memory express) standard. When the storage device 10 is an embedded memory or an external memory, the storage device 10 may be a device according to the universal flash storage (UFS) or embedded multi-media card (eMMC) standard.

[0015] Depending on the embodiment, storage controller 100 may also be referred to as a controller, a device controller, or a memory controller. In one embodiment, the non-volatile memory 200 includes a flash memory, and the storage controller 100 is also referred to as a flash memory controller (FMC). Depending on the embodiment, the non-volatile memory 200 may be embodied by multiple memory chips or multiple memory dies. For example, each of the multiple memory chips may be a dual die package (DDP), a quadruple die package (QDP), or an octuple die package.

[0016] The storage controller 100 controls the non-volatile memory 200 to write data to the non-volatile memory 200 in response to a write request from the host, or controls the non-volatile memory 200 to read data stored in the non-volatile memory 200 in response to a read request from the host. According to this embodiment, the storage controller 100 includes a command and address generator 110, an error detection module 120, an interface (I / F) circuit 130, and first to fourth pins (P1a to P1d). The first to fourth pins (P1a to P1d) correspond to the first to fourth pins (P2a to P2d) of the nonvolatile memory 200, respectively.

[0017] The command and address generator 110 generates commands and addresses (CMD / ADDR) for controlling the non-volatile memory 200 . In one embodiment, the command and address (CMD / ADDR) are generated as a command set including a first command CMD1, an address ADDR, and a second command (e.g., CMD2 in FIG. 2A) that are sequentially transmitted to the non-volatile memory 200. The first command CMD1 indicates the type of memory operation, and the second command CMD2 indicates the memory operation related to the first command CMD1. According to an embodiment, the first command CMD1 is referred to as an "input command", and the second command CMD2 is referred to as a "confirm command" or a "done command".

[0018] The error detection module 120 generates an error detection signal ED for detecting a communication error in the command and address (CMD / ADDR). Depending on the embodiment, the error detection module 120 may be referred to as a "command error detection module," a "command and address error detection module," or a "command set error detection module." For example, the error detection signal ED is a 1-bit signal. However, the invention is not so limited, and the error detection signal ED may also be a multi-bit signal. Specifically, the error detection module 120 generates an error detection signal ED from the first command CMD1 and the address ADDR generated by the command and address generator 110, and provides the generated error detection signal ED to the command and address generator 110.

[0019] In one embodiment, the error detection module 120 generates a parity bit from the first command CMD1 and the address ADDR, and outputs the generated parity bit as an error detection signal ED. In one embodiment, the error detection module 120 generates a Cyclic Redundancy Check (CRC) value from the first command CMD1 and the address ADDR, and outputs the generated CRC value as an error detection signal ED. In one embodiment, the error detection module 120 may generate a checksum from the first command CMD1 and the address ADDR, and output the generated checksum as an error detection signal ED. However, the present invention is not limited thereto, and the error detection module 120 can generate the error detection signal ED from the first command CMD1 and the address ADDR using various error detection programs or error detection logics.

[0020] The interface circuit 130 transmits a plurality of data signals DQ to the non-volatile memory 200 via the first pin P1a, or receives a plurality of data signals DQ from the non-volatile memory 200. A command CMD, an address ADDR, and data DATA are transmitted via a plurality of data signals DQ. For example, a plurality of data signals DQ are transmitted via a plurality of data signal lines, respectively. The following description will focus on an embodiment in which the number of first pins P1a is eight. However, the present invention is not limited thereto, and the number of first pins P1a may be variously changed according to the embodiment.

[0021] The interface circuit 130 receives a ready / busy output signal (nR / B) indicating status information of the nonvolatile memory 200 from the nonvolatile memory 200 via the second pin P1b. The interface circuit 130 also provides a command latch enable signal CLE and an address latch enable signal ALE to the non-volatile memory 200 via a third pin P1c and a fourth pin P1d, respectively. The interface circuit 130 transmits a data signal DQ including a command CMD to the non-volatile memory 200 by transmitting a command latch enable signal CLE having an enable state, and transmits a data signal DQ including an address ADDR to the non-volatile memory 200 by transmitting an address latch enable signal ALE having an enable state.

[0022] The non-volatile memory 200 includes a memory cell array 210 , a control logic circuit 220 , and an interface circuit 230 . The interface circuit 230 receives a plurality of data signals DQ from the storage controller 100 via the first pin P2a, or transmits a plurality of data signals DQ to the storage controller 100. The interface circuit 230 also receives a command latch enable signal CLE and an address latch enable signal ALE from the storage controller 100 via a third pin P2c and a fourth pin P2d, respectively. The interface circuit 230 transmits a ready / busy output signal (nR / B) to the storage controller 100 via the second pin P2b. When the non-volatile memory 200 is busy (ie, when an internal operation of the non-volatile memory 200 is being performed), the interface circuit 230 transmits a ready / busy output signal (nR / B) to the storage controller 100 indicating the busy state.

[0023] When the non-volatile memory 200 is in a ready state (i.e., no internal operations of the non-volatile memory 200 are being performed or have been completed), the interface circuit 230 transmits a ready / busy output signal (nR / B) to the storage controller 100 indicating the ready state. For example, while the non-volatile memory 200 reads data DATA from the memory cell array 210 in response to a read command, the interface circuit 230 transmits a ready / busy output signal (nR / B) indicating a busy state (e.g., a low level) to the storage controller 100. For example, while the non-volatile memory 200 is programming data DATA in the memory cell array 210 in response to a program command, the interface circuit 230 transmits a ready / busy output signal (nR / B) indicating a busy state to the storage controller 100.

[0024] The memory cell array 210 includes a plurality of memory cells. For example, the memory cells may be flash memory cells. However, the present invention is not limited thereto, and the memory cells may be Resistive Random Access Memory (RRAM) cells, Ferroelectric Random Access Memory (FRAM®) cells, Phase Change Random Access Memory (PRAM) cells, Thyristor Random Access Memory (TRAM) cells, or Magnetic Random Access Memory (MRAM) cells. Hereinafter, examples of the present invention will be described, focusing on an embodiment in which the memory cells are NAND flash memory cells.

[0025] The control logic circuit 220 generally controls various operations of the non-volatile memory 200 . The control logic circuit 220 determines the data signal DQ received through the first pin P2a during the enable period of the command latch enable signal CLE as a command CMD, and determines the data signal DQ received through the first pin P2a during the enable period of the address latch enable signal ALE as an address ADDR. The control logic circuit 220 generates control signals for controlling other components of the non-volatile memory 200 according to commands and addresses (CMD / ADDR). For example, the control logic circuit 220 generates various control signals for programming data DATA in the memory cell array 210 or for reading data DATA from the memory cell array 210 .

[0026] In one embodiment, the control logic circuit 220 determines whether a communication error occurs in the command and address (CMD / ADDR) based on the error detection signal ED included in the command and address (CMD / ADDR). If the determination result indicates that a communication error has occurred in the command and address (CMD / ADDR), the nonvolatile memory 200 transmits an error message (eg, symbol E in FIG. 2B) to the storage controller 100. For example, the error message E is transmitted to the storage controller 100 via the first pin P2a.

[0027] On the other hand, if a communication error does not occur in the command and address (CMD / ADDR), the nonvolatile memory 200 executes a memory operation based on the command and address (CMD / ADDR). For example, if the command (CDM / ADDR) includes a read command, data DATA may be read from the memory cell array 210, which will be described in more detail with reference to FIGS. 2A, 2B, and 3. FIG. For example, if the command (CDM / ADDR) includes a write command, data DATA may be written to the memory cell array 210, which will be described in more detail with reference to FIGS. 4A, 4B, and 5. FIG.

[0028] 2A and 2B are timing diagrams illustrating communication between the storage controller 100 and the non-volatile memory 200 during a read operation of the non-volatile memory 200 according to one embodiment of the present invention. 1 and 2A, the storage controller 100 sequentially transmits a first command 211, an address 212, and a second command 213 to the non-volatile memory 200 via a plurality of data signal lines. The first command 211 includes an input command (for example, 00h) indicating that the type of memory operation is a read operation, and the address 212 includes first and second column addresses (C1, C2) and first to third row addresses (R1, R2, R3). The second command 213 is also a confirm command that indicates the read page size. For example, if the read page size is 4KB, the second command 213 includes a 4KB read command 50h. For example, if the read page size is 8KB, the second command 213 includes an 8KB read command 20h. For example, if the read page size is 16 KB, the second command 213 includes a 16 KB read command 30h.

[0029] In one embodiment, the error detection module 120 generates an error detection signal ED from the first command 211 and the address 212, and the command and address generator 110 generates the second command 213 such that a reserved bit of the second command 213 includes the error detection signal ED. For example, the error detection signal ED is included in the most significant bit (MSB) of the second command 213, but the present invention is not limited to this. The non-volatile memory 200 determines whether or not a communication error has occurred in the first command 211 and the address 212 based on the error detection signal ED. If it is determined that no communication error has occurred in the first command 211 and the address 212, the non-volatile memory 200 executes a read operation and transmits the read data (R-DATA) to the storage controller 100.

[0030] Specifically, the first time t WB Thereafter, the non-volatile memory 200 performs a read operation for a period of time t R During this time, a read operation is performed. Read operation time t R From the end of the second time t RR Thereafter, the non-volatile memory 200 transmits read data (R-DATA) to the storage controller 100 via the multiple data signal lines. For example, at the first time t WB corresponds to the enable section of the write enable signal, and the second time t RR corresponds to the enable section of the read enable signal.

[0031] 1 and 2B, the nonvolatile memory 200 determines whether or not a communication error has occurred in the first command 211 and the address 212 based on the error detection signal ED. If the determination result indicates that a communication error has occurred in the first command 211 and the address 212, the nonvolatile memory 200 generates an error message E and transmits the error message E to the storage controller 100 via a plurality of data signal lines. In response to the error message E, the storage controller 100 sequentially transmits a first command 214, an address 215, and a second command 216 to the non-volatile memory 200 via a plurality of data signal lines. For example, first command 214, address 215, and second command 216 may be substantially identical to previously transmitted first command 211, address 212, and second command 213, although the invention is not so limited.

[0032] FIG. 3 is a flowchart illustrating a read operation method between the storage controller 100 and the non-volatile memory 200 according to an embodiment of the present invention. 1 to 3, in step S100, the storage controller 100 generates a read command and an address. For example, the read command corresponds to the first command 211 in FIGS. 2A and 2B, and the address corresponds to the address 212 in FIGS. 2A and 2B. In step S110, the storage controller 100 generates an error detection signal ED from the read command and the address. In step S120, the storage controller 100 generates a confirm command including the error detection signal ED. For example, the confirm command corresponds to the second command 213 in Figures 2A and 2B.

[0033] In step S130, the storage controller 100 transmits a command and address (CMD / ADDR) to the non-volatile memory 200 via a plurality of data signal lines. For example, the command and address (CMD / ADDR) includes a read command, an address, and a confirm command, and the read command, the address, and the confirm command are sequentially transmitted to the non-volatile memory 200 via a number of data signal lines. In step S140, the non-volatile memory 200 detects a command and address (CMD / ADDR) communication error based on the error detection signal ED. Here, the command and address (CMD / ADDR) error is a communication error that occurs during the transmission of the command and address (CMD / ADDR). For example, the control logic circuit 220 detects a communication error in the command and address (CMD / ADDR) through a logic operation on the error detection signal ED.

[0034] In step S150, the non-volatile memory 200 determines whether a communication error occurs in the command and address (CMD / ADDR). If it is determined that a communication error has occurred in the command and address (CMD / ADDR), the non-volatile memory 200 transmits an error message E to the storage controller 100 in step S160. For example, an error message E is transmitted to the storage controller 100 via multiple data signal lines.

[0035] In step S170, the storage controller 100 again transmits a command and address (CMD / ADDR) to the non-volatile memory 200 via a plurality of data signal lines. For example, the command and address (CMD / ADDR) includes a read command, an address, and a confirm command, and the read command, the address, and the confirm command are sequentially transmitted to the non-volatile memory 200 via a number of data signal lines. For example, the read command, address, and confirm command correspond to first command 214, address 215, and second command 216, respectively, in FIG. 2B.

[0036] In step S180, the non-volatile memory 200 executes a read operation according to a command and address (CMD / ADDR). Specifically, the control logic circuit 220 determines the read operation time t R During this period, data stored in the memory cell array 210 is read according to a command and address (CMD / ADDR). In step S190, the non-volatile memory 200 transmits the read data R-DATA to the storage controller 100 via a plurality of data signal lines.

[0037] 4A and 4B are timing diagrams illustrating communication between the storage controller 100 and the non-volatile memory 200 during a write operation of the non-volatile memory 200 according to one embodiment of the present invention. 1 and 4A, the storage controller 100 sequentially transmits a first command 411, an address 412, write data (W-DATA), and a second command 413 to the non-volatile memory 200 via a plurality of data signal lines. The first command 411 includes an input command (for example, 80h) indicating that the type of memory operation is a write operation, and the address 412 includes first and second column addresses (C1, C2) and first to third row addresses (R1, R2, R3). The second command 413 is also a confirm command (eg, 10h) that instructs a write operation.

[0038] In one embodiment, the error detection module 120 generates an error detection signal ED from the first command 411 and the address 412, and the command and address generator 110 generates the second command 413 such that a reserved bit of the second command 413 includes the error detection signal ED. For example, the error detection signal ED is included in the MSB of the second command 413, but the present invention is not limited thereto. The nonvolatile memory 200 determines whether or not a communication error has occurred in the first command 411 and the address 412 based on the error detection signal ED. If it is determined that no communication error has occurred in the first command 411 and the address 412, the nonvolatile memory 200 executes the write operation. Specifically, the first time t WB Thereafter, the non-volatile memory 200 is programmed for a program operation time t PROG During this time, a write operation is performed. For example, at the first time t WB corresponds to the enable section of the write enable signal. Program operation time t PROG After the completion of the write operation, the non-volatile memory 200 transmits a response message to the storage controller 100 via a number of data signal lines, indicating that the write operation is complete.

[0039] 1 and 4B, the nonvolatile memory 200 determines whether a communication error has occurred in the first command 411 and the address 412 based on the error detection signal ED. If the determination result indicates that a communication error has occurred in the first command 411 and the address 412, the nonvolatile memory 200 generates an error message E and transmits the error message E to the storage controller 100 via a plurality of data signal lines. In response to the error message E, the storage controller 100 sequentially transmits a first command 414, an address 415, write data (W-DATA), and a second command 416 to the non-volatile memory 200 via a plurality of data signal lines. For example, the first command 414, address 415, write data (W-DATA), and second command 416 are substantially identical to the previously transmitted first command 411, address 412, write data (W-DATA), and second command 413, although the present invention is not limited thereto. In one embodiment, in response to the error message E, the storage controller 100 sequentially transmits the first command 414, the address 415, and the second command 416 to the non-volatile memory 200 via multiple data signal lines, without transmitting write data (W-DATA).

[0040] FIG. 5 is a flowchart illustrating a write operation method between the storage controller 100 and the non-volatile memory 200 according to an embodiment of the present invention. 1, 4A, 4B, and 5, in step S200, the storage controller 100 generates a write command and address. For example, the write command corresponds to the first command 411 in FIGS. 4A and 4B, and the address corresponds to the address 412 in FIGS. 4A and 4B. In step S210, the storage controller 100 generates an error detection signal ED from the write command and the address.

[0041] In step S220, the storage controller 100 generates a confirm command including the error detection signal ED. For example, the Confirm command corresponds to the second command 413 in Figures 4A and 4B. In step S230, the storage controller 100 transmits a command and address (CMD / ADDR) and write data (W-DATA) to the non-volatile memory 200 via a plurality of data signal lines. For example, the command and address (CMD / ADDR) includes a write command, an address, and a confirm command, and the write command, the address, the write data (W-DATA), and the confirm command are sequentially transmitted to the non-volatile memory 200 via a plurality of data signal lines.

[0042] In step S240, the non-volatile memory 200 detects an error in the command and address (CMD / ADDR) based on the error detection signal ED. For example, a command and address (CMD / ADDR) error is a communication error that occurs during the transmission of a command and address (CMD / ADDR). For example, the control logic circuit 220 detects a communication error in the command and address (CMD / ADDR) through a logic operation on the error detection signal ED. In step S250, the non-volatile memory 200 determines whether a communication error occurs in the command and address (CMD / ADDR). If it is determined that a communication error has occurred in the command and address (CMD / ADDR), the non-volatile memory 200 transmits an error message E to the storage controller 100 in step S260. For example, an error message E is transmitted to the storage controller 100 via multiple data signal lines.

[0043] In step S270, the storage controller 100 again transmits the command and address (CMD / ADDR) to the non-volatile memory 200 via a plurality of data signal lines. For example, the command and address (CMD / ADDR) includes a write command, an address, and a confirm command, and the write command, the address, and the confirm command are sequentially transmitted to the non-volatile memory 200 via a plurality of data signal lines. For example, the write command, address, and confirm command correspond to the first command 414, address 415, and second command 416, respectively, of FIG. 4B. In step S280, the non-volatile memory 200 executes a write operation according to a command and address (CMD / ADDR). Specifically, the control logic circuit 220 performs a program operation time t PROG During this period, data is written to the memory cell array 210 by a command and an address (CMD / ADDR). In step S290, the non-volatile memory 200 transmits a response message indicating the completion of the write operation to the storage controller 100 via a plurality of data signal lines.

[0044] FIG. 6 is a block diagram specifically showing the configuration of the storage controller 100 according to an embodiment of the present invention. Referring to both Figures 1 and 6, the storage controller 100 includes a command and address generator 110, an error detection module 120, a processor 140, an ECC (Error Correction Code) engine 150, a host interface 160, and a non-volatile memory interface 170, which communicate via a bus 180. The processor 140 includes a CPU (Central Processing Unit) or a microprocessor, and controls the overall operation of the storage controller 100 . In one embodiment, the processor 140 may be implemented as a multi-core processor, for example a dual-core processor or a quad-core processor.

[0045] In one embodiment, the command and address generator 110 and the error detection module 120 may be implemented in software. For example, the non-volatile memory 200 stores program code for generating commands and addresses, and when power is applied to the storage device 10, the program code stored in the non-volatile memory 200 is loaded into the operating memory of the storage controller 100. The processor 140 executes program code loaded into the operating memory to generate an error detection signal ED, a command and an address (CMD / ADDR) as shown in FIGS. However, the present invention is not so limited, and in one embodiment, the command and address generator 110 and the error detection module 120 may be embodied in hardware. Additionally, in one embodiment, the command and address generator 110 and the error detection module 120 may be implemented by a combination of software and hardware.

[0046] Although the command and address generator 110 and the error detection module 120 are illustrated in FIG. 6 as separate functional blocks from the non-volatile memory interface 170, the present invention is not so limited. In one embodiment, at least one of the command and address generator 110 and the error detection module 120 may be embodied as included in the non-volatile memory interface 170 .

[0047] The host interface 160 transmits and receives packets to and from the host. Packets transmitted from the host to the host interface 160 include commands or data to be recorded in the non-volatile memory 200, and packets transmitted from the host interface 160 to the host include responses to commands or data read from the non-volatile memory 200. The non-volatile memory interface 170 transmits data to be recorded in the non-volatile memory 200, i.e., write data (e.g., (W-DATA) in Figures 4A and 4B) to the non-volatile memory 200, or receives data read from the non-volatile memory 200, i.e., read data (e.g., (R-DATA) in Figures 2A and 2B). Such a non-volatile memory interface 170 may be implemented to comply with a standard protocol such as Toggle or ONFI (Open NAND Flash Interface).

[0048] The ECC engine 150 performs error detection and correction functions associated with read data read from the non-volatile memory 200 . More specifically, the ECC engine 150 generates parity bits for write data to be written to the non-volatile memory 200, and the parity bits thus generated are stored in the non-volatile memory 200 together with the write data. When reading data from the non-volatile memory 200, the ECC engine 150 corrects errors in the read data using the parity bits read from the non-volatile memory 200 along with the read data, and outputs the error-corrected read data. Thus, ECC engine 150 performs data-related error detection and correction functions, while error detection module 120 performs command and address-related error detection functions. According to one embodiment, error detection module 120 may also perform command and address related error detection and correction functions.

[0049] Although not shown in the figure, the storage controller 100 may further include a Flash Translation Layer (FTL), a packet manager, a buffer memory, and an advanced encryption standard (AES) engine. The storage controller 100 further includes a working memory into which a flash translation layer is loaded, and the processor 140 executes the flash translation layer to control data write and read operations to the non-volatile memory 200 .

[0050] FIG. 7 is a block diagram specifically showing the configuration of a non-volatile memory 200 according to an embodiment of the present invention. 1 and 7, the non-volatile memory 200 includes a memory cell array 210, a control logic circuit 220, an interface circuit 230, a page buffer circuit 240, a voltage generator 250, and a row decoder 260. The interface circuit 230 receives a number of data signals DQ, a command latch enable signal CLE, and an address latch enable signal ALE from the storage controller 100, and transmits a ready / busy output signal (nR / B) to the storage controller 100. For example, the interface circuit 230 may include multiple drivers and multiple receivers.

[0051] The interface circuit 230 determines that the multiple data signals DQ include a command CMD, an address ADDR, or data DATA based on the command latch enable signal CLE and the address latch enable signal ALE. When the multiple data signals DQ include a command CMD or an address ADDR, the interface circuit 230 provides the command CMD or the address ADDR to the control logic circuit 220 . When the multiple data signals DQ include data DATA, the interface circuit 230 provides the data DATA to the page buffer circuit 240 .

[0052] The control logic circuit 220 generally controls various operations within the non-volatile memory 200 . The control logic circuit 220 outputs various control signals in response to a command CMD and / or an address ADDR from the interface circuit 230 . For example, the control logic circuit 220 outputs a voltage control signal (CTRL_vol), a row address (X-ADDR), and a column address (Y-ADDR). The control logic circuit 220 includes an error detection module 221, which detects a communication error in the command CMD and the address ADDR. Specifically, the error detection module 221 detects a communication error in the command CMD and the address ADDR by executing a logic operation on the error detection signal ED included in the command CMD. If a communication error is detected, the control logic circuit 220 generates an error message and provides the generated error message to the interface circuit 230 .

[0053] The interface circuit 230 provides a number of data signals DQ, including an error message, to the storage controller 100 . On the other hand, the control logic circuit 220 controls the page buffer circuit 240, the voltage generator 250, and the row decoder 260 so that no communication error is detected and a memory operation is performed according to the command CMD and the address ADDR. The memory cell array 210 is connected to a page buffer circuit 240 via bit lines BL, and is connected to a row decoder 260 via word lines WL, string select lines SSL, and ground select lines GSL. In an exemplary embodiment, memory cell array 210 includes a three-dimensional memory cell array, which includes a plurality of NAND strings. Each NAND string includes memory cells connected to respective word lines stacked vertically on a substrate.

[0054] The following specifications are incorporated herein by reference: U.S. Patent No. 7,679,133, U.S. Patent No. 8,553,466, U.S. Patent No. 8,654,587, U.S. Patent No. 8,559,235, and U.S. Patent Application Publication No. 2011 / 0233648.

[0055] In an exemplary embodiment, memory cell array 210 includes a two-dimensional memory cell array that includes a number of NAND strings arranged along rows and columns. The page buffer circuit 240 selects at least one of the bit lines BL in response to a column address (Y_ADDR). The page buffer circuit 240 acts as either a write driver or a sense amplifier depending on the mode of operation. For example, during a program operation, the page buffer circuit 240 applies a bit line voltage corresponding to the data to be programmed to a selected bit line. During a read operation, the page buffer circuit 240 senses the current or voltage of a selected bit line to sense the data stored in the memory cell.

[0056] The voltage generator 250 generates various kinds of voltages for performing program, read, and erase operations according to a voltage control signal (CTRL_vol). For example, the voltage generator 250 generates a program voltage, a read voltage, a program verify voltage, an erase voltage, etc. as the word line voltage VWL. The row decoder 260 selects one of a plurality of word lines WL in response to a row address (X_ADDR), and selects one of a plurality of string selection lines SSL. For example, during a program operation, the row decoder 260 applies a program voltage and a program verify voltage to a selected word line, and during a read operation, the row decoder 260 applies a read voltage to a selected word line.

[0057] FIG. 8 is a block diagram showing a schematic configuration of a storage device 10a according to an embodiment of the present invention. Referring to FIG. 8, the storage device 10a includes a storage controller 100a and a non-volatile memory 200a. The storage device 10a corresponds to a modified example of the storage device 10 in FIG. 1, and the contents described in detail with reference to FIGS. 1 to 7 also apply to this embodiment, so that repeated description will be omitted.

[0058] The command and address generator 110a generates commands and addresses (CMD / ADDR) for controlling the non-volatile memory 200a. In one embodiment, the command and address (CMD / ADDR) are generated as a command set including a first command CMD1, an address ADDR, and a second command (eg, CMD2 in FIG. 2A) that are sequentially transmitted to the non-volatile memory 200a. A CRC (cyclic redundancy check) module 125 generates a CRC value (CRC-x) by performing a CRC on the first command CMD1 and the address ADDR.

[0059] Specifically, when transmitting commands and addresses (CMD / ADDR) via multiple data signal lines, the CRC module 125 calculates a check value, i.e., a CRC value (CRC-x), to check whether there are errors in the transmitted commands and addresses (CMD / ADDR). The generated CRC value (CRC-x) is transmitted to the non-volatile memory 200a via the first pin P1a. where x is a positive integer determined by the size of the CRC value to be generated. For example, if the CRC module 125 implements (CRC-16) logic, then x is 16 and a CRC value (CRC-16) is generated for a 16-bit signal. For example, if the CRC module 125 implements (CRC-8) logic, then x is 8 and a CRC value (CRC-8) is generated for an 8-bit signal.

[0060] The CRC module 125 calculates a CRC value (CRC-x) according to the command and address (CMD / ADDR) before transmitting the command and address (CMD / ADDR), and transmits the CRC value (CRC-x) together with the command and address (CMD / ADDR) to the non-volatile memory 200a. In one embodiment, the CRC module 125 calculates a CRC value (CRC-x) for the received command and address (CMD / ADDR) after completing transmission of the command and address (CMD / ADDR), and if the two CRC values ​​are different from each other, it can be determined that an error was added due to noise, etc. during the command and address (CMD / ADDR) transmission process.

[0061] In one embodiment, when the CRC module 125 receives an error message E from the non-volatile memory 200a, it can determine that an error has been added due to noise, etc. during the command and address (CMD / ADDR) transmission process. The machine learning module 190 predicts the occurrence of command and address (CMD / ADDR) communication errors according to a reliability probability value. Specifically, the machine learning module 190 calculates the actual error rate of the command and address (CMD / ADDR), i.e., the communication error rate E S and the decision error rate M determined by machine learning E The sum of these is the reference value B C Based on the comparison result, a machine learning decision system is applied when transmitting the command and address (CMD / ADDR).

[0062] If a communication error of the command and address (CMD / ADDR) is predicted to occur, the machine learning module 190 enables the CRC module 125, which causes the CRC module 125 to calculate a CRC value (CRC-x) from the first command CMD1 and the address ADDR, and the storage controller 100a transmits the CRC value (CRC-x) together with the command and address (CMD / ADDR) to the non-volatile memory 200a. On the other hand, if it is predicted that no communication error has occurred in the command and address (CMD / ADDR), the machine learning module 190 disables the CRC module 125, so that the storage controller 100a transmits only the command and address (CMD / ADDR) to the non-volatile memory 200a and does not transmit the CRC value (CRC-x) to the non-volatile memory 200a.

[0063] Thus, according to this embodiment, the storage controller 100a uses the machine learning module 190 to predict communication errors in commands and addresses, and generates an error detection signal (e.g., a CRC value) only when a communication error is predicted, and transmits the error detection signal (CRC value) to the non-volatile memory 200a. This allows the storage controller 100a to reduce performance degradation caused by the generation and transmission of error detection signals.

[0064] 9A-9C are timing diagrams illustrating communication between the storage controller 100a and the non-volatile memory 200a during a read operation of the non-volatile memory 200a according to one embodiment of the present invention. The communication between the storage controller 100a and the non-volatile memory 200a in this embodiment corresponds to a modified example of the communication between the storage controller 100 and the non-volatile memory 200 illustrated in Figures 2A and 2B, and the contents described in detail with reference to Figures 2A and 2B also apply to this embodiment.

[0065] 8 and 9A, the machine learning module 190 predicts that no command and address (CMD / ADDR) communication errors will occur. At this time, the machine learning module 190 disables the CRC module 125, so that the CRC module 125 does not calculate the CRC value. The storage controller 100a sequentially transmits a first command 911, an address 912, and a second command 914 to the non-volatile memory 200a via a plurality of data signal lines. For example, first command 911 and address 912 correspond to first command 211 and address 212, respectively, of FIG. 2A. For example, the second command 914 may also be a confirm command indicating the read page size and may not include an error detection signal. For example, the second command 914 includes 50h, 20h, or 30h. The non-volatile memory 200a performs the read operation and transmits the read data (R-DATA) to the storage controller 100a.

[0066] 8 and 9B together, the machine learning module 190 predicts that a command and address (CMD / ADDR) communication error will occur. At this time, the machine learning module 190 enables the CRC module 125, thereby causing the CRC module 125 to calculate a CRC value 913 from the first command 911 and the address 912, and the storage controller 100a sequentially transmits the first command 911, the address 912, the CRC value 913 and the second command 914 to the non-volatile memory 200a via multiple data signal lines.

[0067] The CRC value 913 corresponds to the CRC value (CRC-x) generated by the CRC module 125 . For example, CRC module 125 applies (CRC-16) error detection logic to perform a CRC on first command 911 and address 912 to calculate (CRC-16)(1) and (CRC-16)(2), where (CRC-16)(1) and (CRC-16)(2) are each provided as 8 bits. The non-volatile memory 200 a determines whether or not a communication error has occurred in the first command 911 and the address 912 based on the CRC value 913 . If it is determined that no communication error has occurred in the first command 911 and the address 912, the non-volatile memory 200a executes a read operation and transmits the read data (R-DATA) to the storage controller 100a.

[0068] 8 and 9C, the non-volatile memory 200a determines whether a communication error has occurred in the first command 911 and the address 912 based on the CRC value 913. If it is determined that a communication error has occurred in the first command 911 and the address 912, an error message E is generated and transmitted to the storage controller 100a via a plurality of data signal lines. In response to the error message E, the storage controller 100a sequentially transmits a first command 915, an address 916, a CRC value 917, and a second command 918 to the non-volatile memory 200a via a plurality of data signal lines. For example, first command 915, address 916, CRC value 917, and second command 918 are substantially identical to previously transmitted first command 911, address 912, CRC value 913, and second command 914, although the present invention is not limited thereto.

[0069] 10A-10C are timing diagrams illustrating communication between the storage controller 100a and the non-volatile memory 200a during a write operation of the non-volatile memory 200a according to one embodiment of the present invention. The communication between the storage controller 100a and the non-volatile memory 200a in this embodiment corresponds to a modified example of the communication between the storage controller 100 and the non-volatile memory 200 illustrated in Figures 4A and 4B, and the contents described in detail with reference to Figures 4A and 4B also apply to this embodiment.

[0070] 8 and 10A, the machine learning module 190 predicts that no command and address (CMD / ADDR) communication errors will occur. At this time, the machine learning module 190 disables the CRC module 125, so that the CRC module 125 does not calculate the CRC value. The storage controller 100a sequentially transmits a first command 1011, an address 1012, write data (W-DATA), and a second command 1014 to the non-volatile memory 200a via a plurality of data signal lines.

[0071] For example, a first command 1011 and an address 1012 correspond to the first command 411 and the address 412, respectively, of FIG. 4A. For example, the second command 1014 is a confirm command (eg, reference numeral 10h in FIG. 8) instructing a write operation, and does not need to include an error detection signal. The non-volatile memory 200a executes a write operation of the write data (W-DATA), and when the write operation is completed, transmits a response message indicating that the write operation is completed to the storage controller 100a via a plurality of data signal lines.

[0072] 8 and 10B together, the machine learning module 190 predicts that a command and address (CMD / ADDR) communication error will occur. At this time, the machine learning module 190 enables the CRC module 125, so that the CRC module 125 calculates the CRC value 1013 from the first command 1011 and the address 1012, and the storage controller 100a sequentially transmits the first command 1011, the address 1012, the CRC value 1013, write data (W-DATA), and the second command 1014 to the non-volatile memory 200a via multiple data signal lines.

[0073] The CRC value 1013 corresponds to the CRC value (CRC-x) generated by the CRC module 125 . For example, CRC module 125 applies CRC-16 error detection logic to perform a CRC on first command 1011 and address 1012 to calculate (CRC-16)(1) and (CRC-16)(2), where (CRC-16)(1) and (CRC-16)(2) are each provided as 8 bits. The non-volatile memory 200 a determines whether or not a communication error has occurred in the first command 1011 and the address 1012 based on the CRC value 1013 . If the determination result indicates that no communication error has occurred in the first command 1011 and the address 1012, the nonvolatile memory 200a executes the write operation of the write data (W-DATA).

[0074] 8 and 10C, the non-volatile memory 200a determines whether a communication error has occurred in the first command 1011 and the address 1012 based on the CRC value 1013. If it is determined that a communication error has occurred in the first command 1011 and the address 1012, an error message E is generated and transmitted to the storage controller 100a via a plurality of data signal lines. In response to the error message E, the storage controller 100a sequentially transmits a first command 1015, an address 1016, a CRC value 1017, and a second command 1018 to the non-volatile memory 200a via a plurality of data signal lines. For example, first command 1015, address 1016, CRC value 1017, and second command 1018 are substantially identical to previously transmitted first command 1011, address 1012, CRC value 1013, and second command 1014, although the present invention is not limited thereto.

[0075] FIG. 11 is a block diagram specifically showing the configuration of a storage controller 100a according to an embodiment of the present invention. Referring to both Figures 8 and 11, the storage controller 100a includes a command and address generator 110, a CRC module 125, a processor 140, an ECC engine 150, a host interface 160, a non-volatile memory interface 170, and a machine learning module 190, which communicate via a bus 180. The storage controller 100a corresponds to a modified example of the storage controller 100 in FIG. 6, and the details described with reference to FIG. 6 also apply to this embodiment.

[0076] In one embodiment, the CRC module 125 is implemented in software. For example, the non-volatile memory 200a stores program code for performing CRC, and when power is applied to the storage device 10a, the program code stored in the non-volatile memory 200 is loaded into the operating memory of the storage controller 100a. The processor 140a executes the program code loaded into the operating memory, and performs a CRC on the command and address (CMD / ADDR) to generate a CRC value (CRC-x). However, the present invention is not so limited, and in one embodiment, the CRC module 125 may also be embodied in hardware. In one embodiment, the CRC module 125 may also be implemented by a combination of software and hardware.

[0077] In one embodiment, the machine learning module 190 is implemented in software. For example, the non-volatile memory 200a stores program code for executing machine learning, and when power is applied to the storage device 10a, the program code stored in the non-volatile memory 200 is loaded into the operating memory of the storage controller 100a. The processor 140a executes program codes loaded in the operating memory to predict communication errors that may occur during transmission of commands and addresses (CMD / ADDR), and enables the CRC module 125 according to the prediction results. However, the present invention is not so limited, and in one embodiment, the machine learning module 190 may also be embodied in hardware. In one embodiment, the machine learning module 190 may also be embodied by a combination of software and hardware.

[0078] FIG. 12 is a flowchart illustrating a method of operating the storage controller 100a according to an embodiment of the present invention. Referring to FIG. 12, in step S310, the machine learning module 190 of the storage controller 100a performs learning. Step S310 begins when the command and address generator 110 of the storage controller 100a issues a command and an address. Specifically, the machine learning module 190 executes learning as to whether or not a communication error occurs for a command and an address transmitted from the storage controller 100a to the non-volatile memory 200a.

[0079] In step S320, it is determined whether the number of times n that the command and address have been processed is greater than a first reference value N1. As a result of the determination, if the processing count n is greater than the first reference value N1, execute step S330; otherwise, the machine learning module 190 continues to perform learning. For example, the first reference value N1 may be 1,000,000 times, but the present invention is not limited thereto. The machine learning module 190 performs learning during a first period, for example, from the time point when the first command and address is transmitted to the time point when the 1,000,000th command and address is transmitted. As a result, the machine learning module 190 calculates the communication error occurrence rates, that is, statistical values, of the 1st to 1,000,000th commands and addresses. A detailed description relating to steps S310 and S320 will be provided below with reference to FIG.

[0080] In step S330, the machine learning module 190 collects judgment data based on machine learning by predicting whether a command and address (CMD / ADDR) communication error occurs. At this time, the machine learning module 190 continues to learn about the commands and addresses transmitted from the storage controller 100a to the non-volatile memory 200a, and whether or not a communication error occurs with respect to the commands and addresses.

[0081] In step S340, it is determined whether the number of times n that the command and address have been processed is greater than a second reference value N2. If it is determined that the processing count n is greater than the second reference value N2, execute step S350; otherwise, the machine learning module 190 continues learning. For example, the second reference value N2 may be 2,000,000 times, but the present invention is not limited thereto. The machine learning module 190 collects judgment data through machine learning by predicting whether or not a communication error will occur during the second period, for example, from the 1,000,001st command and address transmitted at the 1,000,001st time to the 2,000,000th command and address transmitted at the 2,000,000th time. As a result, the machine learning module 190 calculates the machine learning decision error rate or the decision error rate M E Calculate. For example, the judgment error rate M E can be 0.000007.

[0082] Furthermore, the machine learning module 190 continuously collects determination data by machine learning by predicting whether or not a communication error will occur for each of the 1,000,001st command and address to the 2,000,000th command and address during the second period. As a result, the machine learning module 190 calculates the communication error occurrence rate E S Calculate. In this case, the communication error rate E S corresponds to the statistical value where a communication error actually occurred. For example, the communication error rate E S can be 0.000007. A detailed description relating to steps S330 and S340 will be provided below with reference to FIG.

[0083] In step S350, the communication error occurrence rate E S and the judgment error rate M E The sum of these is the reference value B C It is determined whether it is smaller than or not. Here, the reference value B C is a reference value for applying the machine learning judgment system, which may be, for example, 0.0015%, i.e., 0.000015. As a result of the judgment, the communication error occurrence rate E S and the judgment error rate M E The sum of these is the reference value B C If so, execute step S370; otherwise, continue with step S330. In step S360, the storage controller 100a applies the judgment system of the machine learning module 190 to predict whether a command and address communication error has occurred.

[0084] For example, the communication error rate E S is 0.000007, and the decision error rate M E is 0.000007, and the reference value B C When is 0.000015, the communication error rate E S and the judgment error rate M E The sum of these, 0.1000014, is the reference value B C is smaller than 0.000015. This allows the storage controller 100a to apply the judgment system of the machine learning module 190 to predict the occurrence of a communication error for commands and addresses issued thereafter.

[0085] At step S370, the communication error occurrence rate ME determined by machine learning S is the standard value B C It is determined whether it is smaller than or not. Here, the communication error rate ME S applies a machine learning judgment system to perform communication error prediction for commands and addresses, and transmits a CRC value along with the command and address only when a communication error is predicted, which corresponds to a statistical value where an error actually occurred. As a result of the judgment, the communication error occurrence rate ME S is the standard value B C If so, continue with step S360; otherwise, execute step S330.

[0086] For example, communication error rate ME Sis 0.000016, and when the reference value BC is 0.000015, the communication error occurrence rate ME S 0.000016 is the reference value B C is greater than 0.000015. This causes the machine learning module 190 to continue with the step of collecting decision data in step S330. On the other hand, the communication error rate ME S is the standard value B C If , the decision system of the machine learning module 190 is deemed suitable. Thus, in step S360, the storage controller 100a continues to apply the judgment system of the machine learning module 190 to predict whether a command and address communication error has occurred. A detailed description relating to steps S360 and S370 will be provided below with reference to FIG.

[0087] FIG. 13 is a flowchart illustrating a method of operating the storage controller 100a and the non-volatile memory 200a in the first section according to an embodiment of the present invention. Referring to both Figures 9 and 13, the first section corresponds to the section from the time when a command and address (CMD / ADDR) is issued in the storage controller 100a to the time when the number of times n the command and address (CMD / ADDR) is processed reaches a first reference value N1. For example, the first reference value N1 may be 1,000,000 times.

[0088] In step S400, the storage controller 100a generates a command and an address. In step S410, the storage controller 100a generates a CRC value from the generated command and address. For example, as illustrated in FIG. 9C, the storage controller 100a generates a CRC value 913 from a first command 911 instructing a read operation and an address 912. For example, as illustrated in FIG. 10C, the storage controller 100a generates a CRC value 1013 from a first command 1011 instructing a write operation and an address 1012.

[0089] In step S420, the storage controller 100a transmits a command and address (CMD / ADDR) and a CRC value (eg, reference numbers 911 to 914 in FIG. 9C or reference numbers 1011 to 1014 in FIG. 10C) to the non-volatile memory 200a via a plurality of data signal lines. In step S440, the non-volatile memory 200a detects an error in the command and address (CMD / ADDR) based on the CRC value. In step S450, the non-volatile memory 200a determines whether an error has occurred. If it is determined that an error has occurred, in step S460, the nonvolatile memory 200a transmits an error message E to the storage controller 100a via the multiple data signal lines.

[0090] In step S470, the storage controller 100a again transmits the command and address (CMD / ADDR) and the CRC value (eg, reference numbers 915-918 in FIG. 9C or reference numbers 1015-1018 in FIG. 10C) to the non-volatile memory 200a via a plurality of data signal lines.

[0091] In step S480, the storage controller 100a executes machine learning. Specifically, the machine learning module 190 performs learning to determine a communication error of the command and address (CMD / ADDR) based on whether or not an error message E related to the command and address (CMD / ADDR) is received in the first section. For example, the first section corresponds to the transmission section of the first to 1,000,000th commands and addresses. At this time, the machine learning module 190 calculates a communication error occurrence rate based on a statistical value of actual errors occurring in the first to 1,000,000th commands and addresses in the first section. In step S490, the non-volatile memory 200a executes a memory operation according to the command and address.

[0092] FIG. 14 is a flowchart illustrating a method of operating the storage controller 100a and the non-volatile memory 200a in the second section according to an embodiment of the present invention. 9 and 14, the second section corresponds to the section from the first reference value N1 until the number of times n of command and address (CMD / ADDR) processing in the storage controller 100a reaches the second reference value N2. For example, the second reference value N2 may be 2,000,000 times. Steps S500 to S590 shown in FIG. 14 may be performed after step S490 in FIG.

[0093] In step S500, the storage controller 100a generates a command and an address. In step S510, the storage controller 100a generates a CRC value from the generated command and address. In step S520, the machine learning module 190 predicts whether a communication error will occur in the command and address. Specifically, the machine learning module 190 determines whether a communication error occurs for each command and address issued in the second section based on the results learned in the first section. In one embodiment, steps S510 and S520 may be performed substantially simultaneously. In one embodiment, step S520 may be performed before step S510.

[0094] In step S530, the storage controller 100a transmits a command and address (CMD / ADDR) and a CRC value (eg, reference numbers 911 to 914 in FIG. 9C or reference numbers 1011 to 1014 in FIG. 10C) to the non-volatile memory 200a via a plurality of data signal lines. In step S540, the non-volatile memory 200a detects an error in the command and address (CMD / ADDR) based on the CRC value. In step S550, the non-volatile memory 200a determines whether an error has occurred. If it is determined that an error has occurred, in step S560, the nonvolatile memory 200a transmits an error message E to the storage controller 100a via the multiple data signal lines. In step S570, the storage controller 100a again transmits the command and address (CMD / ADDR) and the CRC value (eg, reference numbers 915-918 in FIG. 9C or reference numbers 1015-1018 in FIG. 10C) to the non-volatile memory 200a via a plurality of data signal lines.

[0095] In step S580, the storage controller 100a collects prediction data or judgment data through machine learning. For example, the second section corresponds to the transmission section of the 1,000,001st to 2,000,000th commands and addresses. Specifically, the machine learning module 190 calculates a machine learning judgment error rate M based on the error judgment results and the actual error occurrence results related to the 1,000,001st to 2,000,000th commands and addresses in the second section. E Calculate.

[0096] In addition, the machine learning module 190 continues to perform learning to determine a communication error of the command and address (CMD / ADDR) based on whether or not an error message E related to the command and address (CMD / ADDR) is received in the second section. In this case, the machine learning module 190 calculates a communication error occurrence rate E based on the statistical values ​​of actual errors occurring in the first to second million commands and addresses in the first and second sections. S Calculate. In step S590, the non-volatile memory 200a executes a memory operation according to the command and address.

[0097] FIG. 15 is a flowchart illustrating a method of operating the storage controller 100a and the non-volatile memory 200a in the third section according to an embodiment of the present invention. 9 and 15, the third section corresponds to the section after the number of times n of command and address (CMD / ADDR) processing in the storage controller 100a reaches the second reference value N2. For example, the second reference value N2 may be 2,000,000 times. Steps S600 to S690 shown in FIG. 15 may be performed after step S590 in FIG.

[0098] In step S600, the storage controller 100a generates a command and an address. In step S610, the machine learning module 190 predicts whether a communication error will occur in the command and address. In step S620, the machine learning module 190 determines whether a communication error is predicted to occur. If it is determined that a communication error is expected to occur, step S640 is performed. On the other hand, if it is predicted that no communication error will occur, in step S630, the storage controller 100a transmits a command and address (CMD / ADDR) to the non-volatile memory 200a via a plurality of data signal lines.

[0099] In step S640, the storage controller 100a generates a CRC value from the command and address (CMD / ADDR). In step S650, the storage controller 100a transmits a command and address (CMD / ADDR) and a CRC value (eg, reference numbers 911 to 914 in FIG. 9C or reference numbers 1011 to 1014 in FIG. 10C) to the non-volatile memory 200a via a plurality of data signal lines. In step S660, the non-volatile memory 200a detects an error in the command and address (CMD / ADDR) based on the CRC value.

[0100] In step S670, the non-volatile memory 200a determines whether an error has occurred. If it is determined that an error has occurred, in step S675, the nonvolatile memory 200a transmits an error message E to the storage controller 100a via the multiple data signal lines. In step S680, the storage controller 100a again transmits the command and address (CMD / ADDR) and the CRC value (eg, reference numbers 915-918 in FIG. 9C or reference numbers 1015-1018 in FIG. 10C) to the non-volatile memory 200a via a plurality of data signal lines. In step S690, the non-volatile memory 200a executes a memory operation according to the command and address.

[0101] 16A and 16B are timing diagrams illustrating communication between a storage controller 100a and a non-volatile memory 200a according to one embodiment of the present invention. Referring to both Figures 8, 16A and 16B, the CRC module 125 includes a plurality of error detection logics including a first error detection logic and a second error detection logic, and generates an error detection signal, i.e., a CRC value, associated with the command and address in a selected error detection logic among the plurality of error detection logics. Specifically, the CRC module 125 applies a first error detection logic to perform an error detection operation associated with each of the multiple commands / addresses, and changes the selected error detection logic from the first error detection logic to the second error detection logic based on a comparison result between the communication error rate of the multiple commands / addresses and the error rate of the first error detection logic.

[0102] In one embodiment, the first error detection logic may be (CRC-k) error detection logic and the second error detection logic may be (CRC-m) error detection logic. Here, k and m are positive integers, and k is greater than m. The CRC module 125 applies (CRC-k) error detection logic to calculate a first CRC value from each of the first commands / addresses, and if the (CRC-k) error rate is greater than the communication error rate for the first command / address, applies (CRC-m) error detection logic to calculate a second CRC value from each of the second commands / addresses.

[0103] In one embodiment, the plurality of error detection logics further includes a third error detection logic, where the first error detection logic may be a (CRC-k) error detection logic and the third error detection logic may be a (CRC-l) error detection logic. Here, k and l are positive integers, and k is smaller than l. The CRC module 125 applies (CRC-k) error detection logic to calculate a first CRC value from each of the first commands / addresses, and if the (CRC-k) error rate is not greater than the communication error rate for the first command / address, applies (CRC-l) error detection logic to calculate a second CRC value from each of the second commands / addresses.

[0104] Specifically, during the first interval, the storage controller 100a applies (CRC-16) error detection logic to calculate a CRC value, ie, (CRC-16), from the command and address. For example, the first section corresponds to a section from the time when a command and an address are issued until the number of times the command and address are processed or issued reaches a predetermined reference value. The storage controller 100a sequentially transmits a first command 1611, an address 1612, a CRC value 1613, and a second command 1614 to the non-volatile memory 200a via a plurality of data signal lines. For example, the first command 1611 includes an input command (e.g., 80h) indicating that the type of memory operation is a read operation, and the address 1612 includes first and second column addresses (C1, C2) and first to third row addresses (R1, R2, R3). The second command 1614 may be a confirm command indicating the read page size (eg, 50h, 20h, or 30h).

[0105] The CRC module 125 calculates a CRC value 1613 from the first command 1611 and the address 1612 . For example, CRC module 125 applies (CRC-16) error detection logic to perform a CRC on first command 1611 and address 1612 to calculate (CRC-16)(1) and (CRC-16)(2), where (CRC-16)(1) and (CRC-16)(2) are each provided as 8 bits. The nonvolatile memory 200 a determines whether or not a communication error has occurred in the first command 1611 and the address 1612 based on the CRC value 1613 . If it is determined that no communication error has occurred in the first command 1611 and the address 1612, the non-volatile memory 200a executes a read operation and transmits read data 1615 to the storage controller 100a.

[0106] During the second interval after the first interval, the storage controller 100a applies (CRC-8) error detection logic to calculate a CRC value, ie, (CRC-8), from the command and address. For example, the second section corresponds to a section from the end of the first section until the number of times commands and addresses are processed or issued reaches a predetermined reference value. The storage controller 100a sequentially transmits a first command 1616, an address 1617, a CRC value 1618, and a second command 1619 to the non-volatile memory 200a via a plurality of data signal lines.

[0107] The CRC module 125 calculates a CRC value 1618 from the first command 1616 and the address 1617 . For example, the CRC module 125 calculates a (CRC-8) by applying a (CRC-8) error detection logic to perform a CRC on the first command 1616 and the address 1617, where the (CRC-8) is provided in 8 bits. The non-volatile memory 200 a determines whether or not a communication error has occurred in the first command 1616 and the address 1617 based on the CRC value 1618 . If it is determined that no communication error has occurred in the first command 1616 and the address 1617, the non-volatile memory 200a executes a read operation and transmits read data 1620 to the storage controller 100a.

[0108] During the third interval following the second interval, the storage controller 100a applies (CRC-4) error detection logic to calculate a CRC value, ie, (CRC-4), from the command and address. For example, the third section corresponds to a section from the end of the second section until the number of times commands and addresses are processed or issued reaches a predetermined reference value. The storage controller 100a sequentially transmits a first command 1621, an address 1622, a CRC value 1623, and a second command 1624 to the non-volatile memory 200a via a plurality of data signal lines.

[0109] The CRC module 125 calculates a CRC value 1623 from the first command 1621 and the address 1622 . For example, the CRC module 125 calculates a (CRC-4) by applying a (CRC-4) error detection logic to perform a CRC on the first command 1621 and the address 1622, where the (CRC-4) is provided in 4 bits. The non-volatile memory 200 a determines whether or not a communication error has occurred in the first command 1621 and the address 1622 based on the CRC value 1623 . If it is determined that no communication error has occurred in the first command 1621 and the address 1622, the non-volatile memory 200a executes a read operation and transmits read data 1625 to the storage controller 100a.

[0110] During the fourth section after the third section, the storage controller 100a applies the (CRC-1) error detection logic to calculate a CRC value, ie, (CRC-1), from the command and address. For example, the fourth section corresponds to a section from the end of the third section until the number of times commands and addresses are processed or issued reaches a predetermined reference value. The storage controller 100a sequentially transmits a first command 1626, an address 1627, a CRC value 1628, and a second command 1629 to the non-volatile memory 200a via a plurality of data signal lines.

[0111] The CRC module 125 calculates a CRC value 1628 from the first command 1626 and the address 1627 . For example, the CRC module 125 calculates (CRC-1) by applying a (CRC-1) error detection logic to perform a CRC on the first command 1626 and the address 1627, where (CRC-1) is provided in 1 bit. The non-volatile memory 200 a determines whether or not a communication error has occurred in the first command 1626 and the address 1627 based on the CRC value 1628 . If it is determined that no communication error has occurred in the first command 1626 and the address 1627, the non-volatile memory 200a executes a read operation and transmits read data 1630 to the storage controller 100a. However, the invention is not so limited, and a (CRC-1) may be included in the reserved bits of the second command 1629.

[0112] FIG. 17 is a flowchart illustrating a method of operating the storage controller 100a according to an embodiment of the present invention. 8 and 17, the storage controller 100a compares the actual error rate of commands and addresses with the reliability of the error detection logic, and dynamically changes the error detection logic according to the comparison result. The storage controller 100a repeatedly performs the comparison operation every predetermined reference number n.

[0113] Specifically, after applying the first error detection logic, if the number of times n of command and address processing corresponds to the reference number N, the storage controller 100a performs a comparison operation to determine whether to change the error detection logic. In addition, when the error detection logic is changed from the first error detection logic to the second error detection logic, if the number of times n of command and address processing corresponds to the reference number N after applying the second error detection logic, the storage controller 100a performs a comparison operation to determine whether to change the error detection logic. Hereinafter, the operation method of the storage controller 100a will be described with reference to FIGS. 8, 16 and 17, taking as an example a case where the error detection logic is a CRC error detection logic.

[0114] If a command is issued, in step S710, the CRC module 125 applies (CRC-16) error detection logic to calculate a CRC value from the command and address. In step S720, it is determined whether the number of times n of command and address processing to which the (CRC-16) error detection logic has been applied corresponds to a reference number N. For example, the reference number of times N may be 5,000,000 times, but the present invention is not limited thereto. If it is determined that the number of times n of processing the command and address is less than the reference number N, then in step S710, the CRC module 125 continues to apply the (CRC-16) error detection logic to calculate a CRC value from the command and address.

[0115] On the other hand, if the command and address processing count n corresponds to the reference count N, then in step S730, it is determined whether the (CRC-16) error rate is greater than the actual error rate. For example, the error rate of (CRC-16) is 0.000015258789. If the (CRC-16) error rate is greater than the actual error rate, step S740 is performed. On the other hand, if the error rate of (CRC-16) is not as high as the actual error rate, it is determined that the actual error rate is very high. In this case, an error detection signal is generated from the command and address by applying another error detection logic having a lower error rate than (CRC-16) (step S735).

[0116] In step S740, the CRC module 125 calculates a CRC value from the command and address by applying an error detection logic that has a higher error rate (CRC-8) than (CRC-16). In step S750, it is determined whether the number of times n of command and address processing to which the (CRC-8) error detection logic has been applied corresponds to the reference number N. For example, the reference number of times N may be 5,000,000 times, but the present invention is not limited thereto. If it is determined that the number of times n of processing the command and address is less than the reference number N, then in step S740, the CRC module 125 continues to apply the (CRC-8) error detection logic to calculate a CRC value from the command and address.

[0117] On the other hand, if the command and address processing count n corresponds to the reference count N, then in step S760, it is determined whether the (CRC-8) error rate is greater than the actual error rate. If the (CRC-8) error rate is greater than the actual error rate, step S770 is performed. On the other hand, if the (CRC-8) error rate is not as high as the actual error rate, it is determined that the actual error rate is high. In that case, returning to step S710, the CRC module 125 applies (CRC-16) error detection logic to calculate a CRC value from the command and address. For example, the error rate of (CRC-8) is 0.00390625, and the actual error rate E S is 0.0015, the error rate of (CRC-8) is the actual error rate E S Since it is greater than , step S770 is executed.

[0118] In step S770, the CRC module 125 calculates a CRC value from the command and address by applying an error detection logic that has a higher error rate (CRC-4) than (CRC-8). In step S780, it is determined whether the number of times n of command and address processing to which the (CRC-4) error detection logic has been applied corresponds to the reference number N. For example, the reference number of times N may be 5,000,000 times, but the present invention is not limited thereto. If it is determined that the number of times n the command and address have been processed is less than the reference number n, then in step S770, the CRC module 125 continues to apply the (CRC-4) error detection logic to calculate a CRC value from the command and address.

[0119] On the other hand, if the command and address processing count n corresponds to the reference count N, then in step S790, it is determined whether the (CRC-4) error rate is greater than the actual error rate. For example, the error rate of (CRC-4) is 0.0625. If the (CRC-4) error rate is greater than the actual error rate, execution continues to step S770. On the other hand, if the (CRC-4) error rate is not as high as the actual error rate, it is determined that the actual error rate is high. In that case, returning to step S740, the CRC module 125 applies (CRC-8) error detection logic to calculate a CRC value from the command and address.

[0120] According to the above-described embodiment, the storage controller 100a selects one of a plurality of error detection logics according to the command and address error rate, thereby reducing the amount of calculation of the storage controller 100a according to the actual communication error rate.

[0121] FIG. 18 is a block diagram showing a schematic configuration of a storage device 20 according to an embodiment of the present invention. Referring to FIG. 18, the storage device 20 includes a memory device 300 and a memory controller 400. The memory device 300 corresponds to the non-volatile memory 200 of FIG. 1 or the non-volatile memory 200a of FIG. The memory controller 400 corresponds to the storage controller 100 in FIG. 1 or the storage controller 100a in FIG.

[0122] The memory device 300 includes first to eighth pins (P11 to P18), a memory interface circuit 310, a control logic circuit 320, and a memory cell array 330. The memory interface circuit 310 receives a chip enable signal nCE from the memory controller 400 via a first pin P11. The memory interface circuit 310 transmits and receives signals to and from the memory controller 400 via the second to eighth pins (P12 to P18) in response to a chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (eg, low level), the memory interface circuit 310 transmits and receives signals to and from the memory controller 400 via the second to eighth pins (P12 to P18).

[0123] The memory interface circuit 310 receives a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE from the memory controller 400 via the second to fourth pins (P12 to P14). The memory interface circuit 310 receives a data signal DQ from the memory controller 400 via a seventh pin P17, or transmits a data signal DQ to the memory controller 400. A command CMD, an address ADDR, and data DATA are transmitted via a data signal DQ. For example, the data signal DQ may be transmitted over multiple data signal lines. In this case, the seventh pin P17 includes a plurality of pins corresponding to a plurality of data signals DQ.

[0124] The memory interface circuit 310 obtains the command CMD from the data signal DQ received during the enable section (eg, high level state) of the command latch enable signal CLE based on the toggle timing of the write enable signal nWE. The memory interface circuit 310 obtains the address ADDR from the data signal DQ received during the enable section (eg, high level state) of the address latch enable signal ALE based on the toggle timing of the write enable signal nWE. In an exemplary embodiment, the write enable signal nWE holds a static state (eg, a high level or a low level) and toggles between a high level and a low level. For example, the write enable signal nWE toggles in a section in which the command CMD or the address ADDR is transmitted. As a result, the memory interface circuit 310 obtains the command CMD or the address ADDR based on the toggle timing of the write enable signal nWE.

[0125] The memory interface circuit 310 receives a read enable signal nRE from the memory controller 400 via a fifth pin P15. The memory interface circuit 310 receives a data strobe signal DQS from the memory controller 400 via a sixth pin P16, or transmits a data strobe signal DQS to the memory controller 400. In a data output operation of the memory device 300, the memory interface circuit 310 receives a toggling read enable signal nRE via the fifth pin P15 before outputting the data DATA. The memory interface circuit 310 generates a data strobe signal DQS that toggles based on the toggling of the read enable signal nRE. For example, the memory interface circuit 310 generates a data strobe signal DQS that starts toggling after a preset delay (eg, tDQSRE) based on the toggling start time of the read enable signal nRE. The memory interface circuit 310 transmits a data signal DQ including data DATA based on the toggle timing of the data strobe signal DQS. Thus, the data DATA is aligned with the toggle timing of the data strobe signal DQS and transmitted to the memory controller 400 .

[0126] In a data input operation of the memory device 300, when a data signal DQ including data DATA is received from the memory controller 400, the memory interface circuit 310 receives a data strobe signal DQS that toggles together with the data DATA from the memory controller 400. The memory interface circuit 310 obtains the data DATA from the data signal DQ based on the toggle timing of the data strobe signal DQS. For example, the memory interface circuit 310 obtains the data DATA by sampling the data signal DQ at the rising and falling edges of the data strobe signal DQS.

[0127] The memory interface circuit 310 transmits a ready / busy output signal (nR / B) to the memory controller 400 via an eighth pin P18. The memory interface circuit 310 transmits status information of the memory device 300 to the memory controller 400 via a ready / busy output signal (nR / B). When the memory device 300 is busy (ie, when an internal operation of the memory device 300 is being performed), the memory interface circuit 310 transmits a ready / busy output signal (nR / B) to the memory controller 400 indicating the busy state. When the memory device 300 is in a ready state (i.e., an internal operation of the memory device 300 is not being performed or has been completed), the memory interface circuit 310 transmits a ready / busy output signal (nR / B) to the memory controller 400 indicating the ready state.

[0128] For example, while the memory device 300 is reading data DATA from the memory cell array 330 in response to a page read command, the memory interface circuit 310 transmits a ready / busy output signal (nR / B) indicating a busy state (e.g., a low level) to the memory controller 400. For example, while the memory device 300 is programming data DATA in the memory cell array 330 in response to a program command, the memory interface circuit 310 transmits a ready / busy output signal (nR / B~) indicating a busy state to the memory controller 400.

[0129] The control logic circuit 320 generally controls various operations of the memory device 300 . The control logic circuit 320 receives the command and address (CMD / ADDR) obtained from the memory interface circuit 310 . The control logic circuit 320 generates control signals for controlling other components of the memory device 300 according to the received command and address (CMD / ADDR). For example, the control logic circuit 320 generates various control signals for programming data DATA in the memory cell array 330 or for reading data DATA from the memory cell array 330 .

[0130] The memory cell array 330 stores the data DATA obtained from the memory interface circuit 310 under the control of the control logic circuit 320 . The memory cell array 330 outputs the stored data DATA to the memory interface circuit 310 under the control of the control logic circuit 320 . The memory cell array 330 includes a plurality of memory cells.

[0131] For example, the memory cells may be flash memory cells. However, the present invention is not limited thereto, and the memory cells may be Resistive Random Access Memory (RRAM) cells, Ferroelectric Random Access Memory (FRAM®) cells, Phase Change Random Access Memory (PRAM) cells, Thyristor Random Access Memory (TRAM) cells, or Magnetic Random Access Memory (MRAM) cells. Hereinafter, embodiments of the present invention will be described, focusing on an embodiment in which the memory cells are NAND flash memory cells.

[0132] The memory controller 400 includes first to eighth pins (P21 to P28) and a controller interface circuit 410. The first to eighth pins (P21 to P28) correspond to the first to eighth pins (P11 to P18) of the memory device 300. The controller interface circuit 410 transmits a chip enable signal nCE to the memory device 300 via a first pin P21. The controller interface circuit 410 transmits and receives signals to and from the memory device 300 selected by the chip enable signal nCE via the second to eighth pins (P22 to P28).

[0133] The controller interface circuit 410 transmits a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE to the memory device 300 via the second to fourth pins (P22 to P24). The controller interface circuit 410 transmits a data signal DQ to the memory device 300 or receives a data signal DQ from the memory device 300 via a seventh pin P27. The controller interface circuit 410 transmits data signals DQ, which include a command CMD or an address ADDR, along with a toggling write enable signal nWE to the memory device 300 .

[0134] The controller interface circuit 410 transmits a data signal DQ including a command CMD to the memory device 300 by transmitting a command latch enable signal CLE having an enable state, and transmits a data signal DQ including an address ADDR to the memory device 300 by transmitting an address latch enable signal ALE having an enable state. The controller interface circuit 410 transmits a read enable signal nRE to the memory device 300 via a fifth pin P25. The controller interface circuit 410 receives a data strobe signal DQS from the memory device 300 or transmits a data strobe signal DQS to the memory device 300 via a sixth pin P26.

[0135] In a data output operation of the memory device 300 , the controller interface circuit 410 generates a toggling read enable signal nRE and transmits the read enable signal nRE to the memory device 300 . For example, the controller interface circuit 410 generates a read enable signal nRE that is changed from a fixed state (eg, high or low) to a toggle state before the data DATA is output. This causes the memory device 300 to generate a data strobe signal DQS that toggles based on the read enable signal nRE. The controller interface circuit 410 receives a data signal DQ, which includes data DATA, along with a toggling data strobe signal DQS from the memory device 300 . The controller interface circuit 410 obtains the data DATA from the data signal DQ based on the toggle timing of the data strobe signal DQS.

[0136] In a data input operation of the memory device 300, the controller interface circuit 410 generates a toggling data strobe signal DQS. For example, the controller interface circuit 410 generates a data strobe signal DQS that is changed from a fixed state (eg, high or low) to a toggle state before transmitting data DATA. The controller interface circuit 410 transmits the data signal DQ including the data DATA to the memory device 300 based on the toggle timing of the data strobe signal DQS. The controller interface circuit 410 receives a ready / busy output signal (nR / B) from the memory device 300 via an eighth pin P28. The controller interface circuit 410 determines the status information of the memory device 300 based on the ready / busy output signal (nR / B).

[0137] FIG. 19 is a block diagram showing a schematic configuration of a system 1000 to which a storage device according to an embodiment of the present invention is applied. The system 1000 of FIG. 19 may essentially be a mobile system such as a mobile phone, a smart phone, a tablet personal computer, a wearable device, a healthcare device, or an Internet of Things (IoT) device. However, the system 1000 of FIG. 19 is not necessarily limited to a mobile system, but may also be a personal computer, a laptop computer, a server, a media player, or an automotive device such as a navigation system.

[0138] Referring to FIG. 19, the system 1000 includes a main processor 1100, memory (1200a, 1200b), and storage devices (1300a, 1300b), and further includes one or more of an image capturing device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supplying device 1470, and a connecting interface 1480.

[0139] A main processor 1100 controls the overall operation of the system 1000 , and more specifically, the operation of the other components that make up the system 1000 . Such a main processor 1100 may be realized by a general-purpose processor, a dedicated processor, an application processor, or the like. The main processor 1100 includes one or more CPU cores 1110, and further includes a controller 1120 for controlling memories (1200a, 1200b) and / or storage devices (1300a, 1300b).

[0140] According to one embodiment, the main processor 1100 further includes an accelerator 1130, which is a dedicated circuit for high-speed data calculations such as AI (artificial intelligence) data calculations. Such accelerator 1130 may include a GPU (Graphics Processing Unit), an NPU (Neural Processing Unit), and / or a DPU (Data Processing Unit), and may also be embodied as a separate chip that is physically independent from other components of the main processor 1100.

[0141] The memory (1200a, 1200b) is used as the main storage of the system 1000 and includes volatile memory such as SRAM and / or DRAM, but may also include non-volatile memory such as flash memory, PRAM and / or RRAM. The memories (1200a, 1200b) may be implemented in the same package as the main processor 1100.

[0142] The storage devices 1300a and 1300b function as non-volatile storage devices that store data regardless of the power supply, and have a relatively large storage capacity compared to the memories 1200a and 1200b. The storage devices (1300a, 1300b) include storage controllers (1310a, 1310b) and non-volatile memory (NVM) (1320a, 1320b) that stores data under the control of the storage controllers (1310a, 1310b). The non-volatile memory (1320a, 1320b) may include flash memory with a 2D (2-dimensional) structure or a 3D (3-dimensional) V-NAND (Vertical NAND) structure, but may also include other types of non-volatile memory such as PRAM and / or RRAM. 19, a storage device (1300a, 1300b) corresponds to the storage device (10, 10a, or 20) illustrated in FIG. 1, FIG. 8, or FIG.

[0143] The storage devices (1300a, 1300b) may be included in the system 1000 while being physically separated from the main processor 1100, and may be embodied in the same package as the main processor 1100. In addition, the storage devices (1300a, 1300b) may have the form of a solid state device (SSD) or a memory card, and may be removably connected to other components of the system 1000 through an interface such as the connection interface 1480 described below. Such storage devices (1300a, 1300b) may be devices to which standard protocols such as UFS (universal flash storage), eMMC (embedded multi-media card), or NVMe (non-volatile memory express) are applied, but this is not necessarily the case.

[0144] The image capture device 1410 captures still or video images and may be a camera, a camcorder, a webcam, and / or the like. The user input device 1420 receives various types of data input from a user of the system 1000 and may be a touch pad, a keypad, a keyboard, a mouse, and / or a microphone. The sensor 1430 senses various types of physical quantities obtained from outside the system 1000 and converts the sensed physical quantities into electrical signals. Such sensors 1430 may be a temperature sensor, a pressure sensor, a light sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyroscope sensor.

[0145] The communications device 1440 facilitates the transmission and reception of signals to and from other devices external to the system 1000 via a variety of communication protocols. Such communication device 1440 may be embodied including an antenna, a transceiver, and / or a modem, etc. Display 1450 and speaker 1460 function as output devices for outputting visual and audible information, respectively, to a user of system 1000. The power supply device 1470 appropriately converts the power supplied from a battery (not shown) built into the system 1000 and / or an external power source, and supplies the power to each component of the system 1000. The connection interface 1480 provides a connection between the system 1000 and external devices that can be connected to the system 1000 to send data to and receive data from the system 1000 .

[0146] The connection interface 1480 may be implemented using a variety of interface methods, such as ATA (Advanced Technology Attachment), SATA (Serial ATA), e-SATA (external SATA), SCSI (Small Computer Small Interface), SAS (Serial Attached SCSI), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe, IEEE 1394, USB (universal serial bus), SD (secure digital) card, MMC (multi-media card), eMMC, UFS, eUFS (embedded Universal Flash Storage), and CF (compact flash) card interfaces.

[0147] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0148] 10, 10a, 100a Storage Device 100, 100a Storage Controller 110, 110a Command and Address Generator 120 Error Detection Module 125 CRC Module 130, 230 I / F circuit 140 processors 150 ECC engine 160 Host I / F 170 Non-volatile memory I / F 190 Machine Learning Module 200, 200a Non-volatile memory 200a Non-volatile memory 210 Memory Cell Array 220 Control Logic Circuit 221 Error Detection Module 240 Page Buffer Circuit 250 Voltage Generator 260 Row Decoder 270 CRC Module

Claims

1. A storage controller configured to control a non-volatile memory, comprising: a command and address generator configured to generate the first command, the address, and the second command as a command set; wherein the second command includes an error detection signal for detecting a communication error between the first command and the address, an error detection module configured to generate the error detection signal from the first command and the address such that the non-volatile memory detects a communication error in the first command and the address; an interface circuit configured to sequentially transmit the first command, the address, and the second command as the command set to the non-volatile memory; the first command indicates a type of memory operation to be performed on the non-volatile memory; The storage controller, wherein the second command corresponds to a confirm command related to a memory operation.

2. 2. The storage controller according to claim 1, wherein the error detection signal is a 1-bit signal.

3. The error detection module is further configured to generate a parity bit from the first command and the address; 2. The storage controller of claim 1, wherein the parity bit is the error detection signal.

4. The error detection module is further configured to generate a Cyclic Redundancy Check (CRC) value from the first command and the address; 2. The storage controller of claim 1, wherein the CRC value is the error detection signal.

5. The error detection module is further configured to generate a checksum from the first command and the address; 2. The storage controller of claim 1, wherein the checksum is the error detection signal.

6. the interface circuit further transmits a command latch enable signal having an enable level to the nonvolatile memory during a transmission period of the first command and the second command; The storage controller of claim 1 , further comprising: a latch enable signal having an enable level that is transmitted to the non-volatile memory during the address transmission period.

7. The storage controller of claim 1, wherein the interface circuit is further configured to receive an error message from the non-volatile memory when a communication error is detected.

8. 8. The storage controller of claim 7, wherein the interface circuit sequentially transmits the first command, the address, and the second command to the non-volatile memory again based on the error message.

9. A non-volatile memory, an interface circuit configured to sequentially receive a first command, an address, and a second command as a command set from the storage controller; wherein the second command includes an error detection signal for detecting a communication error between the first command and the address, a memory cell array including a plurality of memory cells; a control logic circuit configured to detect a communication error in the first command and the address based on the error detection signal; the first command indicates a type of memory operation to be performed on the non-volatile memory; The non-volatile memory, wherein the second command corresponds to a confirm command related to a memory operation.

10. The non-volatile memory of claim 9, wherein the error detection signal is a one-bit signal.

11. The non-volatile memory of claim 9, wherein the error detection signal includes a parity bit generated from the first command and the address.

12. The non-volatile memory of claim 9, wherein the error detection signal includes a CRC (Cyclic Redundancy Check) value generated from the first command and the address.

13. The non-volatile memory of claim 9, wherein the error detection signal includes a checksum generated from the first command and the address.

14. The non-volatile memory of claim 9, wherein the interface circuit is further configured to transmit an error message to the storage controller if a communication error is detected.

15. A method of operating a storage controller configured to control a non-volatile memory, comprising: generating a first command and an address; generating an error detection signal from the first command and the address; Thereby, the non-volatile memory detects a communication error in the first command and the address, generating a confirm command including the error detection signal; sequentially transmitting the first command, the address, and the confirm command to the non-volatile memory as a command set; the first command includes a read command or a write command; A method for operating a storage controller, wherein the confirm command is associated with a read operation corresponding to the read command or a write operation corresponding to the write command.

16. The method of claim 15, wherein the step of generating the error detection signal includes a step of generating the error detection signal including a one-bit signal.

17. The method of claim 15, wherein the step of generating the error detection signal includes a step of generating the error detection signal including a parity bit from the first command and the address.

18. The method of claim 15, wherein the step of generating the error detection signal includes a step of generating the error detection signal including a CRC (Cyclic Redundancy Check) value from the first command and the address.

19. The method of claim 15, wherein the step of generating an error detection signal includes a step of generating the error detection signal including a checksum from the first command and the address.

20. The method of claim 15, further comprising the step of receiving an error message from the non-volatile memory when the communication error is detected.

Images