Manufacturing method of ferroelectric memory and oxram resistive random access memory at the same time, and device accumulating the ferroelectric memory and oxram resistive random access memory at the same time

Abstract

To provide a method for manufacturing FeRAM and OxRAM at the same time.SOLUTION: A method contains: a step of accumulating a first electrode layer 201 which is equivalently performed to a segment Z1 and a segment Z2; a step of accumulating a layer of an active material based of a dioxide hafnium which is equivalently performed to the Z1 and the Z2; a step of accumulating a first conductive layer 204 which is equivalently performed to the Z1 and the Z2; a step of manufacturing a mask in the Z2 while keeping a vacancy of the Z1; a step of removing the layer 204 in the Z1 in a state where the Z2 is protected by the mask; a step of removing the mask in the Z2; a step of being contacted to the layer 204 in the Z2, being contacted with the layer 203 in the Z1, and accumulating a second conductive layer 206 that is selected so as to make oxygen depletion in the active material layer by the material; and a step of accumulating a third conductive layer which is equivalently performed to the Z1 and the Z2.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present invention relates to the manufacture of memory, and more specifically to the co-manufacturing of FeRAM ferroelectric memory and OxRAM resistive random-access memory, each of which has a layer of hafnium dioxide-based active material. The present invention also relates to a device in which OxRAM memory and FeRAM memory are co-integrated. [Background technology]

[0002] Development related to artificial intelligence (AI) has long been limited to the software portion. However, AI has many applications in embedded electronic devices, and it is no longer possible to rely solely on the cloud for AI-based computing. The emergence of embedded AI and the need to directly process algorithms within components raises hardware issues more than ever before. In such cases, AI needs to be processed locally at the core of the component. For this reason, the use of certain types of ultra-small memory is a particularly promising solution. However, AI-based systems use a lot of data and therefore require a large amount of memory on a single chip to store network states and parameters. Furthermore, not only the computation itself, but also the data transfer between the processor and memory consumes a very large amount of energy. For this reason, there is a tendency to use small, high-speed memory that minimizes energy dissipation during reading and writing as much as possible.

[0003] All neural networks used in AI require at least two stages: - The first so-called learning and training phase involves optimizing the model's parameters or set of weights from the dataset; this first phase requires numerous write operations in memory, and therefore the memory must have high write endurance. - The second so-called inference stage involves presenting the trained model with a test dataset and waiting for predictions; unlike the previous stage, this stage requires numerous read operations in memory, and therefore the memory must have extremely good read endurance.

[0004] There are different types of memory that can partially satisfy the above requirements.

[0005] For example, ferroelectric memory or FeRAM memory has key characteristics such as being non-volatile, meaning it retains stored information even when the voltage is cut off, consuming very little energy, having shorter write and read times compared to other types of non-volatile memory such as FLASH memory, being able to be integrated on large scale on low-voltage chips, being accessible with low latency, and having excellent radiation immunity. Furthermore, this type of memory has 10 10 It has extremely high write endurance, exceeding the number of cycles.

[0006] Ferroelectric memory is a capacitive memory having two residual polarization states, +Pr and -Pr. Figure 25 shows the operation of ferroelectric memory. This operation is based on the ferroelectric properties of the active material placed between the two electrodes. By applying a potential difference that creates an electric field with a value higher than the positive coercive field +Ec between the two electrodes, the ferroelectric memory enters a high residual polarization state +Pr. By applying a potential difference that creates an electric field with a value lower than the negative coercive field -Ec, the ferroelectric memory enters a low residual polarization state -Pr. In this case, the high residual polarization state +Pr corresponds to the binary logic state "0", and the low residual polarization state -Pr corresponds to the binary logic state "1", thereby allowing information to be stored. Note that the residual polarization state remains even when the application of the potential difference is stopped: this explains the non-volatile nature of ferroelectric memory. When reading from ferroelectric memory, it is not priori known which polarization state the memory is in. Therefore, during reading, it is assumed that a given state and voltage exist, for example, that a positive voltage exceeding the voltage that creates an electric field with a value higher than the positive coercivity +Ec is applied: if the memory was already in a highly residual polarization +Pr state, this polarization state would not change, and no peak current would be observed (or only a very small peak current would be observed). Conversely, if the memory was in a low non-volatile bias state -Pr, a much higher current peak would be observed. The result of this reading operation is that it is destructive to the polarization state. Thus, it is easy to see that ferroelectric memory meets the high-volume write criteria required for the learning and training phases, but is not suitable for the inference phase, which requires extremely good read endurance.

[0007] Other types of so-called resistive random-access memory are known, such as OxRAM memory, or "Oxide Resistive RAMs." These memories can have at least two resistive states, corresponding to a high-resistance state ("HRS") and a low-resistance state ("LRS"), when a voltage is applied.

[0008] The main characteristics of OxRAM memory are its non-volatility (i.e., retaining stored information even when the voltage is cut off), its faster write and read times compared to other types of non-volatile memory such as FLASH memory, its ability to be integrated on a large chip, its low latency accessibility, and its excellent resistance to radiation and temperature. Therefore, OxRAM memory appears to be an excellent candidate for AI applications. However, its write and erase endurance is quite limited (approximately 10%). 5 This cycle makes 0xRAM memory less efficient during the learning and training phases.

[0009] OxRAM memory has a MIM (metal-insulator-metal) structure, which includes an active material with variable electrical resistance, generally a transition metal oxide (e.g., WO3, HfO2, Ta2O5, TiO2, etc.), disposed between two metal electrodes. The transition from the "HRS" state to the "LRS" state is governed by the formation and rupture of conductive filaments between the two electrodes. These conductive filaments are created by the presence of oxygen depletion in the active layer of the memory. By changing the potential applied to the electrodes, the distribution of the filaments can be changed, and therefore the electrical conductivity between the two electrodes can be changed. In the active layer, the conductive filaments are ruptured or reformed during the write and subsequent reset cycles of this cell, causing the resistance level of the memory cell to fluctuate (set, V, V, respectively). SET , or reset, V RESET(A set operation occurs when the filament is reformed, creating an LRS state, by applying a voltage to the electrode terminals, and a reset operation occurs when the filament is broken again, creating an HRS state). The manufacturing of filament memory includes a so-called "formation" step in which the filament is formed for the first time in an active layer that initially has no filaments. The active layer is initially completely electrically insulated. During the initial formation step, conductive filaments are formed in the active layer by a kind of controlled dielectric breakdown in the active layer. The formed filaments then extend through the active layer, electrically connecting the lower electrode and the upper electrode. To perform this formation step, a voltage can be applied between the lower electrode and the upper electrode of the memory cell in question, and then the value of this voltage is progressively increased, exceeding a formation voltage V, which causes dielectric breakdown of the active layer. forming The voltage can be increased to a threshold voltage called V. After this formation step, the memory cell is ready for use. The conductive filament is then breakable, then reformable, and then formed at a voltage V. forming The circuit continues to break again at voltages below a certain level.

[0010] As you can see from the above, neither ferroelectric memory nor OxRAM fully meets the requirements of AI-based systems due to limitations in read (in the case of FeRAM) or write (in the case of OxRAM).

[0011] Patent application FR3090196 describes the simultaneous integration of OxRAM and FeRAM memory on the same chip, even if not explicitly related to AI applications, thereby enabling the combination of the write and read advantages of both types of memory. This simultaneous integration takes advantage of the fact that the same active material, HfO2, is used in the active layers of both OxRAM and FeRAM.

[0012] However, the manufacturing method for achieving this simultaneous integration, as described in patent application FR3090196, is complex to implement, insofar as it requires a masking level to differentiate the doping of the active layer used in FeRAM from that used in OxRAM. This method further involves the use of sub-microsecond laser annealing to reduce the heating time of the doped active material and to ensure sufficient crystallization of hafnium dioxide into a form that provides ferroelectric properties without overheating the underlying layer. Furthermore, the electrical efficiency of the OxRAM obtained by this method is not entirely satisfactory. [Prior art documents] [Patent Documents]

[0013] [Patent Document 1] French Patent Application Publication No. 3090196 [Overview of the Initiative] [Problems that the invention aims to solve]

[0014] This invention provides a solution to the above-mentioned problems by making it easier to manufacture a ferroelectric memory that is simultaneously integrated with an OxRAM resistive random-access memory while maintaining the efficient characteristics of both FeRAM memory and OxRAM memory. [Means for solving the problem]

[0015] For this purpose, one object of the present invention is a method for simultaneously manufacturing a ferroelectric memory comprising a first electrode, a second electrode, and a layer of hafnium dioxide active-based material disposed between the first and second electrodes, and an OxRAM resistive random-access memory comprising a first electrode, a second electrode, and a layer of hafnium dioxide HfO2-based active material disposed between the second and first electrodes, the following steps: - A step of depositing a first electrode layer, performed in exactly the same manner for the section for forming the OxRAM resistive random-access memory and the section for forming the ferroelectric memory; - A step of depositing a hafnium dioxide-based active material layer that is performed equally for both a section for forming an OxRAM resistive change memory and a section for forming a ferroelectric memory; - A step of depositing a first conductive layer that is performed equally for both a section for forming an OxRAM resistive change memory and a section for forming a ferroelectric memory; - A step of forming a mask in a section of the first conductive layer for forming a ferroelectric memory while leaving a section of the first conductive layer for forming an OxRAM resistive change memory empty; - A step of removing the first conductive layer in the section of the first conductive layer for forming an OxRAM resistive change memory, where the section of the first conductive layer for forming a ferroelectric memory is protected by the mask; - A step of removing the mask in the section of the first conductive layer for forming a ferroelectric memory; - A step of depositing a second conductive layer, wherein the second conductive layer contacts the first conductive layer in the section of the first conductive layer for forming a ferroelectric memory and contacts the active material layer in the section of the first conductive layer for forming an OxRAM resistive change memory, and the material of the second conductive layer is selected such that when the second conductive layer contacts the active layer of the OxRAM, it creates oxygen depletion in the active layer of the OxRAM; - A step of depositing a third conductive layer that is performed equally for both a section for forming an OxRAM and a section for forming a ferroelectric memory, wherein the third conductive layer contacts the second conductive layer is a method comprising.

[0016] According to the present invention, unlike the case of patent application FR3090196, there is no need for additional masking to obtain different dopings in the respective active layers of the FeRAM memory and the OxRAM memory. Surprisingly, the inventors have found that (unlike patent application FR3090196 where the active layer of the OxRAM memory was doped much more than the active layer of the ferroelectric memory) the same active layer of both memories can actually achieve both the ferroelectric effect in FeRAM and the OxRAM memory effect in the resistive change memory. Therefore, the doping of the hafnium dioxide active layer required for FeRAM is also sufficient for the resistive operation of OxRAM. The same reasoning applies to an active layer formed by a hafnium dioxide-based alloy, such as HfZrO2: in the case of HfZrO2, the ternary alloy HfZrO2 does not necessarily require doping of the active layer, and the active layer is the same for OxRAM and FeRAM. Generally, the hafnium dioxide-based layer of the active material is understood to be a doped HfO2 layer or a hafnium dioxide-based alloy such as HfZrO2 that is not necessarily doped.

[0017] To do this, the method of the present invention advantageously uses a modification of the upper electrode that will be different for OxRAM and FeRAM. In fact, according to the method of the present invention, the upper electrodes are respectively: - in the case of OxRAM, by a bilayer formed by a second conductive layer and a third conductive layer, - in the case of FeRAM, by a trilayer formed by a first conductive layer, a second conductive layer, and a third conductive layer to be formed.

[0018] The second conductive layer is in direct contact with the hafnium dioxide-based active layer for OxRAM and is an "oxygen scavenging layer" type layer, meaning that when this second conductive layer comes into contact with the active layer of OxRAM, it creates oxygen depletion in the hafnium dioxide-based active layer of OxRAM. For example, this may be a titanium Ti or hafnium Hf layer. Conversely, the active layer on the FeRAM side is in contact with the first conductive layer, on which the second conductive layer is deposited, which is not an oxygen depletion layer, for example, a TiN layer. In this way, oxygen depletion is created in the hafnium dioxide-based layer of OxRAM without creating oxygen depletion in the hafnium dioxide-based layer of FeRAM, thereby ensuring efficient resistive operation of OxRAM despite the same doping in the active layers of OxRAM and FeRAM.

[0019] Furthermore, the method according to the present invention can eliminate the need for localized submicrosecond laser annealing. In fact, sufficient crystallization of hafnium dioxide in an orthorhombic form, which imparts ferroelectric properties, is directly achieved by the thermal budget of various manufacturing steps in "back-end" integration, particularly suitable for CMOS technology. Moreover, using an active layer crystallized in an orthorhombic phase based on HfO2, which is typically used by those skilled in the art, does not impede the operation of the OxRAM memory.

[0020] In addition to the features discussed above, a method according to one aspect of the present invention may have one or more complementary features, individually or in any technically possible combination, from the following: - The step of leaving a section of the first conductive layer for forming the OxRAM resistive random-access memory empty, while fabricating a mask in the section of the first conductive layer for forming the ferroelectric memory, is as follows: - A step of depositing a mask on the first conductive layer in a section of the first conductive layer for forming a ferroelectric memory and in a section of the first conductive layer for forming an OxRAM resistive random-access memory; - Leaving a mask in a section of the first conductive layer for forming a ferroelectric memory while removing the mask in a section of the first conductive layer for forming an OxRAM resistive change memory comprises. - The method according to the invention comprises doping the layer of the active material, which is carried out equally for the section for forming an OxRAM resistive change memory and the section for forming a ferroelectric memory, at the end of the step of depositing a hafnium dioxide-based layer of the active material - The doping step is carried out by ion implantation, or using a doping precursor, or by co-sputtering. - The dopant element used in the doping step is selected from one of the following elements: Si, Al, Zr, Gd, Ge, Y or N; - The dopant element is Si (the doping step is preferably carried out by ion implantation, preferably the thickness of the active material layer is on the order of 10 nm), and the layer of the active material is 10 14 ions / cm 2 and 5.10 14 ions / cm<000001​​​​​​​​​​​​​​In ferroelectric memory and resistive OxRAM memory, the layers of hafnium dioxide-based active material are formed by the same hafnium dioxide-based active material layers present on a first dedicated compartment and a second dedicated compartment. The second electrode of the ferroelectric memory is formed in a second dedicated compartment by a triple layer including a first conductive layer in contact with the active layer, a second conductive layer on the first conductive layer, and a third conductive layer on the second conductive layer. The second electrode of the OxRAM resistive random-access memory is formed in a first dedicated compartment by a double layer including a second conductive layer in contact with the active layer and a third conductive layer on the first conductive layer. The material of the second conductive layer is selected such that when the second conductive layer comes into contact with the active layer of the OxRAM, it creates oxygen depletion in the active layer of the OxRAM resistive random-access memory. It is a device.

[0022] The device according to the present invention can be obtained, in particular, by the simultaneous manufacturing method of the present invention.

[0023] In addition to the features discussed above, the device according to the present invention may have one or more complementary features, individually or in any technically possible combination, from the following: - The thickness of the active layer and / or the second conductive layer is typically between 3 nm and 15 nm. - The thickness of the third conductive layer is typically between 20 nm and 200 nm. - The ferroelectric memory includes a pit with an inner wall in which a triple layer is sequentially arranged, comprising a first electrode layer, a hafnium dioxide-based active material layer, and a first conductive layer, a second conductive layer, and a third conductive layer on the second conductive layer.

[0024] The present invention also relates to a method for training and inference of an artificial intelligence system including a device according to the present invention, wherein a ferroelectric memory is used in the training phase and an OxRAM resistive random-access memory is used in the inference phase.

[0025] The present invention and its various applications can be better understood by reading the following description and examining the attached drawings.

[0026] The drawings are provided as examples only and are not intended to limit the present invention in any way. [Brief explanation of the drawing]

[0027] [Figure 1] This figure shows various steps of a method for the simultaneous manufacturing of a ferroelectric memory and an OxRAM memory according to a first embodiment of the present invention. [Figure 2] This figure shows various steps of a method for the simultaneous manufacturing of a ferroelectric memory and an OxRAM memory according to a first embodiment of the present invention. [Figure 3] This figure shows various steps of a method for the simultaneous manufacturing of a ferroelectric memory and an OxRAM memory according to a first embodiment of the present invention. [Figure 4] This figure shows various steps of a method for the simultaneous manufacturing of a ferroelectric memory and an OxRAM memory according to a first embodiment of the present invention. [Figure 5] This figure shows various steps of a method for the simultaneous manufacturing of a ferroelectric memory and an OxRAM memory according to a first embodiment of the present invention. [Figure 6] This figure shows various steps of a method for the simultaneous manufacturing of a ferroelectric memory and an OxRAM memory according to a first embodiment of the present invention. [Figure 7] This figure shows various steps of a method for the simultaneous manufacturing of a ferroelectric memory and an OxRAM memory according to a first embodiment of the present invention. [Figure 8] This figure shows various steps of a method for the simultaneous manufacturing of a ferroelectric memory and an OxRAM memory according to a first embodiment of the present invention. [Figure 9] This figure shows various steps of a method for the simultaneous manufacturing of a ferroelectric memory and an OxRAM memory according to a first embodiment of the present invention. [Figure 10]This figure shows various steps of a method for the simultaneous manufacturing of a ferroelectric memory and an OxRAM memory according to a first embodiment of the present invention. [Figure 11] Figures 1 to 10 show flowcharts of the method steps according to the first embodiment of the present invention. [Figure 12] This figure shows an alternative embodiment of the method shown in Figure 11. [Figure 13] This figure shows various steps of a method for the simultaneous manufacturing of a ferroelectric memory and an OxRAM memory according to a second embodiment of the present invention. [Figure 14] This figure shows various steps of a method for the simultaneous manufacturing of a ferroelectric memory and an OxRAM memory according to a second embodiment of the present invention. [Figure 15] This figure shows various steps of a method for the simultaneous manufacturing of a ferroelectric memory and an OxRAM memory according to a second embodiment of the present invention. [Figure 16] This figure shows various steps of a method for the simultaneous manufacturing of a ferroelectric memory and an OxRAM memory according to a second embodiment of the present invention. [Figure 17] This figure shows various steps of a method for the simultaneous manufacturing of a ferroelectric memory and an OxRAM memory according to a second embodiment of the present invention. [Figure 18] This figure shows various steps of a method for the simultaneous manufacturing of a ferroelectric memory and an OxRAM memory according to a second embodiment of the present invention. [Figure 19] This figure shows various steps of a method for the simultaneous manufacturing of a ferroelectric memory and an OxRAM memory according to a second embodiment of the present invention. [Figure 20] This figure shows various steps of a method for the simultaneous manufacturing of a ferroelectric memory and an OxRAM memory according to a second embodiment of the present invention. [Figure 21] This figure shows various steps of a method for the simultaneous manufacturing of a ferroelectric memory and an OxRAM memory according to a second embodiment of the present invention. [Figure 22]This figure shows various steps of a method for the simultaneous manufacturing of a ferroelectric memory and an OxRAM memory according to a second embodiment of the present invention. [Figure 23] This figure shows various steps of a method for the simultaneous manufacturing of a ferroelectric memory and an OxRAM memory according to a second embodiment of the present invention. [Figure 24] Figures 13 to 23 show flowcharts of the method steps according to a second embodiment of the present invention. [Figure 25] This diagram shows the operation of a ferroelectric memory. [Figure 26] This figure shows the ferroelectric memory and OxRAM memory according to the present invention, which are simultaneously integrated in the backend of a CMOS transistor. [Modes for carrying out the invention]

[0028] Unless otherwise specified, the same element appearing in different drawings shall have a unique reference numeral.

[0029] The present invention relates to a method for simultaneously manufacturing FeRAM ferroelectric memory and OxRAM memory, each having a hafnium dioxide-based material such as hafnium dioxide HfO2 or an HfZrO2 alloy as the active material (in the case of HfZrO2, the steps of depositing and doping the active layer with HfO2 can be considered equivalent to the deposit of a ternary HfZrO2 alloy). This active material exhibits ferroelectric properties when doped with a specific dopant element to obtain an appropriate dopant element concentration and then crystallized in an orthorhombic phase. This material can also be used in OxRAM-type resistive random-access memory, which is based on the formation of conductive filaments when the material is oxygen-depleted.

[0030] Figures 1 to 10 show various steps 101 to 110 (flowchart in Figure 11) of the first embodiment of the simultaneous manufacturing method 100 according to the present invention.

[0031] Figure 1 shows the first step 101 of Method 100 according to one embodiment of the present invention.

[0032] Figure 2 shows the second step 102 of method 100 according to one aspect of the present invention.

[0033] Figure 3 shows the third step 103 of method 100 according to one aspect of the present invention.

[0034] Figure 4 shows the fourth step 104 of Method 100 according to one embodiment of the present invention.

[0035] Figure 5 shows the fifth step 105 of method 100 according to one aspect of the present invention.

[0036] Figure 6 shows the sixth step 106 of method 100 according to one aspect of the present invention.

[0037] Figure 7 shows the seventh step 107 of Method 100 according to one aspect of the present invention.

[0038] Figure 8 shows the eighth step 108 of method 100 according to one aspect of the present invention.

[0039] Figure 9 shows the ninth step 109 of method 100 according to one aspect of the present invention.

[0040] Figure 10 shows the tenth step 110 of method 100 according to one aspect of the present invention.

[0041] Figure 11 shows a flowchart of the steps of a method according to one embodiment of the present invention shown in Figures 1 to 10.

[0042] Method 100 according to one aspect of the present invention includes step 101 of conformally depositing a first electrode layer 201 as shown in Figure 1. This deposition is carried out exactly the same way for a section Z1 for forming an OxRAM resistive random-access memory and a section Z2 for forming an FeRAM ferroelectric memory. In other words, a single layer of the first electrode 201 is deposited: the portion of the first electrode layer located within the first section Z1 becomes the first electrode layer 201 of the OxRAM resistive random-access memory, while the portion of the first electrode layer located within the second section Z2 becomes the first electrode layer 201 of the FeRAM ferroelectric memory. For clarity, the layer 201 is represented by two parts in Z1 and Z2, but it should be understood that the layer 201 is a single layer deposited to form both the OxRAM memory and the FeRAM memory, and that this then enables insulation between the memories.

[0043] The first electrode layer 201 is disposed on, for example, tungsten vias 200a and 200b for connecting the OxRAM memory and FeRAM memory to a lower Cu metal level, respectively. The first electrodes 201 for both OxRAM and FeRAM are referred to as the bottom electrodes. Naturally, the first electrode layer 201 can also be deposited on substrates not shown.

[0044] The conductive material of the first electrode layer 201 is, for example, titanium nitride (TiN). TiN is a non-limiting example, and other conductive materials such as TaN or W can also be used.

[0045] Sedimentation can be seen, for example, as physical vapor deposition (PVD).

[0046] The thickness of the first electrode layer 201 is, for example, between 10 nm and 200 nm.

[0047] Method 100 according to the present invention then includes a step 102 of depositing an active material layer 202, as shown in Figure 2, which is conformally deposited hafnium dioxide HfO2. Similar to step 101 of depositing the electrode layer 201, the step of depositing the active material layer 202 is to deposit a single layer 202 of the active material, where a first compartment Z1 of this single layer 202 of the active material is intended to become the active material layer 202 of an OxRAM resistive random-access memory, and a second compartment Z2 of the active material layer 202 is intended to become the active material layer 202 of an FeRAM ferroelectric memory.

[0048] The active material layer 202 may be deposited directly on the first electrode layer 201, or on another layer previously deposited on the first electrode layer 201.

[0049] The deposition is atomic layer deposition, or ALD, performed at temperatures between 200°C and 300°C, which allows for the deposition of layers of, for example, very little thickness, in this case between 5 nm and 10 nm. This type of HfO2 thickness is suitable for active layer thicknesses usable for both OxRAM and FeRAM operation. The thickness of the active layer 202 is, for example, about 10 nm.

[0050] Method 100 also includes step 103 of doping the active material layer 202. "Doping a layer" means the act of introducing atoms of another material, called impurities, into the material of the layer.

[0051] According to one embodiment shown in Figure 3, the doping step 103 is performed by ion implantation. Ion implantation doping involves accelerating ionized impurities with an electric field to impart the energy necessary for them to enter the material to be doped.

[0052] The dopant element used is preferably silicon (Si). However, other dopant elements such as aluminum (Al), zirconium (Zr), germanium (Ge), gadolinium (Gd), yttrium (Y), or nitrogen (N) can also be used.

[0053] According to step 103, the entire layer 202 (i.e., both on section Z1 dedicated to fabricating OxRAM and on section Z2 dedicated to fabricating FeRAM) is doped in exactly the same way.

[0054] The active material layer 202, for example, at energies between 2 keV and 4 keV, is 10 14 Ions / cm 2 and 5.10 14 Ions / cm 2 It is exposed to dopant doses between [a certain range]. This doping range is applicable not only to the use of the active layer in OxRAM resistive random-access memory (which undergoes oxygen depletion as detailed below) but also to the use of the active layer in FeRAM memory to obtain an orthorhombic phase with an appropriate thermal budget. Unlike patent application FR3090196, in which the active layer of compartment Z1 was relatively overdoped with the active layer of compartment Z2, in this case the active layer 202 is doped exactly equally.

[0055] According to one embodiment not shown, the doping step 103 may be carried out simultaneously with the deposition of the active layer using a doping precursor. For example, the doping precursor is used during ALD deposition by alternating cycles of deposition of hafnium dioxide (HfO2) and dopant elements and by the number of cycles (i.e., referred to as an ALD supercycle). The doping precursor is, for example, silicon dioxide (SiO2).

[0056] In another embodiment (not shown), doping can also be performed simultaneously with the active layer by co-sputtering via PVD (vapor deposition) or PLD (pulsed laser deposition).

[0057] At the end of the doping step 103, shown in step 104 of Figure 4, the active material layer 202 has become, for example, a layer 203 of HfO2 active material doped with Si.

[0058] Method 100 according to the present invention then includes step 105 (Figure 5) of depositing a first conductive layer 204 on a doped layer 203 of HfO2 active material. This deposition is carried out exactly the same way for section Z1 for forming a resistive OxRAM and section Z2 for forming an FeRAM ferroelectric memory.

[0059] The conductive material of the first conductive layer 204 is, for example, titanium nitride (TiN). TiN is a non-limiting example, and other conductive materials such as TaN or W can also be used.

[0060] The deposition is, for example, physical vapor deposition, or PVD.

[0061] The thickness of the first conductive layer 204 is on the order of 10 nm or more.

[0062] The method according to the present invention then includes step 106 of fabricating a mask 205 over a compartment Z2 for forming a ferroelectric memory of the first conductive layer 204, leaving compartment Z1 open for forming an OxRAM resistive random-access memory of the first conductive layer 204. The mask 205 is made of, for example, silicon nitride (SiN), silicon oxide (SiO2), or a resin. Thus, the mask 205 covers the portion of the first conductive layer 204 located in compartment Z2. In known methods, the mask 205 is, for example: - A hard mask is conformally deposited to cover the first conductive layer in both section Z1 and section Z2. - Removing the hard mask portion in section Z1 while stopping it on the first conductive layer 204. It can be fabricated by the following method. The removal step is performed, for example, by lithography and etching.

[0063] Therefore, at the end of step 106, only section Z1 of the first conductive layer 204 is directly accessible on the surface.

[0064] Method 100 includes step 107 of removing the first conductive layer 204 in a compartment Z1 of the first conductive layer for forming an OxRAM resistive random-access memory, while compartment Z2 of the first conductive layer 204 for forming a ferroelectric memory is protected by a mask 205. This removal operation is performed, for example, by plasma etching of the first conductive layer 204 of TiN, and the plasma etching of TiN is highly selective for HfO2 in the active layer 203 such that etching stops on the HfO2 active layer 203 in compartment Z1.

[0065] Method 100 then includes step 108 of removing the mask 205 in section Z2 for forming a ferroelectric memory while the process is stopped on the first conductive layer 204. At the end of step 108, the active layer 203 is exposed in section Z1 and covered by the first conductive layer 204 in section Z2. The operation to remove the mask 205 is performed, for example, using oxygen plasma ("oxygen stripping") if the mask 205 is made of resin.

[0066] Method 100 then comprises step 109 of conformally depositing a second conductive layer 206, the second conductive layer 206 in contact with the first conductive layer 204 in section Z2 for forming the ferroelectric memory and in contact with the active material layer 203 in section Z1 for forming the OxRAM resistive random-access memory, and then conformally depositing a third conductive layer 207, which is carried out exactly equally in section Z1 for forming the OxRAM resistive random-access memory and section Z2 for forming the ferroelectric memory, the third conductive layer 207 in contact with the second conductive layer 206.

[0067] The deposition of layers 206 and 207 is, for example, physical vapor deposition, or PVD.

[0068] The conductive material for the third conductive layer 207 is, for example, titanium nitride (TiN). TiN is a non-limiting example, and other conductive materials such as TaN can also be used. Note that the material selected for the third conductive layer 207 may be different from the material selected for the first conductive layer 204.

[0069] The thickness of the third conductive layer 207 is, for example, between 20 nm and 200 nm.

[0070] The conductive material of the second conductive layer 206 is selected to be a material ("oxygen exclusion layer") that pumps oxygen into the active layer 203 located in section Z1 on which the second conductive layer 206 is deposited. By pumping oxygen into the active layer 206, the second conductive layer 206 creates oxygen depletion in the portion of the active layer 203 dedicated to the fabrication of the OxRAM, and oxygen depletion is necessary for the proper operation of the OxRAM. On the other hand, since the second conductive layer 206 is deposited on the first conductive layer 204 in section Z2 dedicated to the FeRAM, it does not come into contact with the active layer 203 in section Z2, and therefore does not create any depletion in the active layer 203 on the Z2 side. The material of the second conductive layer 206 is, for example, titanium (Ti) or hafnium when the material of the third conductive layer 207 is TiN. When the material of the third conductive layer 207 is TaN, it may be tantalum (Ta) hafnium. Note that Ti (Ta) is an excellent bonding material for TiN (TaN) upper layers.

[0071] The thickness of the second conductive layer 206 is substantially the same as the thickness of the active layer 203, for example, between 5 nm and 10 nm.

[0072] According to step 110 of method 100 shown in Figure 10, two upper vias 208a and 208b are fabricated on a third conductive layer 207 in a compartment Z1 dedicated to OxRAM and a compartment Z2 dedicated to FeRAM, respectively.

[0073] Figure 12 shows an alternative embodiment 111 of Method 100 according to one aspect of the present invention. Thus, between step 108 and step 109, it is possible to remove a portion of the thickness of the active layer in section Z1 dedicated to OxRAM (referred to here as 203a) and a portion of the thickness of the first conductive layer in section Z2 dedicated to FeRAM (referred to here as 204a). This step 111 is performed before depositing the second and third conductive layers. This removal can be performed, for example, by an argon plasma that allows for the removal of several nanometers of the upper layer in a uniform and controlled manner regardless of its chemical properties ("pre-clean" type plasma). This allows for both the removal of native oxides on the first conductive layer (e.g., TiN) and a reduction in the thickness of the active material on the OxRAM side (thus enabling a reduction in the formation voltage and write voltage of the OxRAM in particular).

[0074] The material of the active layer 203 needs to be crystallized in an orthorhombic phase so that the active layer 203 can operate as a ferroelectric memory in section Z2. Several solutions are considered to achieve this. A first solution is annealing at a temperature between 300°C and 500°C, for example, on the order of 450°C, which is suitable for back-end processes: this annealing may be performed, for example, in step 105 (before or preferably after the deposition of the first conductive layer 204). However, this annealing can be omitted by using the cumulative thermal budget on the order of 300°C of the manufacturing method in Figure 11, with the end of the manufacturing method added which is not shown here, and in particular by including encapsulation of the OxRAM and FeRAM memory points by spacers or by a continuous layer of insulators after back-end integration of the memory points above the CMOS transistors. Therefore, generally, the active layer 203 is heat-treated to crystallize it in an orthorhombic phase, and this heat treatment is either annealing (preferably performed after the deposition of the first conductive layer 204) or a heat treatment that ensures orthorhombic crystallization without necessarily performing specific annealing, by a step that results in the encapsulation of OxRAM and FeRAM memory. An example of encapsulation at the CMOS transistor level and the OxRAM and FeRAM memory levels, integrated in the backend and encapsulated in the oxide layer, is shown in Figure 26.

[0075] At the end of Method 100 according to the present invention, a device is obtained that simultaneously integrates a ferroelectric memory located in a dedicated compartment Z2 and an OxRAM memory located in a dedicated compartment Z1. The ferroelectric memory includes a first electrode (known as the lower electrode), a second electrode (known as the upper electrode), and a layer of hafnium dioxide HfO2 active material disposed between the first and second electrodes. Similarly, the OxRAM resistive random-access memory includes a first electrode (known as the lower electrode), a second electrode (known as the upper electrode), and a layer of hafnium dioxide HfO2 active material disposed between the first and second electrodes. The lower electrodes of the FeRAM memory and the OxRAM memory are formed by the same layer 201 of the first electrode. The layer of hafnium dioxide HfO2 active material of the FeRAM memory and the OxRAM memory is formed by the same doped layer 203 of HfO2 active material crystallized in an orthorhombic phase.

[0076] The upper electrode of the FeRAM is formed by a triple layer including a first conductive layer 204, a second conductive layer 206, and a third conductive layer 207 in a compartment Z2 dedicated to the FeRAM.

[0077] The upper electrode of the OxRAM is formed by a double layer including a second layer 206 and a third layer 207 in a compartment Z1 dedicated to the OxRAM.

[0078] When the device according to the present invention is in its original state immediately after manufacturing, the switching compartment (i.e., active layer) of the OxRAM memory must be formed for the first time by applying a forming voltage Vforming, which is higher than the write voltage Vset, between the two electrodes of the OxRAM memory. Subsequently, the OxRAM enters a normal operating mode in which the write voltage Vset and the erase voltage Vreset (which has a different sign from the write voltage) are used to switch the resistance state of the OxRAM resistive random-access memory.

[0079] By applying a Pup programming voltage higher than the voltage that creates an electric field greater than the positive coercivity (+Ec) between the electrodes of the FeRAM memory, the ferroelectric memory is brought into a high residual polarization state (+Pr). Similarly, by applying a Pdown voltage higher than the voltage that creates an electric field greater than the negative coercivity (-Ec) to the FeRAM memory, the FeRAM is brought into a low residual polarization state (-Pr).

[0080] Figures 13 to 23 show various steps 101' to 111' (flowchart in Figure 23) of a second embodiment of the simultaneous manufacturing method 100' according to the present invention.

[0081] Figure 13 shows the first step 101' of method 100' according to one aspect of the present invention.

[0082] Figure 14 shows the second step 102' of method 100' according to one aspect of the present invention.

[0083] Figure 15 shows the third step 103' of method 100' according to one aspect of the present invention.

[0084] Figure 16 shows the fourth step 104' of method 100' according to one aspect of the present invention.

[0085] Figure 17 shows the fifth step 105' of method 100' according to one aspect of the present invention.

[0086] Figure 18 shows the sixth step 106' of method 100' according to one aspect of the present invention.

[0087] Figure 19 shows the seventh step 107' of method 100' according to one aspect of the present invention.

[0088] Figure 20 shows the eighth step 108' of method 100' according to one aspect of the present invention.

[0089] Figure 21 shows the ninth step 109' of method 100' according to one aspect of the present invention.

[0090] Figure 22 shows the tenth step 110' of method 100' according to one aspect of the present invention.

[0091] Figure 23 shows the eleventh step 111' of method 100' according to one aspect of the present invention.

[0092] Figure 24 shows a flowchart of the steps of method 100' according to one embodiment of the present invention, as shown in Figures 13 to 23.

[0093] Method 100' according to a second embodiment of the present invention is very similar to Method 100 described above, but differs in that it aims to obtain a three-dimensional structure of simultaneously integrated OxRAM resistive random-access memory and ferroelectric memory. The advantage of such a configuration is that it can increase the capacitance surface area of ​​the FeRAM, especially in the case of ultra-high-end nodes.

[0094] Method 100' according to the present invention includes step 101' conformally depositing a first electrode layer 201' as shown in Figure 13. This deposition is carried out exactly the same way for section Z1 for forming an OxRAM resistive random-access memory and section Z2 for forming an FeRAM ferroelectric memory. In other words, a single layer 201' of the first electrode is deposited: the portion of the first electrode layer 201' located in the first section Z1 becomes the first electrode layer 201' of the OxRAM resistive random-access memory, and the portion of the first electrode layer 201' located in the second section Z2 becomes the first electrode layer of the FeRAM ferroelectric memory. For clarity in the figure, the 201' layer is represented as two parts on section Z1 and Z2, but it should be understood that in reality it is a single layer deposited to form both OxRAM and FeRAM memories, and then insulation can be achieved between the memories.

[0095] Unlike the first embodiment, the first electrode layer 201' is deposited, for example, in pit 300 in section Z1 and pit 301 in section Z2, and both pits 300 and 301 are positioned above vias 200a' and 200b' made of, for example, tungsten, for connecting the OxRAM memory and FeRAM memory to the underlying Cu metal level, respectively. The first electrode 201' for both OxRAM and FeRAM is referred to as the lower electrode. The pits 300 and 301 can also be replaced by conductive vias to which the first electrode layer 201' will be deposited. The pits 300 and 301 are made of, for example, a TEOS-type oxide. After the deposition of the TEOS or oxide / SiN2 superlayer, lithography and subsequent etching are performed, for example, to etch the pits up to the vias 200a' and 200b', and then the resin is removed using oxygen plasma.

[0096] The conductive material of the first electrode layer 201' is, for example, titanium nitride (TiN).

[0097] The deposition of the first electrode 201' layer is carried out as conformally as possible, such as atomic layer deposition (ALD), so that the layer 201' fits snugly against the inner walls of pits 300 and 301.

[0098] The thickness of the first electrode layer 201' is, for example, between 10 nm and 200 nm.

[0099] Method 100' according to the present invention then includes a step 102' of depositing a layer 202' of the active material shown in Figure 14, which is to perform conformal deposition of hafnium dioxide HfO2. Similar to step 101' of depositing the electrode layer 201', the step of depositing the layer 202' of the active layer material is to deposit a single layer 202' of the active material, where a first compartment Z1 of this single layer 202' of the active material is intended to become the active material layer 202' of an OxRAM resistive random-access memory, and a second compartment Z2 of the active material layer 202' is intended to become the active material layer 202' of an FeRAM ferroelectric memory.

[0100] The deposition is a highly conformal deposition of atomic thin films or ALD (atomic layer deposition) between 200°C and 300°C, which allows for the deposition of layers of as little as 5 nm and 10 nm in thickness, for example. This type of HfO2 thickness is suitable for active layer thicknesses usable for both OxRAM and FeRAM operation. The thickness of the active layer 202' is, for example, about 10 nm. It should be understood that the use of pits gives the memory a three-dimensional shape to increase the surface area of ​​the active material, and therefore the useful capacitive surface area of ​​the ferroelectric memory.

[0101] Method 100' also includes step 103' of doping a layer 202' of the active material.

[0102] According to one embodiment shown in Figure 15, the doping step 103' is performed by plasma immersion ion implantation to make the doping as conformal as possible.

[0103] The dopant element used is preferably silicon (Si). However, other dopant elements such as aluminum (Al), zirconium (Zr), germanium (Ge), gadolinium (Gd), yttrium (Y), or nitrogen (N) can also be used.

[0104] According to this step 103', the entire layer 202' (i.e., both on section Z1 dedicated to fabricating OxRAM and on section Z2 dedicated to fabricating FeRAM) is doped in exactly the same way. The active material layer 202' is doped, for example, in the case of Si doping, at an energy between 2 keV and 4 keV. 14 Ions / cm 2 and 5.10 14 Ions / cm 2 They are exposed to dopant doses between [a certain level] and [another level].

[0105] Similar to the first embodiment, the doping step 103' may be performed simultaneously with the deposition of the active layer using a doping precursor. For example, the doping precursor is used during ALD deposition by alternating cycles of deposition of hafnium dioxide (HfO2) and dopant elements, and by the number of cycles (i.e., referred to as an ALD supercycle). The doping precursor is, for example, silicon dioxide (SiO2). Doping can also be performed simultaneously with the active layer by simultaneous sputtering via PVD (vapor deposition) or PLD (pulsed laser deposition).

[0106] At the end of the doping step 103' shown in step 104' of Figure 16, the active material layer 202' has become, for example, a layer 203' of HfO2 active material doped with Si.

[0107] Method 100' according to the present invention then includes step 105' (Figure 17) of conformally depositing a first conductive layer 204' on a layer 203' of doped HfO2 active material. This deposition is carried out exactly the same way in section Z1 for forming an OxRAM resistive random-access memory and in section Z2 for forming an FeRAM ferroelectric memory.

[0108] The conductive material of the first conductive layer 204 is, for example, titanium nitride (TiN). TiN is a non-limiting example, and other conductive materials such as TaN or W can also be used.

[0109] Deposition can be, for example, physical vapor deposition (PVD) or atomic layer deposition (ALD).

[0110] The thickness of the first conductive layer 204' is on the order of 10 nm or more.

[0111] Method 100' according to the present invention then includes step 106' of fabricating a mask 205' in a section Z2 of the first conductive layer 204' for forming a ferroelectric memory, while leaving a section Z1 of the first conductive layer 204' for forming an OxRAM resistive random-access memory open. The mask 205' is made of, for example, silicon nitride (SiN), silicon oxide (SiO2), or a resin. Thus, the mask 205' covers the portion of the first conductive layer 204' located in section Z2. In known methods, the mask 205' is, for example: - A hard mask is deposited to cover the first conductive layer in both section Z1 and section Z2; - By removing the hard mask portion in section Z1 while it is stopped on the first conductive layer 204', It can be manufactured. The removal step is performed, for example, by lithography and etching. For illustrative purposes, mask 205' is shown floating above pit 301, but this is not necessarily intended to show a hard mask floating above the pit. If the mask is made of resin (spin-off deposited), the resin will fill the pit, which does not alter the method described.

[0112] Therefore, at the end of step 106', only section Z1 of the first conductive layer 204' is directly accessible on the surface.

[0113] Method 100' includes step 107' of removing the first conductive layer 204' in a compartment Z1 of the first conductive layer for forming an OxRAM resistive random-access memory, while compartment Z2 of the first conductive layer 204' for forming a ferroelectric memory is protected by a mask 205'. This removal operation is performed, for example, by plasma etching the first conductive layer 204' of TiN, and the plasma etching of TiN is highly selective for HfO2 in the active layer 203' such that the etching stops on the HfO2 active layer 203' in compartment Z1.

[0114] Method 100' then includes step 108' of removing the mask 205' in section Z2 for forming a ferroelectric memory, while the mask is stopped on the first conductive layer 204'. At the end of step 108', the active layer 203' is exposed in section Z1 and covered by the first conductive layer 204' in section Z2. The operation to remove the mask 205' is performed, for example, using oxygen plasma ("oxygen stripping").

[0115] Method 100' then includes step 109' of conformally depositing a second conductive layer 206', the second conductive layer 206' in contact with the first conductive layer 204' in section Z2 for forming a ferroelectric memory and in contact with the active material layer 203' in section Z1 for forming an OxRAM resistive random-access memory. Step 109' also includes non-conformally depositing a third conductive layer 207', which is carried out in exactly the same way in section Z1 for forming an OxRAM resistive random-access memory and in section Z2 for forming a ferroelectric memory, the third conductive layer 207' in contact with the second conductive layer 206. The deposition of the third conductive layer 207' is non-conformal to fill the unfilled portions of pits 300 and 301, respectively.

[0116] The deposition of layers 206' and 207' is, for example, physical vapor deposition, i.e., PVD. The deposition method will be selected as conformal or non-conformal depending on the pit diameter. Conformal deposition is preferred when the pit diameter is typically less than 100 nm.

[0117] The conductive material for the third conductive layer 207' is, for example, titanium nitride (TiN). TiN is a non-limiting example, and other conductive materials such as TaN can also be used. Note that the material selected for the third conductive layer 207' may be different from the material selected for the first conductive layer 204'.

[0118] The thickness of the third conductive layer 207' must be such that pits 300 and 301' are completely filled.

[0119] The conductive material of the second conductive layer 206' is selected as a material ("oxygen exclusion layer") designed to pump oxygen into the active layer 203' located in section Z1 on which the second conductive layer 206' is deposited. By pumping oxygen into the active layer 206', the second conductive layer 206' creates oxygen depletion in the portion of the active layer 203' dedicated to creating the OxRAM, and oxygen depletion is necessary for the proper operation of the OxRAM. On the other hand, since the second conductive layer 206' is deposited on the first conductive layer 204' in section Z2 dedicated to the FeRAM, it does not come into contact with the active layer 203' in section Z2, and therefore does not create any depletion in the active layer 203' on the Z2 side. The material of the second conductive layer 206' is, for example, Ti or hafnium, when the material of the third conductive layer 207' is TiN. When the material of the third conductive layer 207' is TaN, it may also be tantalum-Ta hafnium. Note that Ti (Ta) is an excellent bonding material for the TiN (TaN) upper layer.

[0120] The thickness of the second conductive layer 206' is substantially the same as the thickness of the active layer 203', for example, between 5 nm and 10 nm.

[0121] According to step 110' of method 100' shown in Figure 22, the controlled chemical mechanical polishing (CMP) removal of all layers 207', 206', 203', and 201' is performed with the removal stopped at the top surface of pits 300 and 301.

[0122] According to step 111 of method 100 shown in Figure 10, two upper vias 208a' and 208b' are fabricated on a third conductive layer 207' at the level of compartment Z1 dedicated to OxRAM and compartment Z2 dedicated to FeRAM, respectively.

[0123] At the end of method 100' according to the present invention, a device is obtained that simultaneously integrates a ferroelectric memory located in a dedicated compartment Z2 and an OxRAM resistive random-access memory located in a dedicated compartment Z1. The ferroelectric memory is arranged three-dimensionally within a pit 301 whose inner wall is continuously covered by a first electrode (referred to as the lower electrode), a layer of hafnium dioxide HfO2 active material, and a second electrode (referred to as the upper electrode). Similarly, the OxRAM memory is arranged three-dimensionally within a pit 300 whose inner wall is continuously covered by a first electrode (referred to as the lower electrode), a layer of hafnium dioxide HfO2 active material, and a second electrode (referred to as the upper electrode). The lower electrodes of the FeRAM memory and OxRAM memory are formed by the same layer as the first electrode 201'. The layer of hafnium dioxide HfO2 active material of the FeRAM memory and OxRAM memory is formed by the same layer of doped HfO2 active material 203' crystallized in an orthorhombic phase.

[0124] The upper electrode of the FeRAM is formed by a triple layer comprising a first conductive layer 204', a second conductive layer 206', and a third conductive layer 207' in a pit 301 in a continuous manner.

[0125] The upper electrode of the OxRAM resistive random-access memory is formed by a double layer that continuously includes a second conductive layer 206' and a third conductive layer 207' within the pit 300.

[0126] According to an alternative embodiment of method 100' of the second embodiment of the present invention, between step 108' and step 109', it is possible to remove a portion of the thickness of the active layer in section Z1 dedicated to OxRAM and a portion of the thickness of the first conductive layer in section Z2 dedicated to FeRAM. This step is performed before the deposition of the second and third conductive layers.

[0127] As described above in Method 100 according to the first embodiment, in order to operate the active layer 203' as a ferroelectric memory in section Z2, the material of the active layer 203' needs to be crystallized in an orthorhombic phase.

[0128] The operations for memory formation, writing, and reading are the same as those described above.

[0129] According to a third embodiment of the method of the present invention, it is also possible to fabricate a two-dimensional OxRAM resistive random-access memory as described with reference to Method 100 of the first embodiment, and a three-dimensional ferroelectric memory (i.e., in pits to increase the capacitive surface area) as described with reference to Method 100' of the second embodiment of the present invention. [Explanation of Symbols]

[0130] 100, 100' way Steps 101-111 and 101'-111'. 200a, 200b, 200a', 200b' Beer 201, 201' Layer of the first electrode 202, 202' Layer of active material 203, 203' active layer 204, 204' First conductive layer 205, 205' Mask 206, 206' Second conductive layer 207, 207' Third conductive layer 208a, 208b, 208a', 208b' Upper via 300, 301 pits

Claims

1. 1. A method (100, 100') for simultaneously manufacturing a ferroelectric memory including a first electrode, a second electrode, and a layer of hafnium dioxide-based active material disposed between the first and second electrodes, and an OxRAM resistive memory including a first electrode, a second electrode, and a layer of hafnium dioxide-based active material disposed between the first and second electrodes, the method comprising: a step (101, 101') of depositing a layer (201, 201') of first electrodes, carried out identically for the section (Z1) intended to form the OxRAM resistive memory and for the section (Z2) intended to form the ferroelectric memory; a step (102, 102') of depositing a layer (202, 202') of hafnium dioxide-based active material, carried out identically for the zone (Z1) intended to form the OxRAM resistive memory and for the zone (Z2) intended to form the ferroelectric memory; a step (105, 105') of depositing a first conductive layer (204, 204') carried out identically for the zone (Z1) intended to form the OxRAM resistive memory and for the zone (Z2) intended to form the ferroelectric memory; - making (106, 106') a mask (205, 205') in a section (Z2) of the first conductive layer intended to form a ferroelectric memory, leaving open a section (Z1) of the first conductive layer intended to form an OxRAM resistive memory; a step (107, 107') of removing the first conductive layer (204, 204') in the section (Z1) of the first conductive layer intended to form the OxRAM resistive memory, the section (Z2) of the first conductive layer intended to form the ferroelectric memory being protected by a mask (205, 205'); - removing (108, 108') the mask (205, 205') in the sections (Z2) of the first conductive layer intended to form the ferroelectric memory; a step (109, 109') of depositing a second conductive layer (206, 206'), said second conductive layer (206, 206') being in contact with the first conductive layer (204, 204') in the section (Z2) of the first conductive layer intended to form a ferroelectric memory and in contact with the layer (203, 203') of active material in the section (Z1) of the first conductive layer intended to form an OxRAM, the material of the second conductive layer (206, 206') being chosen so as to create an oxygen vacancy in the active layer (203, 203') of the OxRAM when the second conductive layer is in contact with it, a step (109, 109') of depositing a third conductive layer (207, 207'), carried out identically for the zone (Z1) for forming the OxRAM and for the zone (Z2) for forming the ferroelectric memory, said third conductive layer (207, 207') being in contact with the second conductive layer (206, 206'); The method (100, 100') includes:

2. The step of creating a mask in a section of the first conductive layer for forming a ferroelectric memory, while leaving a section of the first conductive layer for forming an OxRAM resistive memory free, comprises the steps of: depositing a mask on the first conductive layer in a section of the first conductive layer intended to form a ferroelectric memory and in a section of the first conductive layer intended to form an OxRAM resistive memory; removing the mask in the section of the first conductive layer intended to form the OxRAM resistive memory, while leaving the mask in the section of the first conductive layer intended to form the ferroelectric memory; 2. The method of claim 1, comprising:

3. 3. A method according to claim 1 or 2, characterized in that at the end of the step (102, 102') of depositing a layer of hafnium dioxide-based active material, it comprises a step (103, 103') of doping the layer (202, 202') of active material, carried out identically for the section (Z1) intended to form an OxRAM resistive memory and for the section (Z2) intended to form a ferroelectric memory.

4. 4. The method of claim 3, wherein the doping step is performed by ion implantation, or by using a doping precursor, or by co-sputtering.

5. 4. The method of claim 3, wherein the dopant element used in the doping step is selected from one of the following: Si, Al, Zr, Gd, Ge, Y or N.

6. The dopant element is Si, and during the doping step, the layer of active material is １４ ions / cm ２ and 5.10 １４ ions / cm ２ 4. The method of claim 3, wherein the dopant is exposed to a dopant dose between 0.1 and 1.

0.

7. 1. A device including an OxRAM resistive memory located in a first dedicated partition and a ferroelectric memory located in a second dedicated partition, the ferroelectric memory comprises a first electrode, a second electrode and a layer of hafnium dioxide-based active material disposed between the first and second electrodes; the OxRAM resistive memory comprises a first electrode, a second electrode and a layer of hafnium dioxide-based material disposed between the first electrode and the second electrode; the bottom electrode of the OxRAM ferroelectric and resistance change memory is formed by the same first electrode layer present on the first dedicated section and on the second dedicated section; the layer of hafnium dioxide-based active material of the OxRAM ferroelectric and resistive memory is formed by a layer of the same hafnium dioxide-based active material present on the first dedicated section and on the second dedicated section, the second electrode of the ferroelectric memory is formed, in a second dedicated section, by a triple layer including a first conductive layer in contact with the active layer, a second conductive layer on the first conductive layer, and a third conductive layer on the second conductive layer; the second electrode of the resistive OxRAM is formed, in a first dedicated section, by a double layer including a second conductive layer in contact with the active layer and a third conductive layer on the first conductive layer; A device in which the material of the second conductive layer is selected so as to create an oxygen depletion in the active layer of the OxRAM resistive memory when the second conductive layer is in contact with the active layer of the OxRAM resistive memory.

8. 8. The device according to claim 7, characterized in that the thickness of the active layer and / or the thickness of the second conductive layer is between 3 nm and 15 nm.

9. 8. The device of claim 7, wherein the thickness of the third conductive layer is between 20 nm and 200 nm.

10. 8. The device of claim 7, wherein the ferroelectric memory comprises a pit having an inner wall with successively arranged layers of a first electrode, a layer of hafnium dioxide-based active material, and a triple layer including a first conductive layer, a second conductive layer, and a third conductive layer on the second conductive layer.

11. 11. A method for training and inference of an artificial intelligence system comprising a device according to any one of claims 7 to 10, characterized in that a ferromagnetic memory is used in the training phase and an OxRAM resistive memory is used in the inference phase.

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