Methods for polishing semiconductor substrates

Abstract

To provide methods for manufacturing a semiconductor structure that improve the wafer flatness by solving the problem with single side polishing methods often resulting in flatness worsened toward a wafer edge.SOLUTION: In a method for manufacturing a semiconductor structure, a polishing method 100 comprises alternately using a first polishing slurry and a second polishing slurry during polishing. The first and second polishing slurries each contain silica particles, where the silica particles of the first slurry contain more silica than the particles of the second slurry. The alternate use of the first and second polishing slurries improves the wafer flatness.SELECTED DRAWING: Figure 1

Description

Cross-reference to Related Applications

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 291,085, filed on December 17, 2021, which is hereby incorporated by reference in its entirety.

Technical Field

[0002] The field of the present disclosure relates to methods for polishing semiconductor substrates, and more particularly to methods for reducing the Site Total Indicated Reading (STIR) of polished semiconductor substrates.

Background Art

[0003] Semiconductor wafers are used in the production of semiconductor devices such as integrated circuit (IC) chips, silicon-on-insulator (SOI) wafers, and radio frequency - SOI (RF - SOI) wafers. Typically, the rough surface of a semiconductor wafer needs to be further processed to have characteristics that meet the stringent parameters for the manufacture of semiconductor devices such as IC chips, SOI wafers, and RF - SOI wafers.

[0004] Generally, the surface of a semiconductor wafer is polished to improve surface characteristics including the roughness and microdefects of the polycrystalline layer. One method of polishing a semiconductor wafer is called chemical mechanical polishing (CMP). In the CMP process, a circular polishing pad is often used. This pad is rotated, and the wafer is brought into contact with the pad while applying slurry to the pad and pressing it forcibly. However, the wafer contacts the pad unevenly, especially towards the wafer edge. Such uneven contact affects the surface characteristics after polishing, and the wafer may become unsatisfactory or additional processing may be required. For example, due to uneven contact between the pad and the wafer, the wafer may taper at high speed. STIR (Site Total Indicated Reading) measures the flatness of the wafer for each site. In a single-sided polishing method, STIR often deteriorates towards the wafer edge.

[0005] A method for manufacturing semiconductor structures that improves wafer flatness is needed.

[0006] This section is intended to introduce to the reader various aspects of the technology that may be relevant to the various aspects of the disclosure described and / or claimed below. We believe this discussion will be useful in providing the reader with background information to facilitate a better understanding of the various aspects of the disclosure. Therefore, please understand that these statements should be read in this context and not as an endorsement of prior art. [Overview of the project]

[0007] One aspect of the present disclosure relates to a method for polishing a semiconductor substrate having a surface and a back surface substantially parallel to the surface. The surface of the substrate is brought into contact with a polishing pad in the presence of a first polishing slurry in a first polishing step. The surface of the substrate is brought into contact with a polishing pad in the presence of a second polishing slurry in a second polishing step. The second polishing step is started after the first polishing step. The surface of the substrate is brought into contact with a polishing pad in the presence of a first polishing slurry in a third polishing step. The third polishing step is started after the second polishing step.

[0008] Various improvements to the features pointed out in relation to the above-described embodiments of this disclosure exist. Further features may also be incorporated into the above-described embodiments of this disclosure. These refined and additional features may exist individually or in any combination. For example, the various features discussed below in relation to any of the illustrated embodiments of this disclosure may be incorporated individually or in any combination into any of the above-described embodiments of this disclosure. [Brief explanation of the drawing]

[0009] [Figure 1] This is a block diagram of one embodiment of a method for polishing semiconductor structures. [Figure 2] This is a block diagram of another embodiment of a method for polishing semiconductor structures. [Figure 3] This is a block diagram of another embodiment of a method for polishing semiconductor structures. [Figure 4] This is a schematic diagram of one embodiment of a wafer polishing system. [Figure 5] This is a flowchart illustrating one embodiment of a method for processing semiconductor wafers. [Figure 6] This is a block diagram illustrating one embodiment of a method for polishing a semiconductor structure using multiple substrate polishing devices. [Figure 7] This graph shows the wafer edge removal profile when using a single slurry. [Figure 8] This is a graph illustrating one embodiment of the method disclosed herein and wafer edge removal by a conventional method. [Figure 9] This is a box plot of STIR and ECURV for a substrate processed according to Example 1. [Figure 10] This is a probability plot of STIR and ECURV for substrates processed according to Example 1.

[0010] Corresponding reference letters indicate the corresponding parts throughout the drawing. [Modes for carrying out the invention]

[0011] This application claims the interests of U.S. Provisional Patent Application No. 63 / 291,085, filed on 17 December 2021, which is incorporated herein by reference in its entirety.

[0012] The provisions of this disclosure relate to methods for polishing semiconductor substrates. Examples of substrates that can be polished according to the methods described herein include silicon substrates, such as single-crystal silicon semiconductor substrates. In some embodiments, the substrate is a multilayer substrate, such as a substrate having a layer of single-crystal silicon in it. Single-crystal silicon semiconductor substrates can be used to prepare electronic devices such as integrated circuit (IC) chips, silicon-on-insulator (SOI) wafers, and radio frequency-SOI (RF-SOI) wafers. In embodiments in which the substrate is used to manufacture SOI wafers, the SOI wafers can be manufactured by processes described in U.S. Patent No. 10,128,146. The substrate may have any diameter suitable for use by those skilled in the art, including wafers with diameters of, for example, 200 mm, 300 mm, greater than 300 mm, or 450 mm. In some embodiments, the substrate to be polished has a diameter of 200 mm.

[0013] Referring here to Figure 1 of the present application, an embodiment of the polishing method 100 of the present disclosure is shown. Method 100 includes polishing the surface of a substrate to achieve a desired surface roughness. The polishing step may be single-sided polishing (i.e., the back side is not polished), which is typical for processing a 200 mm substrate. Single-sided polishing can reduce the surface roughness of the wafer, as measured by atomic force microscopy (AFM), to less than about 2.0 Å at scan sizes of about 10 μm × about 10 μm to about 100 μm × about 100 μm. Single-sided polishing can even reduce the surface roughness to less than about 1.5 Å or less than about 1.2 Å at scan sizes of about 10 μm × about 10 μm to about 100 μm × about 100 μm. Single-sided polishing removes at least about 1 μm of material from the surface of the substrate, which is typical for processing a 200 mm substrate where a single polishing step is performed.

[0014] Single-sided polishing can be achieved, for example, by chemical mechanical planarization (CMP). CMP typically involves immersing the wafer in a polishing slurry and polishing the wafer with a polymer pad. A combination of chemical and mechanical means is used to smooth the wafer surface. Typically, polishing continues until a chemical and thermal steady state is achieved and the wafer achieves its target shape and flatness.

[0015] A suitable polisher for single-sided polishing can be obtained from Lapmaster SFT (e.g., LGP-708, Chiyoda-ku, Japan). According to embodiments of this disclosure, the pad used for single-sided polishing is a suede-type pad (also referred to as a polyurethane foam pad) such as the SURFIN pad from Fujimi (Kiyosu, Japan), the CIEGAL pad from Chiyoda KK (Osaka, Japan), or the SPM pad from Rohm and Haas. Polyurethane-impregnated polyethylene pads such as the SUBA pad, available from Rohm and Haas, can also be used.

[0016] The single-sided polishing 100 may be performed for at least 60 seconds, or at least 120 seconds, at least 180 seconds, or at least 240 seconds or more. The slurry flow rate may be in the range of approximately 100 ml / min to approximately 1,000 ml / min, and the pad pressure may be approximately 75 g / cm². 2 ~Approx. 125g / cm 2 While the range may be such, it should be understood that other polishing times, pad pressures, and slurry flow rates may be used without departing from the scope of this disclosure.

[0017] Referring to Figure 1, the polishing method includes a first polishing step 110 in which the surface of the substrate is brought into contact with a polishing pad in the presence of a first polishing slurry. In a second step 120, the surface of the substrate is brought into contact with a polishing pad in the presence of a second polishing slurry (i.e., the second step follows the first step in that the second polishing step is started after or corresponding to the cessation of the flow of the first polishing slurry). In a third step 130, the surface of the substrate is brought into contact with a polishing pad in the presence of the first polishing slurry in a third polishing step (i.e., the third polishing step is started after the second polishing step has been performed).

[0018] In some embodiments, each of the first and second polishing slurries is a polydisperse slurry containing colloidal silicon particles. The first slurry contains silica particles having a silica content of X1 wt%, and the second slurry consists of silica particles having a silica content of X2 wt%, where X1 is greater than X2. The silica particles in the first and second slurries may be amorphous silica and are generally spherical. The silica content of the particles can be varied by individually encapsulating the particles in each slurry with a polymer that differs in the degree of encapsulation (i.e., polymer thickness) between the two slurries (i.e., between the first and second slurries). The polymer reduces the silica content within the set of particles. In some embodiments, the ratio of X1 to X2 is at least about 2:1, or at least about 3:1, at least about 5:1, at least about 10:1, or even at least about 15:1. The difference between X1 and X2 (i.e., X1 minus X2) may be approximately 5 wt%, at least approximately 10 wt%, at least approximately 25 wt%, or at least approximately 50 wt%.

[0019] In some embodiments, the silica particles of the first slurry are individually polymer encapsulated. The polymer encapsulated silica particles may consist of at least about 50 wt% silica, or at least about 60 wt%, at least about 70 wt%, about 50 wt% to about 95 wt%, about 60 wt% to about 95 wt%, or about 70 wt% to about 90 wt% silica.

[0020] In some embodiments, the silica particles of the second polishing slurry are also individually encapsulated in a polymer. The silica particles of the second polishing slurry contain less than about 25 wt% silica, or, as in other embodiments, less than about 15 wt%, less than about 10 wt%, about 1 wt% to about 25 wt%, about 1 wt% to about 15 wt% or about 1 wt% to about 10 wt% silica.

[0021] The polymer used for encapsulating the silica particles of the first and / or second polishing slurries may be any of the polymers conventionally used in the field of substrate polishing, particularly silicon wafer polishing. The polymer may be a water-soluble polymer such as cellulose, substituted cellulose, modified starch or xanthan gum.

[0022] The silica particles of each of the first and second polishing slurries have an average particle size. The average diameter of the particles of both slurries can be less than about 100 nm, less than about 50 nm, about 10 nm to about 50 nm, about 20 nm to about 40 nm, or about 30 nm to about 40 nm. In some embodiments, the average diameter of the particles of the first polishing slurry is about 30 nm, and / or the average diameter of the particles of the second polishing slurry is about 35 nm.

[0023] Each polishing slurry is generally a polydisperse colloid in which solid phase silica particles are dispersed in a liquid phase. Suitable liquid phases include aqueous solutions. The slurry can contain additional components typical of polishing slurries used to polish single crystal silicon wafers.

[0024] In each of the three polishing steps 110, 120, and 130, the respective first or second slurry is used without delivering any other slurry to the polishing pad (i.e., only the first or second slurry is used). Each slurry may be delivered to the pad along with other liquids such as deionized water, caustic (e.g., KOH), and / or resins such as nonionic polyethylene oxide polymer (e.g., POLYOX, available from DuPont (Wilmington, DE)).

[0025] After single-sided polishing is complete, the wafer can be rinsed with water and dried. Furthermore, the wafer may be subjected to wet bench cleaning or spin cleaning. Wet bench cleaning may involve contacting the wafer with SC-1 cleaning solution (i.e., ammonium hydroxide and hydrogen peroxide) at an optional high temperature (e.g., about 50°C to about 80°C). Spin cleaning involves contact with HF solution and ozonated water and may be performed at room temperature.

[0026] In some embodiments, an additional polishing step is performed as part of the single-sided polishing. For example, as shown in Figure 2, the surface of the substrate is brought into contact with a polishing pad in the presence of a second polishing slurry in a fourth polishing step 140, which is initiated after the third polishing step 130.

[0027] Another embodiment of the polishing method 100 is shown in Figure 3. In addition to the first polishing step 110, the second polishing step 120, the third polishing step 130, and the fourth polishing step 140, in a fifth polishing step 150 which begins after the fourth polishing step 140, the surface of the substrate is brought into contact with a polishing pad in the presence of the first polishing slurry. Then, in a sixth polishing step 160 which begins after the fifth polishing step 150, the surface of the substrate is brought into contact with a polishing pad in the presence of the second polishing slurry.

[0028] The polishing steps described above may generally include overlapping amounts (for example, the second polishing slurry is applied while the first slurry is stopped). However, generally, each step includes a period in which only the respective slurry is introduced to the polishing pad (for example, the first polishing step uses the first slurry, not the second).

[0029] The polishing steps described above are generally performed with the same polishing pad used to contact the surface of the silicon substrate. The polishing steps are performed with the same polishing equipment.

[0030] In some embodiments, in addition to the polishing method 100 of the embodiments of the present disclosure described above, the semiconductor structure may be processed in additional steps and / or on additional polishing apparatus. For example, a substrate may be polished in a polishing system 200 (Figure 4) having a first polishing apparatus 202A, a second polishing apparatus 202B, and a third polishing apparatus 202C. Although each apparatus 202A, 202B, and 202C is shown in an integrated system 200, any one of apparatuses 202A, 202B, and 202C may be an independent unit. Although three apparatuses 202A, 202B, and 202C are shown and described, the polishing system 200 may include more or fewer apparatuses.

[0031] As shown in Figure 5, each substrate polishing apparatus 202A, 202B, and 202C includes a polishing pad 204 mounted on a pivotable table 206 and a substrate mounting apparatus 208 having a rotatable head 210 for mounting a semiconductor substrate 100 on the polishing pad 204. A ring 211 facilitates the positioning of the substrate 100 relative to the polishing pad 204. In a preferred embodiment, the substrate polishing apparatus 202 may include any number of polishing pads 204, substrate mounting apparatuses 208, and rings 211. In the illustrated embodiment, each substrate polishing apparatus 202 includes two substrate mounting apparatuses 208. The substrate mounting apparatus 208 holds the substrate 100 and brings the substrate 100 into contact with the polishing pad 204 as both the substrate 100 and the polishing pad 204 rotate. The polishing pad 204 polishes the surface 212 of the substrate 100 by abrasion using a polishing slurry 214 applied to the surface 216 of the polishing pad 204.

[0032] In the illustrated embodiment, each substrate polishing apparatus 202 includes a nozzle 218 for dispensing polishing slurry 214. Each apparatus 202 may include multiple nozzles for dispensing multiple slurries or liquids onto the polishing pad 204. In addition, different slurries 214 may be dispensed from any single nozzle 218 during the polishing process.

[0033] During polishing, the polishing slurry 214 is present while the surface of the substrate 100 is in contact with the polishing pad to help polish the surface 212 of the substrate 100. When the polishing pad 204 is pressed against the substrate 100, the polishing pad 204 works the slurry 214 against the surface 212 of the substrate 100, helping to remove material from the surface 212 of the substrate 100 simultaneously and uniformly, and improving the overall smoothness of the substrate 100. Once the surface 212 of the substrate 100 is polished, the silicon is removed, and some minor damage occurs to the surface 212 due to the polishing action of the slurry 214.

[0034] Figure 6 is a flowchart of an exemplary method 20 for polishing a semiconductor substrate using the system 200 shown in Figure 4 or a similar system. Method 20 generally includes positioning the substrate 100 (Figure 5) on a first substrate polishing apparatus 202A (Figure 4) for an initial "rough" polishing 50. The substrate 100 may be polished on the first substrate polishing apparatus 202A for any amount of time suitable for polishing a portion of the substrate 100 and / or achieving the desired smoothness. In some embodiments, the substrate 100 is polished on the first substrate polishing apparatus 202A so that its thickness is reduced by an amount in the range of about 1 μm to 10 μm, or between 6 μm and 7 μm. As a result, the warp and / or bow of the substrate 100 is reduced.

[0035] In the exemplary embodiment, the substrate 100 is moved from the first polishing apparatus 202A to the second polishing apparatus 202B for additional polishing, such as the single-sided polishing method 100 described above (for example, method 100 in Figures 1, 2, or 3). As described above, in some embodiments of the polishing method 100, the substrate 100 is polished on the second substrate polishing apparatus 202B so that its thickness is reduced by an amount in the range of about 1 μm to 10 μm, or 3 μm to about 4 μm. The substrate 100 may be polished on the second polishing apparatus 202B for any time suitable for polishing a portion of the substrate 100 and / or achieving the desired smoothness.

[0036] In polishing method 20, after polishing in the second apparatus 202B is completed, the substrate 100 is transferred to the third polishing apparatus 202C. In the third polishing apparatus 202C, polishing slurry is applied to the polishing pad 204 during the final "touch" or "flash" polishing of the substrate 100, improving the sub-micrometer roughness and substantially removing any remaining small defects on the surface 212 of the substrate 100. The final polish also maintains the flatness of the substrate and imparts a smooth, mirror-like finish to the surface 212 of the substrate 100, which is common for polished wafers and desired by many device manufacturers. This type of final polishing generally removes material less than about 1 μm or between about 0.25 μm and about 0.5 μm from the surface 212 of the substrate 100.

[0037] Compared to conventional methods for polishing substrates, the method of this disclosure offers several advantages. By using first and second polishing slurries alternately, the polishing method can improve wafer flatness, such as STIR measurement. Improved flatness reduces wafer rework and scrap. In some embodiments, the first and second slurries each contain silica particles, with the silica particles in the first slurry containing more silica than those in the second slurry. This results in the first slurry being a "coarse slurry" that removes a relatively large amount of material, while the second slurry is adjusted for edge roll-off control. By using the slurries alternately, flatness can be improved without worsening edge roll-off.

[0038] Examples The process described herein is further illustrated by the following embodiments, which should not be viewed as limiting.

[0039] Example 1: Effects of polishing slurry sequence Figure 7 shows the wafer edge removal profiles (normalized thickness) of two sets of single-crystal silicon wafers (200 mm) polished on one side with different polishing slurries containing polymer-encapsulated colloidal silica. Slurry 1 contained colloidal silica (Nalco DVSTS029) diluted with deionized water. The polishing slurry also contained KOH and POLYOX. The polymer-encapsulated silica particles contained approximately 80 wt% silica (the remainder being polymer) and had an average particle size of approximately 30 nm.

[0040] The second set of silicon wafers (200 mm) was also polished on one side with a colloidal silica slurry (Glanzox-3950) ("Slurry 2") diluted with deionized water, having an average particle size of approximately 35 nm. The polishing slurry also contained KOH and POLYOX. The polymer-encapsulated silica particles contained approximately 5 wt% silica (the remainder being polymer).

[0041] As shown in Figure 7, slurry 1 was more abrasive and removed more material. The second slurry resulted in improved edge roll-off.

[0042] The third set of silicon wafers (200 mm) were polished on one side with colloidal silica slurry according to the following recipe ("POR").

[0043] TIFF2023098845000002.tif52157 Table 1: Polishing recipe using slurry 2 after slurry 1

[0044] The fourth set of silicon wafers (200 mm) were polished on one side with colloidal silica slurry according to the following recipe ("novel").

[0045] TIFF2023098845000003.tif58170 Table 2: Polishing recipe when using slurry 1 and slurry 2 alternately

[0046] As shown in Figure 8, the method of arranging slurry 1 and slurry 2 alternately improves flatness and edge rolloff. Figure 9 shows box plots of STIR and ecurve (edge ​​rolloff deviation) for the new method ("Test") and the method without alternating slurry ("POR"). As shown in Figure 9, the method with alternating slurry improves STIR. Figure 10 shows probability plots of STIR and ecurve (edge ​​rolloff deviation). As shown in Figure 10, the method using alternating slurry shows improvements in STIR and ecurve.

[0047] As used herein, the terms “about,” “substantially,” “essentially,” and “approximately,” when used with dimensions, concentrations, temperatures, or other physical or chemical properties or ranges of properties, are intended to cover variations that may exist at the upper and / or lower limits of a property or range of properties, including, for example, variations resulting from rounding, measurement methods, or other statistical variations.

[0048] When describing elements or embodiments of the present disclosure, the articles “a,” “an,” “the,” and “said” are intended to indicate the presence of one or more elements. The terms “comprising,” “including,” “containing,” and “having” are intended to indicate comprehensiveness and imply that additional elements other than those listed may exist. The use of terms indicating specific orientations (e.g., “top,” “bottom,” “side”) is for explanatory convenience and does not require a specific orientation of the described items.

[0049] Various modifications can be made to the above-described structures and methods without departing from the scope of this disclosure, so all matters included in the above description and shown in the accompanying drawings are intended to be illustrative and not limiting.

Claims

1. 1. A method for polishing a semiconductor substrate having a front surface and a back surface generally parallel to the front surface, comprising: contacting a surface of the substrate with a polishing pad in the presence of a first polishing slurry in a first polishing step; contacting the surface of the substrate with a polishing pad in the presence of a second polishing slurry in a second polishing step, the second polishing step beginning after the first polishing step; and A method comprising: in a third polishing step, contacting the surface of the substrate with a polishing pad in the presence of the first polishing slurry, the third polishing step beginning after the second polishing step.

2. 2. The method of claim 1, further comprising contacting the surface of the substrate with a polishing pad in the presence of a second polishing slurry in a fourth polishing step, the fourth polishing step beginning after the third polishing step.

3. 3. The method of claim 2, further comprising contacting the surface of the substrate with a polishing pad in the presence of the first polishing slurry in a fifth polishing step, the fifth polishing step beginning after the fourth polishing step.

4. 4. The method of claim 3, further comprising contacting the surface of the substrate with a polishing pad in the presence of a second polishing slurry in a sixth polishing step, the sixth polishing step beginning after the fifth polishing step.

5. 2. The method of claim 1, wherein the polishing pad contacting the surface of the substrate in each polishing step is the same polishing pad.

6. The first polishing slurry is X １ % silica content by weight, and the second polishing slurry contains silica particles having a silica content of X ２ % silica content by weight, １ is X ２ The method of claim 1 .

7. X １ and X ２ 7. The method of claim 6, wherein the ratio of is at least about 2:

1.

8. X １ and X ２ 7. The method of claim 6, wherein the ratio of is at least about 10:

1.

9. X １ and X ２ 7. The method of claim 6, wherein the ratio of is at least about 15:

1.

10. X １ and X ２ The method of claim 6, wherein the difference between is at least about 5 wt%.

11. X １ and X ２ The method of claim 6, wherein the difference between is at least about 25 wt%.

12. X １ and X ２ The method of claim 6, wherein the difference between is at least about 50 wt %.

13. 7. The method of claim 6, wherein the silica particles of the first slurry and the silica particles of the second slurry are each polymer-encapsulated.

14. 10. The method of claim 1, wherein the backside is not polished while the front side is polished, and at least about 1 μm of material is removed from the front side of the substrate.

15. The method of claim 1 , wherein the substrate has a diameter of about 200 mm.

16. 2. The method of claim 1, wherein each abrasive slurry is a colloid.

17. 2. The method of claim 1, wherein the first polishing step, the second polishing step, and the third polishing step are each performed using the same polishing apparatus.

18. 18. The method of claim 17, wherein the polishing apparatus is a second polishing apparatus, and prior to the first polishing step, the substrate is placed on the first polishing apparatus, the surface of the substrate contacts a polishing pad of the first polishing apparatus in the presence of one or more second polishing apparatus slurries, and the substrate is transferred from the first polishing apparatus to the second polishing apparatus.

19. 15. The method of claim 14, further comprising transferring the substrate from the second polishing apparatus to a third polishing apparatus, the method comprising contacting the surface of the substrate with a polishing pad of the third polishing apparatus in the presence of one or more third polishing apparatus slurries.

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