Photoelectric conversion device

Abstract

To provide a photoelectric conversion device with which it is possible to cancel out the potential changes of a processing circuit and acquire high quality signals.SOLUTION: Provided is a photoelectric conversion device comprising a pixel array, a signal line to which a pixel signal is outputted from the pixel, a processing circuit that processes the pixel signal of the signal line, a switch that controls electricity conduction between the signal line and an input node of the processing circuit, and a control unit. The control unit carries out a first transition of causing the switch to transition at least from an off state to an on stage while the pixel signal is read out from the pixel to the signal line after floating diffusion is reset, and carries out, while a transfer transistor is performing a transfer, a second transition of causing the switch to go to an off state and transition from the off state to the on state after the transfer.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device.

Background Art

[0002] A CMOS image sensor (photoelectric conversion device) has a plurality of pixels including photoelectric conversion elements and a readout circuit that reads signals from these pixels. When the pixels are arranged in a two-dimensional vertical and horizontal pattern, in the horizontal direction, readout circuits corresponding to the number of pixels are arranged. The readout circuit has functions such as a gain function, a subtraction function, a sample-and-hold function, and an analog-to-digital conversion function.

[0003] Patent Document 1 proposes a method for preventing the potential fluctuation of the floating diffusion due to the transfer pulse φTX in the pixel from varying the input capacitance of the amplifier via the vertical signal line. Specifically, Patent Document 1 inserts a cutoff switch between the vertical signal line and the input capacitance of the column amplifier and turns off the switch so as to include the φTX period. The cutoff switch has a CMOS configuration including NMOS and PMOS, and by inputting pulses of opposite phases to their respective gates, the potential fluctuation of the input capacitance of the column amplifier due to φPVLOFF is canceled out.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Image sensors used in recent cameras and smartphones are becoming increasingly sensitive and gain-increasing. As a result, simply using a CMOS configuration for the cutoff switch and inputting out-of-phase pulses to each gate is becoming insufficient to cancel out potential fluctuations in the column circuit (processing circuit). Consequently, dark offset and dark shading may be introduced, potentially degrading signal quality.

[0006] Therefore, the present invention aims to provide a photoelectric conversion device that can cancel out potential fluctuations in the processing circuit and acquire high-quality signals. [Means for solving the problem]

[0007] A first aspect of the present invention is A pixel array having a plurality of pixels, each including a photodiode, a floating diffusion, and a transfer transistor that performs charge transfer of the photodiode, A signal line from which a pixel signal is output from the aforementioned pixel, A processing circuit for processing the pixel signals of the aforementioned signal lines, A switch that controls the conductivity between the signal line and the input node of the processing circuit, Control unit and Equipped with, The control unit, After the floating diffusion has been reset, and during the period in which the pixel signal is being read from the pixel to the signal line, a first transition is performed to transition the switch from at least the off state to the on state. During the period when the transfer transistor is performing the transfer, the switch is kept in the OFF state. After the transfer, a second transition occurs to transition the switch from the off state to the on state. conduct, This is a photoelectric conversion device characterized by the following features. [Effects of the Invention]

[0008] The present invention provides a photoelectric conversion device that can cancel out potential fluctuations in the processing circuit and acquire high-quality signals. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic diagram of the photoelectric converter in the first embodiment. [Figure 2] This is an equivalent circuit diagram of the unit circuit in the first embodiment. [Figure 3] This is a timing chart showing the read operation related to the example. [Figure 4] This is a timing chart showing the read operation in the first embodiment. [Figure 5] This is a timing chart showing the read operation in the second embodiment. [Figure 6] This is a timing chart showing the read operation related to the example. [Figure 7] This is a timing chart showing the read operation in the third embodiment. [Figure 8] This is an equivalent circuit diagram of the unit circuit in the fourth embodiment. [Figure 9] This is a timing chart showing the read operation in the fourth embodiment. [Figure 10] This is an equivalent circuit diagram within a unit circuit in the fifth embodiment. [Figure 11] This is a schematic diagram of the photoelectric conversion system in the sixth embodiment. [Figure 12] This is a schematic diagram of the photoelectric conversion system and mobile body in the seventh embodiment. [Modes for carrying out the invention]

[0010] <First Embodiment> Referring to FIGS. 1 to 4, an embodiment of a photoelectric conversion device (solid-state imaging device) according to the first embodiment of the present invention will be described. The photoelectric conversion device 101 shown in FIG. 1 has a pixel array 102. The pixel array 102 has a plurality of unit pixels 103, and the plurality of unit pixels 103 are arranged in a matrix. A plurality of vertical signal lines 104 are provided corresponding to pixel columns, and the pixels 103 in each column of the pixel array 102 output pixel signals via the vertical signal lines 104. Further, the pixels 103 in each row of the pixel array 102 are connected to a control signal line 105 and are driven based on a control signal supplied via the control signal line 105. A constant current load 106 is connected to the vertical signal line 104.

[0011] The photoelectric conversion device 101 further includes a control circuit 107, a vertical scanning circuit 108, a column circuit 109, a column ADC 110, a column memory 111, a horizontal scanning circuit 112, a DFE 113, and an output circuit 114. The control circuit 107 controls each block of the photoelectric conversion device 101. The vertical scanning circuit 108 selectively drives the control signal line 105. The column circuit 109 processes the signals on the vertical signal lines. The column ADC (analog-digital converter) 110 performs analog-digital conversion (hereinafter referred to as AD conversion) on the analog signal output from the column circuit 109. The column memory 111 in the column processing circuit holds the digital signal output from the column ADC 110. The horizontal scanning circuit 112 reads out the digital signal held in the column memory 111. The DFE (Digital Front End) 113 performs signal processing such as horizontal clamping on the digital signal read out from the horizontal scanning circuit 112. The output circuit 114 outputs the digital signal processed by the DFE 113.

[0012] Next, the configuration of the unit pixel 103 will be described. As shown in the partial enlarged view of FIG. 1, the unit pixel 103 includes a photodiode 115, a transfer transistor 116, a floating diffusion terminal (FD terminal) 117, a reset transistor 118, a source follower transistor 119, and a row selection transistor 120. The photodiode 115 photoelectrically converts incident light to generate charges corresponding to the amount of incident light. The transfer transistor 116 transfers the charges accumulated in the photodiode 1 15 to the FD terminal 117 according to the PTX signal supplied to the gate from the control signal line 105. The reset transistor 118 resets the charges of the FD terminal 117 according to the PRES signal supplied to the gate from the control signal line 105. The source follower transistor 119 outputs a voltage signal corresponding to the charges held in the FD terminal 117. The row selection transistor 120 outputs the pixel signal to the vertical signal line 104 according to the PSEL signal supplied to the gate from the control signal line 105.

[0013] FIG. 2 is a schematic diagram of an equivalent circuit diagram of the column circuit 109 and the column ADC 110.

[0014] The column circuit 109, which is a processing circuit, is configured by arranging a plurality of unit column circuits 201 in a plurality in the horizontal direction. The unit column circuit 201 includes a cutoff switch 202 and an amplifier 205, and amplifies and outputs the signal supplied from the vertical signal line (VL) 104, which is a signal line.

[0015] The disconnect switch 202 consists of an NMOS switch 202n and a PMOS switch 202p connected in parallel. The gate of the NMOS switch 202n is supplied with the control signal PVLON, and the gate of the PMOS switch 202p is supplied with the control signal PVLONB, which is its inverse phase signal. In other words, the NMOS switch 202n and the PMOS switch 202p are driven by signals with opposite logic levels. The disconnect switch 202 is provided between the vertical signal line 104 and the input node of the column circuit. When the disconnect switch 202 is ON, the vertical signal line (VL) 104 and the column circuit input terminal (VC0) 203 are connected, and when the disconnect switch 202 is OFF, the vertical signal line (VL) 104 and the column circuit input terminal (VC0) 203 are disconnected. In this way, the disconnect switch 202 controls the conduction and non-conductivity of the electrical path between the signal line and the input node of the processing circuit. The vertical signal line 104 is capacitively coupled via the cutoff switch 202, input terminal 203, and input capacitor (C0) 204 to the first input terminal (inverting input terminal) of the amplifier 205 of the processing circuit. Amplifier 205 is a capacitive feedback type amplifier, and its output is connected to the first input terminal (inverting input terminal) via the feedback capacitor (Cf) 206. The feedback capacitor 206 is a variable capacitor, and its capacitance value can be set by a control signal (not shown) supplied from the control circuit 107. The reset switch 207 is provided in parallel with the feedback capacitor 206 and is controlled by the control signal PC0R. The voltage VC0R is supplied to the second input terminal (non-inverting input terminal) of amplifier 205. The output of amplifier 205 is supplied to the column ADC 110 via the output terminal (VCAMPO) 208.

[0016] The column ADC 110 is composed of multiple unit column ADC circuits 209 arranged horizontally. Each unit column ADC circuit 209 has a comparator 211 that converts the analog signal supplied from the unit column circuit 201 into a digital signal and outputs it. The signal from the unit column circuit 201 is input to the first input terminal (inverting input terminal) of the comparator 211 via capacitor 210-1. The ramp signal VRAMP is input to the second input terminal (non-inverting input terminal) of the comparator 211 via capacitor 210-2. The capacitance values ​​of capacitors 210-1 and 210-2 are CIN-1 and CIN-2, respectively. The control signal PCOMPR is supplied to the gates of NMOS switches 212-1 and 212-2. The output of the comparator 211 is output to the column memory 111 via the output terminal (VCOMPO) 213.

[0017] Figure 3 is a timing chart showing a reference example of the readout operation of the photoelectric converter 101. Figure 3 shows the operation of reading out multiple 103-unit pixels arranged horizontally in a selected row, which is called the 1H operation. By performing this 1H operation on multiple rows, the pixel signals of all rows and all columns can be read out.

[0018] The readout operation and its challenges in this example will be explained below with reference to Figure 3. First, during the period t1 to t2, the pulse PRES becomes high and the reset transistor When 118 is turned on, the FD terminal 117 is reset to potential SVDD. Next, during period t3 to t14, PSEL becomes high, turning on the row selection transistor 120, and the source terminal of the source follower transistor 119 is electrically connected to the vertical signal line 104. Next, during period t4 to t5, PC0R becomes high, turning on the reset switch 207, and the input terminal (VC0) 203 and the output terminal (VCAMPO) 208 become potential VC0R, thereby initializing the row circuit.

[0019] During the period t3 to t8, when the potential vn1, which is the reset level of the FD terminal read out on the vertical signal line, is input to the input terminal (VC0) 203 of the column circuit, a potential vn2 is output to the output terminal (VCAMPO) 208 of the column circuit, which is an inverting circuit. Next, during the N-AD period t6 to t7, the potential vn2 of the VCAMPO terminal 208 is converted by the column ADC 110, and the digital signal vn2d, which corresponds to the potential vn2 at time tl1, is stored in the column memory 111. Here, time tl1 is the timing when the comparator 211 inverts when the vn2 input to the comparator 211 and the VRAMP signal become the same.

[0020] During periods t8 to t10, the cutoff switch 202 is turned off, disconnecting the vertical signal line (VL) 104 from the input terminal (VC0) 203 of the column circuit 203. As a result, the potential fluctuation at the FD terminal 117 caused by the pulse PTX transition in the following period t9 to t10 is transmitted to the vertical signal line (VL) 104, but not to the input terminal (VC0) 203 of the column circuit.

[0021] From period t10 onward, the signal from photodiode 115 is read out at FD terminal 117 and output as potential vs1 to vertical signal line (VL) 104. vs1 has an electrical signal superimposed on the reset potential vn1, which has been photoelectrically converted by the photodiode. In darkness, vn1 = vs1. Next, from period t11 onward, the cutoff switch 202 is turned on, and when vs1 is input to the input terminal (VC0) 203 of the column circuit, potential vs2 is output to the output terminal (VCAMPO) 208, which is the output of the column circuit, which is an inverting circuit. Then, during the S-AD period from t12 to t13, the potential vs2 at VCAMPO terminal 208 is AD converted by the column ADC 110, and the digital signal vs2d corresponding to the potential vs2 at time tl2 is held in the column memory 111. During the N-AD period from t6 to t7, the VRAMP ramp voltage is input to comparator 211, and the VCAMPO terminal is also input to comparator 211. At time tl1, when the VRAMP voltage and vn2 match, the comparator inverts, and the count value is stored in column memory 111 as vn2d. During the S-AD period from t12 to t13, at time tl2, when the VRAMP signal and vs2 are compared and match, comparator 211 inverts, and the count value is stored in column memory 111 as vs2d.

[0022] From period t14 onward, the digital values ​​vn2d and vs2d held in memory 111 are read out by the horizontal scanning circuit 112, input to DFE 113, and subjected to digital signal processing. A typical process is the subtraction operation vn2d-vs2d. After these digital signal processing operations, the values ​​are read out from the output circuit 114 to the outside of the photoelectric converter 101.

[0023] Here, we will explain the problems with the above read operation using the cutoff switch 202. According to the above read operation, as described in Patent Document 1, the cutoff switch 202 prevents fluctuations in the vertical signal line (VL) 104 due to PTX transitions from being input to the column circuit of the inverting circuit. However, Patent Document 1 does not consider the fact that the potential of the input terminal (VC0) 203 fluctuates slightly when the cutoff switch 202 is turned off and on.

[0024] NMOS transistor 202n and PMOS transistor constituting the cutoff switch 202 If the conditions for 202p are the same, then, since it is a CMOS configuration, minute fluctuations occurring at the input terminal (VCO) 203 can be canceled out. Therefore, the 104 vertical signal line potential VL will be the same during periods t6-t7 and t8-t11. The conditions for the NMOS transistor 202n and PMOS transistor 202p include, for example, their respective sizes, gate overlap capacitance, charge injection, and thresholds.

[0025] However, due to manufacturing constraints, the aforementioned conditions for transistors are not identical. Therefore, during the period t8 to t11, the potential of the vertical signal line (VL) 104 fluctuates slightly as shown in Figure 3. Also, in recent cameras and smartphones, increasing the gain of the readout circuit is often done as one way to improve sensitivity so that shooting can be done even in dark scenes. For example, the gain is applied using the amplifier 205 that constitutes the unit column circuit 201. The gain is determined by the capacitance ratio C0 / Cf, and the gain C0 / Cf is determined by controlling the variable capacitance of the feedback capacitance (Cf) 206 mentioned earlier. Because gain is applied in this way, the input capacitance 204, amplifier 205, feedback capacitance 206, and reset switch 207 that constitute from the VC0 terminal 203 to the VCAMPO terminal 208 are often collectively called a column amplifier.

[0026] When the gain C0 / Cf is a large value, for example, several tens to several hundreds of times, the operating band of the amplifier 205 becomes a low-frequency region, and the settling of the output VCAMPO of the column circuit 208 becomes very slow. Explained by the timing chart of FIG. 3, the potential fluctuation of the VC0 terminal 203 during the period t8 to t11 caused by the operation of the cutoff switch is fast, and the vn1 at time tl1 and the vs1 at time tl2 are at the same potential. However, the settling of the output VCAMPO of the column amplifier 208 to which the potential fluctuation of VC0 during the period t8 to t11 is input becomes very slow, and as shown in the partial enlarged view of FIG. 3, vn2 at time tl1 and vs2 at time tl2 have different potentials. That is, the relationship becomes vn2 < vs2. As a result, a dark offset occurs, and an accurate black level cannot be obtained, resulting in a problem that a high-quality image cannot be acquired.

[0027] Therefore, in the present disclosure, a method for canceling the dark offset caused by the on / off of the cutoff switch 202 is proposed.

[0028] FIG. 4 is a timing chart showing the readout operation in the photoelectric conversion device 101 according to the present embodiment. In the present embodiment, the operation period ta to tb of the cutoff switch is added to the readout operation shown in FIG. 3. The periods ta to tb are after the completion of the reset of the column circuit 208 and are provided before the N-AD period.

[0029] In this embodiment, the control circuit (control unit) 107 performs the following control: After the FD terminal 117 has been reset and while the pixel signal is being read to the vertical signal line 104, the cutoff switch is transitioned from the off state to the on state (first transition). Then, while the transfer transistor 116 is transferring the charge accumulated in the photodiode to the FD terminal 117, the cutoff switch 202 remains in the off state. Then, after the transfer by the transfer transistor 116 is completed, the cutoff switch 202 is transitioned from the off state to the on state (second transition). The cutoff by the first transition of the cutoff switch 202 occurs before the N signal (reset signal) is AD converted, and the N signal is AD converted (N-AD) after the first transition. The cutoff by the second transition of the cutoff switch 202 occurs before the S signal is AD converted, and the S signal is AD converted (S-AD) after the second transition.

[0030] During the period ta to tb after the FD terminal 117 is reset, PVLON is turned down at time ta and turned up at time tb to operate the cutoff switch 202. As a result, the output VCAMPO of the column amplifier 208 fluctuates in accordance with the potential fluctuation of the VC0 terminal 203 during the period ta to tb caused by the operation of the cutoff switch 202, and its static The static desettling is very slow. Therefore, vn2' at time tl1 is at a potential very close to or the same potential as vs2' at time tl2 during the subsequent period t8~t11. During the period t5~t8, a signal corresponding to the reset potential of FD terminal 117 is output from the column amplifier's output VCAMPO. By making the static desettling of the column amplifier's output VCAMPO after time tb the same degree as the static desettling after time t11, the column amplifier's output VCAMPO in Figure 4 becomes vn2' = vs2'.

[0031] The outputs vn2' and vs2' of the VCAMPO terminal 208 of the column amplifier are converted to digital signals vn2d' and vs2d' during the N-AD and S-AD periods, respectively. The digital signals vn2d' and vs2d' are stored in memory 111. The digital signals vn2d' and vs2d' are read out by the horizontal scanning circuit 112 after time t14. Subsequently, the digital signals vn2d' and vs2d' are input to DFE 113 and subjected to digital signal processing. A typical process is subtraction vn2d'-vs2d', which cancels the offset caused by insufficient static stability of the VCAMPO output of the column amplifier 208 due to the operation of the cutoff switch 202. As a result, a high-quality image with very little offset can be formed.

[0032] <Second Embodiment> A second embodiment of the present invention will be described with reference to Figure 5. Figure 5 is a timing chart showing the readout operation of the photoelectric converter 101 in this embodiment. The configuration of the photoelectric converter 101 is the same as in the first embodiment (Figures 1 and 2).

[0033] In this embodiment, the PVLON signal is transitioned during the period ta' to tb to activate the cutoff switch 202. Time ta' is the time between t4 and t5, when the amplifier 105 is being reset. In this embodiment, the cutoff switch is transitioned to the off state while the amplifier 105 is being reset, and the cutoff switch 202 is transitioned to the on state after the amplifier 105 has been reset. In the first embodiment (Figure 3), the PVLON signal is lowered between times t5 and t6, which is after the amplifier 105 has been reset, but in this embodiment, the PVLON signal is lowered while the amplifier 105 is being reset.

[0034] During the period t4-t5, the column amplifier is reset by the reset switch 207, becoming a unity-gain amplifier. Its operation is fast, and the VCAMPO terminal 208 settles quickly. The output VCAMPO outputs the voltage VC0R. Even if the cutoff switch 202 is operated during the period t4-t5, the VCAMPO terminal 208 does not fluctuate significantly, only outputting the voltage VC0R. Subsequently, at time tb, PVLON is started up, which activates the cutoff switch 202. As a result, the settling of the fluctuation in VCAMPO, the output of the column amplifier, which is caused by the potential fluctuation of the VC0 terminal 203 during the period tb-t8 due to the operation of the cutoff switch 202, is very slow. Therefore, vn2' at time tl1 is very close to or the same potential as vs2' at time tl2 during the subsequent period t8-t11. Therefore, vn2' at time tl1 is at a potential very close to or the same potential as vs2' at time tl2 during the subsequent period t8~t11. During the period t5~t8, a signal corresponding to the reset potential of the 117FD terminal is output from the output VCAMPO of the 208-row amplifier.

[0035] By making the statically settled output VCAMPO of the column amplifier after period tb the same degree of static stability as that at time t11, the output VCAMPO of the column amplifier in Figure 4 becomes vn2' = vs2'. Furthermore, in this embodiment, the time from period t5 to tb can be shortened, and the 1H period can be shortened, so the frame rate can be increased compared to the first embodiment.

[0036] <Third Embodiment> A third embodiment of the present invention will be described with reference to Figures 6 and 7. Figure 6 is a timing chart showing a readout operation according to a reference example for explaining the problem, and Figure 7 is a timing chart showing a readout operation according to this embodiment. The subscripts "L" and "R" in Figures 6 and 7 represent the signals in the left and right columns of the column circuit, respectively. The configuration of the photoelectric converter 101 is the same as in the first embodiment (Figures 1 and 2). The control circuit is located on the left side of the column circuit, and the control signal is supplied from the left side of the column circuit.

[0037] First, the problems addressed in this embodiment will be explained. In the photoelectric converter 101, control signals and voltages are supplied from the control circuit 107 to the column circuit 109, column ADC 110, column memory 111, and horizontal scanning circuit 112. Repeat buffers are placed in the column ADC 110 and column memory 111, which are supplied with high-speed control signals, in an effort to reduce the delay of the control signals. On the other hand, the column circuit 109 is a circuit block that mainly applies gain to analog signals and performs S / H operation, and like the pixel array 102, it is desirable that the pattern layout and other arrangements be made with a constant periodicity. This is because if repeat buffers are placed, the periodicity is disrupted, and fixed pattern noise (FPN) may be generated in the analog signal for each column circuit. Therefore, since the control signal PVLON to the column circuit 109 that handles analog signals is supplied from the left side of the control circuit 107, a delay occurs as shown in Figure 6. The right side, which is closer to the control circuit 107, is more delayed than the left side, so the transition period is delayed. Accordingly, the static determination of the VCAMPO terminal 208 is also delayed on the right side compared to the left. On the other hand, the signals supplied to the column ADC 110 and column memory 111 have reduced delay due to the repeat buffer, so the difference in AD conversion timing between the left and right sides is small. Therefore, the offset is larger for vs2'_R than for vs2'_L, resulting in dark shading.

[0038] Therefore, this disclosure proposes a method for canceling the dark offset that arises depending on the difference in delay amount for each column.

[0039] Figure 7 is a timing chart showing the readout operation in the photoelectric converter 101 of this embodiment.

[0040] During the period ta' to tb, the PVLON signal is transitioned to activate the cutoff switch 202. In this embodiment as well, since the control signal PVLON is supplied from the left side of the control circuit 107, a delay occurs as shown in Figure 7.

[0041] In the left-hand column circuit 109, the PVLON is activated at time tb, thereby activating the 202 cutoff switch. As a result, the output VCAMPO of the column amplifier 208 fluctuates in accordance with the potential fluctuation of the VC0 terminal 203 voltage over the period tb to t8 caused by the operation of the cutoff switch 202, and its settlement is very slow. Therefore, the vn2'_L at time tl1 is at a potential very close to or the same potential as vs2'_L at time tl2 during the subsequent period t8 to t11.

[0042] On the right side of the column circuit 109, the PVLON is started with a delay from time tb, thereby operating the 202 cutoff switch. Therefore, the potential fluctuation at terminal VC0 203 caused by the operation of the cutoff switch 202 is delayed compared to the period tb~t8. In response to the potential fluctuation at terminal VC0 203, the output VCAMPO of the column amplifier 208 fluctuates, and its settlement is very slow. Consequently, vn2'_R at time tl1 is at a potential very close to or the same potential as vs2'_R at time tl2 during the subsequent period t8~t11.

[0043] Here, vn2'_R is larger than vn2'_L, and vs Between 2'_L and vs2'_R, vs2'_R is larger. However, as mentioned earlier, since vn2'_L = vs2'_L and vn2'_R = vs2'_R, if AD conversion is performed by column ADC110 and then subtracted by DFE113, the left and right offsets are eliminated, and the dark shading is also eliminated. As a result, a high-quality image with very little offset and dark shading can be formed.

[0044] <Fourth Embodiment> A fourth embodiment of the present invention will be described with reference to Figures 8 to 9. Figure 8 is an equivalent circuit diagram and schematic diagram of the column circuit 109 and the column ADC 110 in the photoelectric converter 101 according to this embodiment. The column circuit 109 is composed of multiple unit column circuits 801 arranged horizontally, and the column ADC 110 is composed of multiple unit column ADC circuits 209 arranged horizontally.

[0045] Compared to the unit column circuit 201 of Embodiment 1 (Figure 2), the unit column circuit 801 lacks the input capacitor 204, amplifier 205, feedback capacitor 206, and reset switch 207 that constitute the column amplifier. In other words, the unit column circuit 801 consists only of a cutoff switch 202 to which the control signals PVLON and PVLONB (which is inverse phase) are supplied.

[0046] The unit sequence ADC circuit 209 is the same as in Embodiment 1 (Figure 2), so a detailed explanation is omitted. The unit sequence ADC circuit 209 receives the signal from the unit sequence circuit 801 via the AD input terminal (VADIN) 802 and outputs the digital signal after AD conversion to the sequence memory 111.

[0047] Thus, in this embodiment, the vertical signal line 104 is connected to the comparator 211 via the cutoff switch 202 and the capacitor 210-1.

[0048] Figure 9 is a timing chart showing the readout operation of the photoelectric converter 101 according to this embodiment. Even when there is no column amplifier in the column circuit 109 and the signal is not amplified, the transition of the AD input terminal (VADIN) 802 is delayed during the period t8 to t11. The reason for this is explained below. Capacitor 210-1 is driven by a source follower consisting of a source follower transistor 119 and a constant current load 106, which drives terminal VADIN 802 via a row selection transistor 120, a vertical signal line 104, and a cutoff switch 202. First, a parasitic resistance component RL is generated from the on-resistance of the row selection transistor 120, the on-resistance of the cutoff switch 202, and the wiring resistance of the vertical signal line 104 which is wired over a long distance within the pixel region 102. In addition, a parasitic capacitance component CL is generated from the vertical signal line 104 which is wired over a long distance within the pixel region 102. Furthermore, reducing the capacitance value of capacitor CIN-1 would decrease the signal amplitude input to comparator 211, thus requiring a capacitance value of several hundred fF to several pF. These parasitic resistance component RL, parasitic capacitance component CL, and capacitance CIN-1 (210-1) must be driven by a source follower. The size of the source follower transistor 119, which is placed within the unit pixel 103, is also limited and cannot be increased. Also, since the constant current load 106 requires many rows, the current value cannot be increased from the perspective of power consumption. Consequently, the terminal voltage VADIN (802) settles very slowly during the period t8 to t11 and after time t11. Therefore, vs2' does not settle at an ideal potential.

[0049] Therefore, in this embodiment, the control signal PVLON is transitioned during the period ta~tb as well, causing the terminal voltage VADIN(802) to stabilize in the period ta~tb and after time tb, similar to the period t8~t11 and after period t11. The resulting vn2' and vs2' are at very close or identical potentials. vn2' and vs2' are converted using AD during the N-AD period and S-AD period, respectively, and the digital signals vn2d' and vs2d' are stored in memory 111. The digital signals vn2d' and vs2d' are horizontally scanned after t14. The data is read from circuit 112. Subsequently, the digital signals vn2d' and vs2d' are input to DFE113, where digital signal processing is performed. A typical process involves subtraction vn2d'-vs2d', which cancels the offset caused by insufficient static stability of the terminal voltage VADIN resulting from the operation of the cutoff switch 202. As a result, a high-quality image with very little offset can be formed.

[0050] <Fifth Embodiment> A fifth embodiment of the present invention will be described with reference to Figure 10. In this embodiment, the configuration of the circuit breaker switch 202 differs from that of the first to fourth embodiments. This embodiment can be combined with any of the first to fourth embodiments.

[0051] As shown in Figure 10, the cutoff switch 202 of this embodiment has two CMOS switch circuits. The first CMOS switch circuit is configured by connecting an NMOS transistor 202n and a PMOS transistor 202p in parallel. The second CMOS switch circuit is configured by connecting an NMOS transistor 1001n and a PMOS transistor 1001p in parallel and is connected downstream of the first CMOS switch circuit. The NMOS transistor 202n and the PMOS transistor 202p have the same size (gate length and gate width), with the gate length being L and the gate width (channel width) being W. The NMOS transistor 1001n and the PMOS transistor 1001p are dummy switches with a gate length L and a gate width of W × 1 / 2, and their source and drain are short-circuited.

[0052] The control signal PVLON is supplied to the gates of NMOS transistor 202n and PMOS transistor 1001p. On the other hand, the inverse phase signal PVLONB is supplied to the gates of PMOS transistor 202p and NMOS transistor 1001n. In other words, a control signal with the opposite phase to the control signals supplied to the gates of NMOS transistor 202n and PMOS transistor 1001p is supplied to the gates of PMOS transistor 202p and NMOS transistor 1001n.

[0053] The presence of dummy switches 1001n and 1001p makes it extremely difficult for voltage fluctuations in VC0 to occur during the period t8 to t11 in Figure 3, even if the sizes, gate overlap capacitance, charge injection, and thresholds of the NMOS transistor 202n and PMOS transistor 202p differ slightly. Therefore, in the first to fourth embodiments, using the cutoff switches configured as shown in this embodiment further eliminates offset and dark shading. As a result, it is possible to form high-quality images with very little offset and dark shading.

[0054] Although the present invention has been described using the above embodiments, the present invention is not limited to the above embodiments and is effective in circuits equipped with a cutoff switch.

[0055] <Sixth Embodiment> A photoelectric conversion system according to a sixth embodiment of the present invention will be described with reference to Figure 11. Figure 11 is a block diagram showing the schematic configuration of the photoelectric conversion system according to this embodiment.

[0056] The photoelectric conversion device (CMOS image sensor) described in the first to fifth embodiments above is applicable to various photoelectric conversion systems. Applicable photoelectric conversion systems are not particularly limited, but examples include various devices such as digital still cameras, digital camcorders, surveillance cameras, photocopiers, fax machines, mobile phones, in-vehicle cameras, observation satellites, and medical cameras. Furthermore, a camera module comprising an optical system such as a lens and a photoelectric conversion device (photoelectric conversion device) is also included in the photoelectric conversion system. Figure 11 shows a block diagram of a digital still camera as an example of these.

[0057] As shown in Figure 11, the photoelectric conversion system 2000 comprises an imaging device 2001, an imaging optical system 2002, a CPU 2010, a lens control unit 2012, an imaging device control unit 2014, an image processing unit 2016, and an aperture shutter control unit 2018. The photoelectric conversion system 2000 also comprises a display unit 2020, an operation switch 2022, and a recording medium 2024.

[0058] The imaging optical system 2002 is an optical system for forming an optical image of a subject, and includes a lens group, an aperture 2004, etc. The aperture 2004 has the function of adjusting the amount of light during shooting by adjusting its aperture diameter, and also functions as a shutter for adjusting the exposure time when shooting still images. The lens group and the aperture 2004 are held so as to be able to move back and forth along the optical axis, and their coordinated movement realizes a magnification function (zoom function) and a focus adjustment function. The imaging optical system 2002 may be integrated with the photoelectric conversion system, or it may be an imaging lens that can be attached to the photoelectric conversion system.

[0059] The imaging device 2001 is positioned in the image space of the imaging optical system 2002 such that its imaging plane is located there. The imaging device 2001 is a solid-state imaging device (photoelectric converter) as described in the first to fifth embodiments, and is composed of a CMOS sensor (pixel section) and its peripheral circuit (peripheral circuit area). The imaging device 2001 is configured as a two-dimensional single-chip color sensor by arranging pixels, each having multiple photoelectric converters, in a two-dimensional arrangement, and arranging color filters for these pixels. The imaging device 2001 photoelectrically converts the subject image formed by the imaging optical system 2002 and outputs it as an image signal and a focus detection signal.

[0060] The lens control unit 2012 controls the forward and backward movement of the lens group of the imaging optical system 2002 to perform magnification and focus adjustment, and is composed of circuits and processing units configured to realize this function. The aperture shutter control unit 2018 adjusts the amount of light to be captured by changing the aperture diameter of the aperture 2004 (making the aperture value variable), and is composed of circuits and processing units configured to realize this function.

[0061] The CPU2010 is an internal control unit that manages various aspects of the camera body, and includes an arithmetic unit, ROM, RAM, A / D converter, D / A converter, communication interface circuit, etc. The CPU2010 controls the operation of each part of the camera according to the computer program stored in the ROM, etc., and executes a series of shooting operations such as AF (autofocus), imaging, image processing, and recording, including detection of the focus state of the imaging optical system 2002 (focus detection). The CPU2010 also functions as a signal processing unit.

[0062] The imaging device control unit 2014 controls the operation of the imaging device 2001 and performs A / D conversion on the signal output from the imaging device 2001 and transmits it to the CPU 2010. It is composed of circuits and control devices configured to realize these functions. The imaging device 2001 may also have an A / D conversion function. The image processing unit 2016 is a processing unit that generates an image signal by performing image processing such as gamma conversion and color interpolation on the A / D converted signal. It is composed of circuits and control devices configured to realize this function. The display unit 2020 is a display device such as a liquid crystal display (LCD) and displays information related to the camera's shooting mode, a preview image before shooting, a confirmation image after shooting, the focus status when focus is detected, etc. The operation switches 2022 consist of a power switch, a release (shooting trigger) switch, a zoom operation switch, a shooting mode selection switch, etc. The recording medium 2024 is for recording captured images, etc., and may be built into the photoelectric conversion system or may be a removable memory card, etc.

[0063] In this way, by configuring a photoelectric conversion system 2000 to which the imaging device 2001 according to Embodiments 1 to 5 is applied, a high-performance photoelectric conversion system can be realized.

[0064] <Seventh Embodiment> A photoelectric conversion system and mobile body according to a seventh embodiment of the present invention will be described with reference to Figures 12A and 12B. Figures 12A and 12B show the configuration of the photoelectric conversion system and mobile body according to this embodiment.

[0065] Figure 12A shows an example of a photoelectric conversion system 2100 related to an in-vehicle camera. The photoelectric conversion system 2100 has an imaging device 2110. The imaging device 2110 is one of the photoelectric conversion devices (solid-state imaging devices) described in Embodiments 1 to 4 above. The photoelectric conversion system 2100 has an image processing unit 2112 and a parallax acquisition unit 2114. The image processing unit 2112 is a processing unit that performs image processing on a plurality of image data acquired by the imaging device 2110. The parallax acquisition unit 2114 is a processing unit that calculates parallax (phase difference of parallax images) from a plurality of image data acquired by the imaging device 2110. The photoelectric conversion system 2100 also has a distance acquisition unit 2116, which is a processing unit that calculates the distance to an object based on the calculated parallax, and a collision determination unit 2118, which is a processing unit that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 2114 and the distance acquisition unit 2116 are examples of information acquisition means that acquire information such as distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 2118 may use any of this distance information to determine the possibility of a collision. The above-described processing unit may be implemented by specially designed hardware, or by general-purpose hardware that performs calculations based on software modules. Furthermore, the processing unit may be implemented by FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), etc., or by a combination thereof.

[0066] The photoelectric conversion system 2100 is connected to the vehicle information acquisition device 2120 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 2100 is also connected to the control ECU 2130, which is a control device that outputs a control signal to generate braking force on the vehicle based on the judgment result of the collision judgment unit 2118. In other words, the control ECU 2130 is an example of a mobile body control means that controls a moving object based on distance information. The photoelectric conversion system 2100 is also connected to the warning device 2140, which issues a warning to the driver based on the judgment result of the collision judgment unit 2118. For example, if the collision judgment result of the collision judgment unit 2118 indicates a high probability of collision, the control ECU 2130 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 2140 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0067] In this embodiment, the photoelectric conversion system 2100 images the area around the vehicle, for example, in front of or behind it. Figure 12B shows the photoelectric conversion system 2100 when imaging the area in front of the vehicle (imaging range 2150). The vehicle information acquisition device 2120 sends an instruction to the photoelectric conversion system 2100 to operate and perform imaging. By using the imaging device of Embodiments 1 to 3 described above as the imaging device 2110, the photoelectric conversion system 2100 of this embodiment can further improve the accuracy of distance measurement.

[0068] The above explanation described an example of control to prevent collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles, or control systems that automatically stay within their lanes. Furthermore, the photoelectric conversion system can be applied not only to vehicles such as automobiles, but also to mobile objects (transportation equipment) such as ships, aircraft, or industrial robots. The moving devices in mobile objects (transportation equipment) are various drive sources such as engines, motors, wheels, and propellers. In addition, it can be applied not only to mobile objects but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS).

[0069] (Other examples) The photoelectric converter may have a stacked structure (chip stacking structure) comprising a first semiconductor chip (first substrate) on which pixels are provided and a second semiconductor chip (second substrate) on which a readout circuit (amplifier) ​​or signal processing circuit is provided. The readout circuit (amplifier) ​​in the second semiconductor chip can be a column circuit corresponding to the pixel row of the first semiconductor chip. The readout circuit (amplifier) ​​is an example of a signal processing circuit, and other signal processing circuits may be provided on the second semiconductor chip. Furthermore, the readout circuit (amplifier) ​​in the second semiconductor chip can be a matrix circuit corresponding to the pixel or pixel block of the first semiconductor chip. Connections between the first and second semiconductor chips can be made using through-swivels (TSVs), direct bonding of metals such as copper (Cu) for chip-to-chip wiring, or connections between chips using microbumps. [Explanation of Symbols]

[0070] 103 Unit pixel 104 Vertical signal line 107 Control circuit 109-row circuit, 110-row ADC, 115-row photodiode 116 Transfer transistor 117 Floating diffusion 202 Shut-off switch

Claims

1. a pixel array having a plurality of pixels each including a photodiode, a floating diffusion, and a transfer transistor for transferring charge of the photodiode; A signal line through which a pixel signal is output from the pixel; a processing circuit for processing pixel signals from the signal lines; a switch for controlling conduction between the signal line and an input node of the processing circuit; A control unit; Equipped with The control unit is transitioning the switch to an off state after resetting the processing circuit, and then performing a first transition of transitioning the switch from at least an off state to an on state after resetting the floating diffusion during a period in which the pixel signal is being read out from the pixel to the signal line; The resetting of the processing circuit is performed after the resetting of the floating diffusion; The switch is turned off during a period in which the transfer transistor is performing a transfer; performing a second transition after the transfer, transitioning the switch from an off state to an on state; A photoelectric conversion device comprising:

2. the signal line is capacitively coupled via the switch to the processing circuit; 2. The photoelectric conversion device according to claim 1.

3. The processing circuit is a capacitive feedback amplifier.

3. The photoelectric conversion device according to claim 1 or 2.

4. The switch is composed of an NMOS transistor and a PMOS transistor connected in parallel, The NMOS transistor and the PMOS transistor are driven by signals having opposite logic levels.

4. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

5. The NMOS transistor and the PMOS transistor constituting the switch have the same size.

5. The photoelectric conversion device according to claim 4.

6. the first transition is performed before a reset signal, which is a pixel signal before being transferred by the transfer transistor, is AD converted; the second transition is performed after the reset signal is AD converted and before the pixel signal transferred by the transfer transistor is AD converted.

6. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

7. the signal lines are provided in a plurality in correspondence with pixel columns of the pixel array, the switch is provided for each of the signal lines, A control signal for controlling the switch is input from one side of the horizontal direction of the switch.

7. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

8. The switch is a first switch configured by connecting a first NMOS transistor and a first PMOS transistor having the same size in parallel; a second switch configured by connecting a second NMOS transistor and a second PMOS transistor in parallel, the channel width of which is half that of the first NMOS transistor and the first PMOS transistor; Including, The second switch is a dummy switch having a source and a drain shorted together, the second switch is provided between the first switch and an input node of the processing circuit; The gates of the first NMOS transistor and the first PMOS transistor are supplied with signals of opposite phases; The second NMOS transistor is supplied with a signal having an opposite phase to a signal supplied to a gate of the first NMOS transistor, The second PMOS transistor is supplied with a signal having an opposite phase to the signal supplied to the gate of the first PMOS transistor.

8. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

9. a first substrate on which the pixel array is provided; A second substrate on which the processing circuit is provided; 9. The photoelectric conversion device according to claim 1, wherein:

10. The photoelectric conversion device according to any one of claims 1 to 9, a signal processing unit that processes a signal output from the photoelectric conversion device; A photoelectric conversion system comprising:

11. The photoelectric conversion device according to any one of claims 1 to 9, A mobile device; a processing device that acquires information from a signal output from the photoelectric conversion device; a control device that controls the moving device based on the information; A moving object comprising:

Images