Method for manufacturing carrier substrate on semiconductor wafer and device including semiconductor wafer
Patent Information
- Application Number
- JP2023025774
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-02-25
- Filing Date
- 2023-02-22
- Publication Date
- 2026-02-27
AI Technical Summary
Semiconductor wafers exhibit uncontrollable and non-uniform mechanical curvature due to compressive and tensile stresses from previous processing steps, making further processing difficult and increasing the risk of breakage, especially during thinning and vacuum suction.
A method involving the application of a first layer on the semiconductor wafer's front side using a pressing technique, which includes a water-insoluble material, followed by UV irradiation or heat curing, to stabilize the wafer mechanically and even out stresses, allowing for reliable processing. This layer can be partially or fully applied and may include openings or additional materials for precise application and removal.
The method stabilizes the semiconductor wafer for subsequent processing, enabling reliable handling and testing, reduces stress-induced breakage, and allows for cost-effective processing by ensuring the wafer remains flat and stable throughout the manufacturing process.
Smart Images
Figure 00000000_0000_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a carrier substrate on a semiconductor wafer and an apparatus comprising a semiconductor wafer.
Background Art
[0002] Semiconductor components are produced with the aid of up to 600 individual processing steps. Often, semiconductor wafers have to be polished very thinly at the end of the manufacturing process. The disadvantage in this case is that these semiconductor wafers can have inherent compressive and tensile stresses due to various preceding individual processing and structuring and deep etching, such as trench etching in MOSFET / IGBT, so that after the semiconductor wafer has been polished thinly, a high degree of mechanical curvature is seen. This uncontrollable and non-uniform curvature makes further processing difficult and increases the risk of breakage several-fold up to the point where the thin semiconductor wafer can no longer be processed. This disadvantage can not only affect the handling of the wafer, but also makes it impossible to do what is inevitably required in subsequent processing, namely vacuum-sucking the thinned substrate.
Summary of the Invention
Problems to be Solved by the Invention
[0003] The problem of the present invention is to overcome this disadvantage.
Means for Solving the Problems
[0004] A method for manufacturing a carrier substrate on a semiconductor wafer according to the present invention, wherein the semiconductor wafer has a front surface and a back surface, the front surface faces the back surface, and the front surface shows the structured semiconductor wafer side having a contact area, comprises the step of coating at least one first layer on the front surface by pressing technology, wherein the at least one first layer comprises a first material that is water-insoluble, and the step of curing the at least one first layer by UV irradiation, heat or sintering.
[0005] The advantage in this case is that the semiconductor wafer is mechanically stabilized for subsequent processing steps, and the high stresses present due to the thick metal layer, passivation layer, and deep grooves within the semiconductor wafer are homogenized, allowing the semiconductor wafer to be finished with reliable processing until the end of the semiconductor component manufacturing chain. This means that even if the bending of the wafer is appropriately and locally constrained by the dedicated selection of the pressing medium and pressing process, it can be homogenized, thereby enabling stress-free bonding between the semiconductor substrate and the carrier substrate.
[0006] In an advanced form, an opening in the at least one first layer that partially exposes the contact area is generated by a laser. The advantage in this case is that the metallized surface and contact pad maintain contactability for testing purposes for PCM or WLT testing after thinning or metallizing the back surface. In addition, this processing step is very cost-effective.
[0007] In another development, the at least one first layer has a second material that is attached to the front surface above the contact area by a pressing technique, and an opening in the at least one first layer that partially exposes the contact area is created by removing the second material.
[0008] The advantage in this case is that the opening has a sharp or even sharper contour, which allows for a small opening despite a large layer thickness. In the advanced form, a structured planar layer is covered on the front surface, and the structured planar layer fills the recesses on the front surface.
[0009] The advantage in this case is that the mechanical pressure is more favorably distributed during the final wafer processing, particularly during the mechanical back polishing of the wafer, because the pressure during polishing is applied in a perfectly flat phase. If the surface of the pressurized carrier substrate is not flat, it can lead to breakage or uneven wafer thickness after polishing.
[0010] In another development, a medium-soluble, heat-soluble, or light-soluble layer is directly coated in some areas onto the surface. In other words, the layer can be peeled away from the substantial semiconductor substrate by a suitable liquid, or by thermal or light stimulation, or as a result, dissolve itself.
[0011] The advantage in this case is that the carrier substrate can be easily removed before or after wafer sawing, after the final wafer processing is complete. In the advanced form, the coating of the at least one first layer is performed multiple times, and the at least one first layer has a thickness of at least 5 μm, in particular, a thickness of 5 μm to 40 μm.
[0012] The advantage in this case is that the carrier substrate has high stability because an appropriate stress state is incorporated into it through the pressing medium and the pressing process. In another development, the coating of the at least one first layer is performed by inkjet technology, LIFT technology, DLP technology, or stereolithography, such that the at least one first layer includes a coating material.
[0013] The advantage in this case is that the coating material or coating medium can be precisely and directly adjusted and subjected to semiconductor processing via adjustment marks, regardless of whether they are lateral or Z-direction. Through the firm shape of the coating material in the target state, an effect contributing to the stabilization of the semiconductor wafer is induced. The advantage in this case is that these materials can form a mechanically stable carrier or mechanically stable carrier substrate with a defined shape after integration.
[0014] The apparatus includes a semiconductor wafer having a front and a back surface, wherein the front surface faces the back surface, and the front surface indicates a structured semiconductor wafer side having a contact area. According to the present invention, at least one first layer is disposed on the front surface, the at least one first layer comprises a first material that is insoluble in the medium, and the at least one first layer functions as a carrier substrate.
[0015] The advantage in this case is that the semiconductor wafer is mechanically stabilized for final wafer processing. In the advanced form, the at least one first layer has an opening that partially exposes the contact area.
[0016] The advantage in this case is that the contact area remains accessible for testing purposes during the machining process. In the advanced form, the at least one first layer has a thickness of at least 5 μm, in particular, a thickness of 5 μm to 40 μm.
[0017] The advantage in this case is that layers of different materials as the pressing medium, and post-treatment of those layers, can appropriately influence the stress balance of the entire system.
[0018] Further advantages will become apparent from the description of the embodiments below or from the dependent claims. Next, the present invention will be described based on preferred embodiments and the accompanying drawings. [Brief explanation of the drawing]
[0019] [Figure 1] A method for manufacturing a carrier substrate on a semiconductor wafer. [Figure 2] An example of a device having a semiconductor wafer. [Figure 3] Another embodiment of a device having a semiconductor wafer. [Modes for carrying out the invention]
[0020] Figure 1 shows a method 100 for manufacturing a carrier substrate on a semiconductor wafer, the semiconductor wafer having a front side and a back side, and the front side facing the back side. The front side shows the structured semiconductor wafer side with contact areas. Method 100 starts in step 130, where at least one first layer is coated on the front side by means of a pressing technique, and the at least one first layer is coated over the entire surface or has openings that partially expose or bare the contact areas, and the at least one first layer has a first material that is water-insoluble. In other words, after completion of the processing of the front side, a carrier layer or a carrier substrate is produced on the semiconductor wafer. In order to produce a thick carrier substrate, step 130 may be carried out continuously a plurality of times. The first layer can be peeled off from the actual semiconductor substrate by means of a suitable liquid, by means of a thermal or optical stimulus, or, as a result, can dissolve itself. In the next step 150, the at least one first layer is cured by UV irradiation, heat or sintering. If the first layer is coated a plurality of times, an optional final curing step or sintering step follows, so that complete integration of the first material is achieved, thereby improving the mechanical properties of the carrier substrate. Optionally, the at least one first layer is flattened by means of a squeegee in step 140, which is carried out between step 130 and step 150. The phase is filled between the wafer edge and the metal layer and the passivation layer including an organic passivation, for example polyimide and saw grain, to achieve the goal of realizing a completely flat plane of the carrier substrate after the pressing process.
[0021] Optionally, method 100 starts with step 120, which is carried out before step 130, and a structured flattening layer is coated on the front side. In so doing, the recesses on the front side are filled back or filled. As another option, method 100 optionally starts with step 110, which is carried out before any step 120 and before step 130, and a water-soluble layer is directly coated on the front side in some areas.
[0022] In the first embodiment, at least one first layer is structured and coated on the front surface, so that the opening is generated directly above the contact area. In the second embodiment, at least one first layer is coated over the entire surface. The opening is then generated by a laser. In another option, the opening is generated by further lithography steps and etching in downstream steps.
[0023] In the third embodiment, at least one first layer has a second material that is deposited simultaneously with the first material, and the second material is disposed on the front surface above the contact area. The second material may be media-soluble, or thermally or optically soluble. The opening is generated depending on the second material, by the aid of a liquid medium if the second material is media-soluble, or by thermal or optical stimulation if the second material is media-insoluble.
[0024] The coating of at least one first layer is performed, for example, by inkjet technology, laser-induced forward transfer (LIFT) technology, digital light processing (DLP) technology or stereolithography. The first material is media-insoluble and has, for example, an inorganic polymer-based pressing medium. At least one first layer has a layer thickness of at least 5 μm, in particular a layer thickness of 5 μm to 40 μm.
[0025] The carrier substrate may be removed again immediately after mechanical polishing of the back side of the wafer, or held on the semiconductor wafer until the final manufacturing step of dissolving the chip, and decomposed from the wafer by using a processing liquid, for example a solvent placed in a tank, and / or adding an additive, and / or irradiating light and / or applying heat. In another option, two processes can be combined, for example irradiation and supply of a solvent bath or heat. By doing so, the polishing film or protective film can be omitted when laser annealing the back side. The carrier substrate serves an additional protective role during the separation process, so no protective varnish is required. Thereby, dangerous stacking and delamination on very thin wafers are not performed.
[0026] Figure 2 shows an embodiment of an apparatus 200 comprising a semiconductor wafer 201 having a front surface 202 and a back surface 203. The front surface 202 faces the back surface 203. Active regions of semiconductor components are disposed on the front surface 202, and these active regions have contact regions 204. Optionally, a structured planarization layer 205 is disposed on the front surface 202 to equilibrate the recesses of the front surface 202. At least one first layer 206, which functions as a carrier substrate, is disposed on the contact regions 204. At least one first layer 206 has an opening 207. In another option, the first layer 206 covers the contact regions 204 as a whole surface. The carrier substrate can thus completely or partially mask or cover the semiconductor chip.
[0027] Figure 3 shows another embodiment of the apparatus 300 having a semiconductor wafer 301. In Figure 3, reference numerals whose later digits are the same as those in Figure 2 indicate the same components as in Figure 2. In addition, the apparatus 300 has a water-soluble layer 308 on the front surface 302, which serves as a sacrificial layer for removing the carrier substrate after the back surface processing is complete.
[0028] The carrier substrate is temperature stable, suitable for high vacuum, and does not deform. The semiconductor wafers 201 and 301 have, for example, a diameter of 150 mm, 200 mm, or 300 mm and include, for example, silicon, silicon carbide, sapphire, or QST as gallium nitride constituent elements.
[0029] The semiconductor wafers 201 and 301 have rounded edges. These edges are planarized and topologically filled with a pressing medium, resulting in a flat carrier substrate. Planarization is performed by a layer directly covering the front surface. This layer may be a planarization layer or at least one first layer 206 and 306. In other words, the front surface of the semiconductor wafer is planarized before the sealing layer is applied. Optional organic or inorganic planarization layers 205 and 305 serve to reduce wafer curvature during this process.
[0030] At least one first layer 206 and 306 is a pressing medium, i.e., it is made by pressing technology. The pressing medium has an organic or inorganic filler, for example, a mineral-based or ceramic-based filler. In other words, the pressing medium includes a coating material that is applied in a liquid to paste form and becomes a solid layer after a subsequent curing process.
[0031] In this case, the pressing medium having an inorganic component is, for example, a polymer-based one. The thickness of at least one first layer 206 and 306 is 5 μm to 40 μm for a single coating. By coating the first layer 206 and 306 multiple times, the carrier substrate can have a thickness of up to 1000 μm.
[0032] Since the contact areas 204 and 304 are exposed by openings 207 and 307 in at least one first layer 206 and 306, the resulting semiconductor component can be tested during subsequent finishing processes. At least one first layer 206 and 306 then acts as an insulator, so multiple test heads may be used during measurement, and the risk of electrical flashover at breakdown voltage > 1kV is reduced.
[0033] Apparatus 200 and 300 can be used when manufacturing power semiconductor components and power semiconductor modules having a chip thickness smaller than 180 μm during processing. [Explanation of symbols]
[0034] Apparatus with 200 semiconductor wafers 201 Semiconductor wafer 202 Front 203 Back 204 Contact area 205 Planarization layer 206 First Layer 207 Opening Apparatus with 300 semiconductor wafers 301 Semiconductor wafer 302 Front 303 Back 304 Contact area 305 Planarization layer 306 First Layer 307 Opening 308 Water-soluble layer
Claims
1. A method (100) for manufacturing a carrier substrate on a semiconductor wafer, the semiconductor wafer having a front surface and a back surface, the front surface facing the back surface, the front surface being a structured side of the semiconductor wafer having a contact area, comprising: - applying at least one first layer to said front surface by a pressing technique, said at least one first layer comprising a first material that is water insoluble; and - curing (130) said at least one first layer by UV irradiation, heat or sintering; A method (100) comprising:
2. 2. The method (100) of claim 1, wherein the openings in the at least one first layer partially exposing the contact areas are generated by a laser.
3. 2. The method (100) of claim 1, wherein the at least one first layer has a second material applied by a pressing technique over the contact area of the front surface, and an opening in the at least one first layer partially exposing the contact area is created by removing the second material.
4. The method (100) of claim 1, wherein a structured planarization layer is coated on the front surface, the structured planarization layer filling recesses in the front surface.
5. 2. The method (100) of claim 1, characterized in that a medium-fusible, heat-fusible or light-fusible layer is coated directly onto the front surface in some areas.
6. 2. The method (100) according to claim 1, characterized in that the coating (120) of the at least one first layer is performed multiple times, and the at least one first layer has a layer thickness of at least 5 μm, in particular a layer thickness of 5 μm to 40 μm.
7. 7. The method (100) according to any one of claims 1 to 6, characterized in that the coating (120) of the at least one first layer is performed by inkjet technology, LIFT technology, DLP technology or stereolithography, so that the at least one first layer comprises a coating material.
8. An apparatus (200, 300) comprising a semiconductor wafer (201, 301) having a front surface (202, 302) and a back surface (203, 303), said front surface (202, 302) facing said back surface (203, 303), said front surface (202, 302) presenting a structured semiconductor wafer side with contact areas (204, 304), The device is characterized in that at least one first layer (206, 306) is disposed on the front surface (202, 302), the at least one first layer (206, 306) comprising a first material that is insoluble in a medium, and the at least one first layer (206, 306) functions as a carrier substrate.
9. 9. The device (200, 300) of claim 8, characterized in that the at least one first layer (206, 306) has an opening that partially exposes the contact area.
10. 10. The device (200, 300) according to claim 8 or 9, characterized in that the at least one first layer (206, 306) has a layer thickness of at least 5 μm, in particular a layer thickness of 5 μm to 40 μm.