Multilayer ceramic capacitor and circuit board

Abstract

To provide a multilayer ceramic capacitor having a high reliability and provide a circuit board mounting them.SOLUTION: A multilayer ceramic capacitor comprises a ceramic element body, and first and second external electrodes. The ceramic element body includes: a capacity formation part including first and second internal electrodes and a ceramic layer; and a margin part including an end margin part and a side margin part. Each of the first and second internal electrodes includes: an end part constructed by a leading end part coming into contact with the first or second external electrode, and a margin end part coming into contact with the margin part; a first region where a continuous rate of a conductive component in a plan view from a second axial direction is a first continuous rate, and which is arranged along the margin end part; and a second region where the continuous rate of the conductive component in the plan view is a second conductive rate lower than the first conductive rate, and which is arranged in an inner side in a first axial direction and a third axial direction from the first region.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor and a circuit board on which the capacitor is mounted. [Background technology]

[0002] A multilayer ceramic capacitor includes, for example, a ceramic body having internal electrodes alternately drawn out and stacked on a pair of end faces and ceramic layers arranged between the internal electrodes, and a pair of external electrodes covering the pair of end faces, respectively, and connected to the internal electrodes (see Patent Documents 1 and 2). The ends of the internal electrodes other than the drawn-out ends connected to the external electrodes are covered by margins made of ceramic.

[0003] The edges of the internal electrodes covered by the margins may be located at the periphery of the region facing the adjacent internal electrodes in the stacking direction. Therefore, it is known that the electric field formed between the adjacent internal electrodes concentrates at these edges, making them prone to dielectric breakdown. For example, Patent Document 1 discloses a technique for reducing electric field concentration at the edges of the internal electrodes by making the ceramic layer thickness at the periphery of the internal electrode pattern thicker than that at the center. For example, Patent Document 2 discloses a technique for suppressing cracking and a decrease in withstand voltage at the outer edges of the internal electrodes by setting the porosity within a range of 5 to 15% within a region 20 times the thickness of the internal electrode from the outer edge of the internal electrode. This configuration is achieved by the migration of a common material made of ceramic powder contained in the internal electrode from the center of the internal electrode to its outer edge. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-111489 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-335726 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the technology described in Patent Document 1, the center of the laminate is pressed more strongly than the peripheral edge, which reduces the adhesion of the peripheral edge of the laminate, including the margin, raising concerns about delamination, cracks, etc. In the technology described in Patent Document 2, the porosity in the center of the internal electrode may be reduced, which raises concerns about delamination due to reduced adhesion between the ceramic layer and the internal electrode, and cracks due to differences in shrinkage rate during firing between the center of the internal electrode and the ceramic layer.

[0006] Furthermore, in recent years, multilayer ceramic capacitors have also been installed in electronic devices that require particularly high reliability, such as electric vehicles and medical equipment, and therefore there is a demand for highly reliable multilayer ceramic capacitors that can effectively suppress a decrease in insulation resistance.

[0007] In view of the above circumstances, an object of the present invention is to provide a highly reliable multilayer ceramic capacitor and a circuit board on which the same is mounted. [Means for solving the problem]

[0008] In order to achieve the above object, a multilayer ceramic capacitor according to one aspect of the present invention includes a ceramic body and first and second external electrodes. The ceramic body has first and second end faces perpendicular to a first axis direction, a capacitance generating portion, and a margin portion. The capacitance forming portion includes a first internal electrode extended to the first end surface, a second internal electrode extended to the second end surface and facing the first internal electrode in a second axis direction perpendicular to the first axis, and a ceramic layer disposed between the first and second internal electrodes. The margin portion includes a first end margin portion arranged between the first end face and the second internal electrode, a second end margin portion arranged between the second end face and the first internal electrode, and first and second side margin portions respectively arranged on both sides of the capacitance forming portion in a third axis direction perpendicular to the first axis and the second axis. The first and second external electrodes cover the first and second end faces, respectively. The first and second internal electrodes each include: an end portion including a lead end portion in contact with the first or second external electrode and a margin end portion in contact with the margin portion; a first region having a first continuity rate of the conductive component in a plan view seen from the second axis direction and arranged along the margin end portion; The continuity rate of the conductive component in the planar view is a second continuity rate lower than the first continuity rate, and the second region is positioned more inward in the first axis direction and the third axis direction than the first region.

[0009] In the above configuration, the first continuity ratio of the first region arranged along the marginal edge of the internal electrode is higher than the second continuity ratio of the second region. This suppresses spheroidization of the conductive component at and near the marginal edge, thereby suppressing dielectric breakdown due to electric field concentration. Furthermore, by relatively lowering the second continuity ratio of the second region, the adhesion between the ceramic layer and the second region is improved and their sintering behaviors can be made similar. This suppresses delamination, cracks, and other defects in the ceramic body, and also suppresses leakage currents associated with these structural defects. Therefore, the above configuration suppresses a decrease in the insulation resistance of the multilayer ceramic capacitor and improves reliability.

[0010] For example, the margin end portion includes a pair of side end portions contacting the first and second side margin portions, and an end end portion contacting the first or second end margin portion, The first region is From each of the pair of side ends, a pair of side regions located within 10% of the width dimension in the third axial direction of each of the first and second internal electrodes, From the end portions, an end region located within 10% of the length dimension in the first axial direction of the first and second internal electrodes, and including, The second region may occupy the region of each of the first and second internal electrodes excluding the first region. Thereby, a region where the electric field is particularly likely to concentrate can be made the first region, and dielectric breakdown due to the concentration of the electric field can be effectively suppressed. Also, by having the second region occupy a wide range of the internal electrodes, the effect of suppressing structural defects such as delamination and cracks in the ceramic element can be enhanced. Therefore, with the above configuration, the reliability of the multilayer ceramic capacitor can be more effectively enhanced.

[0011] In this case, the first continuity rate may be a value measured in the end region and / or the side region of the first region.

[0012] For example, the second continuity rate may be 70% or more. Thereby, a multilayer ceramic capacitor having a sufficient capacitance and good frequency characteristics such as impedance and Q value can be obtained.

[0013] The continuity rate of the conductive component may gradually decrease from the first region toward the second region. Thereby, the concentration of stress can be alleviated and the reliability of the multilayer ceramic capacitor can be further improved.

[0014] For example, when the value obtained by omega-converting the first continuity rate is a and the value obtained by omega-converting the second continuity rate is b, 0 < a - b ≤ 6.8 may be satisfied. By satisfying ab≦6.8, the difference in sintering behavior between the first and second regions due to the difference in continuity ratio can be reduced, and the generation of stress at the interface with the ceramic layer and the resulting occurrence of cracks, etc. can be suppressed, thereby more reliably improving the reliability of the multilayer ceramic capacitor.

[0015] For example, the first and second continuity rates are respectively: It may be calculated as the ratio of the area of ​​the conductive component that remains undissolved per unit area in each of the first and second regions after the ceramic body is immersed in an etching solution that dissolves ceramics but does not dissolve the conductive component. This makes it possible to clearly and simply calculate the first and second continuity rates of the conductive component in a plan view.

[0016] For example, the conductive component may include nickel, copper, palladium, platinum, silver, gold, tin, or alloys thereof.

[0017] Furthermore, the first region may contain at least one of silver, chromium, iridium, magnesium, molybdenum, osmium, palladium, platinum, rhenium, rhodium, ruthenium, yttrium, and tungsten as an additive.

[0018] For example, the thickness of the second region in the second axis direction may be 0.2 μm or more and 0.85 μm or less.

[0019] For example, the dimension of the multilayer ceramic capacitor in the first axis direction is 0.4 mm or less, The dimension of the multilayer ceramic capacitor in the third axis direction may be 0.2 mm or less.

[0020] For example, the dimension of each of the first and second side margin portions in the third axis direction may be 30 μm or less. For example, the dimension of each of the first and second end margin portions in the first axial direction may be 30 μm or less.

[0021] For example, the thickness of the ceramic layer may be 0.2 μm or more and 0.5 μm or less.

[0022] For example, the dimension of the multilayer ceramic capacitor in the second axis direction may be larger than at least one of the dimension of the multilayer ceramic capacitor in the first axis direction and the dimension of the multilayer ceramic capacitor in the third axis direction. According to the present invention, even in such a multilayer ceramic capacitor having a large dimension in the second axis direction, structural defects in the ceramic body can be suppressed, thereby improving reliability.

[0023] A circuit board according to another aspect of the present invention includes a ceramic capacitor and a mounting substrate on which the multilayer ceramic capacitor is mounted. The multilayer ceramic capacitor includes a ceramic body and first and second external electrodes. The ceramic body has first and second end faces perpendicular to a first axis direction, a capacitance generating portion, and a margin portion. The capacitance forming portion includes a first internal electrode extended to the first end surface, a second internal electrode extended to the second end surface and facing the first internal electrode in a second axis direction perpendicular to the first axis, and a ceramic layer disposed between the first and second internal electrodes. The margin portion includes a first end margin portion arranged between the first end face and the second internal electrode, a second end margin portion arranged between the second end face and the first internal electrode, and first and second side margin portions respectively arranged on both sides of the capacitance forming portion in a third axis direction perpendicular to the first axis and the second axis. The first and second external electrodes cover the first and second end faces, respectively, and are connected to the mounting substrate. The first and second internal electrodes each include: an end portion including a lead end portion in contact with the first or second external electrode and a margin end portion in contact with the margin portion; a first region having a first continuity rate of the conductive component in a plan view seen from the second axis direction and arranged along the margin end portion; The continuity rate of the conductive component in the planar view is a second continuity rate lower than the first continuity rate, and the second region is positioned more inward in the first axis direction and the third axis direction than the first region. [Effects of the Invention]

[0024] As described above, according to the present invention, it is possible to provide a highly reliable multilayer ceramic capacitor and a circuit board on which the same is mounted. [Brief explanation of the drawings]

[0025] [Figure 1] 1 is a perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention; [Figure 2] 2 is a cross-sectional view of the multilayer ceramic capacitor taken along line AA' in FIG. [Figure 3] 2 is a cross-sectional view of the multilayer ceramic capacitor taken along line BB' in FIG. [Figure 4] 3 is a cross-sectional view of a ceramic body of the multilayer ceramic capacitor, taken parallel to the X-axis direction (second axis direction) and Y-axis direction (third axis direction) at the position of a first internal electrode. FIG. [Figure 5] 3 is a cross-sectional view of a ceramic body of the multilayer ceramic capacitor, taken parallel to the X-axis direction (second axis direction) and Y-axis direction (third axis direction) at the position of a second internal electrode. FIG. [Figure 6] FIG. 2 is a cross-sectional view of a circuit board on which the multilayer ceramic capacitor is mounted. [Figure 7] 4 is a flowchart showing a method for manufacturing the multilayer ceramic capacitor. [Figure 8] 3A to 3C are plan views illustrating a manufacturing process of the multilayer ceramic capacitor. [Figure 9] 3A to 3C are perspective views illustrating a manufacturing process of the multilayer ceramic capacitor. [Figure 10]10 is a graph showing the results of an analysis using a Weibull distribution technique of the relationship between the difference (ab) between the omega-converted value (a) of the continuity rate A of the first region of the internal electrode and the omega-converted value (b) of the continuity rate B of the second region and the dielectric breakdown voltage (BDV) for examples and comparative examples of the above embodiment, where A shows the results for Weibull α, which is a parameter of the Weibull distribution, and B shows the results for Weibull β, which is another parameter of the Weibull distribution. DETAILED DESCRIPTION OF THE INVENTION

[0026] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings also show mutually orthogonal X-, Y-, and Z-axes, which define a fixed coordinate system fixed with respect to the multilayer ceramic capacitor 10.

[0027] [Overall structure of a multilayer ceramic capacitor] 1 to 3 are diagrams showing a multilayer ceramic capacitor 10 according to one embodiment of the present invention. Fig. 1 is a perspective view of the multilayer ceramic capacitor 10. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor 10 taken along line A-A' in Fig. 1. Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor 10 taken along line B-B' in Fig. 1.

[0028] The multilayer ceramic capacitor 10 includes a ceramic body 11, a first external electrode 14a, and a second external electrode 14b.

[0029] The ceramic body 11 is configured as a rectangular parallelepiped having a first end face 11a and a second end face 11b perpendicular to the X axis, a first side face 11c and a second side face 11d perpendicular to the Y axis, and a first main face 11e and a second main face 11f perpendicular to the Z axis. Note that the term "rectangular parallelepiped" means that the ceramic body 11 has a substantially rectangular parallelepiped shape, and for example, the ridges connecting the faces of the ceramic body 11 may be rounded.

[0030] The main surfaces 11e and 11f, the end surfaces 11a and 11b, and the side surfaces 11c and 11d of the ceramic body 11 are all flat surfaces. According to this embodiment, the flat surfaces do not necessarily have to be strictly planar as long as they are recognized as flat when viewed overall, and include, for example, surfaces with minute irregularities or gently curved shapes within a predetermined range.

[0031] The multilayer ceramic capacitor 10 of this embodiment has, for example, the following dimensions. The dimension of the multilayer ceramic capacitor 10 in the X-axis direction is, for example, 0.2 mm to 4.8 mm, and preferably 0.4 mm or less. The dimension of the multilayer ceramic capacitor 10 in the Y-axis direction is, for example, 0.1 mm to 3.5 mm, and preferably 0.2 mm or less. The dimension of the multilayer ceramic capacitor 10 in the Z-axis direction is, for example, 0.1 mm to 3.5 mm. Specifically, when the size of the multilayer ceramic capacitor 10 is expressed as (dimension in the X-axis direction) × (dimension in the Y-axis direction) × (dimension in the Z-axis direction), it may be 0.25 mm × 0.125 mm × 0.125 mm, 0.4 mm × 0.2 mm × 0.2 mm, or the like. Note that the "dimension" of the multilayer ceramic capacitor 10 in a certain direction refers to the maximum dimension of the multilayer ceramic capacitor 10 in that direction.

[0032] In the following description, the "inner side in the X-axis direction" refers to the side closer to an imaginary YZ plane that divides the multilayer ceramic capacitor 10 into two equal parts in the X-axis direction, and the "outer side in the X-axis direction" refers to the side away from the imaginary YZ plane. The "inner side in the Y-axis direction" refers to the side closer to an imaginary XZ plane that divides the multilayer ceramic capacitor 10 into two equal parts in the Z-axis direction, and the "outer side in the Z-axis direction" refers to the side away from the imaginary XZ plane.

[0033] The external electrodes 14a, 14b cover both end portions of the ceramic body 11 in the X-axis direction. For example, the first external electrode 14a shown in Figures 1 and 2 extends from the first end face 11a of the ceramic body 11 to both main faces 11e, 11f and both side faces 11c, 11d. The second external electrode 14b shown in Figure 1 extends from the second end face 11b of the ceramic body 11 to both main faces 11e, 11f and both side faces 11c, 11d. However, the shapes of the external electrodes 14a, 14b are not limited to this.

[0034] The ceramic body 11 has a capacitance generating portion 15, a first cover portion 16a, a second cover portion 16b, a first side margin portion 17a, a second side margin portion 17b, a first end margin portion 18a, and a second end margin portion 18b. In this embodiment, the first and second side margin portions 17a, 17b and the first and second end margin portions 18a, 18b constitute a margin portion M of the ceramic body 11 (see FIGS. 4 and 5).

[0035] The first and second cover portions 16a and 16b face each other in the Z-axis direction with the capacitance generating portion 15 interposed therebetween, and constitute the main surfaces 11e and 11f of the ceramic body 11.

[0036] The first and second side margin portions 17a and 17b are disposed on both sides of the capacitance forming portion 15 in the Y-axis direction. That is, the first and second side margin portions 17a and 17b face each other in the Y-axis direction with the capacitance forming portion 15 therebetween. Each of the side margin portions 17a and 17b is also referred to as a side margin portion 17.

[0037] The dimension of each side margin portion 17 in the Y-axis direction may be, for example, 30 μm or less, or 20 μm or less, in order to achieve a compact and large-capacity ceramic body 11. The dimension of each side margin portion 17 in the Y-axis direction may be, for example, 5 μm or more, in order to ensure insulation.

[0038] The first end margin portion 18a is disposed between the first end face 11a and the second internal electrode 13. The second end margin portion 18b is disposed between the second end face 11b and the first internal electrode 12. Each of the end margin portions 18a, 18b is also referred to as an end margin portion 18.

[0039] The dimension of each end margin portion 18 in the X-axis direction may be, for example, 30 μm or less, or 20 μm or less, in order to achieve a compact and large-capacity ceramic body 11. The dimension of each end margin portion 18 in the X-axis direction may be, for example, 10 μm or more, in order to ensure insulation.

[0040] The capacitance forming portion 15 includes ceramic layers 19 and first and second internal electrodes 12, 13 arranged between the ceramic layers 19. The first internal electrode 12 is extended to the first end face 11a. The second internal electrode 13 is extended to the second end face 11b and faces the first internal electrode 12 in the Z-axis direction. The ceramic layer 19 is arranged between the first and second internal electrodes 12, 13. That is, the first and second internal electrodes 12, 13 are alternately stacked in the Z-axis direction with the ceramic layer 19 interposed therebetween. In this embodiment, the ceramic layer 19 and the internal electrodes 12, 13 are each configured in a sheet shape extending along the XY plane.

[0041] The internal electrodes 12 and 13 contain a conductive component as a main component, typically nickel (Ni), but also copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), tin (Sn), and alloys thereof.

[0042] The first internal electrode 12 is connected to the first external electrode 14a at the first end surface 11a. The second end surface 11b side of the first internal electrode 12 is insulated from the second external electrode 14b by a second end margin 18b. The second internal electrode 13 is connected to the second external electrode 14b at the second end surface 11b. The first end surface 11a side of the second internal electrode 13 is insulated from the first external electrode 14a by the first end margin 18a.

[0043] With this configuration, when a voltage is applied between the external electrodes 14a and 14b in the multilayer ceramic capacitor 10, the voltage is applied to the plurality of ceramic layers 19 between the internal electrodes 12 and 13. As a result, a charge corresponding to the voltage between the external electrodes 14a and 14b is stored in the multilayer ceramic capacitor 10.

[0044] The ceramic layer 19 contains a dielectric ceramic as a main component. The dielectric ceramic contained in the ceramic layer 19 has, for example, a perovskite structure represented by the general formula ABO3. Examples of dielectric ceramics having a perovskite structure include materials containing barium (Ba) and titanium (Ti), such as barium titanate (BaTiO3).

[0045] Specifically, the dielectric ceramic may be composed of barium titanate, as well as strontium titanate (SrTiO3), calcium titanate (CaTiO3), magnesium titanate (MgTiO3), calcium zirconate (CaZrO3), calcium titanate zirconate (Ca(Ti,Zr,Ti)O3), barium calcium titanate zirconate ((Ba,Ca)(Ti,Zr)O3), barium zirconate (BaZrO3), titanium oxide (TiO2), or other compositions.

[0046] The ceramic layer 19, the cover portions 16a and 16b, the side margin portion 17, and the end margin portion 18 may have the same or different compositions. From the viewpoint of alleviating stress caused by differences in physical properties between the capacitance forming portion 15 and its surroundings, it is preferable that the cover portions 16a and 16b, the side margin portion 17, and the end margin portion 18 contain dielectric ceramics of the same composition system as the ceramic layer 19.

[0047] The thickness of each ceramic layer 19 in the Z-axis direction can be, for example, 0.2 μm or more and 20 μm or less, and preferably 0.2 μm or more and 0.5 μm or less. This allows the thickness of each ceramic layer 19 in the Z-axis direction to be equal to or greater than the grain size of the crystal grains of the dielectric ceramic, and increases the electrostatic capacitance. The thickness of the ceramic layer 19 is defined as the average value of thicknesses measured at multiple locations on the ceramic layer 19. As an example, a cross section of the ceramic body 11 parallel to the Z-axis direction is observed using a scanning electron microscope (SEM) or a transmission electron microscope (TEM). Six layers are selected from the ceramic layers 19 in the field of view, and the thicknesses are measured at five evenly spaced locations on each layer. The average value of the thicknesses obtained at 30 locations is defined as the thickness of the ceramic layer 19.

[0048] [Internal electrode configuration] 4 and 5 are cross-sectional views of the ceramic body 11. Fig. 4 shows an aspect cut parallel to the XY plane at the position of the first internal electrode 12, and Fig. 5 shows an aspect cut parallel to the XY plane at the position of the second internal electrode 13. In Figs. 4 and 5, the internal electrodes 12 and 13 are represented by hatching, and the margin portion M is represented by a dot pattern.

[0049] 4 and 5, each of the internal electrodes 12, 13 has an end portion E. The end portion E forms the peripheral portion in the X-axis direction and the Y-axis direction of the internal electrodes 12, 13. The end portion E is composed of a lead-out end portion E1 in contact with the first external electrode 14a or the second external electrode 14b, and a margin end portion E2 in contact with the margin portion M.

[0050] The lead-out end portion E1 is a portion of the end portion of the internal electrodes 12, 13 in the X-axis direction that contacts the external electrodes 14a, 14b. The lead-out end portion E1 of the first internal electrode 12 is located on the first end surface 11a. The lead-out end portion E1 of the second internal electrode 13 is located on the second end surface 11b. The margin end portion E2 is a portion of the end portion E excluding the lead-out end portion E1.

[0051] In this embodiment, the margin end E2 further includes a side end E21 that contacts the side margin portion 17 and an end end E22 that contacts the end margin portion 18. In Figures 4 and 5, the boundary between the side end E21 and the end end E22 is curved, but this is not limited to this and may be angular.

[0052] The margin end E2 is located on the periphery of the region where the internal electrodes 12 and 13 face each other. Therefore, the electric field formed between the internal electrodes 12 and 13 is concentrated, making it easy for dielectric breakdown to occur. In particular, as the thickness of the ceramic layers 19 decreases due to the miniaturization of the multilayer ceramic capacitor 10, dielectric breakdown due to the concentration of the electric field becomes even more likely to occur.

[0053] The concentration of the electric field at the margin end E2 is thought to be promoted by the spheroidization of conductive components such as Ni in the internal electrodes 12 and 13. The spheroidization of the conductive components occurs when the conductive components and the ceramics in the internal electrodes 12 and 13 are excessively sintered and shrink. When the conductive components at the margin end E2 become spheroidized, the spheroidized portions become convex, and the local thickness of the ceramic layer 19 may become thinner than the surrounding area. This makes dielectric breakdown more likely to occur. Furthermore, if a portion of the spheroidized conductive component becomes pointed, the electric field may concentrate at that point, causing dielectric breakdown. Furthermore, dielectric breakdown due to such electric field concentration becomes more likely as the ceramic layer 19 becomes thinner.

[0054] On the other hand, in regions where the continuity of the conductive component is high, the conductive component is less likely to become spherical. Therefore, in this embodiment, the continuity rate of the conductive component is locally increased along the margin end E2.

[0055] Specifically, in this embodiment, each of the internal electrodes 12 and 13 has a first region R1 arranged along the margin end E2 and a second region R2 arranged inward in the X-axis direction and the Y-axis direction from the first region R1. In Figures 4 and 5, the first region R1 is represented by dense hatching, and the second region R2 is represented by sparse hatching.

[0056] In the first region R1, the continuity of the conductive component in plan view is a first continuity A. On the other hand, in the second region R2, the continuity of the conductive component in plan view is a second continuity B that is smaller than the first continuity A. Note that "plan view" refers to the plan view when the surface of the internal electrodes 12, 13 extending along the XY plane is viewed from the Z-axis direction.

[0057] In this configuration, the continuity rate of the conductive component in the first region R1 along the margin end E2 is relatively high, which can prevent the conductive component from becoming spherical in the first region R1, thereby preventing dielectric breakdown at the margin end E2 and improving the reliability of the multilayer ceramic capacitor 10.

[0058] Furthermore, in the second region R2, which is located inside the first region R1 in the X-axis and Y-axis directions, the continuity rate of the conductive component is relatively low. This allows ceramic to fill the gaps in the conductive component of the second region R2, improving the adhesion between the ceramic layer 19 and the second region R2. This prevents delamination at the interfaces between the internal electrodes 12, 13 and the ceramic layer 19.

[0059] Furthermore, during firing, stress may occur due to the difference in shrinkage behavior between the ceramic layer 19 and the internal electrodes 12, 13 containing conductive components. In this embodiment, the proportion of ceramic in the second region R2 occupying the center of the internal electrodes 12, 13 can be relatively increased, and the shrinkage behavior of the second region R2 during firing can be made closer to that of the ceramic layer 19. This makes it possible to alleviate stress that occurs during sintering at the interfaces between the internal electrodes 12, 13 and the ceramic layer 19, and to suppress cracks due to this stress.

[0060] In this manner, this embodiment can also suppress leakage current due to structural defects such as delamination and cracks in the ceramic body 11. Therefore, in the multilayer ceramic capacitor 10, a decrease in insulation resistance due to such leakage current can also be suppressed.

[0061] Furthermore, by relatively lowering the continuity rate of the conductive component in the second region R2, it is possible to reduce the material cost for the conductive component compared to the case where the overall continuity rate of the internal electrodes 12, 13 is increased. As will be described later, the internal electrodes 12, 13 in this embodiment can be realized by devising the application of the conductive paste, the firing conditions, etc., and it is possible to suppress an increase in the number of steps and an increase in manufacturing costs.

[0062] In this embodiment, the continuity rates A and B in a plan view seen from the Z-axis direction are used as the continuity rates of the conductive components of the internal electrodes 12 and 13. That is, these continuity rates A and B are the continuity rates in the XY plane of the internal electrodes 12 and 13. By using the continuity rate in the XY plane, it is possible to accurately evaluate the effect of suppressing dielectric breakdown in the first region R1 and the effect of suppressing stress at the interface with the ceramic layer 19 in the second region R2.

[0063] An example of a method for calculating the continuity rates A and B in this embodiment will be described. First, the ceramic body 11 is immersed in an etching solution that dissolves ceramics but not conductive components. The etching solution is, for example, a hydrofluoric acid solution. The concentration of the hydrofluoric acid solution is preferably, for example, 2 to 20%. The immersion time is preferably 12 to 48 hours. As a result, the ceramics of the multilayer ceramic capacitor 10 dissolves, leaving behind the conductive components. In other words, the ceramics and other common materials contained in the internal electrodes 12, 13 also dissolve and disappear. The remaining portions of the internal electrodes 12, 13 made of conductive components have dispersed voids.

[0064] Next, the internal electrode is removed from the ceramic body 11 after immersion. Then, for the removed internal electrode, the ratio of the area of ​​the undissolved conductive component per unit area in each of the first region R1 and the second region R2 is calculated as the continuity ratios A and B. For example, the internal electrode after the treatment is imaged at a magnification of 200 to 2000 times using an SEM. Next, the ratio of the area of ​​the conductive component to the area of ​​each of the first region R1 and the second region R2 is calculated by image processing, and these values ​​are defined as the continuity ratios A and B. The areas of the first region R1 and the second region R2 include voids, and the area of ​​the conductive component is defined as the area of ​​only the portion consisting of the conductive component excluding the voids.

[0065] The continuity ratio A of the first region R1 may be measured in an end region R12 and a side region R11, which will be described later, or may be measured in either the end region R12 or the side region R11.

[0066] In this way, by calculating the continuity ratios A and B using a method of dissolving ceramics, it is possible to clearly and simply calculate the continuity ratios A and B of the conductive components in a plan view of the internal electrodes 12 and 13. In addition to the above method, an XY cross section exposing the internal electrodes 12 and 13 may be cut out from the multilayer ceramic capacitor 10, and the cross section may be enlarged and imaged using an SEM or the like. With this method, it is possible to calculate the continuity ratios A and B from the difference in appearance between the conductive components and other components.

[0067] Furthermore, in this embodiment, the second continuity ratio B of the second region R2 is preferably 70% or more, which makes it possible to obtain a multilayer ceramic capacitor 10 that not only has high reliability but also sufficient capacitance and good frequency characteristics such as impedance and Q value.

[0068] In this embodiment, the first continuity ratio A of the first region R1 is preferably 95% or less, which can reduce the burden of applying conductive paste to increase the first continuity ratio A and suppress an increase in the thickness of the first region R1.

[0069] On the other hand, the margin end E2 includes a side end E21 that contacts the first and second side margin portions 17a, 17b, and an end end E22 that contacts the end margin portion 18. The side end E21 is an end of the margin end E2 that extends, for example, in the X-axis direction. The end end E22 is an end of the margin end E2 that extends, for example, in the Y-axis direction.

[0070] For example, the first region R1 may include a side region R11 extending from the side end E21 and occupying a range within 10% of the width dimension W1 of the internal electrodes 12, 13 in the Y-axis direction, and an end region R12 extending from the end end E22 and occupying a range within 10% of the length dimension L1 of the internal electrodes 12, 13 in the X-axis direction. In this example, the dimension W2 of each side region R11 in the Y-axis direction is 10% of the width dimension W1 of the internal electrodes 12, 13. The dimension L2 of the end region R12 in the X-axis direction is 10% of the length dimension L2 of the internal electrodes 12, 13. The width dimension W1 and length dimension L1 of the internal electrodes 12, 13 are the maximum dimensions of the internal electrodes 12, 13 in the Y-axis direction and the X-axis direction, respectively.

[0071] In this example, the second region R2 occupies the area of ​​the internal electrodes 12, 13 excluding the first region R1. That is, the second region R is located at the center of the internal electrodes 12, 13 in the Y-axis direction, and its dimension W3 in the Y-axis direction is 80% of the width dimension W1 of the internal electrodes 12, 13. The dimension L3 of the second region R2 in the X-axis direction is 90% of the length dimension L1 of the internal electrodes 12, 13.

[0072] By setting the range of the first region R1 in this way, it is possible to surely increase the continuity rate of the region where electric field concentration is likely to occur. As a result, it is possible to suppress dielectric breakdown that occurs between the external electrodes facing each of the side region R11 and / or the end region R12. Further, by setting the range of the second region R2 in this way, the second region R2 will occupy a wide range of the internal electrodes 12 and 13. As a result, it is possible to sufficiently obtain the effect of reducing the difference in sintering behavior between the internal electrodes 12 and 13 and the ceramic layer 19 and the effect of enhancing the adhesion, and it is possible to effectively suppress the leakage current caused by delamination and cracks. Therefore, with this configuration, the reliability of the multilayer ceramic capacitor 10 can be further improved.

[0073] Furthermore, in the present embodiment, when the value obtained by omega-transforming the first continuity rate A of the first region R1 is a and the value obtained by omega-transforming the second continuity rate B of the second region R2 is b, it is preferable to satisfy 0 < a - b ≤ 6.8. The omega-transformed values a and b are expressed by the following equations using the continuity rates A and B. The units of A and B are %, and the units of a and b are dB (decibel). a = 10 × log(A / (100 - A)) b = 10 × log(B / (100 - B))

[0074] By evaluating the difference a - b between the values a and b obtained by omega-transforming the continuity rates A and B, it is possible to evaluate the difference between the continuity rates A and B using a scale that takes into account the values of the continuity rates A and B. That is, the value of a - b can be an index that reflects a more realistic effect than the value of A - B.

[0075] By making a - b greater than 0, the continuity rate A can be made greater than the continuity rate B, and as described above, the reliability of the multilayer ceramic capacitor 10 can be improved. Further, by setting a - b to 6.8 or less, it is possible to suppress the occurrence of cracks and the like at the interface with the ceramic layer 19 due to the large difference in sintering behavior between the first region R1 and the second region R2. As a result, as shown in the examples described later, the breakdown voltage (BDV) can be stably increased and the reliability can be improved.

[0076] Furthermore, by setting ab to be equal to or greater than 2.0 and equal to or less than 6.8, the effect of stably increasing the BDV can be more reliably obtained, and the reliability of the multilayer ceramic capacitor 10 can be further improved.

[0077] Furthermore, if the continuity ratio gradually decreases from the first region R1 toward the second region R2, stress concentration can be alleviated, and the reliability of the multilayer ceramic capacitor 10 can be further improved.

[0078] Furthermore, for example, the thickness of each of the internal electrodes 12, 13 in the second region R2 can be set to, for example, 0.2 μm or more and 0.4 μm or less, which allows the thickness of the internal electrodes 12, 13 to be reduced while maintaining the second continuity ratio B of the second region R2 at, for example, 70% or more, thereby enabling the multilayer ceramic capacitor 10 to be miniaturized and have an increased capacitance.

[0079] In this embodiment, the thickness of each of the internal electrodes 12, 13 in the first region R1 can be, for example, 1.05 to 1.2 times the thickness in the second region R2. By making the thickness in the first region R1 slightly thicker than the thickness in the second region R2, it is possible to suppress distortion of the ceramic body 11 due to imbalance in thickness between the internal electrodes 12, 13 while relatively increasing the first continuity rate A in the first region R1. This makes it possible to suppress cracks and the like due to distortion of the ceramic body 11, thereby more reliably improving reliability.

[0080] In order to relatively increase the first continuity ratio A of the first region R1, in addition to the method of adjusting the thickness of the first region R1 described above, the firing conditions may be adjusted or other methods may be used. The firing conditions will be described later.

[0081] The thickness of each of the first region R1 and the second region R2 of each internal electrode 12, 13 is the average value of thicknesses measured in the Z-axis direction at multiple locations in each region. As an example, the internal electrodes 12, 13 are observed in a cross section of the ceramic body 11 parallel to the Z-axis direction using an SEM or TEM. A field of view including six or more first regions R1 and six or more second regions R2 are selected. Six layers are selected from the internal electrodes 12, 13 in each field of view, and the thicknesses are measured at five evenly spaced locations in each layer. The average of the thicknesses measured at 30 locations in one field of view is then used to determine the thickness of the region included in that field of view. Alternatively, if the dimension of the multilayer ceramic capacitor 10 in the X-axis direction is, for example, 1 mm or larger and easy to handle, the internal electrodes can be removed from the ceramic body 11 after immersion in an etching solution and measured with a contact film thickness meter. In this case, the thickness is calculated in the same way as above: six layers are selected from the internal electrodes 12, 13, and the thicknesses are measured at five evenly spaced locations in each layer. The average of the thicknesses measured at 30 locations is then used to determine the thickness of the target region.

[0082] [Circuit board configuration] The multilayer ceramic capacitor 10 having the above configuration is mounted on, for example, a circuit board 100. Fig. 6 is a cross-sectional view of the circuit board 100 according to this embodiment.

[0083] The circuit board 100 includes a multilayer ceramic capacitor 10 and a mounting substrate 110 on which the multilayer ceramic capacitor 10 is mounted. The mounting substrate 110 has a mounting surface 111 including lands (connection electrodes) 111a. The external electrodes 14a, 14b of the multilayer ceramic capacitor 10 are connected to the lands 111a by, for example, solder H. As a result, the multilayer ceramic capacitor 10 is mounted on the mounting substrate 110 with the second main surface 11f of the multilayer ceramic capacitor 10 facing the mounting surface 111 in the Z-axis direction.

[0084] In such a circuit board 100, a voltage is applied to the external electrodes 14a, 14b from the mounting substrate 110. As described above, the multilayer ceramic capacitor 10 of this embodiment can suppress a decrease in insulation resistance, and therefore the reliability of the circuit board 100 can also be improved.

[0085] [Manufacturing method of multilayer ceramic capacitors] Fig. 7 is a flowchart showing a method for manufacturing the multilayer ceramic capacitor 10. Figs. 8 and 9 are diagrams showing the manufacturing process of the multilayer ceramic capacitor 10. The method for manufacturing the multilayer ceramic capacitor 10 will be described below with reference to these figures.

[0086] (Step S01: Prepare ceramic sheet) In this step, referring to Figures 8 and 9, a first ceramic sheet 101 and a second ceramic sheet 102 for forming the capacitance forming portion 15, and a third ceramic sheet 103 for forming the cover portions 16a and 16b are formed.

[0087] The ceramic sheets 101, 102, and 103 in this step are formed as unfired ceramic green sheets without internal electrodes or other components. First, the materials for the ceramic green sheets are mixed to obtain a slurry. The materials include a dielectric ceramic powder, a binder resin, and an organic solvent. The slurry obtained by pulverizing and mixing these materials is then formed into a sheet using a doctor blade method, a die coater method, a gravure coater method, or the like.

[0088] The thickness of the first and second ceramic sheets 101, 102 is adjusted according to the thickness of the fired ceramic layer 19. The thickness of the third ceramic sheet 103 is adjusted appropriately according to the thickness of the fired cover portions 16a, 16b.

[0089] (Step S02: Internal electrode pattern formation) In this step, referring to FIG. 8, internal electrode patterns 112 and 113 are formed on the first and second ceramic sheets 101 and 102 for forming the capacitance forming portion 15.

[0090] The internal electrode patterns 112, 113 are formed by applying a conductive paste to the ceramic sheets 101, 102. The first internal electrode pattern 112 corresponds to the first internal electrode 12 and is formed on the first ceramic sheet 101. The second internal electrode pattern 113 corresponds to the second internal electrode 13 and is formed on the second ceramic sheet 102.

[0091] The conductive paste used for the internal electrode patterns 112, 113 contains, for example, a conductive powder, a binder resin, an organic solvent, etc. The conductive powder is composed of nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), or a mixture or alloy thereof. Furthermore, the conductive paste preferably contains a ceramic material as a co-material. The ceramic material is, for example, a powder of dielectric ceramics.

[0092] 8, cut lines Lx and Ly are indicated on the ceramic sheets 101, 102, and 103 for separating the ceramic body 11. Each of the internal electrode patterns 112 and 113 is configured, for example, in a rectangular shape extending across one cut line Ly. The second internal electrode pattern 113 is formed to be shifted by one chip in the X-axis or Y-axis direction from the first internal electrode pattern 112.

[0093] In this embodiment, it is preferable to form the peripheral region Ru1 along the ends of the internal electrode patterns 112, 113 in the X-axis direction and the Y-axis direction thicker than the inner region Ru2 located inside the peripheral region Ru1 in the X-axis direction and the Y-axis direction. The peripheral region Ru1 corresponds to the first region R1, and the inner region Ru2 corresponds to the second region R2. Specifically, for example, the conductive paste may be applied to the peripheral region Ru1 multiple times.

[0094] For example, the thickness of the peripheral region Ru1 in the Z-axis direction can be set to be 1.05 to 1.2 times the thickness of the inner region Ru2 in the Z-axis direction, which makes it easier to relatively increase the first continuity ratio A in the first region R1 after firing.

[0095] (Step S03: Lamination) In this step, ceramic sheets 101, 102, and 103 are laminated together to form a laminated sheet 104, as shown in FIG.

[0096] 9, ceramic sheets 101 and 102 that form capacitance forming portions 15 are alternately stacked, and third ceramic sheets 103 are stacked above and below them in the Z-axis direction. These ceramic sheets 101, 102, and 103 are integrated by being pressure-bonded. The number of ceramic sheets 101, 102, and 103 is not limited to the example shown in FIG.

[0097] (Step S04: Cutting) In this step, the laminated sheet 104 is cut along the cut lines Lx and Ly to produce the unsintered ceramic body 11. For cutting, methods such as press cutting and blade dicing can be used.

[0098] (Step S05: Firing) In this step, the green ceramic body 11 is sintered, thereby producing the ceramic body 11 shown in FIGS.

[0099] The firing temperature can be determined based on the sintering temperature of the ceramic body 11. For example, when a barium titanate (BaTiO3)-based material is used, the firing temperature can be approximately 1000 to 1350° C. Furthermore, firing can be carried out, for example, in a reducing atmosphere or a low oxygen partial pressure atmosphere.

[0100] In this embodiment, in addition to increasing the thickness of the peripheral region Ru1, the first region R1 can be formed with relatively high continuity by adjusting the firing conditions as follows. Specifically, during the temperature increase process, it is preferable to maintain a low temperature range (e.g., 800°C or lower) at which the internal electrodes do not start to shrink for a long period of time (e.g., 95 minutes or more). This allows organic matter in the conductive paste to be sufficiently removed. Furthermore, it is preferable to shorten the firing time in a high temperature range (e.g., 800 to 1350°C) at which the internal electrodes start to shrink and sintering progresses. It is also preferable to use a more reducing atmosphere in the high temperature range than in the low temperature range. By making such adjustments in the high temperature range, it is possible to suppress spheroidization in the first region R1 of the internal electrodes 12, 13.

[0101] (Step S06: Forming external electrodes) In this step, external electrodes 14a, 14b are formed on both ends in the X-axis direction of the fired ceramic body 11, thereby producing the multilayer ceramic capacitor 10 shown in FIGS. 1 to 3. The method for forming the external electrodes 14a, 14b in this step can be selected from known methods. For example, a base film is formed by applying a conductive paste to both ends in the X-axis direction of the ceramic body 11 and baking it. Subsequently, one or more plating films are formed on this base film.

[0102] The multilayer ceramic capacitor 10 shown in Figures 1 to 3 is manufactured through the above steps. Note that the manufacturing method in this embodiment is not limited to the above example. For example, the application of the conductive paste in step S06 may be performed before the firing step in step S05. This allows the base film for the external electrodes to be formed simultaneously with the firing of the ceramic body 11.

[0103] [Examples and Comparative Examples] Examples and comparative examples of the above embodiment will be described. In Examples 1 to 6, samples of multilayer ceramic capacitors were produced under the condition that the continuity rate A of the first region of the internal electrode was greater than the continuity rate B of the second region. In Comparative Example 1, a sample of multilayer ceramic capacitor was produced under the condition that the continuity rate A of the first region of the internal electrode was smaller than the continuity rate B of the second region. The continuity rates A and B were adjusted by the thickness of the peripheral region of the internal electrode pattern and the firing conditions.

[0104] The size of the multilayer ceramic capacitor samples was 0.4 mm × 0.2 mm × 0.2 mm in all of Examples 1 to 6 and Comparative Example 1. In addition, in Examples 1 to 6 and Comparative Example 1, the configurations of the multilayer ceramic capacitor samples were substantially the same except for the continuity ratios A and B.

[0105] The continuity ratios A and B of Examples 1 to 6 and Comparative Example 1 were calculated using the method of immersing the multilayer ceramic capacitor in hydrofluoric acid (etchant) as explained in the above embodiment. The calculated continuity ratios A and B were then subjected to omega conversion to calculate a and b. The values ​​for Examples 1 to 6 and Comparative Example 1 are shown in Table 1.

[0106] [Table 1]

[0107] (Evaluation of breakdown voltage) Subsequently, the dielectric breakdown voltage (BDV) was measured using 20 samples each of Examples 1 to 6 and Comparative Example 1. The BDV was measured by applying a DC voltage at a rate of 10 V / second. The relationship between ab and BDV for each of Examples 1 to 6 and Comparative Example 1 was analyzed using the Weibull distribution method. Then, Weibull α and Weibull β, which are parameters of the Weibull distribution, were calculated for each of Examples 1 to 6 and Comparative Example 1. The results are shown in Table 1 and FIG. Weibull α indicates the quantile at which the cumulative failure rate is 63.2%, and Weibull β is a value that determines how the hazard (instantaneous failure rate) changes over time.

[0108] 10, the Weibull α of Comparative Example 1, in which the continuity rate A of the first region was smaller than the continuity rate B of the second region and ab was -1.1, was 289 V. In contrast, the Weibull α of Examples 1 to 6, in which the continuity rate A of the first region was larger than the continuity rate B of the second region, was 294 V or higher. This shows that the samples of Examples 1 to 6 tend to have a higher BDV than the sample of Comparative Example 1.

[0109] 10, the Weibull β of Comparative Example 1, in which the continuity rate A of the first region was smaller than the continuity rate B of the second region and ab was -1.1, was 6.1. In contrast, the Weibull β of Examples 1 to 6, in which the continuity rate A of the first region was larger than the continuity rate B of the second region, was 7.8 or greater. Since the larger the Weibull β, the smaller the BDV variation, the above results show that the samples of Examples 1 to 6 had smaller BDV variation than the sample of Comparative Example 1 and were more likely to achieve stable BDV.

[0110] Furthermore, in Examples 3 to 5 in which ab was 2.0 or more and 6.8 or less, the Weibull β was 15 or more, and it was found that the variation in BDV could be further reduced.

[0111] These results show that the samples of Examples 1 to 6 are less susceptible to a decrease in insulation resistance than the sample of Comparative Example 1, and have improved reliability.

[0112] [Other embodiments] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made within the scope of the gist of the present invention.

[0113] For example, the dimension of the multilayer ceramic capacitor in the Z-axis direction may be larger than at least one of the dimension of the multilayer ceramic capacitor in the X-axis direction and the dimension of the multilayer ceramic capacitor in the Y-axis direction. In other words, the multilayer ceramic capacitor according to the present invention may be a tall type in which the ratio of the dimension in the Z-axis direction is larger than the size exemplified in the above embodiment.

[0114] In such a tall multilayer ceramic capacitor, the capacitance forming portion including the internal electrodes becomes thick in the Z-axis direction, and stress is likely to occur due to the difference in sintering behavior between the internal electrodes and the surrounding ceramic portion. Furthermore, in the above configuration, the number of layers of the internal electrodes increases, and the cost of the conductive material used for the internal electrodes tends to have a significant impact.

[0115] Therefore, in the above configuration, by making the first continuity A of the first region of the internal electrode higher than the second continuity B of the second region, it is possible to suppress dielectric breakdown in the first region. Furthermore, by making the second continuity B of the second region relatively low, cracks and the like caused by the stress are suppressed, and in addition to being able to suppress leakage current, it is also possible to reduce the cost of the conductive material.

[0116] Furthermore, while increasing the thickness of the first region R1 and adjusting the firing conditions have been cited as methods for relatively increasing the continuity ratio A of the first region R1, other methods are not limited thereto. For example, conductive pastes containing different amounts of ceramic material may be used for the first region R1 and the second region R2. In this case, the amount of ceramic material in the conductive paste for forming the first region R1 (peripheral region Ru1) may be made smaller than the amount of ceramic material in the conductive paste for forming the second region R2 (inner region Ru2). For example, when the main material of the conductive paste for forming the first region R1 (peripheral region Ru1) and the second region R2 (inner region Ru2) is Ni, at least one of silver (Ag), chromium (Cr), iridium (Ir), magnesium (Mg), molybdenum (Mo), osmium (Os), palladium (Pd), platinum (Pt), rhenium (Re), rhodium (Rh), ruthenium (Ru), yttrium (Y), and tungsten (W) may be added only to the first region R1 (peripheral region Ru1). Alternatively, the additive may be added to both the first region R1 (peripheral region Ru1) and the second region R2 (inner region Ru2). In this case, the content of the additive in the first region R1 may be adjusted to be higher than that in the second region R2. [Explanation of symbols]

[0117] 10 Multilayer ceramic capacitors 11a,11b end face 12,13 Internal electrode 14a,14b External electrode 15 Capacity forming part 16a, 16b Cover part 17, 17a, 17b Side margin 18, 18a, 18b End margin M margin 19 ceramic layer E end E1 Drawer end E2 margin edge E21 Side end E22 end R1 1st area R11 Side Area R12 End Area R2 2nd area

Claims

1. first and second end surfaces perpendicular to the first axis direction; a capacitance forming portion including a first internal electrode extended to the first end surface, a second internal electrode extended to the second end surface and facing the first internal electrode in a second axis direction perpendicular to the first axis, and a ceramic layer disposed between the first and second internal electrodes; a margin portion including a first end margin portion arranged between the first end surface and the second internal electrode, a second end margin portion arranged between the second end surface and the first internal electrode, and first and second side margin portions respectively arranged on both sides of the capacitance forming portion in a third axis direction orthogonal to the first axis and the second axis; a ceramic body having first and second external electrodes covering the first and second end surfaces, respectively; Equipped with The first and second internal electrodes each include: an end portion including a lead end portion in contact with the first or second external electrode and a margin end portion in contact with the margin portion; a first region, the first region having a first continuity rate of the conductive component in a plan view seen from the second axis direction, the first region being disposed along the margin end portion; a second region having a continuity rate of the conductive component in the plan view that is lower than the first continuity rate, and disposed more inward than the first region in the first axis direction and the third axis direction; Multilayer ceramic capacitor.

2. 2. The multilayer ceramic capacitor according to claim 1, the margin end portion includes a pair of side end portions contacting the first and second side margin portions, and an end end portion contacting the first or second end margin portion, The first region is a pair of side regions located within 10% of the width dimension of each of the first and second internal electrodes in the third axis direction from each of the pair of side end portions; an end region located within 10% of the length of the first and second internal electrodes in the first axis direction from the end end portion, The second region occupies a region of each of the first and second internal electrodes excluding the first region. Multilayer ceramic capacitor.

3. 3. The multilayer ceramic capacitor according to claim 2, The first continuity ratio is a value measured in the end region and / or the side region of the first region. Multilayer ceramic capacitor.

4. 4. The multilayer ceramic capacitor according to claim 1, The second continuity ratio is 70% or more. Multilayer ceramic capacitor.

5. 5. The multilayer ceramic capacitor according to claim 1, The continuity rate of the conductive component gradually decreases from the first region toward the second region. Multilayer ceramic capacitor.

6. 6. The multilayer ceramic capacitor according to claim 1, When the value obtained by omega-converting the first continuity rate is a and the value obtained by omega-converting the second continuity rate is b, the value satisfies 0<a-b≦6.

8. Multilayer ceramic capacitor.

7. 7. The multilayer ceramic capacitor according to claim 1, The first and second continuity rates are, respectively, The ceramic body is immersed in an etching solution that dissolves ceramics but does not dissolve the conductive component, and the ratio is calculated as the ratio of the area of ​​the conductive component that remains undissolved per unit area in each of the first and second regions. Multilayer ceramic capacitor.

8. 8. The multilayer ceramic capacitor according to claim 1, The conductive component includes nickel, copper, palladium, platinum, silver, gold, tin, or an alloy thereof. Multilayer ceramic capacitor.

9. 9. The multilayer ceramic capacitor according to claim 8, The first region contains at least one of silver, chromium, iridium, magnesium, molybdenum, osmium, palladium, platinum, rhenium, rhodium, ruthenium, yttrium, and tungsten as an additive. Multilayer ceramic capacitor.

10. 10. The multilayer ceramic capacitor according to claim 1, The thickness of the second region in the second axis direction is 0.2 μm or more and 0.4 μm or less. Multilayer ceramic capacitor.

11. 11. The multilayer ceramic capacitor according to claim 1, a dimension of the multilayer ceramic capacitor in the first axis direction is 0.4 mm or less; The dimension of the multilayer ceramic capacitor in the third axis direction is 0.2 mm or less. Multilayer ceramic capacitor.

12. 12. The multilayer ceramic capacitor according to claim 1, The dimension of each of the first and second side margin portions in the third axis direction is 30 μm or less. Multilayer ceramic capacitor.

13. 13. The multilayer ceramic capacitor according to claim 1, The dimension of each of the first and second end margin portions in the first axial direction is 30 μm or less. Multilayer ceramic capacitor.

14. 14. The multilayer ceramic capacitor according to claim 1, The thickness of the ceramic layer is 0.2 μm or more and 0.5 μm or less. Multilayer ceramic capacitor.

15. 15. The multilayer ceramic capacitor according to claim 1, The dimension of the multilayer ceramic capacitor in the second axis direction is larger than at least one of the dimension of the multilayer ceramic capacitor in the first axis direction and the dimension of the multilayer ceramic capacitor in the third axis direction. Multilayer ceramic capacitor.

16. Multilayer ceramic capacitors, a mounting substrate on which the multilayer ceramic capacitor is mounted; Equipped with The multilayer ceramic capacitor comprises: first and second end surfaces perpendicular to the first axis direction; a capacitance forming portion including a first internal electrode extended to the first end surface, a second internal electrode extended to the second end surface and facing the first internal electrode in a second axis direction perpendicular to the first axis, and a ceramic layer disposed between the first and second internal electrodes; a margin portion including a first end margin portion arranged between the first end surface and the second internal electrode, a second end margin portion arranged between the second end surface and the first internal electrode, and first and second side margin portions respectively arranged on both sides of the capacitance forming portion in a third axis direction orthogonal to the first axis and the second axis; a ceramic body having first and second external electrodes covering the first and second end faces, respectively, and connected to the mounting substrate; and The first and second internal electrodes each include: an end portion including a lead end portion in contact with the first or second external electrode and a margin end portion in contact with the margin portion; a first region, the first region having a first continuity rate of the conductive component in a plan view seen from the second axis direction, the first region being disposed along the margin end portion; a second region having a continuity rate of the conductive component in the plan view that is lower than the first continuity rate, and disposed more inward than the first region in the first axis direction and the third axis direction; Circuit board.

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