Recording element substrate and recording device including recording element substrate

Abstract

To solve a problem of a conventional technology that disturbance of an input signal occurs due to an influence of a disturbance noise with respect to a signal before being input to the recording head, resulting in error operation of the recording head.SOLUTION: A recording element substrate includes: a plurality of memory modules each including a memory element and a drive circuit that drives the memory element; a plurality of discharge modules; and control data supply means that selects the memory modules or the discharge modules from the memory modules and the discharge modules and controls the selected modules to drive. The recording element substrate includes logical product operation means that inputs a first signal and a second signal that have been output at the same timing when the memory modules are selected, and supplies a signal indicating a logical product of the first signal and the second signal to the control data supply means. When the signal indicating the logical product of the first signal and the second signal is not supplied from the logical product operation means, the control data supply means does not control the memory module to drive.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a printing element substrate and a printing apparatus having the printing element substrate. [Background technology]

[0002] Generally, the recording element substrate mounted on the liquid ejection head is equipped with an OTP (One Time Programmable) ROM for recording unique information such as product information, setting information, etc. One example of an OTPROM is one that uses an anti-fuse element.

[0003] When recording or reading information in the antifuse elements on the recording element substrate, an external signal is input to a logic circuit including drive elements connected in series to the antifuse elements to select and control the drive elements. This external input signal includes, for example, a CLK signal, a DATA signal, and an LT signal (latch signal). The DATA signal is input serially to a shift register in synchronization with the edges of the CLK signal, and the shift register temporarily stores the input data corresponding to each drive element. When the LT signal is input to the latch circuit at a low level, the data stored in the shift register is loaded into the latch circuit, and when the LT signal is input at a high level, the data loaded into the latch circuit is retained. By repeating the above data transfer and driving of the antifuse drive elements, information is recorded or read from the antifuse elements. Furthermore, these drive element control signals are also used to control the heaters on the recording element substrate in thermal inkjet recording devices.

[0004] On the other hand, there is a demand for higher performance, such as higher speed, for inkjet recording devices. One method for increasing recording speed is to shorten the cycle time at which ink is ejected from the nozzles. However, shortening the cycle time means that many signals are transmitted at high frequencies, which can cause problems such as the effects of electromagnetic waves radiated from the signals.

[0005] In addition to the control signals mentioned above, thermal inkjet recording devices also require high currents to drive heaters and record anti-fuse elements, which flow from the recording device body to the print head via long flexible cables. This current-induced noise can interfere with other signals, potentially causing print head malfunctions. Therefore, it is essential to ensure resistance to noise induced by this current.

[0006] Patent Document 1 describes a circuit for verifying data input to a drive unit mounted on a recording head within the drive unit, and the circuit uses the circuit to detect malfunctions due to data transfer errors. Specifically, the print data is input to the calculation unit 80B with a delay of a number of clocks corresponding to the number of registers (number of bits stored) in the shift register array of the data transfer input unit 68 after the print data is input to the calculation unit 80A. The comparison unit 82 compares the parity data for the print data from bits 1 to 256 output from the 1-bit register 84 of the calculation unit 80A with the parity data for the print data from bits 1 to 256 output from the T-FF of the calculation unit 80B. If the two data match, the head drive unit 60 is determined not to be malfunctioning and continues printing. On the other hand, if the two data do not match, the head drive unit 60 is determined to be malfunctioning due to the influence of the aforementioned power supply noise or the like, and a predetermined process is executed. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent No. 4788280 Summary of the Invention [Problem to be solved by the invention]

[0008] However, the technology described in Patent Document 1 uses parity data to verify the data input to the drive unit mounted on the recording head, which poses a problem in that disturbance noise in the signal before it is input to the recording head can cause distortion of the input signal, potentially causing the recording head to malfunction.

[0009] An object of the present invention is to eliminate the influence of disturbance noise and the like on signals used to drive memory elements input to a recording element substrate, and to prevent malfunctions in driving memory elements. [Means for solving the problem]

[0010] In order to achieve the above object, a recording element substrate according to one aspect of the present invention has the following configuration: a recording element substrate having a plurality of memory modules, each including a memory element and a drive circuit for driving the memory element; a plurality of ejection modules; and control data supply means for selecting and driving a memory module or an ejection module from the plurality of memory modules and the plurality of ejection modules, The memory module has a logical product operation means for inputting a first signal and a second signal output at the same timing when the memory module is selected, and supplying a signal indicating the logical product of the first signal and the second signal to the control data supply means, and the control data supply means does not drive and control the memory module if a signal indicating the logical product of the first signal and the second signal is not supplied from the logical product operation means. [Effects of the Invention]

[0011] According to the present invention, it is possible to eliminate the influence of disturbance noise on the signal used to drive the memory element input to the recording element substrate, thereby preventing malfunction of the memory element drive.

[0012] Other features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings, in which the same or similar elements are designated by the same reference numerals. [Brief explanation of the drawings]

[0013] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. [Figure 1] FIG. 2 is a diagram showing the circuit configuration of the recording element substrate according to the first embodiment, and is a diagram showing the arrangement of discharge modules corresponding to even-numbered rows of discharge ports formed on the recording element substrate. [Figure 2] FIG. 2 is a diagram showing the circuit configuration of the recording element substrate according to the first embodiment, and is a diagram showing the arrangement of discharge modules corresponding to odd-numbered rows of discharge ports formed on the recording element substrate. [Figure 3] FIG. 3 is a circuit diagram showing an example of a circuit for preventing malfunction of an anti-fuse element formed on the recording element substrate according to the first embodiment. [Figure 4] 4A and 4B are diagrams showing examples of waveforms of input and output signals in the malfunction prevention circuit when one anti-fuse element is driven in the first embodiment. [Figure 5] FIG. 2 is a diagram illustrating the circuit configuration of the recording element substrate according to the first embodiment and the connection to the inkjet recording apparatus. [Figure 6] FIG. 10 is a diagram showing an example of a malfunction prevention circuit for an anti-fuse element formed on a recording element substrate according to a second embodiment of the present invention. [Figure 7] FIG. 10 is a diagram showing an example of input / output signal waveforms of the malfunction prevention circuit when one anti-fuse element is driven in the second embodiment. [Figure 8] FIG. 10 is a diagram showing an example of a malfunction prevention circuit for an anti-fuse element formed on a recording element substrate according to a third embodiment of the present invention. [Figure 9] FIG. 1 is a perspective view illustrating a liquid ejection head according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although the embodiments describe multiple features, not all of these features are necessarily essential to the invention, and multiple features may be combined in any desired manner. Furthermore, in the accompanying drawings, the same reference numerals are used to designate identical or similar components, and redundant description will be omitted. In the embodiments, a recording element substrate, a liquid ejection head, and a recording apparatus that eject liquid such as ink will be described with reference to the drawings. Note that, while a thermal-type recording element substrate will be used as an example of the present invention, the present invention is not limited to this, and can also be applied to a piezo-type recording element substrate.

[0015] [Embodiment 1] A first embodiment of the present invention will be described with reference to FIGS.

[0016] FIG. 9 is a perspective view illustrating a liquid ejection head (recording head) 200 according to an embodiment of the present invention.

[0017] This liquid ejection head 200 is formed with two recording element substrates 400 that eject liquid. The recording element substrate 400 has a heater (not shown) for heating the ink, and by heating the heater, bubbles are generated in the ink, causing the liquid to be ejected from the ejection openings (nozzles: not shown). The ejection openings are divided into even-numbered columns and odd-numbered columns, and the control circuits and power supply circuits are also separated for each.

[0018] Next, the circuit formed on the recording element substrate according to the first embodiment will be described with reference to FIGS.

[0019] 1 and 2 are diagrams showing the circuit configuration of the recording element substrate 400 according to embodiment 1. Here, Fig. 1 shows the arrangement of discharge modules 104 corresponding to even-numbered rows of discharge ports (not shown) formed on the recording element substrate 400, and Fig. 2 shows the arrangement of discharge modules 204 corresponding to odd-numbered rows of discharge ports (not shown) formed on the recording element substrate 400.

[0020] In FIG. 1, the printing element substrate 400 has two memory modules 106, a discharge module group having a plurality of discharge modules 104 corresponding to the discharge ports in the even-numbered columns, and a control data supply circuit 101.

[0021] The ejection module 104 includes pressure-generating elements (electrothermal conversion elements) Rh that generate energy for ejecting liquid from even-numbered rows of ejection ports (not shown) formed on the printing element substrate, as well as drive elements MD1 and a logic circuit AND1 for driving the pressure-generating elements Rh. In the first embodiment, the drive elements MD1 are MOS transistors. The MOS transistors function as switches that determine whether or not to apply voltage to the pressure-generating elements Rh. The logic circuit AND1 is an AND circuit that drives the drive elements MD1 based on signals from the control data supply circuit 101 and performs logical operations on multiple signals. Driving the drive elements MD1 energizes the pressure-generating elements Rh, generating heat, which generates bubbles in the ink and ejects the ink from the ejection ports, thereby performing printing. A power supply voltage VH1 (e.g., 24 V) is supplied to the pressure-generating elements Rh. A ground potential GNDH is supplied to the source side of the MOS transistor MD1.

[0022] The memory module 106 includes an antifuse element (memory element) Ca, a parallel resistor Rp (resistor) connected in parallel to the antifuse element Ca, and a drive circuit including a drive element MD2 and a logic circuit AND2 for writing information to the antifuse element Ca. The antifuse element Ca permanently retains information when an overvoltage is applied. That is, it functions as a one-time programmable read-only memory (OTP) (One-Time Programmable Read-Only Memory). The antifuse element Ca is in an insulating state before an overvoltage is applied, and becomes a resistive element (resistor) and conductive when an overvoltage is applied. Therefore, the antifuse element Ca can function as a memory by determining, for example, "0" when in an insulating state and "1" when in a conductive state. The parallel resistor Rp prevents information from being erroneously written to the antifuse element Ca when an overvoltage from the power supply voltage VID is applied across both ends of the antifuse element Ca even when the drive element MD2 is in a non-conductive state. The drive element MD2 is, for example, a transistor. When recording the information "1" in the antifuse element Ca, a voltage is applied to the antifuse element Ca by driving the driving element MD2, and the antifuse element Ca is energized by the applied voltage, thereby storing the information "1." A power supply voltage VID (e.g., 24 V) is supplied to the antifuse element Ca, and a ground potential GNDH is supplied to the source side of the MOS transistor MD2.

[0023] Here, the power supply voltage VID and the power supply voltage VH1 are on separate power supply lines, but if the minimum voltage required to write to the anti-fuse element is equal to or lower than the power supply voltage VH1, the power supply voltage VH1 may be used as the power supply voltage VID, for example, in combination with a step-down circuit.

[0024] The control data supply circuit 101 is a circuit for driving each of the drive elements MD1 and MD2, and includes, for example, a shift register (not shown) and a latch circuit (not shown). A clock signal (CLK), a data signal (DATA), a latch signal (LT), and a heat enable signal (HE) are input to the control data supply circuit 101 from outside the recording element substrate via the terminals of the recording element substrate. The data signal (DATA) includes information for selecting the ejection module 104 and the memory module 106. This data signal (DATA) is input in serial format in synchronization with the clock signal (CLK).

[0025] The control data supply circuit 101 receives a data signal (DATA) and generates a block selection signal, a group selection signal, and a switching signal based on the information included in the data signal (DATA). Based on these signals, the ejection modules 104 and memory modules 106 in the even-numbered columns are selected and driven. The control data supply circuit 101 supplies the block selection signal via signal line 102, the group selection signal via signal line 103, and the switching signal via signal line 105 to the logic circuits (AND1 to AND2).

[0026] Furthermore, in order to drive the discharge modules 104 and the memory modules 106 in a time-division manner, as shown in FIG. 1, the discharge modules 104 are divided into eight groups (G1, ..., G8), with three discharge modules 104 in one group. Furthermore, three blocks (1, 2, 3) are assigned to the discharge modules 104 in each group. In this way, the discharge modules 104 and the memory modules 106 can be selected and driven in a time-division manner. Furthermore, when reading the antifuse element, which will be described later, the memory modules 106 can be accessed in a time-division manner.

[0027] Here, the group selection signal is a signal for selecting which group to drive when the multiple discharge modules 104 are divided into multiple groups. The block selection signal is a signal for selecting which pressure generation element Rh to drive among the multiple pressure generation elements Rh in the same group. A DMOS (Double-diffused MOSFET) transistor, which is a MOS transistor that can withstand high voltage, is used for the drive element MD1. Note that in the embodiment, as an example, the multiple discharge modules 104 are divided into eight groups (G1, ..., G8) with three discharge modules in each group, but the present invention is not limited to this. For example, the discharge modules 104 may be divided into eight groups with 16 discharge modules in each group.

[0028] In this way, the control data supply circuit 101 can select and drive the antifuse element Ca using the signal lines 102 and 103. In this case, the switching signal line 105 is used. The switching signal from the switching signal line 105 switches between driving the antifuse element Ca and driving the ejection module 104. Therefore, a block selection signal, a group selection signal, and the switching signal 105 are input to the logic circuit AND2 of the memory module 106. A signal corresponding to the input signal is output from AND2 to the driving element MD2 of the memory module 106, driving the antifuse element Ca and switching it from an insulating state to a conducting state. The driving element MD2 of the memory module 106 is a DMOS transistor, as is the driving element MD1 of the ejection module 104. The logic circuit AND2 of the memory module 106 is composed of a MOS transistor. In the example of FIG. 1, the memory module 106 is selected when the switching signal 105 is high, and the ejection module 104 is selected when the switching signal 105 is low.

[0029] 2 is an electrical circuit diagram in which a discharge module group including a plurality of discharge modules 204 corresponding to odd-numbered rows of discharge ports (not shown) formed on a recording element substrate 400 is formed. This recording element substrate has a plurality of discharge modules 204 and a control data supply circuit 201. The discharge modules 204 and the control data supply circuit 201 have the same circuit configuration as the discharge modules 104 and the control data supply circuit 101 in FIG. 1 and operate in the same manner, so a description thereof will be omitted.

[0030] FIG. 3 is a circuit diagram showing an example of a malfunction prevention circuit 310 for the anti-fuse element formed on the recording element substrate 400 according to the first embodiment.

[0031] This malfunction prevention circuit 310 has a logical product circuit (AND) 300 that controls the control data supply circuit 101 for controlling the discharge modules 104 corresponding to the even-numbered column discharge ports in FIG. 1 and the control data supply circuit 201 for controlling the discharge modules 204 corresponding to the odd-numbered column discharge ports in FIG. 2, and a selector 301. An even-numbered column control data signal (DATA_EVEN) (first signal) and an odd-numbered column control data signal (DATA_ODD (second signal)) are input to the logical product circuit 300. These two input signals are logically ANDed by the logical product circuit 300, and an even-numbered column composite data signal (DATA_EVEN') is generated as its output. When the antifuse element is driven, DATA_EVEN' input to terminal (2) of the selector 301 is selected and input as output signal 312 to the control data supply circuit 101, which controls the memory module 106 in FIG. 1.

[0032] The selector 301 selects either the even column control data signal (DATA_EVEN) or the even column composite data signal (DATA_EVEN') in response to the switching signal 105, and outputs it as an output signal 312. When controlling the ejection module 104 in FIG. 1, it is necessary to input DATA_EVEN as is to the control data supply circuit 101, so the switching signal 105 is set to low level. As a result, the even column control data signal (DATA_EVEN) input to terminal (1) of the selector 301 is selected and output as the output signal 312. On the other hand, when driving the antifuse element, the switching signal 105 goes high level, and the even column composite data signal (DATA_EVEN') input to terminal (2) of the selector 301, which is ANDed by the AND circuit 300 and output, is selected and output as the output signal 312. Note that this switching signal 105 is output, for example, from the control unit 502 (FIG. 5) of the recording device. The control data supply circuit 201 for controlling the ejection modules 204 corresponding to the ejection ports in the odd-numbered columns is controlled by an odd-numbered column control data signal (DATA_ODD).

[0033] 4 is a diagram showing example waveforms of input / output signals in the malfunction prevention circuit 310 when one antifuse element is driven in embodiment 1. The input signals include an even-numbered column control data signal (DATA_EVEN), an odd-numbered column control data signal (DATA_ODD), and a switching signal 105. Note that in this case, since an antifuse element is being driven, the switching signal 105 is set to a high level, but this is omitted in FIG.

[0034] 4A shows a case where input signals DATA_EVEN and DATA_ODD, which are originally pulse signals that invert at the same timing, are inverted at the same timing without being affected by external noise or the like. In this case, the input signals (DATA_EVEN, DATA_ODD) are the same signal, so the output signal (DATA_EVEN') after passing through the AND circuit 300 has the same waveform as the input signal. This output signal (DATA_EVEN') is then selected by the selector 301 and output as the output signal 312. Based on this output signal (DATA_EVEN'), the target memory module 106 is selected and one of the antifuse elements is driven.

[0035] FIG. 4B shows a case where the two input signals (DATA_EVEN) and (DATA_ODD) are different. Only the portions where the logic of the two signals input to the AND circuit 300 at the same timing differs will result in a low level AND. For example, if DATA_EVEN goes low due to a disturbance at timing T410, the corresponding output waveform 412 will also go low. Furthermore, if only DATA_EVEN goes high due to a disturbance at timing T411, the corresponding output waveform 413 will go low. This output signal (DATA_EVEN') is then selected by the selector 301 and output as the output signal 312. Therefore, at timings T410 and T411, the memory module 106 is not selected and the antifuse element is not driven.

[0036] In this way, in the malfunction prevention circuit 310 according to the first embodiment, the intended signal is output only when the two input signals match, thereby preventing malfunction of the anti-fuse element drive due to the influence of external noise on the input signal, etc.

[0037] 5 is a diagram illustrating the circuit configuration of the recording element substrate 400 according to the first embodiment and the connection to an inkjet recording apparatus 501. The recording element substrate 400 has a plurality of memory modules.

[0038] The inkjet recording apparatus 501 includes a control unit 502 and a determination unit 503. The control unit 502 controls the operation of the recording element substrate 400. The determination unit 503 determines whether the anti-fuse element Ca of the memory module is in an insulating state. Furthermore, the control unit 502 determines the information stored in the memory module based on the result of determination by the determination unit 503, and controls the inkjet recording apparatus 501 based on that information.

[0039] The control unit 502 also controls the switching of a switch (SW1). When SW1 is connected to terminal C, a path is established between the read power supply (for example, 5 V) and the antifuse connection terminal A. On the other hand, when SW1 is connected to terminal D, a path is established between the write power supply (for example, 24 V) and the antifuse connection terminal A.

[0040] Furthermore, the control unit 502 generates control data to be sent to the control data supply circuit 101 of the recording element substrate 400 through the CLK terminal and DATA terminal of the recording element substrate 400. The control data includes a clock signal (CLK), a data signal (DATA), a latch signal (LT), and a heat enable signal (HE). This control data selects the driving element MD2 of the memory module 106 and controls its driving.

[0041] Terminal A of the recording element substrate 400 is connected to a write power supply mounted on the inkjet recording apparatus 501, and terminal B of the recording element substrate 400 is connected to a ground mounted on the inkjet recording apparatus 501. When writing information to the antifuse element, SW1 is connected to terminal D to turn on the driving element MD2 of the memory module. This applies a high voltage VID to the gate oxide film constituting the antifuse element Ca. This destroys the gate oxide film, causing the antifuse element Ca to become electrically conductive and write information. Before writing, the antifuse element Ca was a capacitive element, but after writing, it becomes a resistive element Ra. Of the two memory modules 106 shown in Figure 5, memory module A shows a state in which no information has been written to the antifuse element Ca (a state in which dielectric breakdown has not occurred). Memory module B shows a state in which information has been written to the antifuse element and it has become a resistive element Ra (a state in which dielectric breakdown has occurred).

[0042] Next, the operation when reading out information recorded in the antifuse element will be described with reference to FIG. 5. For simplicity of explanation, the discharge modules 104, 204, etc. shown in FIGS. 1 and 2 are omitted. To connect SW1 to terminal C, terminal A is connected to a current source 507 mounted on the inkjet recording apparatus 501, and terminal B is connected to ground. In the first embodiment, when a constant current is supplied from the current source 507 to terminal A, the Vout voltage generated at terminal A is read by the inkjet recording apparatus 501 to determine the write state of the antifuse element. In other words, it is determined whether the stored information is "1" or "0."

[0043] As described above, according to embodiment 1, even if noise occurs at different times in the two input signals input to the recording element substrate when the anti-fuse element is driven, the effect of the disturbance caused by the noise is eliminated, and malfunction when driving the anti-fuse element can be prevented.

[0044] [Embodiment 2] The second embodiment will be described with reference to FIGS.

[0045] 6 is a diagram showing an example of a malfunction prevention circuit 310a for an anti-fuse element formed on a recording element substrate 400 according to the second embodiment of the present invention. In FIG. 6, parts common to those in FIG. 3 are designated by the same reference numerals, and descriptions thereof will be omitted.

[0046] This malfunction prevention circuit 310a includes an inverter circuit 600 in addition to the control data supply circuit 101, the logical product circuit (AND) 300 that controls the control data supply circuit 201, and the selector 301 shown in FIG.

[0047] In the second embodiment, the even-numbered column data signal (DATA_EVEN) is input to an inverter circuit 600, which then logically inverts and outputs the signal. This output signal and the odd-numbered column data signal (DATA_ODD) are input to a logical AND circuit 300, which generates an even-numbered column composite data signal (DATA_EVEN'). When the memory module is driven, this DATA_EVEN' passes through a selector 301 and is input to a control data supply circuit 101 for controlling the even-numbered columns to control the memory module 106 in FIG. 1. The control data supply circuit 201 for controlling the ejection modules 204 corresponding to the ejection ports in the odd-numbered columns is controlled by the odd-numbered column control data signal (DATA_ODD), as in the first embodiment.

[0048] 7 is a diagram showing an example of input / output signal waveforms of the malfunction prevention circuit 310a when one antifuse element is driven in embodiment 2. The input signal includes an even-numbered column control data signal (DATA_EVEN), an odd-numbered column control data signal (DATA_ODD), and a switching signal 105. Note that, since an antifuse element is being driven here, the switching signal 105 is set to a high level, but this is omitted in FIG. 7. In embodiment 2, the logic of DATA_EVEN is inverted in advance with respect to DATA_ODD when input to the printing element substrate 400.

[0049] 7A shows a case where the logically inverted signal of DATA_EVEN and DATA_ODD are inverted at the same time. In this case, the waveform of the inverted signal of DATA_EVEN, the waveform of DATA_ODD, and the waveform of the output signal DATA_EVEN' are the same. Based on this DATA_EVEN', the target memory module 106 in the even-numbered column is selected, and one antifuse element is driven.

[0050] FIG. 7B shows an example of waveforms when noise is introduced into two input signals, DATA_EVEN and DATA_ODD, at the same time. The noise 710 in DATA_EVEN and the noise 712 in DATA_ODD are both the same in timing and magnitude. DATA_EVEN is inverted by the inverter circuit 600, and the noise is also inverted, as shown by reference numeral 711. Furthermore, by passing through the AND circuit AND300, a logical AND operation with DATA_ODD is performed, and as shown by 713, these two noises 711 and 712 cancel each other out. Therefore, the output signal 312 (DATA_EVEN') in this case is a waveform in which the noises 710 and 711 have been removed from the waveform of the input signal.

[0051] As described above, according to the second embodiment, even if noise occurs at different times in the two input signals input to the recording element substrate when the anti-fuse element is driven, the effect of the disturbance caused by the noise is eliminated, and malfunction when driving the anti-fuse element can be prevented.

[0052] [Embodiment 3] 8 is a diagram showing an example of a circuit 310b for preventing malfunction of an anti-fuse element formed on a recording element substrate 400 according to the third embodiment of the present invention. In FIG. 8, parts common to those in FIG. 3 are designated by the same reference numerals, and descriptions thereof will be omitted.

[0053] In the malfunction prevention circuit 310b, the signal line of DATA_ODD is connected to an inverter circuit 800. The operating principle and output results in this case are the same as those in the second embodiment, and therefore a description thereof will be omitted.

[0054] As described above, according to the third embodiment, when the anti-fuse element is driven, even if noise of the same magnitude is introduced at the same timing to two input signals that are originally inverted at the same timing and input to the recording element substrate, the effect of the noise is eliminated, and malfunction when driving the anti-fuse element can be prevented.

[0055] (Other embodiments) The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program. It can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0056] The present invention is not limited to the above-described embodiments, and various modifications and variations can be made without departing from the spirit and scope of the present invention. Therefore, the following claims are appended to apprise the public of the scope of the present invention. [Explanation of symbols]

[0057] 101, 201...control data supply circuit, 104...ejection module, 105...switching signal, 106...memory module, 300...logical product circuit AND, 301...selector, 310, 310a, 310b...malfunction prevention circuit, 400...printing element substrate, 501...inkjet printing apparatus, 502...control unit, 503...determination unit

Claims

1. a recording element substrate having a plurality of memory modules, each including a memory element and a drive circuit for driving the memory element; a plurality of ejection modules; and control data supply means for selecting and driving a memory module or an ejection module from the plurality of memory modules and the plurality of ejection modules, a logical product operation means for inputting a first signal and a second signal output at the same timing when the memory module is selected, and supplying a signal indicating the logical product of the first signal and the second signal to the control data supply means; The recording element substrate is characterized in that the control data supplying means does not control the driving of the memory module when a signal indicating the logical product of the first signal and the second signal is not supplied from the logical product calculation means.

2. 2. The recording element substrate according to claim 1, wherein the first signal and the second signal are pulse signals that are inverted at the same timing.

3. 3. The recording element substrate according to claim 1, further comprising a selection means for inputting the output of the logical product calculation means and either the first signal or the second signal, and, when the memory module is selected, selecting the output of the logical product calculation means and supplying it to the control data supply means.

4. further comprising inverting means for inverting the first signal; 4. The recording element substrate according to claim 1, wherein the logical product calculation means inputs the first signal inverted by the inversion means and the second signal and outputs a signal indicating the logical product.

5. further comprising inverting means for inverting the second signal; 4. The recording element substrate according to claim 1, wherein the logical product calculation means inputs the second signal inverted by the inversion means and the first signal and outputs a signal indicating the logical product.

6. 4. The recording element substrate according to claim 3, wherein the selection means, when the ejection module is selected, selects either the first signal or the second signal and supplies the selected signal to the control data supply means.

7. 7. The recording element substrate according to claim 1, wherein the memory element is an anti-fuse element.

8. The print head has a plurality of ejection ports, the plurality of ejection ports are divided into even-numbered rows and odd-numbered rows, A recording element substrate as described in any one of claims 1 to 7, characterized in that the multiple ejection modules include a first group of ejection modules that drive the ejection ports in the even columns and a second group of ejection modules that drive the ejection ports in the odd columns, and the first signal is used to select the first group of ejection modules and the second signal is used to select the second group of ejection modules.

9. A recording element substrate according to any one of claims 1 to 8; a control means for driving a recording head having the recording element substrate to perform recording; A recording device comprising:

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