ESD protection circuit and semiconductor device

Abstract

To provide an ESD protection circuit that can reduce the layout area, reduce a leakage current, and prevent malfunctions.SOLUTION: An ESD protection circuit 100 connected between a VDD terminal and a VSS terminal in parallel with an internal circuit C that operates at a specified operating voltage includes an NMOS transistor 110 in which an N-type high concentration drain region 114a and a gate electrode 116 are connected to the VDD terminal, and a high concentration source region 114b is connected to the VSS terminal, and the NMOS transistor 110 has a threshold voltage and a trigger voltage of a parasitic bipolar transistor that are higher than the operating voltage and lower than the breakdown voltage of the internal circuit C and the breakdown voltage of a gate insulating film 115 of the NMOS transistor 110.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] This invention relates to an ESD protection circuit and a semiconductor device. [Background technology]

[0002] Semiconductor integrated circuits are vulnerable to electrostatic discharge (ESD) and can be easily damaged. Therefore, semiconductor integrated circuits often incorporate ESD protection circuits to protect their internal circuits from electrostatic discharge.

[0003] This ESD protection circuit is designed to activate only when a surge voltage due to electrostatic discharge is applied to the power lines, and to protect the internal circuitry by quickly diverting the surge current to the ground wire or other suitable location without being destroyed itself before the surge current flows into the internal circuitry. Specifically, if the source of the electrostatic discharge is the human body, the ESD protection circuit will operate by sending a surge current of several amperes to ground potential or similar before the surge voltage of several thousand volts caused by the electrostatic discharge reaches the breakdown voltage of the internal circuit.

[0004] Examples of such ESD protection circuits include diode-type ESD protection circuits that utilize breakdown phenomena, GG (Gate Grounded)-MOS (Metal-Oxide-Semiconductor) type ESD protection circuits that utilize snapback operation by parasitic bipolar transistors, and capacitively coupled MOS type ESD protection circuits in which MOS transistors turn on when a voltage with a short rise time is applied.

[0005] As an example of a capacitively coupled MOS-type ESD protection circuit, the drain and source terminals of the MOS transistor are connected to V SS Each terminal except the terminal (V DD Terminals (input terminals or output terminals, etc.) and V SS In a GG-MOS type ESD protection circuit connected between the terminal and the gate terminal, the gate terminal is set to V SSA proposal has been made to connect each terminal except the terminal to a capacitor (see, for example, Patent Document 1). SS In this capacitive-coupled MOS-type ESD protection circuit, since the capacitor between each pad except the SS V terminal and the gate terminal functions as a high-pass filter, when electrostatic discharge occurs at each pad except the SS V terminal, high-frequency components of the surge voltage with a short rise time pass through the capacitor and reach the gate terminal. Then, the potential of the gate fluctuates and the MOS transistor turns on, and a surge current is made to flow on the V terminal side to protect the internal circuit from electrostatic discharge.

Prior Art Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] One aspect of the present invention aims to provide an ESD protection circuit that can reduce the layout area, reduce the leakage current, and prevent malfunction.

Means for Solving the Problems

[0008] The ESD protection circuit according to an embodiment of the present invention is an ESD protection circuit connected in parallel with a protected circuit that operates at a predetermined operating voltage between a first terminal and a second terminal, having an NMOS transistor in which a drain and a gate are connected to the first terminal and a source is connected to the second terminal, where the NMOS transistor has a threshold voltage, an avalanche breakdown voltage of a parasitic diode, and a trigger voltage of a parasitic bipolar transistor that are higher than the operating voltage and lower than a breakdown voltage of the protected circuit and a gate insulating film.​​ [Effects of the Invention]

[0009] According to one aspect of the present invention, it is possible to provide an ESD protection circuit that can reduce the layout area, reduce leakage current, and prevent malfunctions. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a schematic diagram showing an ESD protection circuit and a semiconductor device in one embodiment of the present invention. [Figure 2A] Figure 2A is a schematic cross-sectional view showing an example of the structure of an NMOS transistor in this embodiment. [Figure 2B] Figure 2B is an explanatory diagram showing an example of the operation of an NMOS transistor in this embodiment. [Figure 2C] Figure 2C is an explanatory diagram showing an example of the operation of an NMOS transistor in this embodiment. [Figure 2D] Figure 2D is an explanatory diagram showing an example of the operation of an NMOS transistor in this embodiment. [Figure 2E] Figure 2E is an explanatory diagram showing an example of the operation of an NMOS transistor in this embodiment. [Figure 2F] Figure 2F is a graph showing an example of the current-voltage characteristics of the ESD protection circuit in this embodiment. [Figure 3A] Figure 3A is a circuit diagram showing an ESD protection circuit in a modified example 1 of this embodiment. [Figure 3B] Figure 3B is a circuit diagram showing an ESD protection circuit in a modified example 2 of this embodiment. [Figure 4A] Figure 4A is a schematic cross-sectional view showing another example of the structure of an NMOS transistor in this embodiment. [Figure 4B] Figure 4B is a schematic cross-sectional view showing yet another example of an NMOS transistor in this embodiment. [Figure 4C]Figure 4C is a schematic cross-sectional view showing yet another example of an NMOS transistor in this embodiment. [Figure 4D] Figure 4D is a schematic cross-sectional view showing yet another example of an NMOS transistor in this embodiment. [Figure 4E] Figure 4E is a schematic cross-sectional view showing yet another example of an NMOS transistor in this embodiment. [Figure 4F] Figure 4F is a schematic cross-sectional view showing yet another example of an NMOS transistor in this embodiment. [Figure 4G] Figure 4G is a schematic cross-sectional view showing yet another example of an NMOS transistor in this embodiment. [Figure 4H] Figure 4H is a schematic cross-sectional view showing yet another example of an NMOS transistor in this embodiment. [Figure 5A] Figure 5A is a circuit diagram showing an example of a conventional diode-type ESD protection circuit. [Figure 5B] Figure 5B is a graph showing an example of the current-voltage characteristics (by diode junction area) of a conventional diode-type ESD protection circuit. [Figure 6A] Figure 6A is a circuit diagram showing an example of a conventional GG-MOS type ESD protection circuit. [Figure 6B] Figure 6B is a graph comparing the current-voltage characteristics of a conventional diode-type ESD protection circuit and a conventional GG-MOS-type ESD protection circuit. [Figure 6C] Figure 6C is a graph comparing the current-voltage characteristics of a conventional diode-type ESD protection circuit and a conventional GG-MOS-type ESD protection circuit, taking into account the reduction of leakage current. [Figure 6D] Figure 6D is a graph comparing the current-voltage characteristics of a conventional diode-type ESD protection circuit and a conventional GG-MOS-type ESD protection circuit, without considering the reduction of leakage current. [Figure 7A] Figure 7A is a circuit diagram showing an example of a conventional capacitively coupled MOS type ESD protection circuit. [Figure 7B]FIG. 7B is a graph showing an example of the current-voltage characteristics (by rise time of surge voltage) of a conventional capacitive-coupled MOS type ESD protection circuit.

BEST MODE FOR CARRYING OUT THE INVENTION

[0011] The present invention is based on the finding that, unlike a conventional GG-MOS type ESD protection circuit where the gate is connected to a low-potential terminal such as a ground potential, the internal circuit can be protected even when the gate is connected to a high-potential terminal where static electricity is discharged. Thereby, in one embodiment of the present invention, the layout area can be made smaller than that of a conventional diode type ESD protection circuit, the leakage current can be reduced more than that of a GG-MOS type ESD protection circuit, and malfunction such as that occurring in a capacitive-coupled MOS type ESD protection circuit can be prevented.

[0012] First, as a conventional technique, a diode type ESD protection circuit, a GG-MOS type ESD protection circuit, and a capacitive-coupled MOS type ESD protection circuit will be described with reference to FIGS. 5A to 7B. Hereinafter, the voltage and current due to electrostatic discharge may be simply referred to as "surge voltage" and "surge current".

[0013] FIG. 5A is a circuit diagram showing an example of a conventional diode type ESD protection circuit. As shown in FIG. 5A, this diode type ESD protection circuit 500 is a circuit in which a diode 510 is connected between a V DD terminal and a V SS terminal. When a surge voltage is applied to the V DD terminal, the diode type ESD protection circuit 500 protects the internal circuit C from electrostatic discharge by flowing a surge current through the diode 510 using the avalanche phenomenon. Since the diode 510 can adjust the breakdown voltage by adjusting the impurity concentration of the PN junction, it is easy to correspond to the operating voltages of various semiconductor integrated circuits, has a simple structure with little variation in characteristics, and since it does not use an insulating film, the insulating film is not broken.

[0014] Figure 5B is a graph showing an example of the current-voltage characteristics (by diode junction area) of a conventional diode-type ESD protection circuit. In this graph, the horizontal axis is V DD The voltage across the terminals is shown, and the vertical axis represents the surge current flowing through the diode-type ESD protection circuit. The solid line shows the current-voltage characteristics of a diode with a large junction area, while the dotted line shows the current-voltage characteristics of a diode with a small junction area. Furthermore, in the graphs of Figure 6B, 6C, 6D, and 7B, not only is the graph in Figure 5B assumed, but the graphs in Figures 6B, 6C, 6D, and 7B also assume a so-called 2000V Human Body Model (HBM) when 2000V static electricity charged on the human body is applied to the VDD terminal. In order for the internal circuit to not be damaged by the 2000V HBM, the ESD protection circuit connected in parallel with the internal circuit must block a surge current of approximately 1 ampere before the surge current flows into the internal circuit. SS It needs to be passed through the terminal.

[0015] In the current-voltage characteristic shown by the dotted line in Figure 5B, the diode junction area is small and the parasitic resistance is high, so a surge current of 1 ampere is V SS The surge voltage reaches the breakdown voltage of the internal circuit before it can flow through the terminals. On the other hand, in the current-voltage characteristic shown by the solid line in Figure 6A, because the junction area of ​​the diode is large and the resistance value of the parasitic resistance is low, a surge current of 1 ampere is passed through before the surge voltage reaches the breakdown voltage of the internal circuit. SS It can be passed through the terminal. Therefore, in order for a diode-type ESD protection circuit to protect its internal circuitry from 2000V HBM, the junction area of ​​the diode must be large, which increases the layout area in the semiconductor integrated circuit.

[0016] In terms of reducing the layout area in semiconductor integrated circuits, GG-MOS type ESD protection circuits that utilize snapback operation are more advantageous than diode type ESD protection circuits. Next, we will describe a conventional GG-MOS type ESD protection circuit.

[0017] Figure 6A is a circuit diagram showing an example of a conventional GG-MOS type ESD protection circuit. As shown in Figure 6A, the GG-MOS type ESD protection circuit 600 has a drain and source terminal of the MOS transistor 610 that is V DD Terminals and V SS Each terminal is connected, and the gate terminal is V SS This is a circuit connected to a terminal.

[0018] Figure 6B is a graph comparing the current-voltage characteristics of a conventional diode-type ESD protection circuit and a conventional GG-MOS-type ESD protection circuit. In this graph, the horizontal axis is V DD The voltage at the terminals is shown, and the vertical axis represents the surge current flowing through each ESD protection circuit. The solid line shows the current-voltage characteristics of a GG-MOS type ESD protection circuit with a small layout area, and the dotted line shows the current-voltage characteristics of a diode type ESD protection circuit with a small layout area, similar to the dotted line in Figure 5B. In other words, in Figure 6B, the layout area of ​​a conventional GG-MOS type ESD protection circuit is the same as that of a conventional diode type ESD protection circuit.

[0019] In the current-voltage characteristics of the GG-MOS type ESD protection circuit shown by the solid line in Figure 6B, when a surge voltage is applied, avalanche breakdown occurs in the parasitic diode of the MOS transistor 610, followed by V DD The terminal voltage reaches the trigger voltage. Here, the trigger voltage is the trigger voltage of the parasitic bipolar transistor, which is the voltage at which the parasitic bipolar transistor switches from off to on. When the parasitic bipolar transistor turns on, the current path from drain to source increases compared to when it is off, so the same current can flow with a smaller drain voltage, and as shown in Figure 6B, a phenomenon called snapback occurs where the voltage drops after the trigger voltage is reached. This snapback action allows conventional GG-MOS type ESD protection circuits to limit surge current to 1 ampere before the surge voltage reaches the breakdown voltage of the internal circuit. SS It can be passed through the terminal.

[0020] The leakage current and breakdown voltage of this GG-MOS type ESD protection circuit are affected by multiple parameters such as the gate length of the MOS transistor, the gate insulating film thickness, the channel impurity concentration, and the impurity concentration in the low-concentration region near the drain. Although this makes it more complex than the diode type, the desired characteristics can be finely tuned by adjusting the concentration of impurities injected near the drain region.

[0021] However, if the operating voltage of the internal circuit is around 2V, adjustment becomes difficult with diode-type or GG-MOS-type transistors. Generally, in internal circuits with an operating voltage of around 2V, it is necessary to lower the minimum operating voltage, and in order to improve the on / off ratio of the MOS transistors used in the internal circuit, the gate dielectric thickness of the MOS transistors in the internal circuit is set to 4nm to 5nm. When the gate dielectric is a thin silicon oxide film as described above, the intrinsic breakdown voltage slightly exceeds 10MV / cm, so the intrinsic breakdown voltage of the gate dielectric of the MOS transistor in the internal circuit is often around 5.5V. For this reason, the ESD protection circuit is V DD The protective operation must be performed when the terminal voltage is within the range of 2V to 5.5V. In diode-type ESD protection circuits and GG-MOS-type ESD protection circuits, attempting to keep the protection operation within the above range results in a large leakage current at an operating voltage of 2V, as shown in Figure 6D. Conversely, attempting to suppress the above leakage current results in the protection operation not being completed within the above range, as shown in Figure 6C, exceeding 5.5V before a 1-ampere surge current flows, damaging the internal circuitry.

[0022] Thus, in diode-type ESD protection circuits and GG-MOS-type ESD protection circuits, when the operating voltage of the internal circuit approaches 2V, the trade-off relationship between leakage current and protection operating voltage (i.e., off-current and on-voltage) makes it impossible to satisfy the ESD protection function. The capacitively coupled MOS type ESD protection circuit, which will be explained next, resolves this trade-off.

[0023] Figure 7A is a circuit diagram showing an example of a conventional capacitively coupled MOS type ESD protection circuit. Figure 7B is a graph showing an example of the current-voltage characteristics (by surge voltage rise time) of a conventional capacitively coupled MOS type ESD protection circuit.

[0024] As shown in Figure 7A, the capacitively coupled MOS type ESD protection circuit 700 has a drain and source terminal of the MOS transistor 710 that is V DD Terminals and V SS It is similar to the GG-MOS type in that each terminal is connected, but the gate is connected via capacitor 720 to V DD Connect to the terminal and V through the resistor element 730 SS It differs in that it also connects to terminals. Furthermore, the threshold voltage for the MOS transistor 710 is set to 2V or less.

[0025] In the capacitively coupled MOS-type ESD protection circuit 700, when the rise time of the surge voltage is long, the potential of the capacitively coupled gate does not fluctuate easily, and the ESD protection circuit does not supply current. In other words, in this case, the capacitively coupled MOS-type ESD protection circuit 700 does not perform protection operation in the range of 2V to 5.5V, and the current-voltage characteristics are as shown by the solid line in Figure 7B, reducing leakage current. On the other hand, when the rise time of the surge voltage is short, the potential of the capacitively coupled gate fluctuates, and the MOS transistor 710, which is set to a threshold of 2V or less, performs protection operation by supplying current to the channel, thereby discharging the surge current.

[0026] Thus, this capacitively coupled MOS-type ESD protection circuit 700 eliminates the trade-offs of diode-type ESD protection circuits and GG-MOS-type ESD protection circuits by switching between on and off characteristics through capacitive coupling.

[0027] However, capacitively coupled MOS-type ESD protection circuits can only be used on a limited number of terminals because they will malfunction if used with terminals that are operated by inputting or outputting signals with short rise times equivalent to those of electrostatic discharge. Furthermore, because a high voltage is applied to the gate during operation, capacitively coupled MOS-type ESD protection circuits are less prone to avalanche breakdown, which can cause parasitic bipolar transistors to malfunction. As a result, the current-voltage characteristics of capacitively coupled MOS-type ESD protection circuits are similar to those of the diode-type ESD protection circuit shown by the dotted line in Figure 5B, as shown by the solid line in Figure 7B. When attempting to pass a large current, the layout area must be increased, as shown by the solid line in Figure 5B.

[0028] Therefore, in order to solve the above problems, the present invention was made as follows. An ESD protection circuit in one embodiment of the present invention has an NMOS transistor connected in parallel with a protected circuit operating at a predetermined operating voltage between a first terminal and a second terminal. The drain and gate of the NMOS transistor are connected to the first terminal and the source is connected to the second terminal, and the threshold voltage, the avalanche breakdown voltage of the parasitic diode, and the trigger voltage of the parasitic bipolar transistor are higher than the operating voltage of the protected circuit and lower than the breakdown voltage of the protected circuit and the breakdown voltage of the gate insulating film of the NMOS transistor. As a result, this ESD protection circuit can have a smaller layout area than conventional diode-type or capacitively coupled MOS-type ESD protection circuits, reduce leakage current compared to diode-type or GG-MOS-type ESD protection circuits, and can be used on terminals that input and output voltages with short rise times without malfunctioning like capacitively coupled MOS-type ESD protection circuits. The specified operating voltage is the voltage at which the protected circuit can operate, and it is within the range from the minimum operating voltage to the maximum operating voltage of the protected circuit.

[0029] Embodiments of the present invention will be described in detail below with reference to the drawings. In drawings, identical components are denoted by the same reference numeral, and redundant explanations may be omitted. Furthermore, in the drawings, the X, Y, and Z directions are orthogonal to each other. The direction including the X direction and the opposite direction of the X direction (-X direction) is called the "X-axis direction," the direction including the Y direction and the opposite direction of the Y direction (-Y direction) is called the "Y-axis direction," and the direction including the Z direction and the opposite direction of the Z direction (-Z direction) is called the "Z-axis direction" (height direction, thickness direction). In this regard, in the following embodiments, the Z-axis side of each film may be referred to as the "surface." The drawings are schematic, and the ratios of width, length, and depth may not be exactly as shown.

[0030] (An example of an embodiment) Figure 1 is a schematic diagram showing an ESD protection circuit and a semiconductor device in one embodiment of the present invention. As shown in Figure 1, the semiconductor device 10 has V as the first terminal. DD Terminal and V as a second terminal SS An internal circuit C is connected between the terminal and the circuit. The internal circuit C is V DD V between terminal and ground potential SS It operates based on the operating voltage applied between it and the terminals. The ESD protection circuit 100 is connected in parallel to the internal circuit C, which is the protected circuit that needs to be protected from damage caused by electrostatic discharge. The ESD protection circuit 100 is V DD The drain 110D and gate 110G are electrically connected to the terminals, V SS This is an NMOS (N-channel MOS) transistor 110 to which the source 110S is electrically connected at the terminal.

[0031] The operating voltage of the internal circuit C described above varies depending on the purpose, but in this embodiment, this operating voltage is set to 2V. DD Assume that 2V is applied to the terminal. Generally, when the operating voltage of the internal circuit is 2V, the intrinsic breakdown voltage of the gate insulating film of the MOS transistor included in the internal circuit is approximately 5.5V. Therefore, if there is no ESD protection circuit, V DDIf static electricity is discharged to the terminals, a voltage of 5.5V or higher will be applied to the gate insulating film of the MOS transistor included in the internal circuit, causing it to be destroyed. In other words, the ESD protection circuit 100 is V DD A protective action is performed before the terminal voltage exceeds 5.5V. DD The protection should not activate when the operating voltage of the internal circuit C, which is 2V, is applied to the terminal. Additionally, the thickness of the insulating film should be set so that the intrinsic breakdown voltage of the gate insulating film of the NMOS transistor 110 is 5.5V.

[0032] Figure 2A is a schematic cross-sectional view showing an example of the structure of an NMOS transistor in this embodiment. As shown in Figure 2A, the structure of the NMOS transistor 110 is such that a P-type well region 112, which is a P-type low-concentration region, is formed on the semiconductor substrate 111, and a P-type medium-concentration region 113a is formed on top of this P-type well region 112. In this embodiment, a medium-concentration P-type region 113a is formed on top of the P-type well region 112. However, the embodiment is not limited to this, and instead of forming a medium-concentration P-type region 113a, a low-concentration P-type well region 112 may be made to a medium concentration.

[0033] A gate insulating film 115 is stacked on the upper surface of this P-type medium-concentration region 113a, and a gate electrode 116 is further stacked on top of the gate insulating film 115. Above the P-type medium-concentration region 113a, an N-type high-concentration drain region 114a and an N-type high-concentration source region 114b are formed so as to sandwich the gate electrode 116 when viewed from above. Thus, the P-type medium-concentration region 113a is also provided in the channel region between the N-type high-concentration drain region 114a and the N-type high-concentration source region 114b. Furthermore, above the P-type medium-concentration region 113a, a well electrode 114c is formed as a P-type high-concentration region at a position spaced apart from the N-type high-concentration source region 114b. In this embodiment, the N-type high-concentration source region 114b and the well electrode 114c are spaced apart, but the invention is not limited to this, and the N-type high-concentration source region 114b and the well electrode 114c may be in contact, such as in a butting contact. The N-type high-concentration drain region 114a and the gate electrode 116 are V DD The terminal is connected, and the N-type high-concentration source region 114b and the well electrode 114c are V SS It is connected to the terminal.

[0034] Generally, the well region of an ESD protection circuit is often formed simultaneously with the well region of the internal circuit using the same process. Therefore, it is not necessarily common to form a P-type medium-concentration region 113a in addition to the P-type well region 112, as in this embodiment.

[0035] By adjusting the impurity concentration in this P-type medium-concentration region 113a, it is possible to adjust the threshold voltage of the NMOS transistor 110, the avalanche breakdown voltage of the parasitic diode, and the trigger voltage of the parasitic bipolar diode. As described above, the ESD protection circuit 100 is V DD A protective action is performed before the terminal voltage exceeds 5.5V. DD Since protection should not be activated when the operating voltage of the internal circuit C, 2V, is applied to the terminal, the threshold voltage of the NMOS transistor 110, the avalanche breakdown voltage of the parasitic diode, and the trigger voltage of the parasitic bipolar diode are adjusted to be between 2V and 5.5V by adjusting the impurity concentration in the P-type medium concentration region 113a.

[0036] Here, in an IC where the operating voltage of the internal circuit C is 2V, V DD This section describes the operating principle when positive static electricity flows into the terminals.

[0037] If the threshold voltage of this NMOS transistor 110 is adjusted to, for example, 2.2V, then V DD When 2V is applied to the terminal as the operating voltage, the ESD protection circuit 100 does not perform protective action, and the internal circuit C operates normally. On the other hand, V DD When a surge voltage of 2.2V or more is applied to the terminal, the NMOS transistor 110 turns on, and a surge current flows from the N-type high-concentration drain region 114a to the N-type high-concentration source region 114b via the channel region.

[0038] In this way, by adjusting the impurity concentration in the P-type medium concentration region 113a and setting the threshold voltage higher than the operating voltage and lower than the breakdown voltage of the internal circuit C and the breakdown voltage of the gate insulating film 115 of the NMOS transistor 110, the NMOS transistor 110 is turned on when a surge voltage is applied, protecting the internal circuit C without damaging the NMOS transistor 110 (protection operation 1).

[0039] With only this protection action 1, the current-voltage characteristics will be similar to those shown by the solid line in Figure 7B for "input voltages with short rise times," and the internal circuit C will not be protected in a small area. In order to protect the internal circuit C, the gate width of the gate electrode 116 must be widened to allow a larger surge current to flow, but as a result the layout area will increase and the leakage current will also increase. In the case of conventional GG-MOS type ESD protection circuits, the gate electrode is V SS Because it is connected to the terminal, the electric field near the semiconductor surface between the gate and drain becomes strong, causing surface breakdown, and the carriers generated thereby induce parasitic bipolar operation. On the other hand, in this embodiment, since the gate electrode is connected to the drain electrode, parasitic bipolar transistor operation due to surface breakdown cannot be expected as in the GG-MOS type ESD protection circuit. However, because there is a P-type medium concentration region 113a, avalanche breakdown occurs at the parasitic diode formed at the junction of the P-type medium concentration region 113a and the N-type high concentration drain region 114a, thus inducing parasitic bipolar transistor operation.

[0040] The avalanche breakdown voltage of this parasitic diode and the trigger voltage of the parasitic bipolar transistor whose operation is induced by it are also adjusted by the impurity concentration in the P-type medium concentration region 113a, similar to the threshold voltage. The avalanche breakdown voltage of the parasitic diode is determined similarly to the threshold voltage, where the operating voltage of the internal circuit C is 2V. DDAdjust the voltage to 2V or higher so that the leakage current is below the desired level when applied to the terminals. This will naturally result in the trigger voltage of the parasitic bipolar transistor, which is activated, also being 2V or higher. DD To protect the internal circuit C from ESD surges applied from the terminals, the trigger voltage of the parasitic bipolar diode is adjusted to be 5.5V or less. If, when the avalanche breakdown voltage of the parasitic diode is set to 2V or higher, the trigger voltage of the parasitic bipolar diode exceeds 5.5V, the gate length of the NMOS transistor 110 is shortened to lower only the trigger voltage of the parasitic bipolar diode. Furthermore, the gate electrode is not a GG-MOS type ESD protection circuit. SS Because it is not connected to a terminal, it has the advantage of being able to lower the trigger voltage for parasitic bipolar operation more easily than GG-MOS type ESD protection circuits, thus protecting the internal circuitry more effectively. By operating this parasitic bipolar, in addition to the surge current flowing through the channel region, which is the protection operation 1 described above, a larger surge current can flow through the parasitic bipolar region deeper than the channel region (-Z direction) from the N-type high-concentration drain region 114a to the N-type high-concentration source region 114b (protection operation 2).

[0041] In other words, since there are two paths for surge current to flow—a current path that flows through the channel region (protection operation 1) and a current path that flows through the parasitic bipolar region deeper than the channel region (-Z direction) (protection operation 2)—it is possible to further reduce the area compared to the GG-MOS type ESD protection circuit, which is already area-advantageous among conventional technologies.

[0042] Furthermore, in the structure of the NMOS transistor 110, since the channel region is a P-type medium-concentration region 113a, this is limited to cases where the threshold voltage and the breakdown voltage of the parasitic diode can be adjusted to a desired value at the same time by adjusting the impurity concentration in the P-type medium-concentration region 113a.

[0043] Next, the negative charge of static electricity V DD This section describes the case where a discharge occurs at the terminals.

[0044] As shown in Figure 2E, the negative charge flows forward in the parasitic diode between the N-type high-concentration drain region 114a and the P-type well region 112, and then from the P-type well region 112 through the well electrode 114c, which is the P-type high-concentration region, to V SS The current flows to the terminal. Since there are no points in the above path where a high electric field is applied, it does not cause damage. Therefore, the ESD protection circuit 100, due to the structure of the NMOS transistor 110, can handle negative charges. SS By passing current through the terminals, the internal circuit C can be protected.

[0045] In the method for forming the NMOS transistor 110, for example, first a P-type well region 112 is formed on the semiconductor substrate 111, and then a gate insulating film 115 and a gate electrode 116 are formed on top of it. Then, P-type impurities are injected into the entire surface of the semiconductor substrate 111 so as to penetrate the gate insulating film 115 and the gate electrode 116 to form a medium-concentration P-type region 113a, and then N-type impurities are injected at a high concentration to form a high-concentration N-type drain region 114a and a high-concentration N-type source region 114b. Furthermore, the P-type medium-concentration region 113a may be formed before the formation of the gate insulating film 115 and the gate electrode 116.

[0046] Thus, the ESD protection circuit 100 is V DD Terminal and V SS It has an NMOS transistor 110 connected in parallel with an internal circuit C that operates at a predetermined operating voltage between it and the terminal. The NMOS transistor 110 is V DD The terminals are connected to the N-type high-concentration drain region 114a and the gate electrode 116, V SS An N-type high-density source region 114b is connected to the terminal. As shown in Figure 2F, the threshold voltage, Zener breakdown voltage of the parasitic diode, and trigger voltage of the parasitic bipolar transistor of this NMOS transistor 110 are higher than the operating voltage of the internal circuit C, and lower than the breakdown voltage of the internal circuit C and the breakdown voltage of the gate insulating film 115 of the NMOS transistor 110. As a result, the ESD protection circuit 100 can reduce its layout area, lower leakage current, and prevent malfunctions that can occur in capacitively coupled MOS electrostatic circuits. Furthermore, in the embodiments shown in Figures 1 and 2A to 2F, the gate 110G of the NMOS transistor 110 is V DD Because it is directly connected to the terminal, a sudden influx of surge current may cause the potential of gate 110G to exceed the breakdown voltage of the gate insulating film of the NMOS transistor 110 before protection operation 1 and protection operation 2 are fully performed, potentially destroying the gate insulating film. In that case, it is possible to avoid destruction by the modification 1 shown below.

[0047] Figure 3A shows the ESD protection circuit diagram for Modification 1 of this embodiment. As shown in Figure 3A, the ESD protection circuit 100 in modified example 1 is the same as the ESD protection circuit 100 in Figure 1, except that a resistor 120 is connected between the gate 110G and drain 110D of the NMOS transistor 110.

[0048] In the modified example 1, by connecting a resistor element 120 between the gate 110G and the drain 110D, V DD This can slow down the rapid voltage rise at the gate 110G of the NMOS transistor 110 when static electricity flows into the terminal. As a result, protection operations 1 and 2 are performed before the voltage at the gate 110G exceeds the breakdown voltage of the gate insulating film of the NMOS transistor 110, and the static charge accumulated in the drain 110D can be discharged from the source 110S before it flows into the gate 110G, thereby preventing the destruction of the gate insulating film.

[0049] The resistance value of the resistive element 120 is preferably between a few kΩ and several tens of kΩ.

[0050] Furthermore, in Figures 1, 2A to 2F, and 3A, in the case of the Charged Device Model (CDM) where the entire IC is charged, unlike HBM, charge may remain on the gate 110G of the NMOS transistor 110, potentially causing the gate insulating film to break. In such cases, the breakdown can be avoided by the modified example 2 shown below.

[0051] Figure 3B shows the ESD protection circuit diagram for a modified example 2 of this embodiment. The ESD protection circuit 100 in Modification 2 is the same as the ESD protection circuit 100 in Modification 1, except that a diode 130 is connected between the gate 110G and source 110S of the NMOS transistor 110.

[0052] In the modified example 2, the charge of gate 110G can be released through the diode 130 connected between gate 110G and source 110S, thereby preventing the destruction of the gate insulating film of the NMOS transistor 110.

[0053] The voltage rating of diode 130 is set higher than the operating voltage of internal circuit C to prevent leakage current from being generated when internal circuit C is operating.

[0054] Next, we will explain other examples of NMOS transistor structures other than the NMOS transistor 110 shown in Figure 2A, referring to Figures 4A to 4H. Figures 4A to 4H are schematic cross-sectional views showing the vicinity of the N-type high-concentration drain region 114a, the N-type high-concentration source region 114b, and the gate electrode 116. Furthermore, in the ESD protection circuit shown in Figures 1, 3A, and 3B, any of the NMOS transistors shown in Figures 2A and 4A to 4H may be used.

[0055] Figure 4A shows a structure similar to the NMOS transistor 110 shown in Figure 2A, except that a P-type medium-concentration channel region 117 is further formed in the NMOS transistor 110 shown in Figure 2A. By forming this P-type medium-concentration channel region 117, the impurity concentration of the P-type medium-concentration channel region 117 can be adjusted independently of the P-type medium-concentration region 113a. For example, the operating voltage of the internal circuit C can be set to V DD To suppress leakage current when applied to the terminals, the impurity concentration in the P-type medium-concentration region 113a is adjusted to a lower concentration, thereby increasing the avalanche breakdown voltage of the parasitic diode. As a result, the threshold voltage decreases, and in some cases, the leakage current of the NMOS transistor 110 cannot be suppressed. However, the existence of the P-type medium-concentration channel region 117 allows for independent adjustment of the impurity concentration in this region, enabling the threshold voltage to be raised without altering the avalanche breakdown voltage of the parasitic diode of the NMOS transistor 110, thus suppressing leakage.

[0056] Figure 4B shows a structure similar to the NMOS transistor 110 shown in Figure 4A, except that a P-type medium concentration region 113b is formed directly below the N-type high concentration drain region 114a instead of the P-type medium concentration region 113a. By adopting the structure shown in Figure 4B, not only can the same effect as in Figure 4A be obtained, but the concentration in the base region of the parasitic bipolar transistor directly below the P-type medium-concentration channel region 117 is lower than in Figure 4A. As a result, the trigger voltage of the parasitic bipolar transistor is reduced, making it easier to protect the internal circuit C than in Figure 4A.

[0057] Figure 4C shows a structure similar to the NMOS transistor 110 shown in Figure 4B, except that an N-type low-concentration region 118a is formed in the NMOS transistor 110 shown in Figure 4B. The N-type low-concentration region 118a is a so-called DDD (Double Diffused Drain) structure. This DDD structure is generally used to improve the drain breakdown voltage of MOS transistors, and this structure can also be applied to the present invention. Because this N-type low-concentration region 118a is formed, the N-type high-concentration drain region 114a is substantially expanded, making it easier to disperse heat, and thus improving the electrostatic breakdown voltage.

[0058] Figures 4D to 4G show structures similar to those of the NMOS transistors shown in Figures 2A and 4A to 4C, except that sidewall spacers 119 are provided on the side walls of the gate insulating film 115 and gate electrode 116. Figure 4H shows a structure similar to that of the NMOS transistor shown in Figure 4G, except that the N-type low-concentration region 118a is replaced with a shallowly formed N-type low-concentration region 118b. This sidewall spacer 119 is a technique used in general semiconductor manufacturing processes, and is formed by removing the insulating film formed on the entire surface by etch-back after the gate insulating film 115 and gate electrode 116 have been formed. By using Figures 4D to 4H, the present invention can be applied to manufacturing processes that use sidewall spacers without any additional steps. Here, in Figures 4D to 4F, there is no N-type region directly beneath the sidewall spacer 119. In such a structure, when a positive voltage is applied to the gate electrode 116, the channel directly beneath the sidewall spacer 119 is less likely to invert, making it difficult for channel current to flow. This is problematic when used as a normal MOS transistor. However, as described above, in the present invention, parasitic bipolar operation is performed by avalanche breakdown between the N-type high-concentration drain region 114a and the P-type medium-concentration region 113b, and since the gate is not grounded like in a GG-MOS type ESD protection circuit, the holes generated by avalanche breakdown also raise the potential of the channel, allowing channel current to flow in addition to the current due to parasitic bipolarity. Therefore, protection operation 1 and protection operation 2 work even in these structures, protecting the internal circuit C. Furthermore, due to the reason that the channel under the sidewall spacer 119 is less likely to invert, leakage current can also be suppressed.

[0059] On the other hand, Figures 4G to 4H show that an N-type region exists directly beneath the sidewall spacer 119. These N-type low-concentration regions 118a and 118b are the so-called DDD (Double Diffused Drain) structure and LDD (Lightly Doped Drain) structure. While the DDD and LDD structures are generally used to improve the drain breakdown voltage of transistors, these structures can also be applied to the present invention. Because the N-type low-concentration region 118b is formed, the N-type high-concentration drain region 114a is substantially expanded, making it easier to dissipate heat and thus improving the electrostatic breakdown voltage.

[0060] As described above, the ESD protection circuit in one embodiment of the present invention has an NMOS transistor connected in parallel with a protected circuit operating at a predetermined operating voltage between a first terminal and a second terminal. The drain and gate of this NMOS transistor are connected to the first terminal and the source is connected to the second terminal, and the threshold voltage and the trigger voltage of the parasitic bipolar are higher than the operating voltage and lower than the breakdown voltage of the protected circuit and the breakdown voltage of the gate insulating film of the NMOS transistor of the ESD protection circuit. As a result, this ESD protection circuit can reduce its layout area, lower leakage current, and prevent malfunctions that can occur in capacitively coupled MOS-type ESD protection circuits.

[0061] Although one embodiment of the present invention has been described in detail above, the present invention is not limited to this embodiment and also includes designs and the like that do not depart from the spirit of the invention. Specifically, in this embodiment, the first terminal is V DD Although referred to as terminals, they are not limited to this and may also be called input terminals, output terminals, etc. Furthermore, while Figure 3B shows a modified example in which a resistor and a diode are connected to the NMOS transistor, the example is not limited to this, and the NMOS transistor may be connected only to a diode without a resistor. Furthermore, even if an LDD structure is used for the NMOS transistor, it is possible to avoid forming sidewall spacers. [Explanation of Symbols]

[0062] 10 Semiconductor Devices 100 ESD protection circuit 110 NMOS transistors 110D drain 110S Source 110G Gate 111 Semiconductor substrates 112 P-type well area 113a,113b P-type medium concentration region 114a N-type high-concentration drain region 114b N-type high-concentration source region 115 Gate insulating film 116 Shuttle bus stop 117 P-type medium-concentration channel region (P-type medium-concentration region) 118a,118b N-type low concentration region 119 Sidewall Spacers 120 Resistor elements 130 diodes C Internal circuit (protected circuit)

Claims

1. An ESD protection circuit connected in parallel with a protected circuit that operates at a predetermined operating voltage between a first terminal and a second terminal, an NMOS transistor having a drain and a gate connected to the first terminal and a source connected to the second terminal; The NMOS transistor has a threshold voltage and a trigger voltage of a parasitic bipolar transistor that are higher than the operating voltage and lower than the breakdown voltage of the circuit to be protected and the gate insulating film.

2. 2. The ESD protection circuit of claim 1, further comprising a resistive element connected between the first terminal and the gate of the NMOS transistor.

3. 3. The ESD protection circuit according to claim 1, wherein a diode having an avalanche breakdown voltage higher than the operating voltage is connected between the second terminal and the gate of the NMOS transistor.

4. The NMOS transistor is a semiconductor substrate; a P-type well region formed on the front surface side of the semiconductor substrate; an N-type heavily doped drain region and an N-type heavily doped source region, which are provided above the P-type well region and spaced apart from each other, and which have an impurity concentration higher than that of the P-type well region; a P-type intermediate concentration region provided in at least a region in contact with the N-type heavily doped drain region, the P-type intermediate concentration region having a P-type impurity concentration higher than that of the P-type well region; a gate insulating film provided on a semiconductor surface between the N-type heavily doped drain region and the N-type heavily doped source region; a gate electrode provided on the gate insulating film; 4. The ESD protection circuit according to claim 1, comprising:

5. 5. The ESD protection circuit of claim 4, wherein the medium concentration P-type region also contacts the P-type well region.

6. 6. The ESD protection circuit according to claim 4, wherein the P-type medium concentration region is further provided in a channel region between the N-type high concentration drain region and the N-type high concentration source region.

7. 7. The ESD protection circuit according to claim 4, wherein a P-type medium concentration channel region is provided on the surface of the semiconductor substrate between the N-type high concentration drain region and the N-type high concentration source region.

8. 8. The ESD protection circuit according to claim 4, wherein the NMOS transistor further comprises a DDD structure.

9. 8. The ESD protection circuit according to claim 4, wherein the NMOS transistor further comprises an LDD structure.

10. 10. The ESD protection circuit according to claim 4, wherein the NMOS transistor further comprises sidewall spacers on the sidewalls of the gate insulating film and the gate electrode.

11. 11. A semiconductor device comprising: an ESD protection circuit according to claim 1; and a circuit to be protected from electrostatic discharge by said ESD protection circuit, said circuit being connected in parallel.

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