Display device and inspection method of display device

Abstract

To reduce cost of inspection by a small-sized and simple structure, and to enable stable and diverse inspections.SOLUTION: A precharge circuits 31A and 31B are disposed on both sides of a gate line GL. The precharge circuits 32A and 32B are disposed on both sides of a data line DL. A common electrode inspection circuit 33 is connected to a common electrode. A test data processing circuit 34 is disposed at one end of the gate line GL. A test data processing circuit 35 is disposed at one end of the data line DL. In a first period, first voltage is supplied to a part of the gate line GL, the data line DL, and the common electrode. In a second period, second voltage is supplied to a part of the gate line GL, the data line DL, and the common electrode. The inspection data processing circuits 34 and 35 acquire voltage levels of the gate line GL and the data line DL which are based on supply of the second voltage.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a display device and a method for inspecting a display device.

Background Art

[0002] A liquid crystal display device using thin film transistors is applicable to in-vehicle display devices. Certain in-vehicle display devices are required to have a function of detecting a line defect, which is an abnormality in wiring. A circuit for realizing this function is likely to cause problems such as an increase in the size of the device and an increase in costs in manufacturing and inspection.

[0003] Patent Document 1 discloses a failure inspection circuit connected to a source line and a gate line. FIG. 29 shows a circuit configuration of an active matrix substrate disclosed in Patent Document 1. The active matrix substrate A1 in FIG. 29 has a failure inspection circuit A100. The failure inspection circuit A100 includes determination circuits A105 and A114, and expected value comparison circuits A106 and A115.

[0004] The determination circuit A105 receives a monitor output signal on the source line A11 via the monitor output signal line A104. The voltage level of the monitor output signal detected by the determination circuit A105 is compared with an expected value in the expected value comparison circuit A106. The determination circuit A114 receives a monitor output signal on the gate line A12 via the monitor output signal line A112. The voltage level of the monitor output signal detected by the determination circuit A114 is compared with an expected value in the expected value comparison circuit A115.

[0005] Patent Document 2 discloses an anomaly detection circuit for detecting anomalies in gate signals, which are scanning signals. Figure 30 shows the configuration of the liquid crystal display device disclosed in Patent Document 2. In Figure 30, the liquid crystal display device B10 has an anomaly detection circuit section, including a scanning signal anomaly detection circuit B400 and an anomaly determination circuit B800, located outside the liquid crystal display unit B100. When gate signals GLs are supplied sequentially, the scanning signal anomaly detection circuit B400 shifts the start signal STV. The shifted pulse is sent to the anomaly determination circuit B800. The anomaly determination circuit B800 latches the shifted pulse. Based on the latched data output, it is determined whether or not an anomaly exists.

[0006] Figure 31 shows an example of an abnormality detection circuit disclosed in Patent Document 2. In the abnormality detection circuit B800 shown in Figure 31, the comparator B810 compares the output value of the scanning signal abnormality detection circuit B400 with a predetermined reference voltage value Vref.

[0007] Patent Document 3 discloses a test circuit for detecting short circuits in gate lines and data lines. Figure 32 shows the configuration of the liquid crystal display device disclosed in Patent Document 3. In the liquid crystal display device C1A in Figure 32, a gate line test circuit C10A and a data line test circuit C20A are provided on the gate line drive circuit C2A and data line drive circuit C3A sides, respectively, and connected to the gate line Gm and data line Dn in order to detect short circuits in the gate line Gm and data line Dn.

[0008] Figure 33 is a schematic diagram of the data line test circuit disclosed in Patent Document 3. Figure 34 is a circuit diagram showing the equivalent circuit of the data line test circuit C20A in Figure 33. In Figure 34, the data line potential Vd is determined by the resistive voltage division of the power supply potential VDD based on the short-circuit resistance Rs. The detection logic circuit C21 outputs whether or not there is a short circuit in the data line Dn according to the input data line potential Vd. Figure 35 is a circuit diagram showing the detection logic circuit C21 including the inverter circuit C22n.

[0009] Patent Document 4 discloses a wiring inspection device for identifying the location of short circuits. Figure 36 shows the configuration of the wiring inspection device disclosed in Patent Document 4. The wiring inspection device D1 in Figure 36 includes an imaging means D6 and an image processing means D7. The imaging means D6 captures an infrared image of the substrate member D2. The infrared image data is provided to the image processing means D7. After forming an infrared image and a binarized image, the image processing means D7 identifies the short circuit location from the binarized image.

[0010] Patent Document 5 discloses an inspection apparatus for thin-film transistor liquid crystal substrates. Figure 37 shows the configuration of the inspection apparatus disclosed in Patent Document 5. In Figure 37, probes E36a and E36b are brought into contact with the wiring pattern on the substrate E30. The potential difference between the scan line and the signal line is detected as an infrared image by the infrared image detector E5. The difference image detection circuit E55 and the coordinate detection circuit E56 identify the location of the short-circuit defect by image processing. [Prior art documents] [Patent Documents]

[0011] [Patent Document 1] International Publication No. 2018 / 079636 [Patent Document 2] Japanese Patent Publication No. 2019-113710 [Patent Document 3] U.S. Patent Application Publication No. 2006 / 0226866 [Patent Document 4] U.S. Patent Application Publication No. 2014 / 0204199 Specification [Patent Document 5] U.S. Patent No. 5309108 [Overview of the project] [Problems that the invention aims to solve]

[0012] In the fault testing circuit described in Patent Document 1, a first monitor output signal Gout from one gate line selected from multiple gate lines is input to a first determination circuit, and a second monitor signal Sout from one source line selected from multiple source lines is input to a second determination circuit. In this configuration, wiring and circuit connections become complex, and the size of the circuit increases. Also, if a comparator is used as an analog circuit for the expected value comparison circuit, the size of the circuit increases. Furthermore, if the characteristics of the many thin-film transistors differ, it becomes difficult to set the expected value. Therefore, the technology described in Patent Document 1 makes it difficult to perform stable testing with a small circuit.

[0013] The abnormality detection circuit described in Patent Document 2 uses a comparator as an analog circuit, which increases the size of the circuit. Furthermore, setting the reference voltage value becomes difficult when the characteristics of numerous thin-film transistors differ. Therefore, the technology described in Patent Document 2 makes stable testing with a small circuit difficult. The increased circuit size increases the area around the display device, often referred to as the "frame." Additionally, achieving stable testing tends to increase manufacturing and testing costs.

[0014] The test circuit described in Patent Document 3 connects the power supply potential and the ground potential via a series resistor. This series resistor generates a through-current. The generation of this through-current increases the power consumption of the device. If a configuration is provided to suppress power consumption, an increase in testing costs will occur.

[0015] The devices described in Patent Documents 4 and 5 require special image processing. This results in larger devices and increased manufacturing and inspection costs. Furthermore, while they can identify short-circuit locations, they cannot inspect for open circuits, making diverse inspections difficult.

[0016] This disclosure is made in view of the above circumstances and aims to reduce inspection costs and enable stable and diverse inspections through a compact and simple configuration. [Means for solving the problem]

[0017] To achieve the above object, the display device of the present disclosure includes a pixel portion, wiring and electrodes connected to the pixel portion, and an inspection circuit capable of inspecting abnormalities in the wiring, The inspection circuit supplies a first voltage to one or both of the wiring and the electrodes in a first period, supplies a second voltage to one of the wiring and the electrodes in a second period following the first period, and is capable of detecting the occurrence of an abnormality based on the voltage level of the wiring corresponding to the supply of the second voltage.

[0018] The wiring includes a plurality of gate lines and a plurality of data lines, the electrode is a common electrode, The inspection circuit includes a plurality of first voltage supply circuits arranged on both sides of the plurality of gate lines, a plurality of second voltage supply circuits arranged on both sides of the plurality of data lines, a first inspection data processing circuit arranged on one side of the plurality of gate lines, and a second inspection data processing circuit arranged on one side of the plurality of data lines. The first inspection data processing circuit and the second inspection data processing circuit may be configured using a shift register as a digital logic circuit. Alternatively, the wiring includes a plurality of gate lines and a plurality of data lines, the electrode is a common electrode, and further includes a plurality of scanning circuits arranged on both sides of the plurality of gate lines. The inspection circuit includes a plurality of first voltage supply circuits arranged on both sides of the plurality of gate lines, a plurality of second voltage supply circuits arranged on both sides of the plurality of data lines, a plurality of first inspection data processing circuits arranged on both sides of the plurality of gate lines, The circuit includes a second inspection data processing circuit located on one side of the plurality of data lines, The plurality of first and second test data processing circuits may be configured using shift registers as digital logic circuits.

[0019] For example, the wiring includes a plurality of gate lines and a plurality of data lines, The aforementioned test circuit is Multiple first voltage supply circuits arranged on both sides of the multiple gate lines, Multiple second voltage supply circuits arranged on both sides of the multiple data lines, Includes an inspection data processing circuit located on one side of the plurality of data lines, The plurality of first voltage supply circuits supply low-level voltages included in the first voltage to the plurality of gate lines. The plurality of second voltage supply circuits supply low-level voltages included in the first voltage to the plurality of data lines. The plurality of first voltage supply circuits supply a high-level voltage as the second voltage to the plurality of gate lines. The inspection data processing circuit may acquire the voltage levels in the plurality of gate lines based on the supply of the second voltage, and may detect the occurrence of an abnormality when the voltage level is high.

[0020] Furthermore, the wiring includes multiple gate wires, The aforementioned test circuit is Multiple voltage supply circuits arranged on both sides of the multiple gate lines, Includes an inspection data processing circuit located on one side of the plurality of gate lines, The plurality of voltage supply circuits supply a high-level voltage as the first voltage to the plurality of gate lines. Of the plurality of voltage supply circuits, the voltage supply circuit located on the input terminal side opposite the inspection data processing circuit supplies a low-level voltage as the second voltage to the plurality of gate lines. The inspection data processing circuit may acquire the voltage levels in the plurality of gate lines based on the supply of the second voltage, and may detect the occurrence of an abnormality when the voltage level is high.

[0021] Furthermore, the wiring includes multiple data lines, The aforementioned test circuit is Multiple voltage supply circuits arranged on both sides of the multiple data lines, Includes an inspection data processing circuit located on one side of the plurality of data lines, The plurality of voltage supply circuits supply a high-level voltage as the first voltage to the plurality of data lines. Of the plurality of voltage supply circuits, the voltage supply circuit located on the input terminal side opposite the inspection data processing circuit supplies a low-level voltage as the second voltage to the plurality of gate lines. The inspection data processing circuit may acquire the voltage levels on the plurality of data lines based on the supply of the second voltage, and may detect the occurrence of an abnormality when the voltage level is high.

[0022] Furthermore, the wiring includes multiple data lines, The electrode is a common electrode, The aforementioned test circuit is Multiple first voltage supply circuits arranged on both sides of the multiple data lines, Multiple second voltage supply circuits connected to the common electrode, Includes an inspection data processing circuit located on one side of the plurality of data lines, The plurality of first voltage supply circuits supply low-level voltages included in the first voltage to the plurality of data lines. The plurality of second voltage supply circuits supply the low-level voltage included in the first voltage to the common electrode. The plurality of second voltage supply circuits supply a high-level voltage as the second voltage to the common electrode. The inspection data processing circuit may acquire the voltage levels on the plurality of data lines based on the supply of the second voltage, and may detect the occurrence of an abnormality when the voltage level is high.

[0023] Furthermore, the wiring includes multiple gate wires, The electrode is a common electrode, The aforementioned test circuit is Multiple first voltage supply circuits arranged on both sides of the multiple gate lines, Multiple second voltage supply circuits connected to the common electrode, Includes an inspection data processing circuit located on one side of the plurality of gate lines, The plurality of first voltage supply circuits supply low-level voltages included in the first voltage to the plurality of gate lines. The plurality of second voltage supply circuits supply the low-level voltage included in the first voltage to the common electrode. The plurality of second voltage supply circuits supply a high-level voltage as the second voltage to the common electrode. The inspection data processing circuit may acquire the voltage levels on the plurality of data lines based on the supply of the second voltage, and may detect the occurrence of an abnormality when the voltage level is high.

[0024] The aforementioned wiring includes a plurality of gate lines and a plurality of data lines, The electrode is a common electrode, The aforementioned test circuit is A first inspection data processing circuit that acquires the voltage levels in the plurality of gate lines, It includes a second test data processing circuit that acquires the voltage levels in the plurality of data lines, The aforementioned test circuit is During a first blanking period between multiple display periods, the voltage levels of the multiple gate lines and one or both of the multiple gate lines are acquired by either the first inspection data processing circuit and the second inspection data processing circuit. During the multiple display periods, in the second blanking period following the first blanking period, the inspection data corresponding to the voltage level acquired by either or both of the first inspection data processing circuit and the second inspection data processing circuit may be output. Alternatively, the wiring includes a plurality of gate lines and a plurality of data lines, The electrode is a common electrode, The aforementioned test circuit is A first inspection data processing circuit that acquires the voltage levels in the plurality of gate lines, It includes a second test data processing circuit that acquires the voltage levels in the plurality of data lines, The aforementioned test circuit is During the blanking period between multiple display periods, the voltage levels of one or both of the multiple gate lines and the multiple data lines are acquired by either the first inspection data processing circuit or the second inspection data processing circuit. In the display period following the blanking period among the plurality of display periods, inspection data corresponding to the voltage level acquired by either or both of the first inspection data processing circuit and the second inspection data processing circuit may be output.

[0025] The inspection circuit may be mounted on the same substrate as the pixel unit. The inspection circuit may include a switch circuit of a type selected from CMOS transmission gates, PMOS transistors, or NMOS transistors, corresponding to the thin-film transistors formed on the substrate.

[0026] The inspection method for the display device disclosed herein is: A method for inspecting a display device, During a first period, a test circuit corresponding to the wiring and electrodes connected to the pixel portion of the display device supplies a first voltage to one or both of the wiring and the electrodes. The inspection circuit supplies a second voltage to either the wiring or the electrode during the second period following the first period. The inspection circuit detects the occurrence of an abnormality in accordance with the voltage level of the wiring based on the supply of the second voltage.

[0027] For example, a plurality of first voltage supply circuits arranged on both sides of a plurality of gate lines included in the wiring supply a low level voltage included in the first voltage to the plurality of gate lines. Multiple second voltage supply circuits, arranged on both sides of the multiple data lines included in the wiring, supply the low-level voltage included in the first voltage to the multiple data lines. The plurality of first voltage supply circuits supply a high-level voltage as the second voltage to the plurality of gate lines. A test data processing circuit, positioned on one side of the plurality of data lines, may acquire the voltage levels in the plurality of gate lines based on the supply of the second voltage, and if the voltage level is high, it may be possible to detect the occurrence of an abnormality.

[0028] Furthermore, multiple voltage supply circuits arranged on both sides of the multiple gate lines included in the wiring supply a high-level voltage as the first voltage to the multiple gate lines. Of the plurality of voltage supply circuits, a voltage supply circuit located on the input end side, which is opposite to the inspection data processing circuit located on one side of the plurality of gate lines, supplies a low-level voltage as the second voltage to the plurality of gate lines. The inspection data processing circuit may acquire the voltage levels in the plurality of gate lines based on the supply of the second voltage, and if the voltage level is high, it may be possible to detect the occurrence of an abnormality.

[0029] Furthermore, multiple voltage supply circuits arranged on both sides of the multiple data lines included in the wiring supply a high-level voltage as the first voltage to the multiple data lines. Of the plurality of voltage supply circuits, a voltage supply circuit located on the input end side, which is opposite to the test data processing circuit located on one side of the plurality of data lines, supplies a low-level voltage as the second voltage to the plurality of data lines. The inspection data processing circuit may acquire the voltage levels on the plurality of data lines based on the supply of the second voltage, and if the voltage level is high, it may be possible to detect the occurrence of an abnormality.

[0030] Furthermore, a plurality of first voltage supply circuits, arranged on both sides of the plurality of data lines included in the wiring, supply the low-level voltage included in the first voltage to the plurality of data lines. Multiple second voltage supply circuits connected to the common electrode, which serves as the electrode, supply the low-level voltage included in the first voltage to the common electrode. The plurality of second voltage supply circuits supply a high-level voltage as the second voltage to the common electrode. A test data processing circuit, positioned on one side of the plurality of data lines, may acquire the voltage levels on the plurality of data lines based on the supply of the second voltage, and if the voltage level is high, it may be possible to detect the occurrence of an abnormality.

[0031] Furthermore, the wiring includes multiple gate wires, The electrode is a common electrode, The aforementioned test circuit is Multiple first voltage supply circuits arranged on both sides of the multiple gate lines, Multiple second voltage supply circuits connected to the common electrode, Includes an inspection data processing circuit located on one side of the plurality of gate lines, Multiple first voltage supply circuits, arranged on both sides of the multiple gate lines included in the wiring, supply the low-level voltage included in the first voltage to the multiple gate lines. Multiple second voltage supply circuits connected to the common electrode, which serves as the electrode, supply the low-level voltage included in the first voltage to the common electrode. The plurality of second voltage supply circuits supply a high-level voltage as the second voltage to the common electrode. A test data processing circuit located on one side of the plurality of gate lines may be used to acquire the voltage levels in the plurality of gate lines based on the supply of the second voltage, and to detect the occurrence of an abnormality when the voltage level is high.

[0032] During the first blanking period between multiple display periods, the voltage levels of multiple gate wires and one or both of the multiple gate wires included in the wiring are acquired as the voltage levels in the wiring. During the multiple display periods, in the second blanking period following the first blanking period, inspection data corresponding to the voltage level in the wiring may be output. Alternatively, the wiring includes a plurality of gate lines and a plurality of data lines, The electrode is a common electrode, The aforementioned test circuit is A first inspection data processing circuit that acquires the voltage levels in the plurality of gate lines, It includes a second test data processing circuit that acquires the voltage levels in the plurality of data lines, The aforementioned test circuit is During the blanking period between multiple display periods, the voltage levels of one or both of the gate lines and data lines included in the wiring are acquired as the voltage levels in the wiring. In the display period following the blanking period among the multiple display periods, inspection data corresponding to the voltage level in the wiring may be output. [Effects of the Invention]

[0033] According to this disclosure, the occurrence of anomalies can be detected by acquiring the voltage level of the wiring based on the first voltage in the first period and the second voltage in the second period. This reduces the circuit size and enables stable and diverse testing. Furthermore, it prevents current from flowing during testing, thereby reducing testing costs. [Brief explanation of the drawing]

[0034] [Figure 1] This is a schematic diagram of the display device. [Figure 2] (A) and (B) are diagrams illustrating examples of checking for short circuits in gate and data lines. [Figure 3] (A) and (B) are diagrams illustrating examples of inspecting for gate wire breakage. [Figure 4] (A) and (B) are diagrams illustrating examples of checking for data line breaks. [Figure 5] (A) and (B) are diagrams illustrating examples of checking for short circuits in data lines and common electrodes. [Figure 6] (A) and (B) are diagrams illustrating examples of checking for short circuits in the gate wire and common electrode. [Figure 7] This is a schematic diagram showing other components of the display device. [Figure 8] This diagram shows a schematic connection of the pre-charge circuit. [Figure 9] (A) to (C) are circuit diagrams showing example configurations of switch circuits. [Figure 10] This diagram shows a schematic connection of the test circuit for the common electrode. [Figure 11] (A) and (B) are diagrams showing example configurations of inspection data processing circuits. [Figure 12] This is a circuit diagram showing a CMOS type register circuit. [Figure 13] This is a circuit diagram showing a PMOS type register circuit. [Figure 14] This is a circuit diagram showing an NMOS type register circuit. [Figure 15] (A) and (B) are diagrams showing example configurations of inspection data processing circuits. [Figure 16] This is a circuit diagram showing a CMOS type register circuit. [Figure 17] This is a circuit diagram showing a PMOS type register circuit. [Figure 18] This is a circuit diagram showing an NMOS type register circuit. [Figure 19]This is a timing chart showing the display period and the blanking period. [Figure 20] This is a timing chart showing when short circuits in gate and data lines are checked. [Figure 21] This figure shows an example of what happens when a short circuit occurs in the gate line and data line. [Figure 22] This is a timing chart showing when gate and data line disconnections are being checked. [Figure 23] This figure shows an example where the gate wire is cut. [Figure 24] This is a timing chart for when a short circuit in the data line or gate line and the common electrode is being checked. [Figure 25] This figure shows an example of what happens when a short circuit occurs between the data line and the common electrode. [Figure 26] This is a timing chart for the inspection data processing circuit. [Figure 27] This is a timing chart for the inspection data processing circuit. [Figure 28] This is a timing chart for the inspection data processing circuit. [Figure 29] This figure shows the circuit configuration of the active matrix substrate described in Patent Document 1. [Figure 30] This is a diagram showing the configuration of a liquid crystal display device as described in Patent Document 2. [Figure 31] This figure shows an example of a circuit for an abnormality detection circuit described in Patent Document 2. [Figure 32] This is a diagram showing the configuration of a liquid crystal display device as described in Patent Document 3. [Figure 33] This is a schematic diagram of the data line test circuit described in Patent Document 3. [Figure 34] Figure 33 is a circuit diagram showing the equivalent circuit of the data line test circuit. [Figure 35] This is a circuit diagram showing a detection logic circuit including an inverter circuit. [Figure 36] This is a diagram showing the configuration of the wiring inspection device described in Patent Document 4. [Figure 37] This is a diagram showing the configuration of the inspection device described in Patent Document 5. [Modes for carrying out the invention]

[0035] The display device and the method for driving the display device according to the embodiment will be described below with reference to the drawings.

[0036] Figure 1 shows a schematic configuration of the display device 100. The display device 100 includes a substrate 11, a driver IC 12, and a determination circuit 13. The substrate 11 may be a thin-film transistor (TFT) substrate or the like. The driver IC 12 is electrically connected to the wiring located on the substrate 11. The driver IC 12 supplies drive signals for the display device 100 to each element on the substrate 11. The driver IC 12 may be a semiconductor device, a discrete circuit, or a software-controlled processor. The driver IC 12 may be mounted on the substrate 11 using chip-on-glass (COG) technology. Alternatively, the driver IC 12 may be externally mounted to the substrate 11. The determination circuit 13 uses the inspection data output from the substrate 11 to determine whether or not there is an abnormality.

[0037] Multiple circuit elements are mounted on the substrate 11. For example, the pixel array 21, scanning circuit 22, and demultiplexer 23 mounted on the substrate 11 can have a circuit configuration that can be mounted on a general TFT substrate. The pixel array 21 is a pixel section containing multiple pixel circuits. Each pixel circuit in the pixel array 21 includes a transistor for switching and a liquid crystal element. The pixel array 21 is connected to the scanning circuit 22 via multiple gate lines GL, which become scanning lines. The pixel array 21 is connected to the demultiplexer 23 via multiple data lines DL, which become video signal lines. The gate lines GL and data lines DL are wiring connected to the pixel array 21. The multiple pixel circuits included in the pixel array 21 are connected to a common electrode CB, which serves as a counter electrode. The common electrode CB is an electrode connected to the pixel array 21.

[0038] The pre-charge circuits 31A and 31B mounted on the substrate 11 are positioned on both sides of the gate line GL. The pixel array 21 is connected to the gate line GL between the pre-charge circuits 31A and 31B. Pre-charge circuit 31A is connected to one side of the gate line GL connected to the pixel array 21, and pre-charge circuit 31B is connected to the other side of the gate line GL connected to the pixel array 21. The outputs of pre-charge circuits 31A and 31B are connected to each other via the gate line GL connected to the pixel array 21. Pre-charge circuits 31A and 31B can supply a test voltage to the gate line GL included in the wiring connected to the pixel array 21. Pre-charge circuit 31A is connected to the gate line GL on the same side as the scanning circuit 22 when viewed from the pixel array 21. Pre-charge circuit 31B is connected to the gate line GL on the opposite side of the scanning circuit 22 when viewed from the pixel array 21. The side on the same side as the scanning circuit 22 is the side to which the normal signal is input to the gate line GL.

[0039] The pre-charge circuits 32A and 32B mounted on the substrate 11 are positioned on both sides of the data line DL. The pixel array 21 is connected to the data line DL between the pre-charge circuits 32A and 32B. Pre-charge circuit 32A is connected to one side of the data line DL connected to the pixel array 21, and pre-charge circuit 32B is connected to the other side of the data line DL connected to the pixel array 21. The outputs of pre-charge circuits 32A and 32B are connected to each other via the data line DL connected to the pixel array 21. Pre-charge circuits 32A and 32B can supply a test voltage to the data line DL included in the wiring connected to the pixel array 21. Pre-charge circuit 32A is connected to the data line DL on the same side as the demultiplexer 23 when viewed from the pixel array 21. Pre-charge circuit 32B is connected to the data line DL on the opposite side of the demultiplexer 23 when viewed from the pixel array 21. The side on the same side as the demultiplexer 23 is the side to which the normal signal is input to the data line DL.

[0040] Each pre-charge circuit 31A, 31B, 32A, and 32B includes a voltage generator and a switch circuit. The voltage generators in pre-charge circuits 31A and 31B generate a low or high level voltage that can be supplied to the gate line GL. The switch circuits in pre-charge circuits 31A and 31B switch the connection between the voltage generators in pre-charge circuits 31A and 31B and the gate line GL to off or on. The voltage generators in pre-charge circuits 32A and 32B generate a low or high level voltage that can be supplied to the data line DL. The switch circuits in pre-charge circuits 32A and 32B switch the connection between the voltage generators in pre-charge circuits 32A and 32B and the data line DL to off or on. The wiring including the gate line GL and the data line DL has an input terminal on the side to which the regular signal is input. The wiring including the gate line GL and the data line DL has an output terminal on the opposite side of the input terminal. Pre-charge circuit 31A is connected to the input terminal side of the gate line GL. The pre-charge circuit 31B is connected to the output end of the gate line GL. The pre-charge circuit 32A is connected to the input end of the data line DL. The pre-charge circuit 32B is connected to the output end of the data line DL.

[0041] The switch circuit is constructed using a switch element such as a metal-oxide-silicon field-effect transistor (MOSFET). When the switch circuit is ON, the switch element is in a conductive state. When the switch circuit is OFF, the switch element is in a non-conductive state. The MOS transistor used as the switch element may be a P-channel MOS (PMOS) transistor or an N-channel MOS (NMOS) transistor. The switch circuit may also be a complementary MOS (CMOS) transmission gate using a combination of PMOS and NMOS transistors. The type of switch circuit should be selectable in accordance with the thin-film transistors formed on the substrate 11.

[0042] The common electrode inspection circuit 33 mounted on the substrate 11 has multiple outputs connected to predetermined positions on the common electrode CB. The multiple outputs of the common electrode inspection circuit 33 are connected to each other via the common electrode CB connected to the pixel array 21. The common electrode inspection circuit 33 can supply an inspection voltage to the common electrode CB included in the electrodes connected to the pixel array 21. The common electrode inspection circuit 33 includes a voltage generator and a switch circuit. The voltage generator included in the common electrode inspection circuit 33 generates a low-level or high-level voltage that can be supplied to the common electrode CB. The switch circuit included in the common electrode inspection circuit 33 switches the connection between the voltage generator included in the common electrode inspection circuit 33 and the common electrode CB off or on.

[0043] The inspection data processing circuit 34 mounted on the substrate 11 is located at one end of the gate line GL. The inspection data processing circuit 34 is connected to the gate line GL at the output end, which is opposite the scanning circuit 22 and the precharge circuit 31A as viewed from the pixel array 21. The inspection data processing circuit 35 mounted on the substrate 11 is located at one end of the data line DL. The inspection data processing circuit 35 is connected to the data line DL at the output end, which is opposite the demultiplexer 23 and the precharge circuit 32A as viewed from the pixel array 21. The inspection data processing circuit 34 can acquire the voltage level of the gate line GL. The inspection data processing circuit 35 can acquire the voltage level of the data line DL. The inspection data processing circuit 34 enables detection of the voltage level of the gate line GL included in the wiring connected to the pixel array 21. The inspection data processing circuit 35 enables detection of the voltage level of the data line DL included in the wiring connected to the pixel array 21.

[0044] The pre-charge circuits 31A, 31B, 32A, and 32B, the common electrode inspection circuit 33, and the inspection data processing circuits 34 and 35 are mounted on the substrate 11 and can be included in the inspection circuit of the display device 100. The display device 100 includes a pixel array 21 as a pixel section. The pixel array 21 is connected to gate lines GL and data lines DL as wiring, and to a common electrode CB as an electrode. The inspection circuit of the display device 100 is connected to the wiring, including the gate lines GL and data lines DL, and to electrodes such as the common electrode CB. The inspection circuit of the display device 100 can inspect for abnormalities in the wiring, including the gate lines GL and data lines DL.

[0045] The inspection data processing circuits 34 and 35 use digital logic circuits instead of analog comparators. By using digital logic circuits, which are different from analog circuits, the integration density of the circuits can be increased. In addition, there is no need to correct for characteristic variations of thin-film transistors. The inspection data processing circuits 34 and 35 have a configuration that does not generate through-current. With such inspection data processing circuits 34 and 35, the circuit size is reduced and inspection costs are lowered. Therefore, the inspection circuit of the display device 100 can appropriately inspect for abnormalities such as line defects.

[0046] Examples of tests performed by the test circuit of the display device 100 are schematically shown in Figures 2 to 6. Figures 2(A) and 2(B) show the first example for testing a short circuit between the gate line GL and the data line DL. Figures 3(A) and 3(B) show the second example for testing a break in the gate line GL. Figures 4(A) and 4(B) show the third example for testing a break in the data line DL. Figures 5(A) and 5(B) show the fourth example for testing a short circuit between the data line DL and the common electrode CB. Figures 6(A) and 6(B) show the fifth example for testing a short circuit between the gate line GL and the common electrode CB.

[0047] The gate lines GL1 to GL3 shown in Figures 2(A) and 2(B) are included in multiple gate lines GL. The data lines DL1 to DL4 shown in Figures 2(A) and 2(B) are included in multiple data lines DL. Figure 2(A) shows the first step in the first example of the inspection. In this example, a line defect caused by a short SH1 occurs between gate line GL1 and data line DL2. The precharge circuits 31A and 31B in Figure 2(A) supply a low level voltage to gate lines GL1 to GL3. The precharge circuits 32A and 32B in Figure 2(A) supply a low level voltage to data lines DL1 to DL4. More generally, multiple gate lines GL are supplied with a low level voltage from both precharge circuits 31A and 31B as a common voltage for the same period. Multiple data lines DL are supplied with a low level voltage from both precharge circuits 32A and 32B as a common voltage for the same period. In Figure 2(A), the low-level voltage supplied from pre-charge circuits 31A and 31B to gate lines GL1 to GL3 is included in the first voltage supplied during the first period. In Figure 2(A), the low-level voltage supplied from pre-charge circuits 32A and 32B to data lines DL1 to DL4 is included in the first voltage supplied during the first period.

[0048] Figure 2(B) shows the second and third steps in the first example of the test. In Figure 2(B), precharge circuits 31A and 31B supply a high level of voltage to gate lines GL1 to GL3. Precharge circuits 32A and 32B in Figure 2(B) are in the off state and do not supply voltage to data lines DL1 to DL4. More generally, multiple gate lines GL are supplied with a high level of voltage from both precharge circuits 31A and 31B as a common voltage for the same period. Data lines DL are not supplied with voltage from both precharge circuits 32A and 32B and are in a floating state. In Figure 2(B), the high level of voltage supplied from precharge circuits 31A and 31B to gate lines GL1 to GL3 is included in the second voltage supplied in the second period. Note that precharge circuit 31B may be in the off state during the second period.

[0049] Based on the first and second steps in the first example described above, the inspection data processing circuit 34 acquires the voltage levels of data lines DL1 to DL4. For example, if data lines DL1, DL3, and DL4 are normal, the inspection data processing circuit 34 acquires a low voltage level. Conversely, if data line DL2 contains a line defect due to a short SH1 between it and gate line GL1, the inspection data processing circuit 34 acquires a high voltage level. More generally, if data line DL2 is shorted with at least one of the gate lines GL, the inspection data processing circuit 34 acquires a high voltage level. In the third step, the inspection data processing circuit 34 provides the inspection data output DD11 to the determination circuit 13. The determination circuit 13 can use the inspection data received from the inspection data processing circuit 34 to determine the occurrence of an abnormality.

[0050] The gate lines GL1 to GL4 shown in Figures 3(A) and 3(B) are included in multiple gate lines GL. Figure 3(A) shows the first step in a second example of the inspection. In this example, a line defect due to a break OP1 occurs in gate line GL3. The precharge circuits 31A and 31B in Figure 3(A) supply a high level of voltage to gate lines GL1 to GL4. More generally, multiple gate lines GL are supplied with a high level of voltage from the precharge circuits 31A and 31B on both sides as a common voltage for the same period. In Figure 3(A), the high level of voltage supplied from the precharge circuits 31A and 31B to gate lines GL1 to GL4 is included in the first voltage supplied in the first period.

[0051] Figure 3(B) shows the second and third steps in the second example of the test. In Figure 3(B), the precharge circuit 31A supplies a low level voltage to gate lines GL1 to GL4. In Figure 3(B), the precharge circuit 31B is in the off state and does not supply voltage to gate lines GL1 to GL4. More generally, multiple gate lines GL are supplied with a low level voltage as a common voltage for the same period from the precharge circuit 31A located on the input end side, opposite the test data processing circuit 35. In this case, the multiple gate lines GL are not supplied with voltage from the precharge circuit 31B located on the output end side. In Figure 3(B), the low level voltage supplied from the precharge circuit 31A to gate lines GL1 to GL4 is included in the second voltage supplied in the second period.

[0052] Based on the first and second steps in the second example described above, the inspection data processing circuit 35 acquires the voltage levels of gate lines GL1 to GL4. For example, if gate lines GL1, GL2, and GL4 are normal, the inspection data processing circuit 35 acquires a low voltage level. Conversely, if gate line GL3 contains a line defect due to a break OP1, the inspection data processing circuit 35 acquires a high voltage level. In the third step, the inspection data processing circuit 35 provides the inspection data output DD13 to the determination circuit 13. The determination circuit 13 can use the inspection data received from the inspection data processing circuit 35 to determine the occurrence of an abnormality.

[0053] The data lines DL1 to DL4 shown in Figures 4(A) and 4(B) are included in multiple data lines DL. Figure 4(A) shows the first step in the third example of the test. In this example, a line defect due to a break OP2 occurs in data line DL3. The precharge circuits 32A and 32B in Figure 4(A) supply a high level of voltage to data lines DL1 to DL4. More generally, multiple data lines DL are supplied with a high level of voltage from the precharge circuits 32A and 32B on both sides as a common voltage for the same period. In Figure 4(A), the high level of voltage supplied from the precharge circuits 32A and 32B to data lines DL1 to DL4 is included in the first voltage supplied in the first period.

[0054] Figure 4(B) shows the second and third steps in the third example of the test. In Figure 4(B), the precharge circuit 32A supplies a low level voltage to data lines DL1 to DL4. In Figure 4(B), the precharge circuit 32B is in the off state and does not supply voltage to data lines DL1 to DL4. More generally, multiple data lines DL are supplied with a low level voltage as a common voltage for the same period from the precharge circuit 32A located on the input end side, opposite the test data processing circuit 34. In this case, the multiple data lines DL are not supplied with voltage from the precharge circuit 32B located on the output end side. In Figure 4(B), the low level voltage supplied from the precharge circuit 32A to data lines DL1 to DL4 is included in the second voltage supplied in the second period.

[0055] Based on the first and second steps in the third example described above, the inspection data processing circuit 34 acquires the voltage levels of data lines DL1 to DL4. For example, if data lines DL1, DL2, and DL4 are normal, the inspection data processing circuit 34 acquires a low voltage level. Conversely, if data line DL3 contains a line defect due to a break OP2, the inspection data processing circuit 34 acquires a high voltage level. In the third step, the inspection data processing circuit 34 provides the inspection data output DD13 to the determination circuit 13. The determination circuit 13 can use the inspection data received from the inspection data processing circuit 34 to determine the occurrence of an abnormality.

[0056] In the second example of the inspection, the gate line GL is the target of inspection. The disconnection of the gate line GL is inspected using the inspection data processing circuit 35. In this example, the data line DL is not the target of inspection. When the disconnection of the gate line GL is inspected, the inspection data processing circuit 34 is not used. In the third example of the inspection, the data line DL is the target of inspection. The disconnection of the data line DL is inspected using the inspection data processing circuit 34. In this example, the gate line GL is not the target of inspection. When the disconnection of the data line DL is inspected, the inspection data processing circuit 35 is not used. Therefore, the disconnection of the gate line GL and the disconnection of the data line DL can be inspected simultaneously.

[0057] The data lines DL1 to DL4 shown in Figures 5(A) and 5(B) are included in multiple data lines DL. Figure 5(A) shows the first step in the fourth example of the inspection. In this example, a line defect due to a short SH2 occurs between data line DL3 and the common electrode CB. The precharge circuits 32A and 32B in Figure 5(A) supply a low level voltage to data lines DL1 to DL4. The common electrode inspection circuit 33 in Figure 5(A) supplies a low level voltage to the common electrode CB. More generally, multiple data lines DL are supplied with a low level voltage from the precharge circuits 32A and 32B on both sides as a common voltage for the same period. The common electrode CB is supplied with a low level voltage from the common electrode inspection circuit 33. In Figure 5(A), the low level voltage supplied from the precharge circuits 32A and 32B to data lines DL1 to DL4 is included in the first voltage supplied in the first period. In Figure 5(A), the low-level voltage supplied from the common electrode test circuit 33 to the common electrode CB is included in the first voltage supplied during the first period.

[0058] Figure 5(B) shows the second and third steps in the fourth example of the test. In Figure 5(B), the precharge circuits 32A and 32B are in the off state and do not supply voltage to the data lines DL1 to DL4. More generally, the data line DL is in a floating state, with no voltage supplied from the precharge circuits 32A and 32B on both sides. In Figure 5(B), the common electrode test circuit 33 gradually supplies a high level of voltage to the common electrode CB. The voltage rise of the common electrode CB is slowed down by the pixel capacitance of the pixel array 21, including the holding capacitance of the pixel circuit. Since the voltage of the common electrode CB rises gradually, coupling between the common electrode CB and the gate line GL and data line DL is prevented. In Figure 5(B), the high level of voltage supplied from the common electrode test circuit 33 to the common electrode CB is included in the second voltage supplied in the second period.

[0059] Based on the first and second steps in the fourth example described above, the inspection data processing circuit 34 acquires the voltage levels of data lines DL1 to DL4. For example, if data lines DL1, DL2, and DL4 are normal, the inspection data processing circuit 34 acquires a low voltage level. Conversely, if data line DL3 contains a line defect due to a short SH2 with the common electrode CB, the inspection data processing circuit 34 acquires a high voltage level. In the third step, the inspection data processing circuit 34 provides the inspection data output DD14 to the determination circuit 13. The determination circuit 13 can use the inspection data received from the inspection data processing circuit 34 to determine the occurrence of an abnormality.

[0060] The gate lines GL1 to GL4 shown in Figures 6(A) and 6(B) are included in multiple gate lines GL. Figure 6(A) shows the first step in the fifth example of the inspection. In this example, a line defect due to a short SH3 occurs between gate line GL3 and the common electrode CB. The precharge circuits 31A and 31B in Figure 6(A) supply a low level voltage to the gate lines GL1 to GL4. The common electrode inspection circuit 33 in Figure 6(A) supplies a low level voltage to the common electrode CB. More generally, multiple gate lines GL are supplied with a low level voltage from the precharge circuits 31A and 31B on both sides as a common voltage for the same period. The common electrode CB is supplied with a low level voltage from the common electrode inspection circuit 33. In Figure 6(A), the low level voltage supplied from the precharge circuits 31A and 31B to the gate lines GL1 to GL4 is included in the first voltage supplied in the first period. In Figure 6(A), the low-level voltage supplied from the common electrode test circuit 33 to the common electrode CB is included in the first voltage supplied during the first period.

[0061] Figure 6(B) shows the second and third steps in the sixth example of the test. In Figure 6(B), the precharge circuits 31A and 31B are in the off state and do not supply voltage to the gate lines GL1 to GL4. More generally, the data line DL is in a floating state, with no voltage supplied from the precharge circuits 31A and 31B on both sides. In Figure 6(B), the common electrode test circuit 33 gradually supplies a high level of voltage to the common electrode CB. In Figure 6(B), the high level of voltage supplied from the common electrode test circuit 33 to the common electrode CB is included in the second voltage supplied in the second period.

[0062] Based on the first and second steps in the fifth example described above, the inspection data processing circuit 34 acquires the voltage levels of gate lines GL1 to GL4. For example, if gate lines GL1, GL2, and GL4 are normal, the inspection data processing circuit 34 acquires a low voltage level. Conversely, if gate line GL3 contains a line defect due to a short SH3 between it and the common electrode CB, the inspection data processing circuit 35 acquires a high voltage level. In the third step, the inspection data processing circuit 34 provides the inspection data output DD15 to the determination circuit 13. The determination circuit 13 can use the inspection data received from the inspection data processing circuit 34 to determine the occurrence of an abnormality.

[0063] In the fourth example of the inspection, the data line DL is the target of inspection. A short circuit between the data line DL and the common electrode CB is inspected using the inspection data processing circuit 34. In this example, the gate line GL is not the target of inspection. When a short circuit between the data line DL and the common electrode CB is inspected, the inspection data processing circuit 35 is not used. In the fifth example of the inspection, the gate line GL is the target of inspection. A short circuit between the gate line GL and the common electrode CB is inspected using the inspection data processing circuit 35. In this example, the data line DL is not the target of inspection. When a short circuit between the gate line GL and the common electrode CB is inspected, the inspection data processing circuit 34 is not used. Therefore, a short circuit between the data line DL and the common electrode CB, and a short circuit between the gate line GL and the common electrode CB can be inspected simultaneously.

[0064] The first voltage in the first period includes a common voltage supplied to multiple wirings under inspection. Low-level or high-level voltages supplied to multiple gate lines GL and low-level or high-level voltages supplied to multiple data lines DL are included in the first voltage in the first period, according to the inspection type. In contrast, during the display period, the voltages supplied in response to the scan signal from the scan circuit 22 and the video signal from the demultiplexer 23 include different voltages for multiple wirings. Therefore, the setting of the first voltage in the first period differs from the setting of the voltage in the display period.

[0065] The setting of the second voltage in the second period differs from the setting of the first voltage in the first period. Depending on the test type, the second voltage in the second period may or may not include a common voltage supplied to multiple wirings being tested. When the high-level voltage supplied to the common electrode CB is the second voltage, the gate line GL and data line DL are not supplied with the second voltage and are in a floating state. Therefore, the second voltage in the second period is supplied to one of the wirings and electrodes connected to the pixel array 21, but not to the other.

[0066] Figure 7 shows a schematic configuration of the display device 101 as an example of a configuration different from that of the display device 100. In Figure 7, components similar to those in Figure 1 are denoted by the same reference numerals. The display device 101 has scanning circuits 22A and 22B and inspection data processing circuits 35A and 35B as circuit elements mounted on the substrate 15. The scanning circuits 22A and 22B mounted on the substrate 15 are arranged on both sides of the gate line GL. The pixel array 21 is connected to the gate line GL between the scanning circuits 22A and 22B. Scanning circuit 22A is connected to one side of the gate line GL connected to the pixel array 21, and scanning circuit 22B is connected to the other side of the gate line GL connected to the pixel array 21. The outputs of scanning circuits 22A and 22B are connected to each other via the gate line GL connected to the pixel array 21. When one of the scanning circuits 22A or 22B is outputting a scanning signal, the other does not output a scanning signal. The driver IC 12 may be mounted on the substrate 15 using chip-on-glass (COG) technology. Alternatively, the driver IC 12 may be externally mounted to the substrate 15.

[0067] The inspection data processing circuits 35A and 35B mounted on the substrate 15 are positioned on both sides of the gate line GL. The pixel array 21 is connected to the gate line GL between the inspection data processing circuits 35A and 35B. Inspection data processing circuit 35A is connected to one side of the gate line GL connected to the pixel array 21, and inspection data processing circuit 35B is connected to the other side of the gate line GL connected to the pixel array 21. The inputs of inspection data processing circuits 35A and 35B are connected to each other via the gate line GL connected to the pixel array 21.

[0068] Among the test examples performed by the test circuit of the display device 101, the first example in which a short circuit between the gate line GL and the data line DL is detected is the same as the test example performed by the test circuit of the display device 100. Among the test examples performed by the test circuit of the display device 101, the third example in which a disconnection of the data line DL is checked is the same as the test example performed by the test circuit of the display device 100. Among the test examples performed by the test circuit of the display device 101, the fourth example in which a short circuit between the data line DL and the common electrode CB is detected is the same as the test example performed by the test circuit of the display device 100. Among the test examples performed by the test circuit of the display device 101, the fifth example in which a short circuit between the gate line GL and the common electrode CB is detected is the same as the test example performed by the test circuit of the display device 100.

[0069] The second example of the inspection performed by the inspection circuit of the display device 101, in which a break in the gate line GL is detected, differs from the inspection example performed by the inspection circuit of the display device 100. For example, when one of the inspection data processing circuits 35A and 35B acquires the voltage level of the gate line GL, the other does not acquire the voltage level of the gate line GL. Therefore, when an inspection is performed using one of the inspection data processing circuits 35A and 35B, which are located on both sides of the gate line GL, an inspection is not performed using the other.

[0070] Figure 8 shows a schematic connection of the pre-charge circuit. The gate line GLn shown in Figure 8 is one of several gate lines GL. The data line DLn shown in Figure 8 is one of several data lines DL. The gate line GLn and data line DLn are connected to the pixel circuit PCn included in the pixel array 21. The pixel circuit PCn is also connected to the common electrode CB.

[0071] The gate line GLn is connected to switch circuits SWG1 and SWG2. Switch circuit SWG1 is included in precharge circuit 31A. Switch circuit SWG2 is included in precharge circuit 31B. Voltage generators included in precharge circuits 31A and 31B generate a precharge voltage PCG. When switch circuit SWG1 is ON, the precharge voltage PCG generated in precharge circuit 31A is supplied to the gate line GLn. When switch circuit SWG1 is OFF, the precharge voltage PCG generated in precharge circuit 31A is not supplied to the gate line GLn. When switch circuit SWG2 is ON, the precharge voltage PCG generated in precharge circuit 31B is supplied to the gate line GLn. When switch circuit SWG2 is OFF, the precharge voltage PCG generated in precharge circuit 31B is not supplied to the gate line GLn.

[0072] The data line DLn is connected to switch circuits SWD1 and SWD2. Switch circuit SWD1 is included in precharge circuit 32A. Switch circuit SWD2 is included in precharge circuit 32B. Voltage generators included in precharge circuits 32A and 32B generate the precharge voltage PCD. When switch circuit SWD1 is ON, the precharge voltage PCD generated in precharge circuit 32A is supplied to the data line DLn. When switch circuit SWD1 is OFF, the precharge voltage PCD generated in precharge circuit 32A is not supplied to the data line DLn. When switch circuit SWD2 is ON, the precharge voltage PCD generated in precharge circuit 32B is supplied to the data line DLn. When switch circuit SWD2 is OFF, the precharge voltage PCD generated in precharge circuit 32B is not supplied to the data line DLn.

[0073] The common electrode CB is connected to the switch circuit SWC. The switch circuit SWC is included in the common electrode test circuit 33. The voltage generator included in the common electrode test circuit 33 generates a precharge voltage PCC. When the switch circuit SWC is ON, the precharge voltage PCC generated in the common electrode test circuit 33 is supplied to the common electrode CB. When the switch circuit SWC is OFF, the precharge voltage PCC generated in the common electrode test circuit 33 is not supplied to the common electrode CB.

[0074] The gate line GLn is connected to switch circuits SWT1 and SWT2. Switch circuit SWT1 switches the connection between the scanning circuit 22 and the gate line GLn to off or on. Switch circuit SWT2 switches the connection between the inspection data processing circuit 35 and the gate line GLn to off or on. When switch circuit SWT2 is on, the output signal GOn, which indicates the voltage level of the gate line GLn, is input to the inspection data processing circuit 35. When switch circuit SWT2 is off, the output signal GOn, which indicates the voltage level of the gate line GLn, is not input to the inspection data processing circuit 35.

[0075] The data line DLn is connected to the switch circuit SWT. The switch circuit SWT switches the connection between the test data processing circuit 34 and the data line DLn on or off. When the switch circuit SWT is on, the output signal DOn, which indicates the voltage level of the data line DLn, is input to the test data processing circuit 34. When the switch circuit SWT is off, the output signal DOn, which indicates the voltage level of the data line DLn, is not input to the test data processing circuit 34.

[0076] Examples of switch circuit configurations are shown in Figures 9(A) to 9(C). The type of switch circuit can be selected from CMOS, PMOS, and NMOS types. Figure 9(A) is a circuit diagram showing switch circuit SW1. Switch circuit SW1 is of the CMOS type. Figure 9(B) is a circuit diagram showing switch circuit SW2. Switch circuit SW2 is of the PMOS type. Figure 9(C) is a circuit diagram showing switch circuit SW3. Switch circuit SW3 is of the NMOS type. When the PMOS type switch circuit SW2 is used, the transistor for the switch included in the pixel circuit PCn in Figure 8 is also of the PMOS type.

[0077] In Figure 9(A), switch circuit SW1 includes switch input SI1 and switch output SO1. Switch circuit SW1 receives switch control signal SC1 and its inverted signal. Switch circuit SW1 switches off or on in response to switch control signal SC1 and its inverted signal. In Figure 9(B), switch circuit SW2 includes switch input SI2 and switch output SO2. Switch circuit SW2 receives the inverted signal of switch control signal SC2. Switch circuit SW2 switches off or on in response to the inverted signal of switch control signal SC2. In Figure 9(C), switch circuit SW3 includes switch input SI3 and switch output SO2. Switch circuit SW3 receives switch control signal SC3. Switch circuit SW3 switches off or on in response to switch control signal SC3.

[0078] In Figure 8, a common type is selected for the switch circuits SWG1, SWG2, SWD1, SWD2, SWC, SWT1, SWT2, and SWT. For example, if the thin-film transistor is formed using low-temperature polysilicon with NMOS and PMOS transistors integrated on the same substrate, a CMOS type switch circuit SW1 may be selected. If the thin-film transistor is formed using a specific single-conductivity type of low-temperature polysilicon or organic TFT, a PMOS type switch circuit SW2 may be selected. If the thin-film transistor is formed using another single-conductivity type of low-temperature polysilicon or In-Ga-Zn-O semiconductor (IGZO) or amorphous silicon (a-Si), an NMOS type switch circuit SW3 may be selected. Which type should be selected depends on the manufacturing process of the scanning circuit 22 and demultiplexer 23, which are integrally formed on the substrate 11.

[0079] When the switch circuit SWG1 in Figure 8 is the same as the switch circuit SW1 in Figure 9(A), the switch circuit SWG1 receives the switch control signal GN and its inverted signal. In this case, the switch circuit SWG1 switches off or on in response to the switch control signal GN and its inverted signal. When the switch circuit SWG1 in Figure 8 is the same as the switch circuit SW2 in Figure 9(B), the switch circuit SWG1 receives the inverted signal of the switch control signal GN. In this case, the switch circuit SWG1 switches off or on in response to the inverted signal of the switch control signal GN. When the switch circuit SWG1 in Figure 8 is the same as the switch circuit SW3 in Figure 9(C), the switch circuit SWG1 receives the switch control signal GN. In this case, the switch circuit SWG1 switches off or on in response to the switch control signal GN. Thus, the switch circuit SWG1 in Figure 8 switches off or on in response to one or both of the switch control signal GN and its inverted signal. In Figure 8, the switch circuit SWG2 switches off or on in response to one or both of the switch control signal GF and its inverting signal.

[0080] In Figure 8, switch circuit SWD1 switches off or on in response to one or both of the switch control signal DN and its inverted signal. Switch circuit SWD2 in Figure 8 switches off or on in response to one or both of the switch control signal DF and its inverted signal. Switch circuit SWC in Figure 8 switches off or on in response to one or both of the switch control signal COM and its inverted signal. Switch circuit SWT1 in Figure 8 switches off or on in response to one or both of the switch control signal TEST1 and its inverted signal. Switch circuit SWT2 in Figure 8 switches off or on in response to one or both of the switch control signal TEST2 and its inverted signal. Switch circuit SWT in Figure 8 switches off or on in response to one or both of the switch control signal TEST and its inverted signal. More generally, a switch circuit switches off or on in response to one or both of the switch control signal and its inverted signal.

[0081] Figure 10 shows a schematic connection of the common electrode test circuit 33. In Figure 10, switch circuits SWC11 to SWC1n and switch circuits SWC21 to SWC2n are included in the common electrode test circuit 33. Switch circuits SWC11 to SWC1n are connected to one side of the common electrode CB. Switch circuits SWC21 to SWC2n are connected to the other side of the common electrode CB. The common electrode test circuit 33 includes multiple switch circuits arranged on both sides of the common electrode CB. In Figure 10, a common type is selected for switch circuits SWC11 to SWC1n and switch circuits SWC21 to SWC2n. The types of the multiple switch circuits shown in Figure 10 can be the same as the types of switch circuits SWC in Figure 8.

[0082] When the switch circuit SWC11 in Figure 10 is the same as the switch circuit SW1 in Figure 9(A), the switch circuit SWC11 receives the switch control signal COM and its inverted signal. In this case, the switch circuit SWC11 switches off or on in response to the switch control signal COM and its inverted signal. When the switch circuit SWC11 in Figure 10 is the same as the switch circuit SW2 in Figure 9(B), the switch circuit SWC11 receives the inverted signal of the switch control signal COM. In this case, the switch circuit SWC11 switches off or on in response to the inverted signal of the switch control signal COM. When the switch circuit SWC11 in Figure 10 is the same as the switch circuit SW3 in Figure 9(C), the switch circuit SWC11 receives the switch control signal COM. In this case, the switch circuit SWC11 switches off or on in response to the switch control signal COM. Thus, the switch circuit SWC11 in Figure 10 switches off or on in response to one or both of the switch control signal COM and its inverted signal. Similarly, the multiple switch circuits included in the common electrode test circuit 33, such as the switch circuits SWC11~SWC1n and SWC21~SWC2n in Figure 10, are switched off or on in response to one or both of the switch control signal COM and its inverting signal.

[0083] An example configuration of the inspection data processing circuit 34 is shown in Figures 11(A) and 11(B). The inspection data processing circuit 34 can be any shift register capable of outputting inspection data corresponding to the voltage levels at multiple gate lines GL. The shift register in the inspection data processing circuit 34 can serially output inspection data corresponding to the voltage levels input in parallel from multiple gate lines GL. The shift register SR11 shown in Figure 11(A) is of the CMOS type. The shift register SR12 shown in Figure 11(B) is of the PMOS or NMOS type. The type of shift register in the inspection data processing circuit 34 is the same as the type of precharge circuits 31A, 31B, 32A, and 32B. Which type should be selected depends on the manufacturing process of the scanning circuit 22 and demultiplexer 23 which are integrally formed on the substrate 11.

[0084] The shift register SR11 in Figure 11(A) includes multiple cascaded register circuits RG11. Each register circuit RG11 acquires a voltage level from one of multiple gate lines GL. For example, a register circuit RG11 may be a D-type flip-flop circuit using multiple CMOS inverter circuits and multiple transmission gates. The transmission gate is equivalent to the switch circuit SW1 shown in Figure 9(A). The multiple register circuits RG11 in the shift register SR11 transfer test data from the preceding stage to the succeeding stage using the clock signal GCLK and its inverted signal. The last register circuit RG11 supplies the test data output GTD to the determination circuit 13.

[0085] The shift register SR12 in Figure 11(B) includes multiple cascaded register circuits RG12. Each register circuit RG12 acquires a voltage level from one of multiple gate lines GL. For example, a register circuit RG12 may be a temporary memory circuit using multiple PMOS transistors and retaining capacitors. Alternatively, a register circuit RG12 may be a temporary memory circuit using multiple NMOS transistors and retaining capacitors. The multiple register circuits RG12 in the shift register SR12 transfer the output start signal GST from the preceding stage to the succeeding stage by using the clock signal GCLK and the inverted signal of the clock signal GCLK. Each stage's register circuit RG12 supplies the test data output GTD to the determination circuit 13 at a timing based on the output start signal GST.

[0086] Figure 12 is a circuit diagram showing an example configuration of the register circuit RG11. The register circuit RG11 constitutes a two-stage latch circuit using transmission gates. The register circuit RG11 includes inverter circuits IN11 to IN14 and transmission gates SG11 to SG15. Inverter circuits IN11 and IN12 and transmission gates SG11 and SG12 constitute the first-stage latch circuit. Inverter circuits IN13 and IN13 and transmission gates SG13 and SG14 constitute the second-stage latch circuit. In the second-stage latch circuit, the clock signal GCLK and inverting signal supplied to transmission gates SG13 and SG14 are in opposite phase to the clock signal GCLK and inverting signal supplied to transmission gates SG11 and SG12 in the first-stage latch circuit.

[0087] Terminal GS11 is the D input terminal in register circuit RG11. Terminal GT11 is the Q output terminal in register circuit RG11. Terminal GS11 is connected to terminal GT11 in the preceding register circuit RG11. In the first register circuit RG11, terminal GS11 is unused and only needs to be connected to a low-level voltage source or the ground terminal. Terminal GT11 is connected to terminal GS11 in the subsequent register circuit RG11. In the last register circuit RG11, terminal GT11 provides the test data output GTD.

[0088] Figure 13 is a circuit diagram showing an example configuration of a PMOS type register circuit RG12. The register circuit RG12 in Figure 13 includes multiple PMOS transistors TR21 to TR25 and a retaining capacitor C21. Terminal GS21 is connected to terminal GT22 in the preceding register circuit RG12. In the foremost register circuit RG12, the output start signal GST is input to terminal GS21. Terminal GS22 is connected to terminal GT21 in the preceding register circuit RG12. In the foremost register circuit RG12, terminal GS22 is unused. Terminal GT21 is connected to terminal GS22 in the subsequent register circuit RG12. In the last register circuit RG12, terminal GT21 is unused. Terminal GT22 is connected to terminal GS21 in the subsequent register circuit RG12. In the last register circuit RG12, terminal GT22 is unused.

[0089] Figure 14 is a circuit diagram showing an example configuration of an NMOS type register circuit RG12. The register circuit RG12 in Figure 14 includes multiple NMOS transistors TR31 to TR35 and a retaining capacitor C31. Terminal GS31 is connected to terminal GT32 in the preceding register circuit RG12. In the foremost register circuit RG12, the output start signal GST is input to terminal GS31. Terminal GS32 is connected to terminal GT31 in the preceding register circuit RG12. In the foremost register circuit RG12, terminal GS32 is unused. Terminal GT31 is connected to terminal GS32 in the subsequent register circuit RG12. In the last register circuit RG12, terminal GT31 is unused. Terminal GT32 is connected to terminal GS31 in the subsequent register circuit RG12. In the last register circuit RG12, terminal GT32 is unused.

[0090] An example configuration of the inspection data processing circuit 35 is shown in Figures 15(A) and 15(B). The inspection data processing circuit 35 can be any shift register capable of outputting inspection data corresponding to the voltage levels on multiple data lines DL. The shift register in the inspection data processing circuit 35 can serially output inspection data corresponding to the voltage levels input in parallel from multiple data lines DL. The shift register SR21 shown in Figure 15(A) is of the CMOS type. The shift register SR22 shown in Figure 15(B) is of the PMOS or NMOS type. The type of shift register in the inspection data processing circuit 35 is the same as the type of precharge circuits 31A, 31B, 32A, 32B and the inspection data processing circuit 34. Which type should be selected depends on the manufacturing process of the scanning circuit 22 and demultiplexer 23 which are integrally formed on the substrate 11.

[0091] The shift register SR21 in Figure 15(A) includes multiple cascaded register circuits RG21. Each register circuit RG21 acquires a voltage level from one of multiple data lines DL. For example, a register circuit RG21 may be a D-type flip-flop circuit using multiple CMOS inverter circuits and multiple transmission gates. The transmission gate is equivalent to the switch circuit SW1 shown in Figure 9(A). The multiple register circuits RG11 in the shift register SR21 transfer test data from the preceding stage to the succeeding stage using the clock signal DCLK and its inverted signal. The last register circuit RG21 supplies the test data output DTD to the determination circuit 13.

[0092] The shift register SR22 in Figure 15(B) includes multiple cascaded register circuits RG22. Each register circuit RG22 acquires a voltage level from one of multiple data lines DL. For example, a register circuit RG22 may be a temporary memory circuit using multiple PMOS transistors and retaining capacitors. Alternatively, a register circuit RG22 may be a temporary memory circuit using multiple NMOS transistors and retaining capacitors. The multiple register circuits RG22 in the shift register SR22 transfer the output start signal DST from the preceding stage to the succeeding stage by using the clock signal DCLK and the inverted signal of the clock signal DCLK. Each stage's register circuit RG22 supplies the test data output DTD to the determination circuit 13 at a timing based on the output start signal DST.

[0093] Figure 16 is a circuit diagram showing an example configuration of register circuit RG21. Register circuit RG21 constitutes a two-stage latch circuit using transmission gates. Register circuit RG21 includes inverter circuits IN21 to IN24 and transmission gates SG21 to SG25. Inverter circuits IN21 and IN22 and transmission gates SG21 and SG22 constitute the first-stage latch circuit. Inverter circuits IN23 and IN24 and transmission gates SG23 and SG24 constitute the second-stage latch circuit. In the second-stage latch circuit, the clock signal DCLK and inverting signal supplied to transmission gates SG23 and SG24 are in opposite phase to the clock signal DCLK and inverting signal supplied to transmission gates SG21 and SG22 in the first-stage latch circuit.

[0094] Terminal DS11 is the D input terminal in register circuit RG21. Terminal DT11 is the Q output terminal in register circuit RG21. Terminal DS11 is connected to terminal DT11 in the preceding register circuit RG21. In the foremost register circuit RG21, terminal DS11 is unused and only needs to be connected to a low-level voltage source or the ground terminal. Terminal DT11 is connected to terminal DS11 in the subsequent register circuit RG21. In the last register circuit RG21, terminal DT11 provides the test data output DTD.

[0095] Figure 17 is a circuit diagram showing an example configuration of a PMOS type register circuit RG22. The register circuit RG22 in Figure 17 includes multiple PMOS transistors TR41 to TR45 and a retaining capacitor C41. Terminal DS41 is connected to terminal DT42 in the preceding register circuit RG22. In the foremost register circuit RG22, the output start signal DST is input to terminal DS41. Terminal DS42 is connected to terminal DT41 in the preceding register circuit RG22. In the foremost register circuit RG22, terminal DS42 is unused. Terminal DT41 is connected to terminal DS42 in the subsequent register circuit RG22. In the last register circuit RG22, terminal DT41 is unused. Terminal DT42 is connected to terminal DS41 in the subsequent register circuit RG22. In the last register circuit RG22, terminal DT42 is unused.

[0096] Figure 18 is a circuit diagram showing an example configuration of an NMOS type register circuit RG22. The register circuit RG22 in Figure 18 includes multiple NMOS transistors TR51 to TR55 and a retaining capacitor C51. Terminal DS51 is connected to terminal DT52 in the preceding register circuit RG22. In the foremost register circuit RG22, the output start signal DST is input to terminal DS51. Terminal DS52 is connected to terminal DT51 in the preceding register circuit RG22. In the foremost register circuit RG22, terminal DS52 is unused. Terminal DT51 is connected to terminal DS52 in the subsequent register circuit RG22. In the last register circuit RG22, terminal DT51 is unused. Terminal DT52 is connected to terminal DS51 in the subsequent register circuit RG22. In the last register circuit RG22, terminal DT52 is unused.

[0097] The gate line GL and data line DL are checked when the display device is started. Additionally, the gate line GL and data line DL are checked during the blanking period of the video display. The blanking period of the video display is scheduled after the display period.

[0098] Figure 19 is a timing chart showing the display period and blanking period. When the display device displays an image, multiple blanking periods are set between multiple display periods. In Figure 19, blanking periods TB01 to TB04 are set between display periods TA01 to TA05. Of the inspections described in the first to fifth examples above, the voltage level corresponding to one or more inspections is acquired during one of the multiple blanking periods. In the next of the multiple blanking periods, inspection data corresponding to the voltage level acquisition result is output.

[0099] For example, in the first example of the inspection shown in Figures 2(A) and 2(B), the first and second steps are performed during the blanking period TB01. The inspection data processing circuit 34 acquires the voltage levels on multiple data lines DL during the blanking period TB01. The inspection data processing circuit 34 provides the inspection data output DTD during the blanking period TB02 following the blanking period TB01.

[0100] In the second example inspection in Figures 3(A) and 3(B), and the third example inspection in Figures 4(A) and 4(B), the first and second steps are performed during the blanking period TB03. The inspection data processing circuit 34 acquires the voltage levels of multiple data lines DL during the blanking period TB03. The inspection data processing circuit 35 acquires the voltage levels of multiple gate lines GL during the blanking period TB03. The inspection data processing circuit 34 provides the inspection data output DTD during the blanking period TB04 following the blanking period TB03. The inspection data processing circuit 35 provides the inspection data output GTD during the blanking period TB04 following the blanking period TB03.

[0101] The inspection data output DTD and inspection data output GTD may be provided over multiple display periods. For example, in the first example inspection shown in Figures 2(A) and 2(B), the first and second steps are performed in a blanking period TB01. The inspection data processing circuit 34 provides the inspection data output DTD in a display period TA02 following the blanking period TB01. In the second example inspection shown in Figures 3(A) and 3(B), and the third example inspection shown in Figures 4(A) and 4(B), the first and second steps are performed in a blanking period TB02 following the blanking period TB01. The inspection data processing circuit 34 provides the inspection data output DTD in a display period TA03 following the blanking period TB02. The inspection data processing circuit 35 provides the inspection data output GTD in a display period TA03 following the blanking period TB02. In the fourth example inspection in Figures 5(A) and 5(B), and in the fifth example inspection in Figures 6(A) and 6(B), the first and second steps are performed in the blanking period TB03 following the blanking period TB02. The inspection data processing circuit 34 provides the inspection data output DTD in the display period TA04 following the blanking period TB03. The inspection data processing circuit 35 provides the inspection data output GTD in the display period TA04 following the blanking period TB03.

[0102] Figure 20 is a timing chart showing when a short circuit is checked on the gate line GL and data line DL. The blanking period TB21 in Figure 20 includes the first period TC21, the second period TC22, and the third period TC23. When the first period TC21 begins, the switch control signals GN, GF, DN, and DF in Figure 8 change from low to high levels. These inverting signals change from high to low levels. The precharge voltages PCG and PCD are set to low levels in the first period TC21. The switch circuits SWG1, SWG2, SWD1, and SWD2 in Figure 8 are turned on in the first period TC21. The gate line GLn in Figure 8 is supplied with a low level precharge voltage PCG in the first period TC21. The data line DLn in Figure 8 is supplied with a low level precharge voltage PCD in the first period TC21. Therefore, during the first period TC21, a low-level precharge voltage PCG included in the first voltage is supplied to the gate line GLn from both precharge circuits 31A and 31B, and a low-level precharge voltage PCD included in the first voltage is supplied to the data line DLn from both precharge circuits 32A and 32B. This initializes the voltage levels of the gate line GLn and the data line DLn. Since the precharge voltage PCG is supplied by precharge circuits 31A and 31B located on both sides of the gate line GLn, smooth initialization of the voltage level is possible regardless of the line impedance of the gate line GLn. Since the precharge voltage PCD is supplied by precharge circuits 32A and 32B located on both sides of the data line DLn, smooth initialization of the voltage level is possible regardless of the line impedance of the data line DLn.

[0103] As the first period TC21 in Figure 20 ends, the switch control signals DN and DF change from high to low levels. These inverting signals change from low to high levels. When the second period TC22 begins following the first period TC21, the precharge voltage PCG is set to a high level. The switch control signal GN remains at a high level during the second period TC22. The switch circuit SWG1 in Figure 8 is on during the second period TC22. The switch circuits SWD1 and SWD2 in Figure 8 are off during the second period TC22. The gate line GLn in Figure 8 is supplied with a high-level precharge voltage PCG during the second period TC22. The data line DLn in Figure 8 is floating during the second period TC22. Therefore, during the second period TC22, a high-level precharge voltage PCG is supplied to the gate line GLn as a second voltage from both precharge circuits 31A and 31B. Since the precharge voltage PCG is supplied by the precharge circuits 31A and 31B located on both sides of the gate line GLn, a smooth supply of the second voltage is possible regardless of the line impedance of the gate line GLn.

[0104] When the third period TC23 in Figure 20 begins, the switch control signal TEST changes from a low level to a high level. Its inverse signal changes from a high level to a low level. The switch circuit SWT in Figure 8 is turned on during the third period TC23. The test data processing circuit 34 acquires the voltage level of the data line DLn during the third period TC23. When there is no short circuit between the gate line GLn and the data line DLn, the high-level precharge voltage PCG supplied to the gate line GLn does not affect the data line DLn. In this case, the voltage of the data line DLn is low during the third period TC23.

[0105] Figure 21 illustrates the case where a short circuit occurs between the gate line GLn and the data line DLn. When a short circuit occurs between the gate line GLn and the data line DLn, the high-level precharge voltage PCG supplied to the gate line GLn is transmitted to the data line DLn via the short-circuit resistor RS1. The short-circuit resistor RS1 is the resistance of the short circuit formed between the gate line GLn and the data line DLn. In this case, the voltage across the data line DLn is high during the third period TC23.

[0106] Figure 22 is a timing chart for when the gate line GL is checked for disconnection. In addition, Figure 22 is a timing chart for when the data line DLn is checked for disconnection. The blanking period TB31 in Figure 22 includes the first period TC31, the second period TC32, and the third period TC33. When the first period TC31 begins, the switch control signals GN and GF in Figure 8 change from low to high levels. These inverting signals change from high to low levels. The precharge voltage PCG is set to a high level in the first period TC31. The switch circuits SWG1 and SWG2 in Figure 8 are turned on in the first period TC31. The gate line GLn in Figure 8 is supplied with a high level precharge voltage PCG in the first period TC31. Therefore, in the first period TC31, a high level precharge voltage PCG is supplied to the gate line GLn as the first voltage from both precharge circuits 31A and 31B. This initializes the voltage level of the gate line GLn. Since the precharge voltage PCG is supplied by the precharge circuits 31A and 31B located on both sides of the gate line GLn, a smooth supply of the first voltage is possible regardless of the line impedance of the gate line GLn.

[0107] As the first period TC31 in Figure 22 ends, the switch control signal GF changes from a high level to a low level. Its inverse signal changes from a low level to a high level. At this time, the precharge voltage PCG is set to a low level. The switch control signal GN remains at a high level in the second period TC32 following the first period TC31. In Figure 8, the switch circuit SWG1 is on in the second period TC32. In Figure 8, the switch circuit SWG2 is off in the second period TC32. In Figure 8, the gate line GLn is supplied with a low level precharge voltage PCG via the switch circuit SWG1 in the second period TC32. Therefore, in the second period TC32, a low level precharge voltage PCG is supplied to the gate line GLn from the precharge circuit 31A as a second voltage. In this case, of the precharge circuits 31A and 31B located on both sides of the gate line GLn, precharge circuit 31A, located on the opposite side of the inspection data processing circuit 35, supplies a precharge voltage PCG to the gate line GLn, while precharge circuit 31B, located on the same side as the inspection data processing circuit 35, does not supply a precharge voltage PCG to the gate line GLn. The inspection data processing circuit 35 acquires a low voltage level when there is no break in the gate line GLn, and a high voltage level when there is a break in the gate line GLn.

[0108] When the third period TC33 in Figure 22 begins, the switch control signal TEST2 changes from a low level to a high level. Its inverse signal changes from a high level to a low level. The switch circuit SWT2 in Figure 8 is turned on during the third period TC33. The test data processing circuit 35 acquires the voltage level of the gate line GLn during the third period TC33. If the gate line GLn is not disconnected, the low-level precharge voltage PCG supplied to the gate line GLn via the switch circuit SWG1 is provided as the output signal GOn.

[0109] Figure 23 illustrates the case where the gate line GLn is disconnected. When the gate line GLn is disconnected, the low-level precharge voltage PCG supplied through the switch circuit SWG1 cannot be provided as the output signal GOn. In this case, the output signal GOn of the gate line GLn is at a high level in the third period due to the precharge voltage PCG in the first period TC31.

[0110] When the first period TC31 in Figure 22 begins, the switch control signals DN and DF in Figure 8 change from low to high levels. These inverted signals change from high to low levels. The precharge voltage PCD is set to a high level in the first period TC31. The switch circuits SWD1 and SWD2 in Figure 8 are turned on in the first period TC31. The data line DLn in Figure 8 is supplied with a high-level precharge voltage PCD in the first period TC31. Therefore, in the first period TC31, a high-level precharge voltage PCD is supplied to the data line DLn as the first voltage from both precharge circuits 32A and 32B. This initializes the voltage level of the data line DLn. Since the precharge voltage PCD is supplied by precharge circuits 32A and 32B located on both sides of the data line DLn, smooth supply of the first voltage is possible regardless of the line impedance of the data line DLn.

[0111] As the first period TC31 in Figure 22 ends, the switch control signal DF changes from a high level to a low level. Its inverse signal changes from a low level to a high level. At this time, the precharge voltage PCD is set to a low level. The switch control signal DN remains at a high level in the second period TC32 following the first period TC31. In Figure 8, the switch circuit SWD1 is on in the second period TC32. In Figure 8, the switch circuit SWD2 is off in the second period TC32. In Figure 8, the data line DLn is supplied with a low level precharge voltage PCD via the switch circuit SWD1 in the second period TC32. Therefore, in the second period TC32, a low level precharge voltage PCD is supplied to the data line DLn from the precharge circuit 32A as a second voltage. In this case, of the precharge circuits 32A and 32B located on both sides of the data line DLn, precharge circuit 32A, located on the opposite side of the test data processing circuit 34, supplies a precharge voltage PCD to the data line DLn, while precharge circuit 32B, located on the same side as the test data processing circuit 34, does not supply a precharge voltage PCD to the data line DLn. The test data processing circuit 34 acquires a low voltage level when there is no disconnection in the data line DLn, and acquires a high voltage level when there is a disconnection in the data line DLn.

[0112] In Figure 22, when the third period TC33 begins, the switch control signal TEST changes from a low level to a high level. Its inverse signal changes from a high level to a low level. In Figure 8, the switch circuit SWT is turned on in the third period TC33. The test data processing circuit 34 acquires the voltage level of the data line DLn in the third period TC33. If the data line DLn is not disconnected, the low-level precharge voltage PCD supplied to the data line DLn via the switch circuit SWD1 is provided as the output signal DOn. If the data line DLn is disconnected, the low-level precharge voltage PCD supplied via the switch circuit SWD1 cannot be provided as the output signal DOn. In this case, the output signal DOn of the data line DLn is at a high level in the third period due to the precharge voltage PCD in the first period TC31.

[0113] Figure 24 is a timing chart for when a short circuit is checked between the data line DL and the common electrode CB. In addition, Figure 24 is a timing chart for when a short circuit is checked between the gate line GL and the common electrode CB. The blanking period TB41 in Figure 24 includes the first period TC41, the second period TC42, and the third period TC43. When the first period TC41 begins, the switch control signals DN, DF, and COM in Figure 8 change from low to high levels. These inverting signals change from high to low levels. The precharge voltage PCD is set to a low level in the first period TC41. The precharge voltage PCC is set to a low level in the first period TC41. The switch circuits SWD1, SWD2, and SWC in Figure 8 are turned on in the first period TC41. The data line DLn in Figure 8 is supplied with a low level of precharge voltage PCD in the first period TC41. The common electrode CB in Figure 8 is supplied with a low level of precharge voltage PCC in the first period TC41. Therefore, during the first period TC41, a low-level precharge voltage PCD included in the first voltage is supplied from precharge circuits 32A and 32B to the data line DLn, and a low-level precharge voltage PCC included in the first voltage is supplied from the common electrode test circuit 33 to the common electrode CB. Since the precharge voltage PCD is supplied by precharge circuits 32A and 32B located on both sides of the data line DLn, smooth initialization of the voltage level is possible regardless of the line impedance of the data line DLn. The common electrode test circuit 33 supplies the precharge voltage PCC to the common electrode CB using multiple switch circuits SWC11~SWC1n and SWC21~SWC2n shown in Figure 10, so that smooth initialization of the voltage level is possible regardless of the impedance of the common electrode CB.

[0114] As the first period TC41 in Figure 24 ends, the switch control signals DN and DF change from high to low levels. These inverted signals change from low to high levels. When the second period TC42 begins following the first period TC41, the precharge voltage PCC is set to a high level. The switch control signal COM remains at a high level during the second period TC42. The switch circuit SWC in Figure 8 is on during the second period TC42. The switch circuits SWD1 and SWD2 in Figure 8 are off during the second period TC42. The common electrode CB in Figure 8 is supplied with a high-level precharge voltage PCC during the second period TC42. The data line DLn in Figure 8 is floating during the second period TC42. Therefore, during the second period TC42, a high-level precharge voltage PCC is supplied to the common electrode CB from the common electrode test circuit 33 as a second voltage.

[0115] When the third period TC43 in Figure 24 begins, the switch control signal TEST changes from a low level to a high level. Its inverse signal changes from a high level to a low level. The switch circuit SWT in Figure 8 is turned on during the third period TC43. The test data processing circuit 34 acquires the voltage level of the data line DLn during the third period TC43. When there is no short circuit between the data line DLn and the common electrode CB, the high-level precharge voltage PCC supplied to the common electrode CB does not affect the data line DLn. In this case, the voltage of the data line DLn is low during the third period TC43.

[0116] Figure 25 illustrates the case where a short circuit occurs between the data line DLn and the common electrode CB. When a short circuit occurs between the data line DLn and the common electrode CB, the high-level precharge voltage PCC supplied to the common electrode CB is transmitted to the data line DLn via the short-circuit resistor RS2. The short-circuit resistor RS2 is the resistance of the short circuit formed between the data line DLn and the common electrode CB. In this case, the voltage across the data line DLn is high during the third period TC43.

[0117] When the first period TC41 in Figure 24 begins, the switch control signals GN, GF, and COM in Figure 8 change from low to high levels. These inverted signals change from high to low levels. The precharge voltage PCG is set to a low level in the first period TC41. The precharge voltage PCC is set to a low level in the first period TC41. The switch circuits SWG1, SWG2, and SWC in Figure 8 are turned on in the first period TC41. The gate line GLn in Figure 8 is supplied with a low-level precharge voltage PCG in the first period TC41. The common electrode CB in Figure 8 is supplied with a low-level precharge voltage PCC in the first period TC41. Therefore, in the first period TC41, the low-level precharge voltage PCG included in the first voltage is supplied from the precharge circuits 31A and 31B to the gate line GLn, and the low-level precharge voltage PCC included in the first voltage is supplied from the common electrode test circuit 33 to the common electrode CB. The precharge voltage PCG is supplied by the precharge circuits 31A and 31B located on both sides of the gate line GLn, enabling smooth initialization of the voltage level regardless of the line impedance of the gate line GLn. The common electrode test circuit 33 supplies the precharge voltage PCC to the common electrode CB using the multiple switch circuits SWC11~SWC1n and SWC21~SWC2n shown in Figure 10, enabling smooth initialization of the voltage level regardless of the impedance of the common electrode CB.

[0118] As the first period TC41 in Figure 24 ends, the switch control signals GN and GF change from high to low levels. These inverted signals change from low to high levels. When the second period TC42 begins following the first period TC41, the precharge voltage PCC is set to a high level. The switch control signal COM remains at a high level during the second period TC42. The switch circuit SWC in Figure 8 is on during the second period TC42. The switch circuits SWG1 and SWG2 in Figure 8 are off during the second period TC42. The common electrode CB in Figure 8 is supplied with a high level precharge voltage PCC during the second period TC42. The gate line GLn in Figure 8 is floating during the second period TC42. Therefore, during the second period TC42, a high level precharge voltage PCC is supplied to the common electrode CB from the common electrode test circuit 33 as a second voltage.

[0119] When the third period TC43 in Figure 24 begins, the switch control signal TEST2 changes from a low level to a high level. Its inverse signal changes from a high level to a low level. The switch circuit SWT2 in Figure 8 is turned on during the third period TC43. The test data processing circuit 35 acquires the voltage level of the gate line GLn during the third period TC43. When there is no short circuit between the gate line GLn and the common electrode CB, the high-level precharge voltage PCC supplied to the common electrode CB does not affect the gate line GLn. In this case, the voltage of the gate line GLn is low during the third period TC43. When there is a short circuit between the gate line GLn and the common electrode CB, the high-level precharge voltage PCC supplied to the common electrode CB is transmitted to the gate line GLn through the short-circuit resistor. In this case, the voltage of the gate line GLn is high during the third period TC43.

[0120] Figure 26 is a timing chart for the test data processing circuit 34 including the register circuit RG11 or the test data processing circuit 35 including the register circuit RG21. The register circuit RG11 in Figure 12 constitutes the CMOS type shift register SR11 shown in Figure 11(A). The register circuit RG21 in Figure 16 constitutes the CMOS type shift register SR21 shown in Figure 15(A).

[0121] In Figure 12, the register circuit RG11 receives a signal GON, which indicates the voltage level of the gate line GLn, and inputs this signal GON to the inverter circuit IN11. The output of the inverter circuit IN11 sets the voltage at node N11 to either a high-level voltage VGH or a low-level voltage VGL. For example, if the signal GON is at a low level, the voltage at node N11 is set to the low-level voltage VGH. If the signal GON is at a high level, the voltage at node N11 is set to the high-level voltage VGL.

[0122] When the transmission gate SG12 is ON, the voltage at node N12 is set to be equal to that at node N11. The voltage at node N12 is input to the inverter circuit IN12. The output of the inverter circuit IN12 is set to a high-level voltage VGH or a low-level voltage VGL, corresponding to the voltage level of the signal GOn. For example, when the signal GOn is at a low level, the output voltage of the inverter circuit IN12 is set to a low-level voltage VGL. When the signal GOn is at a high level, the output voltage of the inverter circuit IN12 is set to a high-level voltage VGH. Thus, the first-stage latch circuit obtains the voltage level of the gate line GLn indicated by the signal GOn.

[0123] Next, when transmission gate SG12 is turned off, transmission gates SG13 and SG14 are turned on. When transmission gate SG13 is on, the voltage at node N13 is set to be equal to that of node N12. When transmission gate SG14 is on, the voltage at node N14 is set to be equal to that of node N13. The voltage at node N14 is input to inverter circuit IN14. The output voltage of inverter circuit IN14 is set to a high-level voltage VGH or a low-level voltage VGL, corresponding to the voltage level at node N14. The output voltage of inverter circuit IN14 is input to inverter circuit IN13. The output voltage of inverter circuit IN13 is set to a high-level voltage VGH or a low-level voltage VGL by the output of inverter circuit IN14. In this way, the output of the first-stage latch circuit is obtained by the second-stage latch circuit. Then, when transmission gate SG15 is on, the output voltage of terminal GT11 is set to be equal to the voltage level at node N14.

[0124] In register circuit RG11, when transmission gate SG11 is ON, the voltage at node N11 is set to be equal to the input voltage of terminal GS11. When transmission gate SG11 is ON, transmission gate SG12 is also ON, so the voltage level at terminal GS11 is held by the first-stage latch circuit. Thereafter, similarly, the output of the first-stage latch circuit is acquired by the second-stage latch circuit. When transmission gate SG15 is ON, the output voltage of terminal GT11 is set to be equal to the voltage level of node N14. In this way, the multiple register circuits RG11 included in the shift register SR11 transmit a high-level voltage VGH or a low-level voltage VGL from the preceding stage to the succeeding stage, corresponding to the voltage level of the gate line GLn. The last-stage register circuit RG11 in the shift register SR11 can sequentially supply the test data output GTD to the judgment circuit 13.

[0125] In Figure 16, when the register circuit RG21 acquires the signal DOn, which indicates the voltage level of the data line DLn, the signal DOn is input to the inverter circuit IN21. The voltage at node N51 is set to be equal to the voltage level of signal DOn. The outputs of inverter circuits IN21 and IN22 set the voltage at node N52 to either a high-level voltage VGH or a low-level voltage VGL. For example, if the signal DOn is low, the voltage at node N52 is set to the low-level voltage VGL. If the signal DOn is high, the voltage at node N52 is set to the high-level voltage VGH. Thus, the voltage at node N52 corresponds to the voltage at node N51. Therefore, the first-stage latch circuit acquires the voltage level of the data line DLn indicated by the signal DOn.

[0126] Next, when transmission gates SG23 and SG24 are on, the voltage at node N53 is set to be equal to the voltage at node N52. The outputs of inverter circuits IN23 and IN24 set the voltage at node N54 to either a high level voltage VGH or a low level voltage VGL. For example, if the voltage at node N53 is low, the voltage at node N54 is set to the low level voltage VGL. If the voltage at node N53 is high, the voltage at node N54 is set to the high level voltage VGH. Thus, the voltage at node N54 corresponds to the voltage at node N53. Therefore, the output of the first-stage latch circuit is obtained by the second-stage latch circuit. Then, when transmission gate SG25 is on, the output voltage at terminal GT11 is set to be equal to the voltage level at node N54.

[0127] In register circuit RG21, when transmission gate SG21 is ON, the voltage at node N51 is set to be equal to the input voltage at terminal DS11. When transmission gate SG21 is ON, transmission gate SG22 is also ON, so the voltage level at terminal DS11 is held by the first-stage latch circuit. Thereafter, similarly, the output of the first-stage latch circuit is acquired by the second-stage latch circuit. When transmission gate SG25 is ON, the output voltage at terminal GT11 is set to be equal to the voltage level at node N54. In this way, the multiple register circuits RG21 included in the shift register SR21 transmit a high-level voltage VGH or a low-level voltage VGL from the preceding stage to the succeeding stage, corresponding to the voltage level of the data line DLn. The last-stage register circuit RG21 in the shift register SR21 can sequentially supply the test data output DTD to the determination circuit 13.

[0128] Figure 27 is a timing chart for the test data processing circuit 34, which includes the register circuit RG12, or the test data processing circuit 35, which includes the register circuit RG22. The register circuit RG12 in Figure 13 constitutes the PMOS type shift register SR12 shown in Figure 11(B). The register circuit RG22 in Figure 17 constitutes the PMOS type shift register SR22 shown in Figure 15(B).

[0129] In Figure 13, the register circuit RG12 acquires a signal GON indicating the voltage level of the gate line GLn, and holds that voltage level using the retaining capacitor C21. When the input voltage of terminal GS21 is low, the voltage at node N21 is set to the low-level voltage VGL minus the threshold voltage of the PMOS transistor. As a result, the voltage at terminal GT22 is set to be equal to the high-level clock signal GCLK. When the voltage at node N22 is high, the PMOS transistor TR21 is off, so the supply of the high-level voltage VGH to node N21 is cut off. When the output voltage of terminal GT21 is high, the retaining capacitor C21 is cut off from the test data output GTD. At this time, the test data output GTD corresponding to the voltage level of the retaining capacitor C21 is not supplied to the determination circuit 13.

[0130] Next, when the input voltage of terminal GS21 changes from a low level to a high level, the clock signal GCLK changes from a high level to a low level. The voltage at node N21 drops further due to the bootstrap effect by the amount obtained by subtracting the low level voltage VGL from the high level voltage VGH. The low-level clock signal GLCK is supplied to terminal GT22 without any voltage increase. The retaining capacitor C21 conducts with the test data output GTD. At this time, the test data output GTD corresponding to the voltage level of the retaining capacitor C21 is supplied to the judgment circuit 13.

[0131] Terminal GT22 is connected to terminal GS21 in the subsequent register circuit RG12. The first-stage register circuit RG12 receives an output start signal GST at terminal GS21. After the output start signal GST changes from a high level to a low level, and then changes from a low level to a high level, the first-stage register circuit RG12 supplies the test data output GTD. The output start signal GST is also transmitted from the first-stage register circuit RG12 to the second-stage register circuit RG12. Thereafter, the second-stage register circuit RG12 similarly supplies the data signal output GTD. In this way, the multiple register circuits RG12 included in the shift register SR12 can sequentially supply the test data output GTD to the judgment circuit 13 in accordance with the output start signal GST transmitted from the preceding stage to the succeeding stage.

[0132] In Figure 17, the register circuit RG22 holds the voltage level of the data line DLn using the retaining capacitor C41 when it acquires the signal DOn, which indicates the voltage level of the data line DLn. When the input voltage of terminal DS21 is low, the voltage of node N61 is set to the voltage obtained by subtracting the threshold voltage of the PMOS transistor from the low-level voltage VGL. As a result, the voltage of terminal DT22 is set to be equal to the high-level clock signal GCLK. When the voltage of node N62 is high, the PMOS transistor TR41 is off, so the supply of voltage VGH to node N61 is cut off. When the output voltage of terminal DT21 is high, the retaining capacitor C41 is cut off from the test data output DTD. At this time, the test data output DTD corresponding to the voltage level of the retaining capacitor C41 is not supplied to the determination circuit 13.

[0133] Next, when the input voltage of terminal DT21 changes from a low level to a high level, the clock signal DCLK changes from a high level to a low level. The voltage at node N61 drops further due to the bootstrap effect by the amount obtained by subtracting the low level voltage from the high level voltage. The low-level clock signal DCLK is supplied to terminal DT22 without any voltage increase. The retaining capacitor C41 conducts with the test data output DTD. At this time, the test data output DTD corresponding to the voltage level of the retaining capacitor C41 is supplied to the judgment circuit 13.

[0134] Terminal DT22 is connected to terminal DS21 in the subsequent register circuit RG22. The first-stage register circuit RG22 receives the output start signal DST at terminal DS21. After the output start signal DST changes from a high level to a low level, and then changes from a low level to a high level, the first-stage register circuit RG22 supplies the test data output DTD. The output start signal DST is also transmitted from the first-stage register circuit RG22 to the second-stage register circuit RG22. Thereafter, the second-stage register circuit RG22 similarly supplies the test data output DTD. In this way, the multiple register circuits RG22 included in the shift register RG22 can sequentially supply the test data output DTD to the judgment circuit 13 in accordance with the output start signal DST transmitted from the preceding stage to the succeeding stage.

[0135] Figure 28 is a timing chart for the test data processing circuit 34, which includes the register circuit RG13, or the test data processing circuit 35, which includes the register circuit RG23. The register circuit RG12 in Figure 14 constitutes the NMOS type shift register SR12 shown in Figure 11(B). The register circuit RG22 in Figure 18 constitutes the NMOS type shift register SR22 shown in Figure 15(B).

[0136] In Figure 14, the register circuit RG12 acquires a signal GON indicating the voltage level of the gate line GLn, and holds that voltage level using the retaining capacitor C31. When the input voltage of terminal GS31 is at a high level, the voltage at node N31 is set to the high-level voltage VGH minus the threshold voltage of the NMOS transistor. As a result, the voltage at terminal GT32 is set to be equal to the low-level clock signal GCLK. When the voltage at node N32 is at a low level, the NMOS transistor TR32 is off, so the supply of the low-level voltage VGH to node N31 is cut off. When the output voltage of terminal GT31 is at a low level, the retaining capacitor C31 is cut off from the data signal output GTD. At this time, the data signal output GTD corresponding to the retaining capacitor C31 is not supplied to the decision circuit 13.

[0137] Next, when the input voltage of terminal GS31 changes from a low level to a high level, the clock signal GCLK also changes from a low level to a high level. Due to the bootstrap effect, the voltage at node N31 rises further by the amount obtained by subtracting the low level voltage VGL from the high level voltage VGH. The high-level clock signal GCLK is supplied to terminal GT32 without any voltage drop. The retaining capacitor C31 conducts with the data signal output GTD. At this time, the data signal output GTD corresponding to the voltage level of the retaining capacitor C31 is supplied to the determination circuit 13.

[0138] Terminal GT32 is connected to terminal GS31 in the subsequent register circuit RG12. The first-stage register circuit RG12 receives the output start signal GST at terminal GS31. After the output start signal GST changes from a low level to a high level, and then changes from a high level to a low level, the first-stage register circuit RG12 supplies the data signal output GTD. The output start signal GST is also transmitted from the first-stage register circuit RG12 to the second-stage register circuit RG12. Thereafter, the second-stage register circuit RG12 similarly supplies the data signal output GTD. In this way, the multiple register circuits RG12 included in the shift register SR12 can sequentially supply the data signal output GTD to the determination circuit 13 in correspondence with the output start signal GST transmitted from the preceding stage to the succeeding stage.

[0139] In Figure 18, the register circuit RG22 holds the voltage level of the data line DLn using the retaining capacitor C51 when it acquires the signal DOn, which indicates the voltage level of the data line DLn. When the input voltage of terminal DS31 is low, the voltage of node N71 is set to the voltage obtained by subtracting the threshold voltage of the NMOS transistor from the high-level voltage VGH. As a result, the voltage of terminal DT32 is set to be equal to the low-level clock signal DCLK. When the voltage of node N72 is low, the NMOS transistor TR52 is off, so the supply of the low-level voltage VGH to node N71 is cut off. When the output voltage of terminal DT31 is low, the retaining capacitor C51 is cut off from the data signal output DTD. At this time, the data signal output DTD corresponding to the retaining capacitor C51 is not supplied to the determination circuit 13.

[0140] Next, when the input voltage of terminal DS31 changes from a low level to a high level, the clock signal DCLK also changes from a low level to a high level. The voltage at node N71 rises further due to the bootstrap effect by the amount obtained by subtracting the low level voltage VGL from the high level voltage VGH. The high-level clock signal DCLK is supplied to terminal DT32 without any voltage drop. The retaining capacitor C51 conducts with the data signal output DTD. At this time, the data signal output DTD corresponding to the voltage level of the retaining capacitor C51 is supplied to the determination circuit 13.

[0141] Terminal DT32 is connected to terminal DS31 in the subsequent register circuit RG22. The first-stage register circuit RG22 receives the output start signal DST at terminal DS31. After the output start signal DST changes from a low level to a high level, and then changes from a high level to a low level, the first-stage register circuit RG22 supplies the data signal output DTD. The output start signal DST is also transmitted from the first-stage register circuit RG22 to the second-stage register circuit RG22. Thereafter, the second-stage register circuit RG22 similarly supplies the data signal output DTD. In this way, the multiple register circuits RG22 included in the shift register RG22 can sequentially supply the data signal output DTD to the determination circuit 13 in accordance with the output start signal DST transmitted from the preceding stage to the succeeding stage.

[0142] The judgment circuit 13 can detect wiring abnormalities using the GTD and DTD test data outputs as digital data. Since an analog comparator is not required, the size of the wiring and circuit can be reduced. The test data processing circuits 34 and 35 use shift registers as digital logic circuits, which, along with reducing the circuit size, enables stable testing.

[0143] Although embodiments of the present disclosure have been described above, the present disclosure is not limited to these embodiments. The inspection circuit according to the present invention is applicable to any display device having a plurality of wires and electrodes.

[0144] The test circuit of the display device 100 may be partially or entirely provided outside the substrate 11. The test circuit of the display device 101 may be partially or entirely provided outside the substrate 15. For example, some or all of the pre-charge circuits 31A, 31B, 32A, 32B and the test data processing circuits 34, 35 may be externally connected to the display device 100. Alternatively, some or all of the pre-charge circuits 31A, 31B, 32A, 32B and the test data processing circuits 34, 35 may be included in the driver IC 12.

[0145] A short circuit between the gate line GL and the data line DL can also be checked by supplying a high level of voltage to the data line DL and obtaining the voltage level of the floating gate line GL. A break between the gate line GL and the data line DL can also be checked by supplying a low level of voltage from both sides, and then supplying a high level of voltage from the input end side and obtaining the voltage levels of the gate line GL and the data line DL.

[0146] The inspection circuit for the display device in the present invention supplies a first voltage to one or both of the wiring and electrodes connected to the pixel during a first period. Furthermore, during a second period following the first period, a second voltage is supplied to one of the wiring and electrodes. The occurrence of an anomaly can be detected in accordance with the voltage level of the wiring based on the supply of this second voltage. This enables stable and diverse inspections while preventing increases in circuit size and inspection costs.

[0147] The first voltage in the first period includes an initial voltage for initializing or setting the voltage levels of multiple wirings to be inspected. The second voltage in the second period is a test voltage that causes the voltage levels of multiple wirings to be inspected to differ depending on whether or not there is an abnormality. These initial and test voltages are supplied to multiple wirings or electrodes to be supplied in a single batch during the same period. The voltage levels of the multiple wirings to be inspected are acquired in a single batch during the same period. The test data corresponding to the acquired voltage levels is output by converting the parallel data to serial data. This makes it easy to adjust the inspection time and enables stable inspection with a simple configuration. [Explanation of Symbols]

[0148] 11, 15 circuit boards 12 Driver ICs 13 Judgment circuit 21-pixel array 22, 22A, 22B scanning circuits 23 Demultiplexer 31A, 31B, 32A, 32B Precharge Circuit 33. Test circuit for common electrodes 34, 35, 35A, 35B Inspection data processing circuit 100, 101 Display device

Claims

1. A pixel portion; Wiring and electrodes connected to the pixel unit; An inspection circuit capable of inspecting the wiring for abnormalities, The inspection circuit includes: supplying a first voltage to one or both of the wiring and the electrode during a first period; supplying a second voltage to one of the wiring and the electrode in a second period following the first period; The occurrence of an abnormality can be detected in response to a voltage level of the wiring based on the supply of the second voltage. Display device.

2. the wiring includes a plurality of gate lines and a plurality of data lines; The electrode is a common electrode, The inspection circuit includes: a plurality of first voltage supply circuits disposed on both sides of the plurality of gate lines; a plurality of second voltage supply circuits disposed on both sides of the plurality of data lines; a first test data processing circuit disposed on one side of the plurality of gate lines; a second test data processing circuit disposed on one side of the plurality of data lines; The first test data processing circuit and the second test data processing circuit are configured using a shift register as a digital logic circuit. The display device according to claim 1 .

3. the wiring includes a plurality of gate lines and a plurality of data lines; The electrode is a common electrode, a plurality of scanning circuits disposed on both sides of the plurality of gate lines; The inspection circuit includes: a plurality of first voltage supply circuits disposed on both sides of the plurality of gate lines; a plurality of second voltage supply circuits disposed on both sides of the plurality of data lines; a plurality of first test data processing circuits arranged on both sides of the plurality of gate lines; a second test data processing circuit disposed on one side of the plurality of data lines; the plurality of first test data processing circuits and the second test data processing circuit are configured using shift registers as digital logic circuits; The display device according to claim 1 .

4. the wiring includes a plurality of gate lines and a plurality of data lines; The inspection circuit includes: a plurality of first voltage supply circuits disposed on both sides of the plurality of gate lines; a plurality of second voltage supply circuits disposed on both sides of the plurality of data lines; a test data processing circuit disposed on one side of the plurality of data lines; the first voltage supply circuits supply a low-level voltage included in the first voltage to the gate lines; the second voltage supply circuits supply a low-level voltage included in the first voltage to the data lines; the first voltage supply circuits supply a high-level voltage as the second voltage to the gate lines; the test data processing circuit acquires a voltage level on the plurality of data lines based on the supply of the second voltage, and makes it possible to detect the occurrence of an abnormality when the voltage level is a high level; The display device according to claim 1 .

5. the wiring includes a plurality of gate lines; The inspection circuit includes: a plurality of voltage supply circuits arranged on both sides of the plurality of gate lines; a test data processing circuit disposed on one side of the plurality of gate lines; the plurality of voltage supply circuits supply a high-level voltage as the first voltage to the plurality of gate lines; Among the plurality of voltage supply circuits, a voltage supply circuit arranged on an input end side opposite to the test data processing circuit supplies a low-level voltage as the second voltage to the plurality of gate lines; the test data processing circuit acquires a voltage level on the plurality of gate lines based on the supply of the second voltage, and makes it possible to detect the occurrence of an abnormality when the voltage level is a high level; The display device according to claim 1 .

6. The wiring includes a plurality of data lines, The inspection circuit includes: a plurality of voltage supply circuits disposed on both sides of the plurality of data lines; a test data processing circuit disposed on one side of the plurality of data lines; the plurality of voltage supply circuits supply a high-level voltage as the first voltage to the plurality of data lines; Among the plurality of voltage supply circuits, a voltage supply circuit arranged on an input end side opposite to the test data processing circuit supplies a low-level voltage as the second voltage to the plurality of data lines; the test data processing circuit acquires a voltage level on the plurality of data lines based on the supply of the second voltage, and makes it possible to detect the occurrence of an abnormality when the voltage level is a high level; The display device according to claim 1 .

7. The wiring includes a plurality of data lines, The electrode is a common electrode, The inspection circuit includes: a plurality of first voltage supply circuits disposed on both sides of the plurality of data lines; a plurality of second voltage supply circuits connected to the common electrode; a test data processing circuit disposed on one side of the plurality of data lines; the first voltage supply circuits supply a low-level voltage included in the first voltage to the data lines; the second voltage supply circuits supply a low-level voltage included in the first voltage to the common electrode; the second voltage supply circuits supply a high-level voltage as the second voltage to the common electrode; the test data processing circuit acquires a voltage level on the plurality of data lines based on the supply of the second voltage, and makes it possible to detect the occurrence of an abnormality when the voltage level is a high level; The display device according to claim 1 .

8. the wiring includes a plurality of gate lines; The electrode is a common electrode, The inspection circuit includes: a plurality of first voltage supply circuits disposed on both sides of the plurality of gate lines; a plurality of second voltage supply circuits connected to the common electrode; a test data processing circuit disposed on one side of the plurality of gate lines; the first voltage supply circuits supply a low-level voltage included in the first voltage to the gate lines; the second voltage supply circuits supply a low-level voltage included in the first voltage to the common electrode; the second voltage supply circuits supply a high-level voltage as the second voltage to the common electrode; the test data processing circuit acquires a voltage level on the plurality of gate lines based on the supply of the second voltage, and makes it possible to detect the occurrence of an abnormality when the voltage level is a high level; The display device according to claim 1 .

9. the wiring includes a plurality of gate lines and a plurality of data lines; The electrode is a common electrode, The inspection circuit includes: a first test data processing circuit for acquiring voltage levels on the gate lines; a second test data processing circuit for acquiring voltage levels on the plurality of data lines; The inspection circuit includes: acquiring voltage levels at one or both of the gate lines and the data lines by one or both of the first test data processing circuit and the second test data processing circuit during a first blanking period between a plurality of display periods; outputting test data corresponding to a voltage level acquired by one or both of the first test data processing circuit and the second test data processing circuit in a second blanking period following the first blanking period during the plurality of display periods; The display device according to claim 1 .

10. the wiring includes a plurality of gate lines and a plurality of data lines; The electrode is a common electrode, The inspection circuit includes: a first test data processing circuit for acquiring voltage levels on the gate lines; a second test data processing circuit for acquiring voltage levels on the plurality of data lines; The inspection circuit includes: acquiring a voltage level at one or both of the gate lines and the data lines by one or both of the first test data processing circuit and the second test data processing circuit during a blanking period between a plurality of display periods; outputting test data corresponding to a voltage level acquired by one or both of the first test data processing circuit and the second test data processing circuit during a display period subsequent to the blanking period among the plurality of display periods; The display device according to claim 1 .

11. The inspection circuit is mounted on the same substrate as the pixel unit. The display device according to claim 1 .

12. the inspection circuit includes a switch circuit of a type selected from a CMOS transmission gate, a PMOS transistor, or an NMOS transistor corresponding to the thin film transistor formed on the same substrate; The display device according to claim 11.

13. 1. A method for testing a display device, comprising: supplying a first voltage to one or both of the wiring and the electrode by an inspection circuit corresponding to the wiring and the electrode connected to a pixel unit of the display device during a first period; supplying a second voltage to one of the wiring and the electrode by the inspection circuit in a second period following the first period; the inspection circuit detects the occurrence of an abnormality according to a voltage level of the wiring based on the supply of the second voltage. A method for inspecting a display device.

14. a plurality of first voltage supply circuits arranged on both sides of a plurality of gate lines included in the wiring supply a low-level voltage included in the first voltage to the plurality of gate lines; A low-level voltage included in the first voltage is supplied to the data lines by a plurality of second voltage supply circuits arranged on both sides of the data lines included in the wiring; supplying a high-level voltage as the second voltage to the gate lines by the first voltage supply circuits; a test data processing circuit disposed on one side of the plurality of data lines acquires a voltage level on the plurality of data lines based on the supply of the second voltage, and when the voltage level is a high level, makes it possible to detect the occurrence of an abnormality; The display device inspection method according to claim 13.

15. supplying a high-level voltage as the first voltage to the gate lines by a plurality of voltage supply circuits arranged on both sides of the gate lines included in the wiring; a voltage supply circuit arranged on an input end side of the plurality of gate lines, which is opposite to a test data processing circuit arranged on one side of the plurality of gate lines, supplies a low-level voltage as the second voltage to the plurality of gate lines; the inspection data processing circuit acquires a voltage level on the plurality of gate lines based on the supply of the second voltage, and when the voltage level is a high level, makes it possible to detect the occurrence of an abnormality. The display device inspection method according to claim 13.

16. A plurality of voltage supply circuits arranged on both sides of a plurality of data lines included in the wiring supply a high-level voltage as the first voltage to the plurality of data lines; a voltage supply circuit arranged on an input end side of the plurality of voltage supply circuits, which is opposite to a test data processing circuit arranged on one side of the plurality of data lines, supplies a low-level voltage as the second voltage to the plurality of data lines; the inspection data processing circuit acquires a voltage level on the plurality of data lines based on the supply of the second voltage, and when the voltage level is a high level, makes it possible to detect the occurrence of an abnormality; The display device inspection method according to claim 13.

17. A low-level voltage included in the first voltage is supplied to the data lines by a plurality of first voltage supply circuits arranged on both sides of the data lines included in the wiring; A low-level voltage included in the first voltage is supplied to the common electrode by a plurality of second voltage supply circuits connected to the common electrode as the electrode; supplying a high-level voltage as the second voltage to the common electrode by the plurality of second voltage supply circuits; a test data processing circuit disposed on one side of the plurality of data lines acquires a voltage level on the plurality of data lines based on the supply of the second voltage, and when the voltage level is a high level, makes it possible to detect the occurrence of an abnormality; The display device inspection method according to claim 13.

18. A low-level voltage included in the first voltage is supplied to the plurality of gate lines by a plurality of first voltage supply circuits arranged on both sides of the plurality of gate lines included in the wiring; A low-level voltage included in the first voltage is supplied to the common electrode by a plurality of second voltage supply circuits connected to the common electrode as the electrode; supplying a high-level voltage as the second voltage to the common electrode by the plurality of second voltage supply circuits; a test data processing circuit disposed on one side of the gate lines acquires a voltage level on the gate lines based on the supply of the second voltage, and makes it possible to detect the occurrence of an abnormality when the voltage level is high; The display device inspection method according to claim 13.

19. During a first blanking period between a plurality of display periods, a voltage level at one or both of a plurality of gate lines and a plurality of data lines included in the wiring is obtained as a voltage level at the wiring; outputting test data corresponding to a voltage level on the wiring during a second blanking period following the first blanking period during the plurality of display periods; The display device inspection method according to claim 13.

20. In a blanking period between a plurality of display periods, a voltage level of one or both of a plurality of gate lines and a plurality of data lines included in the wiring is obtained as a voltage level of the wiring; outputting test data corresponding to a voltage level on the wiring during a display period subsequent to the blanking period among the plurality of display periods; The display device inspection method according to claim 13.

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