Electronic device with reduced switching oscillations

Abstract

To provide an electronic device that is free from the drawbacks of the prior art.SOLUTION: An electronic device comprises: a semiconductor body (8, 10) which has a first electrical conductivity (N), and provided with a front surface side (1a); an active region (4) of the semiconductor body, which accommodates a source region (12) and a gate region (14) of the electronic device and which is configured to accommodate, in use, a conductive channel of the electronic device; and an edge region (6) of the electronic device. The edge region (6) surrounds the active region (4), and accommodates at least partially i) an edge terminal region (20) including a second electrical conductivity (P) opposite to the first electrical conductivity (N), extending into the semiconductor body at the front surface side (1a); and ii) a gate connection terminal (24) of conductive material electrically coupled the gate region (14) extending onto the front surface side (1a) partially interposed on the edge termination region (20) and capacitively coupled with a portion of the semiconductor body adjacent and external to the edge termination region (20).SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to an electronic device, and more particularly to a SiCMOSFET with reduced switching oscillations. [Background technology]

[0002] As is well known, it has a wide bandgap, especially an energy value Eg with a bandgap even higher than 1.1 eV, and a low on-state resistance (R on Semiconductor materials having high thermal conductivity, high operating frequency, and high saturation values ​​for the rate of conduction charge are ideal for providing electronic components such as diodes or transistors, especially for power applications. A material that possesses these properties and is used to manufacture electronic components is silicon carbide (SiC). In particular, silicon carbide, in its different polytypes (e.g., 3C-SiC, 4H-SiC, 6H-SiC), is more preferable than silicon in terms of the aforementioned properties.

[0003] Electronic devices mounted on silicon carbide substrates have several advantageous characteristics compared to similar devices mounted on silicon substrates, such as low output resistance in conduction, low leakage current, high operating temperature, and high operating frequency.

[0004] WBG semiconductor devices can operate at high voltages, high temperatures, and high switching frequencies. Among the most popular WBG power devices, SiCMOSFETs have been extensively studied for high-speed switching power converters. However, the high-speed switching characteristics of SiCMOSFETs can lead to undesirable voltage and current oscillations during the turn-on and turn-off switching periods. The resulting voltage overload can cause device damage, increase power loss, and generate considerable noise due to electromagnetic interference. This limits the use of SiCMOSFETs in power electronics applications.

[0005] Switching oscillations, i.e., "ringing" phenomena, have been observed in many studies on SiCMOSFET devices. This switching oscillation phenomenon is closely related to the high-speed switching characteristics of power transistors.

[0006] Furthermore, the current trend of forming body wells close to each other under the gate terminal, which is generated by the corresponding decrease in the range of the gate terminal, is to reduce the capacitive coupling (gate-drain capacitance C in the case of a vertical conduction MOSFET device) between the gate and the lower drain. gd That is, the feedback capacitance) will be reduced. The gate-drain capacitance C gd The reduction may be directly correlated with an increase in the amplitude of the oscillation of the drain voltage during the turn-off step of the MOSFET (the recovery step or recovery of the body diode of the MOSFET). In fact, as is known, the intrinsic body diode of a MOSFET has the same physical limitations as a discrete diode, including undesired behavior during the reverse recovery step. Reverse recovery occurs when the body diode turns off while still carrying a positive forward current.

[0007] Known methods for reducing switching oscillations include, for example, optimization of the PCB layout and increase of the MOSFET gate resistance. As a further approach, there is one that controls the gate charge of a power MOSFET to suppress turn-off oscillations. However, such an approach will increase the complexity of manufacturing and the devices thus manufactured. Summary of the Invention Problems to be Solved by the Invention

[0008] An object of the present invention is to provide an electronic device that eliminates the drawbacks of the prior art. Means for Solving the Problems

[0009] According to the present invention, there is provided an electronic device as defined in claim 1 of the claims.

[0010] For a better understanding of the present invention, reference will now be made to the accompanying drawings, and preferred embodiments of the present invention will be described below by way of purely non-limiting examples.

Brief Description of the Drawings

[0011] [Figure 1] A plan view illustrating a semiconductor die accommodating an electronic device, particularly a MOSFET. [Figure 2] A cross-sectional view illustrating an electronic device, particularly a MOSFET, according to one embodiment of the present invention. [Figure 3] A cross-sectional view illustrating an electronic device, particularly a MOSFET, according to another embodiment of the present invention. [Figure 4] A cross-sectional view illustrating an electronic device, particularly a MOSFET, according to yet another embodiment of the present invention. [Figure 5] A cross-sectional view illustrating an electronic device, particularly a MOSFET, according to yet another embodiment of the present invention. [Figure 6] A cross-sectional view illustrating an electronic device, particularly a MOSFET, according to yet another embodiment of the present invention. [Figure 7] A plan view illustrating the semiconductor die of FIG. 1 when a gate conduction terminal is present in an end region based on a certain aspect of the present invention. [Figure 8] A cross-sectional view illustrating an electronic device, particularly a MOSFET, according to a further embodiment of the present invention.

Modes for Carrying Out the Invention

[0012] The present invention will be described with reference to the accompanying drawings showing a wafer or a part thereof in a three-axis system consisting of X, Y, and Z axes orthogonal to each other.

[0013] Referring to Figure 1, a die, or chip 1, is obtained after the dicing step of the semiconductor wafer. Die 1 is schematically illustrated in a plan view on the XY plane (this is the appearance of the front side of die 1). Die 1 has an outer end 2, which physically defines the boundary of die 1. Die 1 houses at least one electronic device (not shown in Figure 1), such as a MOSFET. Hereafter, both terms, “electronic device” and “MOSFET,” will be used without loss of generality.

[0014] The die 1 comprises at least two functional regions, namely, an active region 4 that typically extends within the central portion of the die 1, and an end region 6 or peripheral region that completely surrounds the active region 4. The end region extends between the active region 4 and the outer end 2.

[0015] The active region 4 is the portion of the die 1 that houses the elements of the electronic device involved in on-state conduction, or generally, the region of the die 1 where the conduction channel is formed (during use). The active region 4 houses, for example, the source region of a MOSFET. The drain region extends along the back side 1b of the die 1 (which is opposite to and parallel to the front side 1a and therefore not shown in Figure 1), for example, in the case of a vertical conduction device. The conduction channel extends between the front side 1a and the back side 1b, i.e., between the source and the drain, mainly in a vertical direction (along the Z) toward the back side 1b within a region of the active region 4.

[0016] On the other hand, the end region 6 is a region that does not have the conductive channel during use. The end region 6 may have functional elements to reduce or prevent crowding of the electric field outside the active region.

[0017] Figure 2 is a cross-sectional view (on the XZ plane) of a portion of die 1, taken, for example, along the scribe line II-II in Figure 1. Figure 2 shows a portion of the electronic device formed on die 1, specifically a vertically conducting MOSFET.

[0018] Referring to Figure 2, die 1 includes a semiconductor body made of silicon carbide (SiC) or silicon (Si) having a first conductivity type (e.g., N-type). The semiconductor body includes a substrate 8 (N+ doped) and a drift layer (N- doped) on the substrate 8. For example, a drain terminal 9 made of a metallic material extends onto the back side 1b of the semiconductor body.

[0019] A body region 11 having a second conductivity type (P) opposite to the first conductivity type, and a source region 12 within the body region 11 having the first conductivity type (and N+ doping) are present on the front side 1a of the drift layer 10. The body region 11 and the source region 12 are regions injected into the drift layer 10 in a manner known in itself.

[0020] The gate region 14 extends upward from the front side 1a and encompasses the gate dielectric 14a and the gate conductive region 14b. The gate dielectric is interposed between the gate conductive region 14b and the semiconductor body (particularly the drift layer 10).

[0021] Figure 2 shows a single body region 11 containing each source region 12, over which each gate region 14 extends, for the sake of simplicity in representation. In particular, these exemplified body regions 11, source regions 12, and gate regions 14 extend near the end of the active region 4, after which the end region 6 begins, as described above.

[0022] The electronic device further has a source (e.g., metal) terminal 16 which extends in contact with the front side 1a in the source region 12 and is separated from the gate region 14 by an insulating layer 18.

[0023] The die 1 further contains an end-termination region 20 within the semiconductor body (particularly within the drift layer 10), which is injected into and faces the front side 1a. The end-termination region 20 has a second conductivity type and has greater doping (P+) than that of the body region 11. The end-termination region 20 extends from the active region 4, making electrical contact with the source region 12 and the body region 11, and proceeds into the end region 6 along the X axis. The end-termination region 20 has the function of preventing or prohibiting the generation of an electric field having a value that would damage the dielectric layer 22a within the dielectric layer 22a located below region 22b.

[0024] The dielectric layer 22a (similar to the gate dielectric 14a) and the conductive layer 22b on the dielectric layer 22a (similar to the gate conductive region 14b) extend above the end termination region 20 (above the front side 1a). However, layers 22a and 22b do not function as gate terminals during use (i.e., they do not contribute to the formation of conductive channels).

[0025] The electronic device further has a gate connection terminal 24 made of a conductive material such as metal or N-type doped polysilicon, which includes a first portion 24a extending in electrical contact with the conductive layer 22b and a second portion 24b extending above the conductive layer 22b at a certain distance in the end region 6. These first and second portions 24a and 24b are structurally a single monolithic component and are electrically continuous with each other. The second portion 24b forms an end shield plate and the gate shield of the electronic device.

[0026] Furthermore, the gate connection terminal 24 makes electrical contact with the gate region 14 (in a manner not shown in the figure). The gate connection terminal 24 also has a region for electrical contact (e.g., by wire bonding or other techniques) to provide gate bias to the electronic device during its service life.

[0027] The dotted line in Figure 2, which distinguishes the active region 4 from the end region 6, should be understood as qualitative. For the purposes of explaining the present invention, the second portion 24b of the gate connector terminal 24 is entirely housed within the end region 6 and is therefore located within the right-hand portion with respect to the dotted boundary line between the active region 4 and the end region 6.

[0028] A passivation layer 28 extends over the gate terminal 24 and the source terminal 16, protecting and insulating them. An opening 28' is provided within the passivation layer 28, allowing for electrical contact with the gate terminal 24 and the source terminal 16 (for example, by wire bonding to provide bias during use).

[0029] The second portion 24b of the gate terminal 24 extends at a certain distance from the front side 1a and is separated from the front side 1a of the semiconductor body (particularly from the drift layer 10) by a dielectric or insulating layer 30. The dielectric layer 30 extends between the conductive layer 22b and the gate terminal 24, and physical contact between the first portion 24a of the gate terminal 24 and the conductive layer 22b is generated by conductive through-vias that extend through the entire thickness (along Z) of the dielectric layer 30.

[0030] The maximum range (thickness) along the Z-axis of the laminate formed by the dielectric layer 30 and the dielectric layer 22a below it is hereafter referred to as Th diel It is expressed as such, and has a value between, for example, 0.8 and 2.4 μm. That is, Th diel This represents the overall thickness of the dielectric layer 22a + dielectric layer 30 between the second portion 24b of the gate connection terminal 24 and the front side 1a.

[0031] According to one embodiment of the present invention, the dielectric layer 22a and the dielectric layer 30 are made of the same material.

[0032] According to a further embodiment of the present invention, the dielectric layer 22a extends exclusively beneath the conductive layer 22b and is not present beneath the dielectric layer 30. In this case, the dielectric layer 30 extends between the front side 1a and the second portion 24b of the gate connection terminal 24, and therefore Th diel This represents the maximum thickness of the dielectric layer 30 between the second portion 24b of the gate connection terminal 24 and the front side 1a.

[0033] According to one aspect of the present invention, the extent of the gate connection terminal 24 (particularly of the second portion 24b) along the X-axis is greater than the extent of the end termination region 20 along the X-axis. That is, in the cross-sectional view of Figure 2 or the plan view of Figure 7, the gate connection terminal 24 is partially superimposed on the end termination region 20 and partially extends beyond the end termination region 20, in such a manner that it faces the semiconductor body (particularly the drift layer 10) via the dielectric layer 30 and, if present, the insulating layer 22a, corresponding to the N-type doped portion of the front side 1a of the semiconductor body, i.e., the area where the end termination region 20 does not extend (is not present).

[0034] The area along X (and similarly along Y, as seen in Figure 7) of the gate connection terminal 24 facing each N-type doped portion on the front side 1a is hereafter L shield To express it as follows.

[0035] It should be noted that the N-type doped portion on the front side 1a facing the gate connection terminal 24 is electrically connected to the drain region 9 of this electronic device. Therefore, a capacitive coupling (schematically shown by the symbol of the capacitor 32 in FIG. 2) is provided between the gate connection terminal 24 (the first plate of the capacitor 32) and the drain region 9 (the second plate of the capacitor 32). In that case, the dielectric layer 30, and if present, the insulating layer 22a form the dielectric intervening between the two plates of the capacitor 32. The gate connection terminal 24 (the first plate of the capacitor 32) is electrically connected to the gate terminal 14 of this MOSFET, and since the second plate of the capacitor 32 coincides with the drain region 9 of this MOSFET from an electrical perspective, a capacitive coupling occurs between the gate terminal 14 and the drain terminal 9 of this MOSFET.

[0036] Thus, the total gate-drain capacitance C of this electronic device (MOSFET) gd , is given by the sum of two capacitive contributions. The first contribution C gd is given by the capacitance between the gate and the drain existing within the active region 4 in the overlapping region between the gate terminal 14 and the N-doped drift layer 10, and the second contribution C gd is given by the capacitance value symbolically indicated by the capacitor 32.

[0037] The capacitance C gd is a non-linear function of voltage and it is an important parameter because it provides a feedback loop between the output and the input of the circuit. The capacitance C gd is also known as the Miller capacitance, and it constitutes a total dynamic input capacitance that is even larger than the sum of the static capacitances. The turn-off delay of the MOSFET device is due to the time required to discharge the input capacitance after removing the bias. Since the input capacitance is a function of the capacitance C gd , an increase in the capacitance C gd (the contribution C gd added based on the present invention)This allows for corresponding adjustment of the turn-off delay and balances the undesirable behavior of the MOSFET body diode during the reverse recovery step, thereby damping recovery current oscillations. Capacitor C set or designed in this manner. gd This alters the response of the electronic device to switching oscillations during the turn-off step period. In particular, an increase in the feedback capacitance corresponds to damping of switching oscillations during the turn-off step period.

[0038] By appropriately defining the range (area) of capacitive coupling between the gate connection terminal 24 and the drift layer 10 during the design step period, a predetermined and / or desired value of capacitance C can be achieved. gd It is possible to generate this effect. The above-described effect is observed for any value of capacitance 32 introduced based on the present invention, but as verified by the inventors, for drain-source voltage (Vds) values ​​of 100V or more, capacitance C in the range of tens of picofarads, for example 65-130pF is possible. gd The value of is a reasonable solution. As mentioned above, capacity C gd Capacity C still exists within the active region 4. gd It is added to and typically has a value of less than 25pF for drain-source voltages (Vds) of 100V or more.

[0039] Therefore, the following relation (1) applies.

number

number

[0040] L shield In contrast, the relationships (1) and (2) mentioned above are based on the following assumptions.

[0041] i) Die 1 is side W die For example, W die It has a substantially square shape (probably with rounded corners) with a thickness of approximately 2000-8000 μm, for example, equal to 4000 μm. ii) The active region 4 is, for example, 3 / 4W die Equal side W AA It has a substantially square shape (probably with rounded corners), and iii) In the active region, volume C gd The value is 1.5pF / mm for Vds≧100V. 2 Being lower.

[0042] As an alternative to the above, relations (1) and (2) can be replaced with the equivalent relations (3) and (4) shown below, in which case the parameter L shield , capacity C gd Area S of the gate connection terminal 24 that contributes to this shield It is replaced by the value of (in the XY plane).

number

number

[0043] According to one aspect of the present invention, the capacity contribution C gd is, total capacity C gd That is, C gd +C gd The MOSFET is selected in such a manner that it triggers a known parasitic turn-on (PTO) phenomenon during the turn-off period of the MOSFET device. When the PTO phenomenon occurs, the MOSFET involuntarily turns on, generating a transient (parasitic) current flow within its active region. The presence of this parasitic current mitigates undesirable oscillation effects during the turn-off step period, and more specifically, it reduces the overall amplitude of the drain-source voltage oscillation by a few percentage points (for example, for a current pulse of 2 A / ns, a decrease in drain-bus supply voltage of less than 15% is observed).

[0044] According to one embodiment, the insulating layer 22a can be omitted in the capacitive coupling region, and in that case, the dielectric interposed between the two capacitive plates is formed exclusively by the dielectric layer 30. Therefore, the dielectric material of layer 30 can be appropriately selected as needed, independently of the material selected for the insulating layer 22a.

[0045] The dielectric layer 30 (and similarly the insulating layer 22a) is made of silicon oxide (SiO2), silicon nitride (SiN, Si 34 , silicon oxynitride (SiO xy It is possible to use one of the following: , or a high-dielectric constant (High-κ) material where κ > 7. Usable high-dielectric constant materials include, for example, aluminum nitride (AlN), aluminum oxynitride (ALON,Al 23 , tantalum oxide (TaO,Ta 25 Examples include hafnium oxide (HfO2), zirconium oxide (ZrO2), etc.

[0046] Figure 3 shows a further embodiment of the present invention. Elements in Figure 3 that are common to those in Figure 2 are given the same reference numerals, and further explanation is omitted.

[0047] The die 1' in Figure 3, in addition to those already described with reference to Figure 2, has a second conductivity type (P-type) and an additional injection region 40 having a lower doping than the doping of the end termination region 20. The injection region 40 extends from the body region 11 at a certain distance to the end portion of the end termination region 20. Thus, the injection region 40 extends as an extension of the end termination region 20. The injection region 40 has the function of distributing and thinning the potential field line in a manner that avoids thickening of the field line on the radius of curvature of the end termination region 20, and therefore maximizes the end breakdown voltage value.

[0048] In this embodiment, the extension or range of the gate terminal 24 (particularly of the second portion 24b) along the X-axis is greater than the maximum height reached along the X-axis by the injection region 40 (which extends as an extension of the end-terminal region 20, as described above). That is, in the cross-sectional view of Figure 3 (or the corresponding plan view in Figure 1), the gate terminal 24 is completely superimposed on the end-terminal region 20 and also extends beyond the injection region 40. In this way, the gate terminal 24 faces the semiconductor body (particularly the drift layer 10) via the dielectric layer 30 (and, if present, the insulating layer 22a), with the injection region 40 not interposed between them. Thus, capacitive coupling (indicated by the symbol capacitor 32) similar to that described with reference to Figure 2 is provided between the gate terminal 24 and the N-type semiconductor body.

[0049] Figure 4 shows a further embodiment of the present invention. Elements in Figure 4 that are common with those in Figures 2 and 3 are given the same reference numerals and further explanation is omitted.

[0050] The die 1'' in Figure 4, in addition to those already described with reference to Figures 2 and 3, has a current spread layer (CSL) 50 which extends into the semiconductor body (particularly into the drift layer 10) facing the front side 1a. The current spread layer 50 is provided by the injection of one or more doping species having a first conductivity type and forms an enrichment layer extending to a certain depth from the front side 1a. Alternatively, the current spread layer 50 is obtained by epitaxial growth. The current spread layer 50 can also be formed by a combination of an epitaxial growth step and subsequent injection (e.g., only within the active region 4).

[0051] In one embodiment, the depth to which the current spread layer 50 extends is greater than the maximum depth reached by the body region 11, the injection region 40, and the end-terminal region 20. That is, in this embodiment, the body region 11, the injection region 40, and the end-terminal region 20 are all completely confined within the current spread layer 50.

[0052] In further embodiments, the current spread layer 50 extends to a depth even lower than the maximum depth reached by the body region 11, the injection region 40, and the end termination region 20 (at least, or exclusively, in the end region 6).

[0053] Regardless of this embodiment, the doping of the current spread layer 50 is greater than the doping of the drift layer 10 that contains it. The current spread layer 50 is, for example, 10 17 Number of children / cm 3 It has a degree of doping.

[0054] The current spread layer 50 extends over the entire or a portion of the surface 1a. Regardless of the layout selected for the current spread layer 50, in the context of the present invention, it extends at least partially superimposed (in the plan view) on the gate terminal 24. In this way, the gate terminal 24 partially faces the current spread layer 50 via the dielectric layer 30 (and, if present, the insulating layer 22a), in which case no injection region 40 or end-termination region 20 is interposed between them. Thus, capacitive coupling similar to that described with reference to Figure 2 or Figure 3 is provided between the gate terminal 24 and the current spread layer 50 in the semiconductor body.

[0055] The use of the current spread layer 50 is known in itself and is widely used in MOSFETs for high-frequency applications, and its advantages and functions are known, so a detailed explanation will be omitted. In the context of the present invention, the presence of the current spread layer 50 has the further advantage in use of improving the capacitive coupling between the gate terminal 24 and the semiconductor body (particularly between the gate terminal 24 and the drain terminal).

[0056] Figure 5 shows an overview of die 1'' (and similarly, dies 1'' and 1'' with respect to die 1'' where further elements are present or lost. In particular, the overview in Figure 5 shows the presence of further injection regions 60 within the semiconductor body (especially within the drift layer 10) facing the front side 1a. The injection regions 60 are second conductivity types (e.g., 5 × 10¹⁶). 16 to 2×10 17 Number of units / cm 3The injection region 60 has a degree of P-type and is formed, for example, in the same steps as forming the injection region 40. The injection region 60 extends a certain distance from the injection region 40 and, in a plan view (XY plane), is at least partially aligned with the final portion 24b' of the gate terminal 24 and, in particular, with the final portion 24b' of the second portion 24b of the gate terminal 24 (along the Z-axis direction). The presence of the injection region 60 does not affect the feedback capacitance represented by the capacitor 32, as previously described, because this capacitive coupling is provided in both cases between the gate terminal 24 and the semiconductor body in the region between the injection region 40 and the injection region 60. The injection region 60 has the function of dispersing and thinning the potential field line in such a manner that it avoids the electric field on the bottom corner of the final portion 24b' of the second portion 24b, and thus avoids the risk of the electric field in the final portion 24b' becoming critical.

[0057] In the embodiment shown in Figure 5, length L shield This is the distance between injection area 40 and injection area 60 (along the X and Y axes).

[0058] Figure 6 shows a further embodiment of the present invention, in which one or more P-type floating regions 61, provided by injecting doping species on the front side 1a, are located between the injection regions 40 and 60. The floating regions 61 extend from each other at a certain distance (i.e., the N-type portions of the semiconductor body, particularly those of the drift layer 10, are located between the floating regions 61 and the next along the X-axis direction). A similar layout can also be provided along the Y-direction.

[0059] In the embodiment shown in Figure 6, length L shield , is the sum of the distances between floating region 61 and the next floating region 61 (along X and, similarly, along Y) (and the distance between injection region 40 and the immediately following floating region 61, and between injection region 60 and the immediately preceding floating region 61).

[0060] The embodiment in Figure 6 relating to the presence of the floating region 61 can, in its own obvious manner, be applied to the embodiments in Figures 2 to 4.

[0061] Figure 7 shows the die 1 of Figure 1 in a plan view (on the XY plane), and schematically shows the extent of the gate connection terminal 24. As can be seen, in this example, the gate connection terminal 24 has a ring shape and completely surrounds the active area 4. However, depending on the specific layout and design requirements, it is also possible to have an embodiment in which the gate connection terminal 24 only partially surrounds the active area 4.

[0062] The advantages of the solutions proposed in this book are clear from the explanation above.

[0063] In particular, according to the technical solution of the present invention, capacity C gd This is the integrated and distributed capacity within the device.

[0064] Capacitance C between the gate terminal and the drain terminal gd The feedback capacitance is increased by a coefficient defined by the capacitive coupling between the gate terminal 24 and the N-type doped region of the semiconductor body located below it. In this way, the increase in feedback capacitance allows for attenuation of the amplitude of drain voltage oscillations during the MOSFET turn-off step (recovery step, or recovery of the MOSFET body diode).

[0065] Although specific embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments, and it is of course possible to make various modifications and alterations without departing from the technical scope of the present invention.

[0066] For example, in a further embodiment of the present invention shown in Figure 8, a P-type capacitive decoupling layer 70 is provided on the front side 1a, extending seamlessly below the gate connection terminal 24, that is, interposed between the gate connection terminal 24 and the N-type doped region of the semiconductor body located below it. This capacitive decoupling layer 70 has a thickness of, for example, between 0.2 and 0.4 μm, and, exemplary, 10 16 Number of units / cm 3 It has a degree of doping. Generally, the capacitive decoupling layer 70 is designed such that when the device is ON (for example, when the drain-source voltage Vds is higher than 5V or 10V), holes are depleted in the capacitive decoupling layer 70, and the capacitive decoupling layer 70 enables capacitive coupling between the gate connection terminal 24 and the N-type doped region of the semiconductor body located below it, thereby forming the capacitor 32 as described above.

[0067] The embodiment in Figure 8 is based on Figure 5, but this embodiment (the presence of layer 70) also applies to the embodiment in Figure 2-4.

[0068] For example, although the present invention has been described with explicit reference to an N-channel device, the technical solutions proposed in this document are equally applicable to P-channel devices.

Claims

1. In electronic devices, A semiconductor body (8, 10) is provided with a front side (1a) and has a first conductivity type (N), The active region (4) of the semiconductor body, which houses the source region (12) and gate region (14) of the electronic device and is configured to house the conductive channel of the electronic device during use, The end region (6) of the electronic device surrounding the active region (4), It has, and the end region (6) is at least partially, An end-terminal region (20) having a second conductivity type (P) opposite to the first conductivity type (N) and extending into the semiconductor body on the front side (1a), and It is electrically coupled to the gate region (14), partially superimposed on the end-terminal region (20) and extending on the front side (1a), and during use, capacitively coupled (32, C) to a part of the semiconductor body adjacent to the end-terminal region (20) and having a first conductivity type (N) externally. ｇｄ A gate connection terminal (24) of a conductive material which is considered to be in a form that establishes ) An electronic device that houses [something].

2. The electronic device according to claim 1, wherein the end termination region (20) is in electrical contact with the source region (12).

3. The electronic device according to claim 1, wherein the active region (4) further includes a body region (11) having a second conductivity type (P), the source region extends within the body region, and the end termination region (20) is also in electrical contact with the body region and has a doping dose greater than that of each of the body regions.

4. The electronic device according to claim 1, further comprising a dielectric layer (30; 30, 22a) interposed between the front side (1a) and the gate connection terminal (24).

5. The electronic device according to claim 4, wherein the gate connection terminal (24) forms a first plate of the capacitor (32), the semiconductor body forms a second plate of the capacitor (32), and the dielectric layer (30; 30, 22a) is interposed between the first plate and the second plate of the capacitor (32).

6. The electronic device according to claim 4, wherein the dielectric layer (30; 30, 22a) is made of silicon oxide, silicon nitride, or silicon oxynitride.

7. The electronic device according to claim 4, wherein the dielectric layer (30; 30, 22a) is made of a high dielectric constant material, in particular a high-κ material having a parameter κ of a value higher than 7.

8. The electronic device according to claim 1, further comprising a first protective ring (40) having a doping value even lower than that of the second conductivity type (P) and the end-terminal region (20), and extending into the semiconductor body in the final portion of the end-terminal region (20).

9. The electronic device according to claim 8, further comprising a second protective ring (60) having a doping value even lower than that of the second conductivity type (P) and the end termination region (20), and extending into the semiconductor body at the final portion (24b') of the gate connection terminal (24).

10. The electronic device according to claim 9, further comprising one or more floating regions (61) having a second conductivity type (P) and extending within the semiconductor body between the first protective ring (40) and the second protective ring (60).

11. The end region (6) further includes a current spread layer (50) that extends into the semiconductor body (8, 10) on the front side (1a), The electronic device according to claim 1, wherein the current spread layer (50) has a doping value even higher than that of the first conductivity type (N) and the portion of the semiconductor body (8, 10) in which it is confined.

12. The electronic device according to claim 4, further comprising a drain region (9) extending on the back side (1b) opposite to the front side (1a) of the semiconductor body (8, 10).

13. The electronic device according to claim 12, wherein the portion of the semiconductor body adjacent to the end termination region (20) and having the first conductivity type externally is also in electrical contact with the drain region (9).

14. The gate region (14) has a first conductivity type (N), and together with the portion of the semiconductor body (8, 10) extending below the gate region (14), the capacitance (C) between the gate region and the drain region of the electronic device. ｇｄ First contribution (C ｇｄ The electronic device according to claim 12, which defines ).

15. The capacitive coupling (32, C ｇｄ ) is the first contribution (C ｇｄ The capacity between the gate region and the drain region (C) is added to ). ｇｄ The second contribution (C ｇｄ The electronic device according to claim 13, which defines the electronic device.

16. The second contribution (C ｇｄ The electronic device according to claim 15, wherein the value is configured to trigger a parasitic turn-on phenomenon during the turn-off period of the electronic device.

17. The overlap between the portion of the semiconductor body that is adjacent to the end terminal region (20) and has an external first conductivity type (N), and the end terminal region (20), has a value L along a reference axis (X; Y) parallel to the front side (1a). ｓｈｉｅｌｄ has, and it satisfies the following relational expression [Math 1] Or, equivalently, [Math 2] It satisfies the following, and furthermore, W ＡＡ This is the maximum range of the active region (4) along the reference axis (X; Y), and the active region (4) has a square shape. ε ｄｉｅｌ The dielectric constant of the material in the dielectric layer (30; 30, 22a), and ε ０ The dielectric constant of vacuum, The electronic device according to claim 13, when dependent on claim 4.

18. The end region (6) is interposed between the end termination region (20) and the gate connection terminal (24) and the portion of the semiconductor body adjacent to the end termination region (20) and having an external first conductivity type (N), and further accommodates a capacitive decoupling layer (70) that extends into the semiconductor body (8, 10) on the front side (1a). The electronic device according to claim 1, wherein the capacitive decoupling layer (70) is configured to deplete a majority carrier having a second conductivity type (P) at some point during use of the electronic device, thereby enabling the establishment of the capacitive coupling.

19. The capacity decoupling layer (70) is 10 １６ On-count / cm ３ The electronic device according to claim 18, having a doping dose of degree and extending within the semiconductor body with a thickness between 0.2 and 0.4 μm.

20. The electronic device according to claim 1, wherein the electronic device is a vertically conducting MOSFET.

21. The electronic device according to any one of the preceding claims, wherein the semiconductor body is silicon carbide.

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