Semiconductor element and manufacturing method thereof

Abstract

To provide a semiconductor element and a manufacturing methods thereof.SOLUTION: A semiconductor element includes a semiconductor stack layer, a protective layer located on the semiconductor stack layer and having an uppermost surface, an electrode located on the semiconductor stack layer and electrically connected to the semiconductor stack layer, and a conductive bump located on the electrode and having an outwardly protruding outermost surface, a top, and a maximum width, the length from the top to the uppermost surface is defined as the thickness of the conductive bump, and the ratio of the thickness to the width is 0.1 to 0.4, and the material of the electrode does not include Au.SELECTED DRAWING: Figure 2B

Description

[Technical Field]

[0001] This disclosure relates to a light-emitting element, and more particularly to a structure of a light-emitting element having conductive bumps and a method for manufacturing the same. [Background technology]

[0002] Light-emitting diodes (LEDs) are widely used in the fields of lighting and displays because they have characteristics such as low energy consumption, long lifespan, small size, fast response, and stable light output.

[0003] With the continuous evolution of LED technology, the brightness of LED dies is continuously improving, and the size of LED dies is also gradually decreasing, for example, to less than 100 μm, 50 μm, or even 30 μm. The applications of LED dies are not limited to general lighting or LCD screen backlights. The direct use of LED dies as pixels in LED displays may become a trend in next-generation displays.

[0004] A single LED display requires millions or even tens of millions of LED dies. Handling such a vast number of LED dies requires high-speed, precise alignment, and reliable die-attach technology. [Overview of the project] [Problems that the invention aims to solve]

[0005] The object of this disclosure is to provide a structure for a light-emitting element having conductive bumps and a method for manufacturing the same. [Means for solving the problem]

[0006] A semiconductor device is provided, which includes a semiconductor stack layer, a protective layer located on the semiconductor stack layer, electrodes located on and electrically connected to the semiconductor stack layer, and conductive bumps located on the electrodes. The distance from the top of the conductive bump to the uppermost surface of the protective layer is defined as the thickness of the conductive bump, and the ratio of the thickness of the conductive bump to the maximum width of the conductive bump is 0.1 to 0.4.

[0007] A method for manufacturing a semiconductor device is provided, which includes providing a substrate; forming a semiconductor stack layer on the substrate; forming electrodes on the semiconductor stack layer; forming bonding pads on the electrodes; forming an adhesive on the bonding pads; providing laser energy to irradiate the bonding pads and the adhesive so that the bonding pads form conductive bumps after melting, the conductive bumps are located on the electrodes, the adhesive covers the conductive bumps; and cleaning the adhesive. [Brief explanation of the drawing]

[0008] [Figure 1A] This is a top view of a semiconductor element array in one embodiment of the present disclosure. [Figure 1B] This is a cross-sectional view along the line segment A-A' in Figure 1A. [Figure 1C] This is a top view of a semiconductor element array in another embodiment of the present disclosure. [Figure 1D] This is a cross-sectional view along the line segment A-A' in Figure 1C. [Figure 1E] This is a cross-sectional view of a semiconductor element array in another embodiment of the present disclosure. [Figure 2A] This is a three-dimensional view of a semiconductor device in one embodiment of the present disclosure. [Figure 2B] This is a cross-sectional view of the semiconductor device shown in Figure 2A, along the BB' line segment. [Figure 2C] This is a cross-sectional view of a semiconductor device in another embodiment of the present disclosure. [Figure 2D] This is a three-dimensional view of a semiconductor device in another embodiment of the present disclosure. [Figure 2E] This is a cross-sectional view of the semiconductor device along the BB' line segment in Figure 2D. [Figure 3A] It is a top view of a semiconductor device in one embodiment of the present disclosure. [Figure 3B] It is a cross-sectional view taken along the line CC' of the semiconductor device in FIG. 3A. [Figure 3C] It is a cross-sectional view taken along the line DD' of the semiconductor device in FIG. 3A. [Figure 4A] It is a cross-sectional view of a semiconductor device array 2000 in one embodiment of the present disclosure. <00*0076>It is a cross-sectional view after removing one semiconductor device from the semiconductor device array shown in FIG. 4A. [Figure 4C] [[ID=*6]]It is a top view after removing one semiconductor device from the semiconductor device array shown in FIG. 4A. [Figure 4D] It is a cross-sectional view of a semiconductor device array 3000 in another embodiment of the present disclosure. [Figure 4E] It is a cross-sectional view of a semiconductor device array 3001 in another embodiment of the present disclosure. [Figure 5A] It is a flowchart for transferring a semiconductor device in one embodiment of the present disclosure. [Figure 5B] It is a flowchart for transferring a semiconductor device in one embodiment of the present disclosure. [Figure 5C] It is a flowchart for transferring a semiconductor device in one embodiment of the present disclosure. [Figure 5D] [[ID=3*]]It is a flowchart for transferring a semiconductor device in one embodiment of the present disclosure. [Figure 6A] It is a flowchart for transferring a semiconductor device in another embodiment of the present disclosure. [Figure 6B] It is a flowchart for transferring a semiconductor device in another embodiment of the present disclosure. [Figure 6C] It is a flowchart for transferring a semiconductor device in another embodiment of the present disclosure. [Figure 7A] It is a flowchart for manufacturing a semiconductor device in one embodiment of the present disclosure. [Figure 7B] This is a flowchart for manufacturing a semiconductor device in one embodiment of the present disclosure. [Figure 7C] This is a flowchart for manufacturing a semiconductor device in one embodiment of the present disclosure. [Figure 7D] This is a flowchart for manufacturing a semiconductor device in one embodiment of the present disclosure. [Figure 8A] This is a flowchart for manufacturing a semiconductor device in another embodiment of the present disclosure. [Figure 8B] This is a flowchart for manufacturing a semiconductor device in another embodiment of the present disclosure. [Figure 8C] This is a flowchart for manufacturing a semiconductor device in another embodiment of the present disclosure. [Figure 8D] This is a flowchart for manufacturing a semiconductor device in another embodiment of the present disclosure. [Figure 9A] This is a three-dimensional view of a semiconductor device in another embodiment of the present disclosure. [Figure 9B] This is a cross-sectional view of the semiconductor device along the BB' line segment in Figure 9A. [Figure 10A] This figure shows that a semiconductor element is fixed to a target substrate in one embodiment of the present disclosure. [Figure 10B] This figure shows that in another embodiment of the present disclosure, the semiconductor element is fixed to the target substrate. [Modes for carrying out the invention]

[0009] The following describes in detail the forms for implementing this disclosure, with reference to the drawings.

[0010] Figure 1A is a top view of a semiconductor element array 1000 in one embodiment of the present disclosure. The semiconductor element array 1000 includes a plurality of semiconductor elements 1 arranged on a substrate in an array manner. The semiconductor elements 1 may be semiconductor elements such as light-emitting diodes (LEDs), laser diodes (LDs), and transistors. The semiconductor element array 1000 may consist of semiconductor elements 1 of the same type or different types. The substrate 10 may be a growth substrate for the semiconductor elements 1, or it may be used as a carrier (mounting body) for the semiconductor elements 1 after the growth substrate has been removed. The substrate 10 may be made of Ge, GaAs, InP, Sapphire, SiC, Si, LiAlO2, ZnO, GaN, AlN, metal, glass, thermal release tape, UV release tape, chemical release tape, heat-resistant tape, blue tape, or a tape having a dynamic release layer (DRL). Each semiconductor element 1 has a pair of conductive bumps 2a and 2b on one side away from the substrate 10, and the pair of conductive bumps 2a and 2b are used for electrical and physical connections to an external circuit (e.g., circuit board, backplane, etc.). In the top view, the projected shape of the conductive bumps is approximately rectangular, as shown in Figures 1A and 3A.

[0011] Figure 1B is a cross-sectional view along the line segment A-A' in Figure 1A. The semiconductor element 1 has a pair of electrodes 3a and 3b on one side away from the substrate 10. Conductive bumps 2a and 2b are placed directly on electrodes 3a and 3b, respectively. The upper surfaces of the conductive bumps 2a and 2b are arc-shaped and not parallel to the upper surfaces of electrodes 3a and 3b.

[0012] The conductive bumps 2a, 2b and electrodes 3a, 3b preferably employ different materials. The electrode material includes metals, such as Au, Ag, Cu, Cr, Al, Pt, Ni, Ti or their alloys, or combinations thereof in stack layers. The conductive bumps 2a, 2b may also include low-melting-point metals or low-liquid-melting-point (Liquidus Melting Point) alloys, the melting point or liquefaction temperature of which is lower than 210°C, for example, Bi, Sn, In or their alloys may be used. In one embodiment, the melting point of the low-melting-point metal or the liquefaction temperature of the low-liquid-melting-point alloy is lower than 170°C. The material of the low-liquid-melting-point alloy may be SnIn alloy or SnBi alloy.

[0013] Figure 1C is a top view of a semiconductor element array 1001 in another embodiment of the present disclosure. The semiconductor element array 1001 includes a plurality of semiconductor elements 1 arranged on a substrate 10 in a predetermined pattern. The substrate 10 has a substantially circular outline. The material of the substrate can be described in the relevant paragraphs above. Figure 1D is a cross-sectional view along the line segment A-A' in Figure 1C. An adhesive structure 4 is between the semiconductor elements 1 and the substrate 10. The semiconductor elements 1 are temporarily fixed on the substrate 10 via the adhesive structure 4. The semiconductor elements 1 have a pair of electrodes 3a, 3b on one side away from the substrate 10. Conductive bumps 2a, 2b are placed directly on the electrodes 3a, 3b, respectively. The upper surfaces of the conductive bumps 2a, 2b are arc-shaped and not perfectly parallel to the upper surfaces of the electrodes 3a, 3b. The adhesive structure 4 may include a polymer, for example, polyimide or benzocyclobutane (BCB). For the materials of the conductive bumps 2a, 2b and electrodes 3a, 3b, refer to the descriptions in the relevant paragraphs above. As shown in Figure 1D, the outer edge (referred to as the outer edge) 42 of the adhesive structure 4 is approximately aligned with the outermost edge (referred to as the outermost edge) 19 of the semiconductor element 1. The adhesive portion 4 has a thickness H4, which is approximately 2-3 μm or 1-10 μm. In another embodiment, the outer edge 42 is not aligned with the outermost edge 19 of the semiconductor element 1, and the adhesive structure 4 may be recessed inward (contracted) or protrude outward from the outermost edge 19 of the semiconductor element 1. The adhesive structure 4 has a maximum width W5, and the semiconductor element 1 has a maximum width W6. W5 is approximately the same as W6. In another embodiment, W5 may be smaller or larger than W6.

[0014] Figure 1E is a cross-sectional view of a semiconductor element array 1001' in another embodiment of the present disclosure. The semiconductor element array 1001' includes a plurality of semiconductor elements 1 arranged on a substrate 10 in a predetermined pattern. The material of the substrate can be found in the description in the relevant paragraphs above. There is an adhesive structure 4 between the semiconductor elements 1 and the substrate 10. The semiconductor elements 1 are temporarily fixed to the substrate 10 via the adhesive structure 4. The semiconductor elements 1 have a pair of electrodes 3a, 3b on one side away from the substrate 10. Conductive bumps 2a, 2b are placed directly on the electrodes 3a, 3b, respectively. The material of the adhesive structure 4, the structure and material of the conductive bumps 2a, 2b and electrodes 3a, 3b can be found in the description in the relevant paragraphs above. As shown in Figure 1E, the adhesive structure 4 includes a raised section 43 and a continuous section 44. The continuous section 44 is a continuous (uninterrupted) structure and is continuously distributed on the substrate 10 so as to pass below all the semiconductor elements 1 and between two adjacent semiconductor elements 1. Each raised portion 43 is located between the semiconductor element 1 and the continuous portion 44, and protrudes upward from the continuous portion 44, corresponding to one semiconductor element 1. The outer edge 42 of the raised portion 43 is aligned with or close to the outermost edge 19 of the semiconductor element 1. The adhesive portion 4 has a thickness H4, which is approximately 2-3 μm. The continuous portion 44 has a thickness H5, which is greater than 0 μm and less than 1 μm. In another embodiment, the outer edge 42 is not aligned with the outermost edge 19 of the semiconductor element 1, and the raised portion 43 may be recessed inward from or protrude outward from the outermost edge 19 of the semiconductor element 1. The raised portion 43 has a maximum width W5, and the semiconductor element 1 has a maximum width W6. W5 is approximately equal to W6. In another embodiment, W5 may be smaller or larger than W6.

[0015] Figure 2A is a three-dimensional view of a semiconductor element 1 in one embodiment of the present disclosure. The maximum side length of the semiconductor element 1 is 100 μm or 50 μm or less. For example, the maximum side length of the semiconductor element is approximately 40 μm, and the width is approximately 20 μm. Conductive bumps 2a and 2b have opposing polarities (positive and negative electrodes), and the minimum horizontal distance D between them is less than 40 μm. For example, the maximum side length of the semiconductor element is approximately 40 μm, and D is approximately 15 μm. Conductive bumps 2a and 2b completely cover the electrodes (for example, electrodes 3a / 3b in Figure 1B) and have outwardly projecting arc-shaped and apex portions 21a and 21b. As shown in Figure 1A, the apex portions 21a and 21b are located approximately at the geometric center of the conductive bumps 2a and 2b and / or the electrodes.

[0016] Figure 2B is a cross-sectional view of the semiconductor element in Figure 2A along the BB' line segment. The semiconductor element 1 is placed on a substrate 10 and has a semiconductor stack layer 14, a protective layer 15, a first electrode 3a, a second electrode 3b, a first conductive bump 2a, and a second conductive bump 2b. The outermost edge 19 of the semiconductor stack layer 14 is an inclined surface and is inclined with respect to the substrate 10. The semiconductor stack layer 14 includes a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13. The first semiconductor layer 11 and the second semiconductor layer 13 each provide electrons and holes, respectively, so that the electrons and holes can recombine in the active layer 12 to emit light rays. The first semiconductor layer 11, the active layer 13, and the second semiconductor layer 13 are III-V semiconductor materials, for example, Al x In y Ga (1-x-y) N or Al x In y Ga (1-x-y)P may be included, where 0≦x, y≦1, and (x+y)≦1. Depending on the active layer material, the LED die can emit red light with a peak value between 610nm and 650nm, green light with a peak value between 530nm and 570nm, cyan light with a peak value between 500nm and 485nm, blue light with a peak value between 450nm and 490nm, violet light with a peak value between 400nm and 450nm, or ultraviolet light with a peak value between 280nm and 400nm. The maximum thickness of the semiconductor stack layer 14 is approximately 10μm or less. In one embodiment, the lower surface 17 of the first semiconductor layer 11 is in contact with the substrate 10 and is a roughened surface. In another embodiment, the lower surface 17 of the first semiconductor layer 11 is a nearly flat surface (not shown). In another embodiment, the substrate 10 is a growth substrate for epitaxially growing the semiconductor stack layer 14, and the entire upper surface of the substrate 10 facing the semiconductor stack layer 14 is a roughened surface (not shown), for example, a patterned sapphire substrate (PSS). In one embodiment, the semiconductor element 1 includes carriers (not shown), which are located beneath the semiconductor stack layer 14 and used to support the semiconductor stack layer 14. The carriers may be an epitaxial growth substrate or a non-epitaxial growth substrate for the semiconductor stack layer 14, and the material of the carriers can be found in the description in the relevant paragraph above for the substrate 10. The selection of materials must be in accordance with theoretical and practical feasibility.

[0017] The semiconductor stack layer 14 has a flat platform 16, which is used to expose the first semiconductor layer 11 outside the active layer 12 and the second semiconductor layer 13. The protective layer 15 covers the upper surface of the second semiconductor layer 13, the sidewalls of the first semiconductor layer 11, the sidewalls of the active layer 12, the sidewalls of the second semiconductor layer 13, and the upper surface of the first semiconductor layer 11 located within the flat platform 16. The protective layer 15 may be in direct contact with the substrate 10. In another embodiment, the protective layer 15 does not contact the substrate 10. The protective layer 15 has a first aperture 5a within the flat platform 16 to expose a portion of the first semiconductor stack layer 11. The protective layer 15 has a second aperture 5b in the second semiconductor layer 13 to expose a portion of the second semiconductor layer 13. The first electrode 3a is located within the flat platform 16 and has a portion formed on the protective layer 15, and this portion covers the protective layer 15 located within the flat platform 16 and a portion of the protective layer 15 located outside the flat platform 16. The first electrode 3a has a first recess 6a formed within the first aperture 5a and electrically connected to the first semiconductor layer 11. The first electrode 3a has a stepped outer shape where it is located on the flat platform 16. The second electrode 3b has a portion located on the protective layer 15 other than the second aperture 5b and a second recess 6b formed within the second aperture 5b and electrically connected to the second semiconductor layer 13.

[0018] The protective layer 15 may have a single-layer or multi-layer structure and has electrical insulation properties. The material of the single-layer structure may include oxides, nitrides, or polymers. The oxides may include Al2O3, SiO2, TiO2, Ta2O5 (Tantalum Pentoxide) or AlO x and the like. The nitrides may include AlN, S i N x and the like. The polymers may include Polyimide or Benzocyclobutane (BCB). The materials of the multi-layer structure may include Al2O3, SiO2, TiO2, Nb2O5, SiN x and combinations of these materials. The multi-layer structure may form a DBR (Distributed Bragg Reflector).

[0019] As shown in Figure 2B, the first conductive bump 2a is formed directly above the first electrode 3a. The first conductive bump 2a can completely or partially fill the first recess 6a of the first electrode 3a, and its outermost surface 22a has a macroscopically smooth, outwardly projecting arc shape. The first conductive bump 2a has a top 21a, which is the region where the first conductive bump 2a is furthest from the substrate 10. As shown in Figure 2B, the outermost surface 22a of the first conductive bump 2a is not parallel to the bottom surface of the first conductive bump 2a, nor is it parallel to the top surface of the first electrode 3a. The bottom surface 17 of the first semiconductor layer 11 is a roughened surface, and the roughness of the outermost surface 22a of the first conductive bump 2a is less than the roughness of the bottom surface 17 of the first semiconductor layer 11, and also less than the roughness of the top surface of the first electrode 3a.

[0020] As shown in Figure 2B, the second conductive bump 2b directly covers the upper part of the second electrode 3b. The second conductive bump 2b can completely or partially fill the second recess 6b of the second electrode 3b, and its outermost surface 22b has a macroscopically smooth, outwardly projecting arc shape. The second conductive bump 2b has a top 21b, which is the region where the second conductive bump 2b is furthest from the substrate 10. As shown in Figure 2B, the outermost surface 22b of the second conductive bump 2b is not parallel to the bottom surface of the second conductive bump 2b, nor is it parallel to the top surface of the second electrode 3b. The roughness of the outermost surface 22b of the second conductive bump 2b is less than the roughness of the bottom surface 17 of the first semiconductor layer 11, and also less than the roughness of the top surface of the second electrode 3b. Preferably, the top 21a of the first conductive bump 2a and the top 21b of the second conductive bump 2b are located at approximately the same elevation (height), which is advantageous for the semiconductor element 1 to be subsequently stably fixed on the substrate. However, in reality, there may be height differences that are acceptable in the manufacturing process. The lowest surfaces of the first conductive bump 2a and the second conductive bump 2b are usually formed conformally on the first electrode 3a and the second electrode 3b, respectively, and their lowest points are often not at the same height. As shown in Figure 2B, the first conductive bump 2a has a vertical distance from its top 21a to the uppermost surface 151 of the protective layer 15, which is the first thickness H1, and the first conductive bump 2a has a first (maximum) width W1, with H1 / W1 being between 0.1 and 0.4, preferably 0.1 and 0.25. The second conductive bump 2b has a vertical distance from its top 21b to the uppermost surface 151 of the protective layer 15, which is the second thickness H2, and the second conductive bump 2b has a second (maximum) width W2, with H2 / W2 being between 0.1 and 0.4, preferably 0.1 and 0.25. H1 / W1 and H2 / W2 may be the same or different. The second thickness H2 of the second conductive bump 2b is 4-6 μm.

[0021] If the first conductive bump 2a is more densely packed into the first recess 6a of the first electrode 3a, and the second conductive bump 2b is more densely packed into the second recess 6b of the second electrode 3b, the reliability of the physical and electrical connection between the semiconductor element 1 and the circuit board (not shown) can be improved, and the probability of failure (e.g., malfunction) can be reduced. More specifically, although the structure of the semiconductor element 1 is as shown in Figure 2B, if the conductive bumps 2a / 2b are not present, when the semiconductor element 1 is fixedly connected to the circuit board with solder, the solder located between the first electrode 3a and the circuit board (not shown) may form holes near the first recess 6a, and the solder located between the second electrode 3b and the circuit board (not shown) may form holes near the second recess 6b. These holes can reduce the strength of the fixed connection between the semiconductor element 1 and the circuit board.

[0022] If the process for forming conductive bumps includes a heat treatment step, under certain (predetermined) combinations of conductive bump and electrode materials, the conductive bumps can form discretely distributed metal particles inside them after the heat treatment step, as shown in Figure 2C. Figure 2C is a cross-sectional view of semiconductor device 1 in another embodiment of the present disclosure. For the structure of Figure 2C, refer to the description in Figure 2B and its related paragraphs. Inside the first conductive bump 2a and the second conductive bump 2b are discretely distributed particles 7 of irregular size and irregular shape, the material of which is different from that of conductive bumps 2a and 2b but is the same as some of the material of electrodes 3a and 3b, for example, gold, platinum, or an alloy of the aforementioned materials. The shape of the particles 7 may be elongated, polygonal, leaf-shaped, or teardrop-shaped.

[0023] Figures 2D to 2E show a semiconductor element 1' in another embodiment of the present disclosure. Its structure can be described in Figures 2A to 2B and the relevant paragraphs. As shown in Figure 2D, the conductive bumps 2a and 2b have outwardly projecting arc shapes and have vertices 21a and 21b. The vertices 21a and 21b are not at the same height. The vertices 21a are slightly lower than the vertices 21b. Figure 2E is a cross-sectional view of the semiconductor element 1' in Figure 2D along the BB' line segment. The conductive bump 2a is located above the base 16, and when the volume of conductive bump 2a is close to that of conductive bump 2b, some of the conductive bump 2a needs to fill the base 16, so the vertices 21a of conductive bump 2a are slightly lower than the vertices 21b of conductive bump 2b. In one embodiment, the first thickness H1 of the first conductive bump 2a is 0.4 to 1 μm smaller than the first thickness H1 of the first conductive bump 2a.

[0024] Figure 3A is a top view of a semiconductor element 1 in one embodiment of the present disclosure. Figure 3B is a cross-sectional view of the semiconductor element 1 along the CC' line segment in Figure 3A. Figure 3C is a cross-sectional view of the semiconductor element 1 along the DD' line segment in Figure 3A. The semiconductor element 1 includes a semiconductor stack layer 14, and electrodes 3 and conductive bumps 2 located on the semiconductor stack layer 14. In Figure 3A, the projected shape of the conductive bumps 2 and electrodes 3 is substantially rectangular. In the cross-sectional view, the outermost surface 22 of the conductive bump 2 has a macroscopically smooth, outwardly projecting arc shape. As shown in Figure 3B, the outermost surface 22 is in contact with the upper surface of the electrode 3, and the tangent at the contact point of the conductive bump 2 and the upper surface of the electrode 3 form an angle θ1. The angle θ1 is close to 90 degrees, preferably 70 degrees < θ1 < 90 degrees. As shown in Figure 3C, the outermost surface 22 is in contact with the upper surface of the electrode 3, and the tangent at the contact point of the conductive bump 2 and the upper surface of the electrode 3 form an angle θ2. The angle θ2 < angle θ1, and preferably 30 degrees < θ2 < 70 degrees. In other words, as shown in Figure 3A, the cross-sectional shape of the conductive bump 2 in the direction parallel to the side length of the electrode 3 is different from the cross-sectional shape in the diagonal direction of the electrode 3.

[0025] Figure 4A shows a semiconductor element array 2000 in one embodiment of the present disclosure. The semiconductor element array 2000 includes a plurality of semiconductor elements 1 (for convenience, only three semiconductor elements 1 in one dimension are shown in the figure, but the semiconductor element array 2000 may include m*n semiconductor elements 1, where m and n are positive integers greater than or equal to 0, and m and n are not simultaneously 0) and a carrier 30. The semiconductor elements 1 are arranged on the carrier 30 in a manner in which conductive bumps 2 face the carrier 30 (also called a flip-chip). The carrier 30 can support and fix the semiconductor elements 1. The carrier 30 includes a mounting plate 31 and an adhesive layer 32, the material of the mounting plate 31 may be a translucent material such as glass, sapphire, or polymer material that can transmit light of a specific wavelength emitted by a light-emitting diode or laser diode. The adhesive layer 32 may include a thermal removal adhesive, a photodissociable adhesive, a chemical removal adhesive, a heat-resistant adhesive, a blue tape, or a tape having a dynamic release layer. In another embodiment, the adhesive layer may include a polymer, such as polyimide or benzocyclobutane (BCB). When the aforementioned semiconductor element 1 is arranged on the carrier 30 in a flip-chip manner, the smooth, outwardly protruding outermost surface 22 of the conductive bump 2 directly contacts the adhesive layer 32. As shown in Figure 4A, the conductive bump 2 can partially indent into the adhesive layer 32, with the indented portion having a maximum width W3 parallel to the surface of the adhesive layer 32, and the conductive bump 2 itself having a maximum width W4, where W4 > W3. Furthermore, the outermost surface 22 of the conductive bump 2 is a smooth arc shape, and the projected area of ​​the portion of the conductive bump 2 indented into the adhesive layer in a given projection direction (for example, the area of ​​the indentation 34 in Figure 4C) is smaller than the area of ​​the electrode, and the adhesive force is also relatively low, which is advantageous for the subsequent transfer process of transferring the semiconductor element 1 from the carrier 30 to another location. The transfer process of the semiconductor element 1 will be described later.

[0026] Figures 4B and 4C are side and top views, respectively, of the semiconductor element array 2000 after one semiconductor element 1 has been removed from Figure 4A. As shown in Figure 4C, from the top view, a removal region 33 (as indicated by the dotted line) is defined on the upper surface of the carrier 30, which represents the area exposed on the carrier 30 after the removal of the semiconductor element 1, i.e., the projected area of ​​the semiconductor element 1 in the top view. The removal region 33 includes an indentation 34. The indentation 34 is the area where the conductive bump 2 has been pressed into the adhesive layer 32, and the indentation 34 has a projected area in the top view. Experimental results show that when the ratio of the projected area of ​​the conductive bump indentation 34 to the projected area of ​​the semiconductor element 1 is less than 0.2, the semiconductor element 1 can be easily picked up from the carrier 30 and transferred to another position.

[0027] Figures 4D to 4E show semiconductor element arrays in another embodiment of the present disclosure. Figure 4D shows a semiconductor element array 3000, for which you can refer to Figure 4A and the description in the relevant paragraphs. The semiconductor element array 3000 includes a plurality of semiconductor elements 1 and a carrier 30. The carrier 30 includes a mounting plate 31 and a single adhesive layer 32. The semiconductor elements 1 are arranged on the carrier 30 such that conductive bumps 2 face the carrier 30. The conductive bumps 2 and electrodes 3 are completely embedded in the adhesive layer 32 and can be completely covered by the adhesive layer 32. The adhesive layer 32 also covers the lower surface of the semiconductor elements 1 that is not covered by the electrodes 3. By being temporarily fixed on the adhesive layer 32, the relative positions between the plurality of semiconductor elements 1 are maintained and do not change in subsequent processes. Figure 4E shows a semiconductor element array 3001, for which you can refer to Figure 4D and the description in the relevant paragraphs. The semiconductor element array 3001 includes a plurality of semiconductor elements 1 and a carrier 30. The carrier 30 includes a mounting plate 31 and a plurality of mutually separated adhesive layers 32, where one adhesive layer 32 corresponds to one semiconductor element 1 in horizontal position and width. There is a gap (space) 33 greater than 0 between two adjacent adhesive layers 32. The plurality of semiconductor elements 1 are arranged on the carrier 30 in such a way that conductive bumps 2 face the carrier 30. The conductive bumps 2 and electrodes 3 are completely embedded in the adhesive layers 32 and can be completely covered by the adhesive layers 32. In addition, the adhesive layers 32 also cover the lower surface of the semiconductor element 1 that is not covered by the electrodes 3.

[0028] Figures 5A to 5D illustrate the steps for transferring semiconductor elements 1 in one embodiment of the present disclosure. As shown in Figure 5A, a plurality of semiconductor elements 1 are arranged on a carrier 30 in the form of an array. Each semiconductor element 1 is in contact with the adhesive layer 32 of the carrier 30 by a portion of the surface of a conductive bump 2 and is temporarily fixed on the carrier 30. A pickup tool 40 is provided to move the semiconductor elements 1 from the carrier 30 to another location. The pickup tool 40 has a plurality of pickup parts 41, each pickup part 41 corresponding to the position of a semiconductor element 1 waiting to be picked up. As shown in Figure 5B, the pickup tool 40 moves to approach the plurality of semiconductor elements 1, causing the pickup parts 41 to make contact with the semiconductor elements 1, and then moves upward to cause the semiconductor elements 1 picked up by the pickup parts 41 to leave the carrier 30. Note that the viscosity between the pickup parts 41 and the semiconductor elements 1 must be greater than the viscosity between the semiconductor elements 1 and the carrier 30 during the execution of the pickup step (during pickup). Semiconductor elements 1 that are not in contact with the pickup parts 41 remain on the carrier 30. As shown in Figure 5C, the pickup tool 40 moves above a predetermined position on the target substrate 50 together with the semiconductor element 1, which is temporarily fixed on the pickup unit 41. At this predetermined position, the semiconductor element 1 can directly or indirectly contact the target substrate 50 and ultimately be placed or fixed directly on the target substrate 50. As shown in Figure 5D, the semiconductor element 1 remains on the target substrate 50 away from the pickup tool 40, and the pickup tool 40 can move to the same or a different carrier 30 to pick up another semiconductor element 1. After the transfer, the semiconductor element 1 is positioned on the target substrate 50 in such a way that the conductive bump 2 faces the target substrate 50. The target substrate 50 may be a circuit board applied to a display, a TFT substrate, a substrate with an RDL (Redistribution Layer), or a sub-mount of a package. In another embodiment, the target substrate 50 may be a temporary carrier similar to the carrier 30 described above. In Figures 5A to 5D, the contact method between the semiconductor element 1 and the carrier 30 is not limited to the embodiment shown in Figure 4A, but may also be the embodiment shown in Figures 4D and 4E.

[0029] Figures 6A to 6C illustrate the steps for transferring semiconductor elements 1 in another embodiment of the present disclosure. Figure 6A shows that multiple semiconductor elements 1 are placed on a carrier 30 in the form of an array. Each semiconductor element 1 is in contact with the adhesive layer 32 of the carrier 30 by a portion of the surface of a conductive bump 2 and is temporarily fixed on the carrier 30. Subsequently, the structure of Figure 6A is inverted or the target substrate 50 is moved so that the semiconductor elements 1 are positioned between the carrier 30 and the target substrate 50, but the semiconductor elements 1 do not directly contact the target substrate 50, for example, as shown in Figure 6B, so that the semiconductor elements 1 are suspended above the target substrate 50. Laser energy L1 is provided to irradiate a specific (predetermined) position of the adhesive layer 32 from the side of the mounting plate 31, and this specific position corresponds to one semiconductor element 1 that needs to be transferred. The laser energy L1 may be a single-shot laser or a multi-shot laser. In one embodiment, a single-shot laser or a multi-shot laser may be irradiated to one position on one semiconductor element 1 or one adhesive layer 32 in one irradiation process. In another embodiment, a single-shot laser or a multi-shot laser may be irradiated to multiple positions on one semiconductor element 1 or one adhesive layer 32, each in one irradiation process. As shown in Figure 6C, after irradiation with laser energy L1, the adhesive layer 32 experiences a decrease in viscosity between the semiconductor element 1 and the adhesive layer 32, or the force that causes the semiconductor element 1 to move downward becomes greater than the viscosity of the adhesive layer 3 relative to the semiconductor element 1, thereby causing the semiconductor element 1 to fall from the carrier 30 onto the target substrate 50. After transfer, the semiconductor element 1 is positioned on the target substrate 50 in such a way that the conductive bump 2 leaves the target substrate 50. In another embodiment, in the step shown in Figure 6B, the semiconductor element 1 may first make direct contact with the target substrate 50 and then be irradiated with laser energy L1, thereby allowing the semiconductor element 1 to be more accurately aligned with the target substrate 50. By selectively applying the removal step to the semiconductor element 1 after the steps shown in Figure 6C, the adhesive layer 32 remaining on the conductive element 1 can be removed.The removal step may include dry etching or wet etching, and dry etching may be an oxygen plasma etching process. In Figures 6A to 6C, the contact method between the semiconductor element 1 and the carrier 30 is not limited to the embodiment shown in Figure 4A, but may also be the embodiment shown in Figures 4D and 4E.

[0030] Figures 7A to 7D show the steps for manufacturing a semiconductor device 1 in one embodiment of the present disclosure. As shown in Figure 7A, a plurality of semiconductor units 100 are placed on a substrate 10. The semiconductor unit 100 includes a semiconductor stack layer 14, a protective layer 15, a first electrode 3a, and a second electrode 3b. The semiconductor unit 100 is placed on the substrate 10 in such a way that the first electrode 3a and the second electrode 3b are separated from the substrate 10. The first electrode 3a and the second electrode 3b each have recesses, and for a description of the relevant structure, refer to the description in the relevant paragraph above. Subsequently, adhesive 80 (two lumps) are formed on the first electrode 3a and the second electrode 3b at two separate locations. The adhesive 80 includes a resin 81 and a plurality of conductive particles 82 dispersed in the resin 81. In one embodiment, the method of forming the adhesive 80 may be printing, coating, spraying, or dispensing. The printing method may include aerosol jet printing or inkjet printing. The resin 81 material includes thermosetting plastic and flux. The thermosetting plastic may be epoxy resin, silicone resin, PMMA (polymethyl methacrylate), and episulfide. The melting point of the conductive particles 82 is lower than the curing temperature of the resin 81. In one embodiment, the material of the conductive particles 82 may be gold, silver, and copper. In another embodiment, the material of the conductive particles 82 may be a low-melting-point metal or a low-liquid-melting-point alloy. In one embodiment, the melting point or liquefaction temperature of the low-melting-point metal or low-liquid-melting-point alloy is lower than 210°C. In another embodiment, the melting point or liquefaction temperature of the low-melting-point metal or low-liquid-melting-point alloy is lower than 170°C. The material for the low-liquid melting point alloy may be a tin alloy, such as a tin-indium alloy or a tin-bismuth alloy.

[0031] As shown in Figure 7B, the adhesive 80 is heated by irradiating the adhesive 80 or a nearby area with laser energy L2. The laser energy L2 may include an ultraviolet (UV) laser beam, a visible light laser beam, or an infrared (IR) laser beam. In one embodiment, the laser energy L2 is an infrared pulse mode laser beam, with a wavelength in the range of 750 nm to 2,000 nm, and a spot size of 0.004 to 0.002 cm. 2 The beam diameter is 100-500 μm, the pulse length is less than 20 milliseconds (ms), the repetition frequency is 500-4000 Hz, the duty cycle is 1%-10%, the laser power is 100 W, and the laser energy is 595-850 J / cm². 2 As shown in Figure 7C, during the heating process, the conductive particles 82 can gather on the first electrode 3a and the second electrode 3b to form first conductive bumps 2a and second conductive bumps 2b having outwardly protruding arc-shaped outer surfaces. The resin 81 can move onto the first conductive bumps 2a and the second conductive bumps 2b, and the region 18 between the first electrode 3a and the second electrode 3b. After heating, the first conductive bumps 2a and the second conductive bumps 2b harden, while the resin 81 covering them heats up but does not fully harden (uncured), remaining in a liquid or semi-liquid state. Subsequently, as shown in Figure 7D, a washing step is performed to remove the uncured resin 81, thereby exposing the first conductive bumps 2a and the second conductive bumps 2b to the external environment, which are then used for contact with the carrier during the subsequent transfer. The cleaning step can be performed using a solvent, which may include NMP (N-Methylpyrrolidinone), MEK (Methyl Ethyl Ketone), ACE (Acetone), or ACE (Isopropyl Alcohol).

[0032] Figures 8A to 8D show the steps for manufacturing a semiconductor device 1 in another embodiment of the present disclosure. As shown in Figure 8A, a plurality of semiconductor units 100 are placed on a substrate 10. The semiconductor unit 100 includes a semiconductor stack layer 14, a protective layer 15, a first electrode 3a, and a second electrode 3b. The semiconductor unit 100 is placed on the substrate 10 in such a way that the first electrode 3a and the second electrode 3b are separated from the substrate 10. The first electrode 3a and the second electrode 3b each have recesses, and for a description of the relevant structures, refer to the relevant paragraphs above. A first bonding pad 23a and a second bonding pad 23b are formed on the first electrode 3a and the second electrode 3b, respectively, by electroplating, chemical plating, or vapor deposition. The upper surface 24a of the first bonding pad 23a and the upper surface 24b of the second bonding pad 23b are substantially conformal to the upper surfaces of the first electrode 3a and the second electrode 3b, respectively; that is, their contours are similar and they have recesses and / or a rough texture. A block of adhesive 83 is formed on the semiconductor unit 100, the first bonding pad 23a, and the second bonding pad 23b. In this example, the adhesive 83 consists only of resin. In another embodiment, the adhesive 83 contains resin and conductive particles at a relatively low concentration (compared to the conductive particles in Figure 7A). In one embodiment, the method of forming the adhesive 80 may be by printing, coating, spraying, and dispensing. Of these, the printing method may include aerosol jet printing or inkjet printing. For the materials of the first bonding pad 23a and the second bonding pad 23b, refer to the description in the paragraphs related to the conductive bumps 2a and 2b above. For the material of the resin, refer to the description in the related paragraphs above.

[0033] As shown in Figure 8B, the adhesive 83, the first bonding pad 23a, and the second bonding pad 23b are heated by irradiating them with laser energy L3. The laser energy L3 may include an ultraviolet (UV) laser beam, a visible light laser beam, or an infrared (IR) laser beam. In one embodiment, the laser energy L3 is an infrared laser beam, and its wavelength is in the range of 750 nm to 2,000 nm. As shown in Figure 8C, during the heating process, the first bonding pad 23a and the second bonding pad 23b are heated and melt into the adhesive 83, and gather on the first electrode 3a and the second electrode 3b (if the resin contains conductive particles, the conductive particles may also move partially or completely toward the first electrode 3a and the second electrode 3b after being heated), forming first conductive bumps 2a and second conductive bumps 2b having outwardly protruding arc-shaped outer surfaces. The adhesive 83 can move over the first conductive bump 2a, the second conductive bump 2b, and the region 18 between the first electrode 3a and the second electrode 3b. After heating, the first conductive bump 2a and the second conductive bump 2b harden, and the adhesive 83 (or resin) covering them heats up but does not harden completely, remaining in a liquid or semi-liquid state. Subsequently, as shown in Figure 8D, a cleaning step is performed to remove the uncured adhesive 83 (or resin), thereby exposing the first conductive bump 2a and the second conductive bump 2b to the external environment for contact with the carrier during the subsequent transfer. For details on the cleaning step, please refer to the explanation in the relevant paragraph of Figure 7D above.

[0034] In another embodiment, the cleaning steps described in Figures 7D and 8D above may not completely remove the adhesive between the conductive bumps 2a and 2b, and some may remain on the semiconductor device 100. To avoid affecting the subsequent transfer and die-attach processes, the maximum height of the remaining (residual) adhesive is preferably not higher than the conductive bumps 2a and 2b. Figure 9A is a stereoscopic view of the semiconductor device 20 in another embodiment of the present disclosure. Figure 9B is a cross-sectional view of the semiconductor device 20 along the BB' line segment in Figure 9A. As shown in Figure 9A, the semiconductor device 20 has two separate first conductive bumps 2a and second conductive bumps 2b on its upper side. Between the first conductive bump 2a and the second conductive bump 2b is at least one mass of remaining adhesive 84 covering the semiconductor device 20. In the top view, the remaining adhesive 84 has an irregular shape and an unfixed area. As shown in Figure 9B, the semiconductor device 20 has a semiconductor stack layer 14, a protective layer 15, a first electrode 3a, a second electrode 3b, a first conductive bump 2a, and a second conductive bump 2b. The outermost edge 19 of the semiconductor stack layer 14 is an inclined surface and is inclined with respect to the substrate 10. The semiconductor stack layer 14 includes a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13. The remaining adhesive 84 is located on the protective layer 15 between the first conductive bump 2a and the second conductive bump 2b. The uppermost surface of the residual adhesive 84 is not higher than the maximum height of the first conductive bump 2a and the second conductive bump 2b and has a rough outer surface. Since the height of the remaining adhesive 84 does not exceed the conductive bumps 2a and 2b, it does not affect the subsequent transfer and die-attach processes.

[0035] Figure 10A shows how a semiconductor element 1 is die-attached to a target substrate 51 in one embodiment of the present disclosure. The target substrate 51 may be a circuit board with conductive circuits, a TFT substrate, a substrate with an RDL (Redistribution Layer), or a sub-substrate of a package, which is applied to a display. There are a plurality of conductive connection pads 52 on the target substrate 51. The semiconductor element 1 may be any one of the above structures. The conductive bumps are heated, melted, and hardened to form a bonding layer 53, which connects the semiconductor element 1 to the conductive connection pads 52. The semiconductor element 1 can receive power and / or drive signals through the conductive connection pads 52 and the bonding layer 53. The bonding layer 53 can selectively cover the side surface 521 of the conductive connection pads 52. In the process of heating the conductive bumps to form the bonding layer 53, dispersed metal particles may appear in the bonding layer 53 due to adjustments of process parameters such as heating temperature and heating time. Figure 10B shows how a semiconductor element 1 is die-attached to a target substrate 51 in another embodiment of the present disclosure. After the bonding layer 53 hardens, irregular particles 8 appear in the bonding layer 53. In other words, discretely distributed and irregularly shaped particles 8 are scattered in the bonding layer 53, and the material of the particles 8 is different from that of the bonding layer 53, but is the same as the material of some of the electrodes 3a, 3b and / or conductive connection pads 52 of the semiconductor element 1, for example, gold, platinum, or an alloy of the aforementioned materials. In one embodiment, the heating and hardening method may be laser energy, and the laser energy may include ultraviolet (UV) laser beam, visible light laser beam, or infrared (IR) laser beam. In one embodiment, the wavelength of the infrared laser beam is in the range of 750 nm to 2,000 nm.

[0036] In another embodiment, the materials for the conductive bumps and electrodes of the semiconductor device do not contain gold (Au). Such a configuration can be used for semiconductor devices 1, 1', and 20 in any one of the embodiments described above, i.e., the conductive bumps 2a, 2b and electrodes 3a, 3b do not contain Au. When electrodes 3a, 3b contain Au and conductive bumps 2a, 2b contain Sn, Au and Sn readily form an Au-Sn intermetallic compound (Au-Sn IMC), for example, AuSn4, in the conductive bumps 2a, 2b after heating. The melting point of the Au-Sn intermetallic compound can reach 300°C or higher, which is usually higher than the melting point of Sn in the conductive bumps 2a, 2b. The manufacturing process temperature at which semiconductor elements 1, 1', and 20 are fixed to the target substrate 51 typically follows the melting point of Sn in the conductive bumps 2a and 2b to avoid excessively high temperatures damaging the semiconductor elements 1, 1', and 20. Therefore, if there is an excess of Au-Sn intermetallic compound that does not melt at the manufacturing process temperature during the manufacturing process, it will hinder the stable fixation of semiconductor elements 1, 1', and 20 to the target substrate 51. Furthermore, since Au-Sn intermetallic compounds are brittle materials, the presence of excess Au-Sn intermetallic compound in the conductive bumps can easily lead to structural defects, potentially reducing the reliability of the semiconductor elements or the manufacturing process.

[0037] In another embodiment, the conductive bumps and electrodes of the semiconductor device do not contain Au, but the conductive connection pad of the target substrate does contain Au. Specifically, the conductive connection pad has multiple metal layers stacked on top of each other, and the outermost layer of these metal layers, i.e., the layer in direct contact with the conductive bump, is an Au layer. Such a configuration can be used for semiconductor devices 1, 1', and 20 in any one of the embodiments described above, i.e., the conductive bumps 2a, 2b and electrodes 3a, 3b do not contain Au, but the conductive connection pad 52 of the target substrates 50, 51 contains Au. The Au in the conductive connection pad can, on the one hand, prevent oxidation of the material beneath it, and on the other hand, it can form a high-melting-point connection layer between the conductive connection pad and the conductive bump by forming an intermetallic compound with other metals in the conductive bump, such as Sn.

[0038] In another embodiment, the electrodes of the semiconductor device have multiple metal layers stacked on top of each other, with the outermost layer of these metal layers, i.e., the layer in direct contact with the conductive bump, being a thin Au layer. Such a configuration can be used for semiconductor devices 1, 1', and 20 in any one of the embodiments described above, i.e., electrodes 3a and 3b include a single thin Au layer. The thin Au layer can prevent oxidation of the other metal layers beneath it and is not thick enough to generate an excess Au-Sn intermetallic compound with the conductive bump. The electrode structure, along the direction from the semiconductor device to the conductive bump, is, for example, a Cr / Ni / Au stacked layer, a Cr / Ni / Pt / Au stacked layer, a Cr / Al / Ni / Pt / Au stacked layer, a Cr / Ti / Al / Ni / Pt / Au stacked layer, a Cr / Al / Cr / Pt / Au stacked layer, etc. In the cross-sectional view of the semiconductor device (e.g., Figures 2B, 2C, 2E, and 9B), to achieve the antioxidant effect, the thickness of the thin Au layer needs to be greater than 50 angstroms (Å), for example, 250 angstroms and 125 angstroms. Conversely, to avoid the formation of excessive Au-Sn intermetallic compounds, the thickness of the thin Au layer needs to be less than 500 angstroms. When the total electrode thickness is between 3000 angstroms and 5000 angstroms, the ratio of the thin Au layer thickness to the electrode thickness is between 0.01 and 0.16, for example, 0.04 and 0.07. Even if the thin Au layer forms an Au-Sn intermetallic compound with Sn, this Au-Sn intermetallic compound is usually thin and does not completely cover the electrode. For example, this thin Au-Sn intermetallic compound has a thickness of less than 2000 angstroms and is scattered or discontinuously distributed at the boundary between the electrode and the conductive bump, and does not interfere with the fixation of the semiconductor device to the target substrate. Also, even if a thin Au layer is used, the Au may still be scattered in the region of the conductive bump that eventually separates from the electrode.

[0039] While preferred embodiments of the Disclosure have been described above, the Disclosure is not limited to these embodiments, and any modification of the Disclosure, as long as it does not deviate from the spirit of the Disclosure, falls within the technical scope of the Disclosure. [Explanation of symbols]

[0040] 1, 1', 20 Semiconductor devices 2, 2a, 2b Conductive bumps 3, 3a, 3b electrode 4 Adhesive structure 5a First hole 5b Second hole 6a First recess 6b Second recess 7, 8 particles 10 circuit boards 11 First Semiconductor Layer 12 Active layer 13 Second Semiconductor Layer 14 Semiconductor Stack Layers 15 Protective layer 16 flat platform 17 Lower surface 18 areas 19 Outermost edge 21, 21a, 21b top 22, 22a, 22b outermost surface 23a First bonding pad 23b Second bonding pad 24a, 24b top surface 30 Carriers (mounting units) 31 Mounting plate 32 Adhesive layer 33 areas 34 Indentations 40 Pickup Tools 41 Pickup section 50, 51 Target substrate 52 Conductive connection pads 53 Bonding layer 80, 84 Adhesive 81, 83 Resin 82 Conductive particles 151 Top surface 521 Side surface 1000, 1001, 1001', 2000 semiconductor element array θ1, θ2 included angle D distance H1, H2, H3, H4, H5 Thickness L1, L2, L3 laser energy W1, W2, W3, W4 width

Claims

1. A semiconductor device, It includes a semiconductor stack layer, a protective layer, electrodes and conductive bumps, The aforementioned semiconductor stack layer is First semiconductor layer; A second semiconductor layer located on the first semiconductor layer and having a top surface; and The second semiconductor layer includes a groove that penetrates the second semiconductor layer, The protective layer is located on the semiconductor stack layer and has an uppermost surface. The electrode is located on the first semiconductor layer and has a first upper surface. The aforementioned conductive bump is A first portion that is filled into the groove and connected to the electrode; and The second semiconductor layer includes a second portion located on the top surface of the second semiconductor layer, A semiconductor element wherein the conductive bump has an outermost surface, and the outermost surface has an outwardly protruding arc shape.

2. A semiconductor device according to claim 1, A semiconductor device further comprising a plurality of particles discretely distributed within the conductive bump.

3. A semiconductor device according to claim 2, A semiconductor device wherein the material of the plurality of particles is partially the same as the material of the electrode, and different from the material of the conductive bump.

4. A semiconductor device according to claim 1, A semiconductor element having a recess in the electrode and a conductive bump filling the recess.

5. A semiconductor device according to claim 1, A semiconductor element in which the conductive bump has a substantially rectangular shape in the top view.

6. A semiconductor device according to claim 1, A semiconductor element further comprising the electrode, the conductive bump, and an adhesive located on the protective layer.

7. A semiconductor device according to claim 1, A semiconductor element in which the outermost surface is not parallel to the electrode.

8. A semiconductor device according to claim 1, The electrode is a semiconductor device having multiple metal layers stacked on top of each other.

9. A semiconductor device according to claim 1, A semiconductor device in which the electrode and the conductive bump are made of different materials.

10. A semiconductor device according to claim 1, The electrode material is a semiconductor element that does not contain gold.

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