Semiconductor device and manufacturing method thereof
Patent Information
- Application Number
- JP2022207017
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-05-20
- Filing Date
- 2022-12-23
- Publication Date
- 2026-01-06
Smart Images
Figure 00000000_0000_ABST
Abstract
Description
[Technical Field]
[0001] This patent document relates to memory circuits or devices and their applications in semiconductor devices. [Background technology]
[0002] In recent years, with the miniaturization, low power consumption, high performance, and diversification of electronic devices, there has been a demand for semiconductor devices capable of storing information in various electronic devices such as computers and portable communication devices, and research into this field is ongoing. Among these semiconductor devices are those that can store data by utilizing the property of switching between different resistance states depending on the applied voltage or current, such as resistive random access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM®), magnetic random access memory (MRAM), and electronic fuses (E-fuses). Summary of the Invention [Problem to be solved by the invention]
[0003] The problem to be solved by the embodiments of the present invention is to provide a semiconductor device and a manufacturing method thereof, in which an electrode layer around a variable resistance layer is formed of a Thickness Dependent Metal-Insulator Transition (TDMIT) material that exhibits different resistance depending on the thickness, and atoms of the TDMIT material are redeposited on the sidewalls of the variable resistance layer during a patterning process, and the resulting material is used as a sidewall protection layer, thereby lowering the Shunt Fail Rate (SFR) due to bypass current and shortening the turn-around time (TAT) of the process, and significantly reducing the number of IBEs for removing the redeposited material and the sidewall process for protecting the variable resistance layer. [Means for solving the problem]
[0004] A semiconductor device according to one embodiment of the present invention for solving the above problems may include a first wiring, a second wiring arranged on the first wiring at a distance from the first wiring, a variable resistance layer arranged between the first wiring and the second wiring, and an electrode layer including a thickness-dependent metal-insulator transition (TDMIT) material that exhibits resistance that varies depending on the thickness, and arranged at least either between the first wiring and the variable resistance layer or between the variable resistance layer and the second wiring.
[0005] In addition, a method for manufacturing a semiconductor device according to an embodiment of the present invention for solving the above problems may include the steps of forming a Thickness Dependent Metal-Insulator Transition (TDMIT) material layer on a substrate, the TDMIT material layer exhibiting resistance that varies depending on its thickness, forming a variable resistance layer, and performing a patterning process to form the TDMIT material layer and the variable resistance layer as an electrode layer and a variable resistance layer pattern, respectively. [Effects of the Invention]
[0006] According to the semiconductor device and the manufacturing method thereof according to the above-described embodiments of the present invention, the electrode layer around the variable resistance layer is formed of a TDMIT material, and during the patterning process, atoms of the TDMIT material are redeposited on the sidewalls of the variable resistance layer, and this material is used as a sidewall protection layer. This makes it possible to lower the SFR and shorten the TAT of the process, and also to substantially eliminate the need for multiple IBEs to remove the redeposited material and the sidewall process for protecting the variable resistance layer. [Brief explanation of the drawings]
[0007] [Figure 1A] 1A and 1B are diagrams illustrating a semiconductor device according to an embodiment of the present invention. [Figure 1B] 1A and 1B are diagrams illustrating a semiconductor device according to an embodiment of the present invention. [Figure 2A] 1A to 1C are cross-sectional views illustrating steps in a method for forming a semiconductor device according to an embodiment of the present invention. [Figure 2B] 1A to 1C are cross-sectional views illustrating steps in a method for forming a semiconductor device according to an embodiment of the present invention. [Figure 2C] 1A to 1C are cross-sectional views illustrating steps in a method for forming a semiconductor device according to an embodiment of the present invention. [Figure 2D] 1A to 1C are cross-sectional views illustrating steps in a method for forming a semiconductor device according to an embodiment of the present invention. [Figure 3A] 10A to 10C are cross-sectional views illustrating steps in a method for forming a semiconductor device according to another embodiment of the present invention. [Figure 3B] 10A to 10C are cross-sectional views illustrating steps in a method for forming a semiconductor device according to another embodiment of the present invention. [Figure 3C] 10A to 10C are cross-sectional views illustrating steps in a method for forming a semiconductor device according to another embodiment of the present invention. [Figure 3D] 10A to 10C are cross-sectional views illustrating steps in a method for forming a semiconductor device according to another embodiment of the present invention. [Figure 3E] 10A to 10C are cross-sectional views illustrating steps in a method for forming a semiconductor device according to another embodiment of the present invention. [Figure 4A] 10A to 10C are cross-sectional views illustrating steps in a method for forming a semiconductor device according to another embodiment of the present invention. [Figure 4B] 10A to 10C are cross-sectional views illustrating steps in a method for forming a semiconductor device according to another embodiment of the present invention. [Figure 4C] 10A to 10C are cross-sectional views illustrating steps in a method for forming a semiconductor device according to another embodiment of the present invention. [Figure 5A] 10A to 10C are cross-sectional views illustrating steps in a method for forming a semiconductor device according to another embodiment of the present invention. [Figure 5B] 10A to 10C are cross-sectional views illustrating steps in a method for forming a semiconductor device according to another embodiment of the present invention. [Figure 5C] 10A to 10C are cross-sectional views illustrating steps in a method for forming a semiconductor device according to another embodiment of the present invention. [Figure 5D]10A to 10C are cross-sectional views illustrating steps in a method for forming a semiconductor device according to another embodiment of the present invention. [Figure 6A] 10A to 10C are cross-sectional views illustrating steps in a method for forming a semiconductor device according to another embodiment of the present invention. [Figure 6B] 10A to 10C are cross-sectional views illustrating steps in a method for forming a semiconductor device according to another embodiment of the present invention. [Figure 6C] 10A to 10C are cross-sectional views illustrating steps in a method for forming a semiconductor device according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION
[0008] Various embodiments will now be described in detail with reference to the accompanying drawings.
[0009] The drawings are not necessarily drawn to scale, and in some instances, the proportions of at least some of the structures depicted in the drawings may be exaggerated to clearly illustrate features of the embodiments. When the drawings or detailed description disclose a multilayer structure having two or more layers, the relative positions and order of the layers as shown reflect a particular embodiment only and are not intended to limit the scope of the present invention; the relative positions and order of the layers may vary. Furthermore, the drawings or detailed description of a multilayer structure may not reflect all layers present in a particular multilayer structure (e.g., one or more additional layers may exist between two layers shown). For example, when a first layer is shown on a second layer or on a substrate in a multilayer structure in the drawings or detailed description, it may not only represent that the first layer can be formed directly on the second layer or on the substrate, but also represent that one or more other layers may exist between the first and second layers or between the first layer and the substrate.
[0010] 1A and 1B are diagrams showing a semiconductor device according to one embodiment of the present invention, where Fig. 1A is a perspective view and Fig. 1B is a cross-sectional view taken along line AA' in Fig. 1A.
[0011] As shown in Figures 1A and 1B, the semiconductor device of this embodiment can have a cross-point structure formed on a substrate 100, including a first wiring 110 extending in a first direction, a second wiring 130 located on the first wiring 110 and extending in a second direction intersecting the first direction, and memory cells 120 arranged at each intersection between the first wiring 110 and the second wiring 130.
[0012] The substrate 100 may include a semiconductor material, such as silicon, etc. A desired substructure (not shown) may be formed within the substrate 100. For example, the substructure may include a driving circuit (not shown) electrically connected to control the first wiring 110 and / or the second wiring 130 formed on the substrate 100.
[0013] The first interconnection 110 and the second interconnection 130 are connected to the memory cell 120 and can transmit a voltage or current to the memory cell 130 to drive the memory cell 120. One of the first interconnection 110 and the second interconnection 130 can function as a word line, and the other can function as a bit line. The first interconnection 110 and the second interconnection 130 can have a single-layer structure or a multi-layer structure including a conductive material. Examples of the conductive material can include, but are not limited to, a metal, a metal nitride, a conductive carbon material, or a combination thereof. For example, the first interconnect 110 and the second interconnect 130 may include tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), tungsten nitride (WN), tungsten silicide (WSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbon nitride (SiCN), or a combination thereof.
[0014] The memory cells 120 may be arranged in a matrix form along the first and second directions so as to overlap the intersection region between the first wiring 110 and the second wiring 130. In this embodiment, the memory cells 120 have a size equal to or smaller than the intersection region between the first wiring 110 and the second wiring 130, but in other embodiments, the memory cells 120 may have a size larger than this intersection region.
[0015] The spaces between the first interconnect 110, the second interconnect 130, and the memory cell 120 may be filled with an insulating material.
[0016] The memory cell 120 may include a stacked structure, which may include a lower electrode layer 121 , a selection element layer 122 , an intermediate electrode layer 123 , a variable resistance layer 124 , a sidewall protection layer 125 , and an upper electrode layer 126 .
[0017] The resistance variable layer 124 can store different data by switching between different resistance states depending on a voltage or current applied across its upper and lower ends. The resistance variable layer 124 may include a material used in RRAM, PRAM, FRAM, MRAM, etc., such as a material having variable resistance characteristics used in RRAM, PRAM, FRAM, MRAM, etc. The resistance variable layer 124 may include a metal oxide such as a transition metal oxide or a perovskite-based material, a phase change material such as a chalcogenide-based material, a ferroelectric material, a ferromagnetic material, etc., used in RRAM, PRAM, FRAM, MRAM, etc. The resistance variable layer 124 may have a single-layer structure or a multi-layer structure that exhibits variable resistance characteristics by combining two or more layers. In one embodiment, the resistance variable layer 124 may include a magnetic tunnel junction (MTJ) structure. However, the present embodiment is not limited thereto, and the memory cell 120 may include other memory layers instead of the variable resistance layer 124 that can store different data in various ways.
[0018] The selection element layer 122 can function to control the approach to the variable resistance layer 124. To this end, the selection element layer 122 can have a characteristic of adjusting the current flow according to the magnitude of the applied voltage or current, i.e., the selection element layer 122 can have a characteristic of barely allowing current to flow when the magnitude of the applied voltage or current is equal to or less than a predetermined threshold, and allowing current to flow that rapidly increases substantially in proportion to the magnitude of the applied voltage or current when the magnitude exceeds the predetermined threshold. The selection element layer 122 can be made of MIT (Metal Insulator Transition) elements such as NbO2, TiO2, VO2, WO2, ZrO2 (Y2O3), Bi2O3-BaO, (La2O3) x (CeO2) 1-x MIEC (Mixed Ion-Electron Conducting) elements such as those described above, OTS (Ovonic Threshold Switching) elements including chalcogenide-based materials such as Ge2Sb2Te5, As2Te3, As2, and As2Se3, and tunneling insulating layers made of various insulating materials such as silicon oxide, silicon nitride, and metal oxide, and having a thin thickness to allow electron tunneling under a specific voltage or current, may be used. The selection element layer 122 may have a single layer structure or a multi-layer structure that combines two or more layers to exhibit selection element characteristics.
[0019] In one embodiment, the select device layer 122 may be configured to perform a threshold switching operation. The threshold switching operation may refer to the select device layer 122 sequentially achieving a turn-on and turn-off state as follows when an external voltage is applied to the select device layer 122 in a sweeping manner. The turn-on state may be achieved by a phenomenon in which the operating current increases nonlinearly above a predetermined first threshold voltage when the absolute value of the voltage applied to the select device layer 122 is gradually increased from an initial state. The turn-off state may be achieved by a phenomenon in which the operating current decreases nonlinearly below a predetermined second threshold voltage when the absolute value of the voltage applied to the select device layer 122 is gradually decreased again from a turned-on state.
[0020] In one embodiment, the select element layer 122 may include an insulating material doped with a dopant. In one embodiment, the select element layer 122 may include an oxide, nitride, oxynitride, or a combination thereof doped with a dopant. For example, the oxide, nitride, oxynitride, or a combination thereof may include silicon oxide, titanium oxide, aluminum oxide, tungsten oxide, hafnium oxide, tantalum oxide, niobium oxide, silicon nitride, titanium nitride, aluminum nitride, tungsten nitride, hafnium nitride, tantalum nitride, niobium nitride, silicon oxynitride, titanium oxynitride, aluminum oxynitride, tungsten oxynitride, hafnium oxynitride, tantalum oxynitride, niobium oxynitride, or a combination thereof. The dopant doped into the select element layer 122 may include an n-type or p-type dopant and may be introduced by an ion implantation process. The dopant may include, for example, one or more selected from the group consisting of boron (B), nitrogen (N), carbon (C), phosphorus (P), arsenic (As), aluminum (Al), silicon (Si), and germanium (Ge). As an example, the selection element layer 122 may include silicon oxide doped with As or Ge.
[0021] The select element layer 122 can perform a threshold switching operation through a doping region formed in the material layer for the select element layer 122. Therefore, the size of the threshold switching operation region can be controlled by the distribution area of the dopant. The dopant can form trap sites for conductive carriers in the select element layer 122. These trap sites can achieve threshold switching operation characteristics by capturing or inverting conductive carriers moving between the middle electrode layer 123 and the upper electrode layer 125 in response to the application of an external voltage.
[0022] The lower electrode layer 121 may be formed between the first wiring 110 and the selection element layer 122. The lower electrode layer 121 is located at the bottom of the memory cell 120 and electrically connected to the first wiring 110, and may function as a current or voltage transmission path between the first wiring 110 and the memory cell 120. The intermediate electrode layer 123 is located between the selection element layer 122 and the resistance variable layer 124 and may serve to physically separate them while electrically connecting them. The upper electrode layer 126 is located at the top of the memory cell 120 and may function as a current or voltage transmission path between the second wiring 130 and the memory cell 120. At least one of the lower electrode layer 121, the intermediate electrode layer 123, and the upper electrode layer 126 may be omitted.
[0023] In this embodiment, the electrode layers around the resistance variable layer 124 among the lower electrode layer 121, the intermediate electrode layer 123, and the upper electrode layer 126 may contain a thickness-dependent metal-insulator transition (TDMIT) material that exhibits different resistance depending on the thickness. That is, in FIG. 1B, one or both of the intermediate electrode layer 123 and the upper electrode layer 126 located above and below the resistance variable layer 124 may contain the TDMIT material.
[0024] Typically, the electrode around the variable resistance layer 124, e.g., the intermediate electrode, may have a single-layer structure or a multi-layer structure including various conductive materials, such as metals, metal nitrides, conductive carbon materials, or combinations thereof. For example, the intermediate electrode may include tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), tungsten nitride (WN), tungsten silicide (WSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbon nitride (SiCN), or combinations thereof, such as TiN. When the intermediate electrode is patterned, TiN or the like forming the intermediate electrode may be redeposited on the sidewall of the variable resistance layer 124, and the redeposited material may cause a shunt fail of the variable resistance layer 124. Therefore, several IBE (Ion Beam Etch) processes must be performed to remove the redeposited material, and a sidewall process must be performed to protect the variable resistance layer 124, resulting in a problem of reduced process efficiency.
[0025] To solve this problem, in this embodiment, the electrodes around the resistance variable layer 124, i.e., the intermediate electrode layer 123 and / or the upper electrode layer 126, are formed of a TDMIT material, and during the patterning process, atoms of the TDMIT material are redeposited on the sidewalls of the resistance variable layer 124 to form the sidewall protection layer 125.
[0026] The middle electrode layer 123 and / or the top electrode layer 126 may have a thickness that allows the TDMIT material to exhibit conductivity.
[0027] The sidewall protection layer 125 may have a thickness that allows the TDMIT material to exhibit insulating properties.
[0028] The thickness of the intermediate electrode layer 123 and / or the top electrode layer 126 can be greater than the thickness of the sidewall protection layer 125 .
[0029] TDMIT material is an MIT material that exhibits a resistance that varies with thickness. For example, the resistance of TDMIT material can change nonlinearly with thickness. MIT material refers to a material whose electrical resistance decreases rapidly when it transitions from an insulator to a metal due to external stimuli such as temperature and an electric field. The decrease is about 10 4 -10 5 This is an extremely large value, about 100 times larger than the resistance of an insulating material. The MIT phenomenon refers to a phenomenon in which an insulating material changes from insulating to metallic properties at a specific temperature or electric field. A TDMIT material refers to a material among such MIT materials whose resistance changes depending on its thickness. Examples of TDMIT materials that can be used in this embodiment include, but are not limited to, at least one of V2O3, LaNiO3, SrRuO3, NdNiO3, PrNiO3, SnO2:Sb, or a combination thereof. Here, SnO2:Sb refers to SnO2 doped with Sb. Such materials may exhibit a characteristic in which their resistance increases rapidly when they are thin.
[0030] In this embodiment, the intermediate electrode layer 123 and / or the upper electrode layer 126 may be formed to a thickness that allows the TDMIT material to exhibit conductivity. That is, the thickness of the intermediate electrode layer 123 and / or the upper electrode layer 126 may be selected depending on the TDMIT material contained therein. When patterning the intermediate electrode layer 123 and / or the upper electrode layer 126, the TDMIT material may be redeposited on the sidewalls of the resistance variable layer 124. The patterning of the intermediate electrode layer 123 and / or the upper electrode layer 126 is generally performed by an IBE process, and the redeposited layer formed by this IBE process may be formed to a thin thickness. In this way, the sidewall protection layer 125 containing the redeposited TDMIT material formed on the sidewalls of the resistance variable layer 124 is formed to a thin thickness, and therefore, may exhibit insulating properties. Therefore, according to this embodiment, the electrode around the resistance variable layer 124 may exhibit conductivity, and the sidewall protection layer 125 formed on the sidewalls of the resistance variable layer 124 may be adjusted to exhibit insulating properties. The insulating sidewall protective layer 125 can prevent or reduce shunt failure of the resistance variable layer 124 due to bypass current. Furthermore, it can significantly reduce the number of IBE processes for removing redeposition materials and the sidewall process for protecting the resistance variable layer 124, which have been required in the past, thereby improving process efficiency and simplification. Furthermore, the sidewall protective layer 125 is formed by redeposition that naturally occurs during patterning of the middle electrode layer 123 and / or the upper electrode layer 126, rather than by a separate formation process, which can provide an advantageous effect in terms of process efficiency.
[0031] The lower electrode layer 121 that is not in contact with the variable resistance layer 124, and the intermediate electrode layer 123 or upper electrode layer 126 that does not contain the TDMIT material may have a single-layer structure or a multi-layer structure containing various conductive materials, such as metals, metal nitrides, conductive carbon materials, or combinations thereof. For example, the bottom electrode layer 121 may include tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), tungsten nitride (WN), tungsten silicide (WSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbon nitride (SiCN), or a combination thereof.
[0032] In this embodiment, the memory cell 120 includes a lower electrode layer 121, a selection element layer 122, an intermediate electrode layer 123, a variable resistance layer 124, a sidewall protection layer 125, and an upper electrode layer 126, which are sequentially stacked. However, as long as the memory cell structure 120 has data storage characteristics, various modifications can be made. For example, at least one of the lower electrode layer 121, the intermediate electrode layer 123, and the upper electrode layer 126 can be omitted. For example, if the lower electrode layer 121 is omitted, the first wiring 110 can function as the lower electrode layer 121 instead of the omitted lower electrode layer 121. If the upper electrode layer 126 is omitted, the second wiring 130 can function as the upper electrode layer 126 instead of the omitted upper electrode layer 126. In addition, the positions of the variable resistance layer 124 and the selection element layer 122 can be interchanged. Furthermore, in addition to the layers (121 to 126), the memory cell 120 may further include one or more layers (not shown) for improving the characteristics of the memory cell 120 or for improving the process.
[0033] The plurality of memory cells 120 thus formed may be spaced apart from one another at regular intervals, with trenches formed therebetween. The trenches between the plurality of memory cells 120 may have a height-to-width (H / W) aspect ratio within a range of, for example, about 1:1 to 40:1, about 10:1 to 40:1, about 10:1 to 20:1, about 5:1 to 10:1, about 10:1 to 15:1, about 1:1 to 25:1, about 1:1 to 30:1, about 1:1 to 35:1, about 1:1 to 45:1, or about 1:1 to 40:1.
[0034] In some embodiments, such trenches may have sidewalls that are substantially perpendicular to the top surface of the substrate 100. Also, in one embodiment, adjacent trenches may be spaced substantially equidistant from one another, but in other embodiments, the spacing between adjacent trenches may vary.
[0035] Although the present embodiment has been described with respect to a single layer of cross-point structures, two or more layers of cross-point structures may be stacked vertically.
[0036] Next, one embodiment of a method for manufacturing the semiconductor device of the present embodiment will be described with reference to Figures 2A to 2D. Detailed description of the content similar to the embodiment of Figures 1A and 1B will be omitted.
[0037] 2A to 2D are cross-sectional views illustrating steps in a method for forming a semiconductor device according to one embodiment of the present invention.
[0038] The first wiring 210 may be formed on a substrate 200 on which a predetermined substructure (not shown) is formed. The first wiring 210 may be formed by forming a conductive layer for forming the first wiring 210 on the substrate 200 and then etching the conductive layer using a line-shaped mask pattern extending in a first direction. The first wiring 210 may have a single-layer structure or a multi-layer structure including a conductive material.
[0039] Next, a lower electrode layer material layer 221A, a selection device layer material layer 222A, and an intermediate electrode layer material layer 223A may be formed on the first wiring 210.
[0040] The lower electrode material layer 221A may have a single layer structure or a multi-layer structure including various conductive materials, such as metals, metal nitrides, conductive carbon materials, or combinations thereof.
[0041] The material layer 222A for the selection device layer may include an MIT material, an MIEC material, an OTS material including a chalcogenide-based material, a tunneling insulating material, a doped insulating material, or the like.
[0042] The intermediate electrode layer material layer 223A may include a TDMIT material, such as, but not limited to, at least one of V2O3, LaNiO3, SrRuO3, NdNiO3, PrNiO3, SnO2:Sb, or a combination thereof.
[0043] The intermediate electrode layer material layer 223A may be formed to a thickness that allows the TDMIT material to exhibit conductivity, and thus the thickness of the intermediate electrode layer material layer 223A may be determined depending on the TDMIT material included therein.
[0044] As shown in FIG. 2B, a variable resistance layer material layer 224A can be formed on the structure of FIG. 2A.
[0045] The variable resistance layer material layer 224A may include an MTJ structure.
[0046] As shown in FIG. 2C, the material layer 224A for the variable resistance layer, the material layer 223A for the intermediate electrode layer, the material layer 222A for the selection element layer, and the material layer 221A for the lower electrode layer can be sequentially etched using a patterning process using a mask pattern (not shown), thereby forming the lower electrode layer 221, the selection element layer 222, the intermediate electrode layer 223, the variable resistance layer 224, and the sidewall protection layer 225.
[0047] Here, the patterning process can be performed by, for example, an IBE process.
[0048] During the patterning process, atoms of the TDMIT material are redeposited on the sidewalls of the resistance variable layer 224 by etching the material layer 223A for the intermediate electrode layer, thereby forming the sidewall protection layer 225.
[0049] The sidewall protection layer 225 may be formed to a thickness that allows the TDMIT material to exhibit insulating properties. Thus, the thickness of the sidewall protection layer 225 may be determined depending on the TDMIT material included. Since the material layer redeposited by the IBE process is formed to a thin thickness, the sidewall protection layer 225 may be formed to a thickness that allows the TDMIT material to exhibit insulating properties.
[0050] The sidewall protection layer 225 can significantly reduce the SFR and process TAT of the variable resistance layer 224, and can omit an additional process for removing redeposited materials.
[0051] As shown in FIG. 2D, a top electrode layer 226 and a second interconnect 230 can be formed on the structure of FIG. 2C.
[0052] The upper electrode layer 226 may have a single layer structure or a multi-layer structure including various conductive materials, such as metal, metal nitride, conductive carbon material, or a combination thereof. The upper electrode layer 226 may be formed by forming a material layer for forming the upper electrode layer 226 and then etching the material layer using a mask pattern.
[0053] In this embodiment, the upper electrode layer 226 may be patterned separately from the variable resistance layer 224, or in other embodiments, may be patterned simultaneously with the variable resistance layer 224. For example, after the step shown in FIG. 2B , a material layer for the upper electrode layer 226 may be formed on the material layer for the variable resistance layer 224A, and then the material layer for the upper electrode layer 226, the material layer for the variable resistance layer 224, the material layer for the intermediate electrode layer 223A, the material layer for the selection element layer 222A, and the material layer for the lower electrode layer 221A may be sequentially etched using a mask pattern (not shown), thereby forming the lower electrode layer 221, the selection element layer 222, the intermediate electrode layer 223, the variable resistance layer 224, the sidewall protection layer 225, and the upper electrode layer 226.
[0054] The second wiring 230 may be formed by forming a conductive layer for forming the second wiring 230 and then etching the conductive layer using a line-shaped mask pattern extending in the second direction. The second wiring 230 may have a single-layer structure or a multi-layer structure including a conductive material.
[0055] 2A to 2D may include a substrate 200, a first interconnection 210, a memory cell 220, and a second interconnection 230. The memory cell 220 may include a lower electrode layer 221, a selection element layer 222, an intermediate electrode layer 223, a variable resistance layer 224, a sidewall protection layer 225, and an upper electrode layer 226. The intermediate electrode layer 223 may include a TDMIT material and may be formed to a thickness that allows the TDMIT material to exhibit conductivity. The sidewall protection layer 225 may include a redeposited TDMIT material derived from the intermediate electrode layer 223 and may be formed to a thickness that allows the TDMIT material to exhibit insulation.
[0056] According to this embodiment, the insulating sidewall protection layer 225 is formed on the sidewall of the variable resistance layer 224 by redeposition, which can reduce shunt failure due to bypass current, shorten the process TAT, and significantly reduce the number of IBE processes for removing redeposition materials and the sidewall process for protecting the variable resistance layer 224.
[0057] In this embodiment, the middle electrode layer 223 is formed of a TDMIT material, but in other embodiments, the top electrode layer 226, or both the middle electrode layer 223 and the top electrode layer 226, may be formed of a TDMIT material.
[0058] Furthermore, although the semiconductor device according to this embodiment includes all of the lower electrode layer 221, the intermediate electrode layer 223, and the upper electrode layer 226, in other embodiments, at least one of the upper electrode layer 226 or the lower electrode layer 221 may be omitted.
[0059] In addition, although the variable resistance layer 224 is located on the upper side of the selection element layer 222 in this embodiment, the variable resistance layer 224 may be located on the lower side of the selection element layer 222 in other embodiments.
[0060] The substrate 200, first wiring 210, memory cell 220, lower electrode layer 221, selection element layer 222, intermediate electrode layer 223, variable resistance layer 224, sidewall protection layer 225, upper electrode layer 226, and second wiring 230 shown in Figure 2D can correspond to the substrate 100, first wiring 110, memory cell 120, lower electrode layer 121, selection element layer 122, intermediate electrode layer 123, variable resistance layer 124, sidewall protection layer 125, upper electrode layer 126, and second wiring 130 shown in Figure 1B, respectively.
[0061] 3A to 3E are cross-sectional views illustrating steps in a method for forming a semiconductor device according to another embodiment of the present invention.
[0062] 3A to 3E are similar to the embodiment shown in FIGS. 2A to 2D, except that a lower electrode contact (see reference numeral 340 in FIG. 3E) and an upper electrode contact (see reference numeral 350 in FIG. 3E) are further formed. Detailed descriptions of the embodiment shown in FIGS. 3A to 3E that are similar to those described in relation to the embodiment shown in FIGS. 2A to 2D will be omitted.
[0063] As shown in FIG. 3A, an interlayer insulating layer (not shown) having a trench is formed on a substrate 300 on which a predetermined substructure (not shown) is formed, and a conductive layer for forming a first wiring 310 is formed in the trench. After that, the first wiring 310 can be formed by etching using a line-shaped mask pattern extending in a first direction.
[0064] Next, an interlayer insulating layer 301 having a hole is formed on the first wiring 310, and then a material layer for a lower electrode contact 340 is formed in the hole, followed by a planarization process to form the lower electrode contact 340.
[0065] The material layer for the bottom electrode contact 340 may have a single layer structure or a multi-layer structure including a metal, a metal nitride, a conductive carbon material, or a combination thereof.
[0066] As shown in FIG. 3B, a material layer 321A for a lower electrode layer, a material layer 322A for a selection device layer, and a material layer 323A for an intermediate electrode layer may be sequentially formed on the interlayer insulating layer 301 and the lower electrode contact 340.
[0067] The intermediate electrode layer material layer 323A may include a TDMIT material, such as, but not limited to, at least one of V2O3, LaNiO3, SrRuO3, NdNiO3, PrNiO3, SnO2:Sb, or a combination thereof.
[0068] The intermediate electrode layer material layer 323A may be formed to a thickness that allows the TDMIT material to exhibit conductivity, and thus, the thickness of the intermediate electrode layer material layer 323A may be determined depending on the TDMIT material included therein.
[0069] As shown in FIG. 3C, a variable resistance layer material layer 324A can be formed on the structure of FIG. 3B.
[0070] As shown in FIG. 3D, the material layer 324A for the variable resistance layer, the material layer 323A for the intermediate electrode layer, the material layer 322A for the selection element layer, and the material layer 321A for the lower electrode layer can be sequentially etched using a patterning process using a mask pattern (not shown), thereby forming the lower electrode layer 321, the selection element layer 322, the intermediate electrode layer 323, the variable resistance layer 324, and the sidewall protection layer 325.
[0071] Here, the patterning process can be performed by, for example, an IBE process.
[0072] During the patterning process, the TDMIT material is re-deposited on the sidewalls of the resistance variable layer 324 by etching the intermediate electrode material layer 323A, thereby forming the sidewall protection layer 325.
[0073] The sidewall protection layer 325 may be formed to a thickness that allows the TDMIT material to exhibit insulating properties. Thus, the thickness of the sidewall protection layer 325 may be determined depending on the TDMIT material included. Since the material layer redeposited by the IBE process is formed to a thin thickness, the sidewall protection layer 325 may be formed to a thickness that allows the TDMIT material to exhibit insulating properties.
[0074] As shown in Figure 3E, a top electrode layer 326, a top electrode contact 350, and a second interconnect 330 can be formed on the structure of Figure 3D.
[0075] The upper electrode contact 350 can be formed by forming an interlayer insulating layer 302 having a hole on the structure in which the upper electrode layer 326 is formed, forming a material layer for the upper electrode contact 350 in the hole, and then performing a planarization process.
[0076] Alternatively, in another embodiment, an interlayer insulating layer 302 having holes may be formed on the structure of FIG. 3D, and a material layer for the upper electrode layer 326 and the upper electrode contact 350 may be formed in the holes, followed by a planarization process to form the upper electrode layer 326 and the upper electrode contact 350.
[0077] The material layer for the bottom electrode contact 340 may have a single layer structure or a multi-layer structure including a metal, a metal nitride, a conductive carbon material, or a combination thereof.
[0078] 3A to 3E may include a substrate 300, a first interconnection 310, a bottom electrode contact 340, a memory cell 320, a top electrode contact 350, and a second interconnection 330. The memory cell 320 may include a bottom electrode layer 321, a selection element layer 322, an intermediate electrode layer 323, a variable resistance layer 324, a sidewall protection layer 325, and a top electrode layer 326. The intermediate electrode layer 323 may include a TDMIT material and may be formed to a thickness that allows the TDMIT material to exhibit conductivity. The sidewall protection layer 325 may include a redeposited TDMIT material derived from the intermediate electrode layer 323 and may be formed to a thickness that allows the TDMIT material to exhibit insulation.
[0079] According to this embodiment, the insulating sidewall protection layer 325 is formed on the sidewall of the variable resistance layer 324 by redeposition, which can reduce shunt failure due to bypass current, shorten the process TAT, and significantly reduce the number of IBE processes for removing redeposition materials and the sidewall process for protecting the variable resistance layer 324.
[0080] In this embodiment, the middle electrode layer 323 is formed of a TDMIT material, but in other embodiments, the top electrode layer 326, or both the middle electrode layer 323 and the top electrode layer 326, may be formed of a TDMIT material.
[0081] Furthermore, although the semiconductor device according to this embodiment includes both the bottom electrode contact 340 and the top electrode contact 350, in other embodiments, at least one of the bottom electrode contact 340 or the top electrode contact 350 may be omitted.
[0082] Furthermore, although the semiconductor device according to this embodiment includes all of the lower electrode layer 321, the intermediate electrode layer 323, and the upper electrode layer 326, in other embodiments, at least one of the upper electrode layer 326 or the lower electrode layer 321 may be omitted.
[0083] In addition, although the variable resistance layer 324 is located on the upper side of the selection element layer 322 in this embodiment, the variable resistance layer 324 may be located on the lower side of the selection element layer 322 in other embodiments.
[0084] The substrate 300, first wiring 310, memory cell 320, lower electrode layer 321, selection element layer 322, intermediate electrode layer 323, variable resistance layer 324, sidewall protection layer 325, upper electrode layer 326, and second wiring 330 shown in Figure 3E can correspond to the substrate 200, first wiring 210, memory cell 220, lower electrode layer 221, selection element layer 222, intermediate electrode layer 223, variable resistance layer 224, sidewall protection layer 225, upper electrode layer 226, and second wiring 230 shown in Figure 2D, and the substrate 100, first wiring 110, memory cell 120, lower electrode layer 121, selection element layer 122, intermediate electrode layer 123, variable resistance layer 124, sidewall protection layer 125, upper electrode layer 126, and second wiring 130 shown in Figure 1B, respectively.
[0085] 4A to 4C are cross-sectional views illustrating steps in a method for forming a semiconductor device according to another embodiment of the present invention.
[0086] Detailed descriptions of content similar to that described in relation to the embodiment shown in FIGS. 2A to 2D will be omitted.
[0087] As shown in FIG. 4A, a first wiring 410 may be formed on a substrate 400 on which a predetermined substructure (not shown) is formed.
[0088] Next, a material layer for a lower electrode layer 421A, a material layer for a selection element layer 422A, a material layer for a middle electrode layer 423A, a material layer for a variable resistance layer 424A, and a material layer for an upper electrode layer 426A may be formed.
[0089] The lower electrode material layer 421A and the intermediate electrode material layer 423A may have a single layer structure or a multi-layer structure including various conductive materials, such as metals, metal nitrides, conductive carbon materials, or combinations thereof.
[0090] The upper electrode layer material layer 426A may include a TDMIT material, such as, but not limited to, at least one of V2O3, LaNiO3, SrRuO3, NdNiO3, PrNiO3, SnO2:Sb, or a combination thereof.
[0091] The upper electrode layer material layer 426A may be formed to a thickness that allows the TDMIT material to exhibit conductivity, and thus the thickness of the upper electrode layer material layer 426A may be determined depending on the TDMIT material included therein.
[0092] As shown in FIG. 4B, a patterning process using a mask pattern (not shown) is performed to sequentially etch the upper electrode layer material layer 426A, the variable resistance layer material layer 424A, the intermediate electrode layer material layer 423A, the selection element layer material layer 422A, and the lower electrode layer material layer 421A, thereby forming the lower electrode layer 421, the selection element layer 422, the intermediate electrode layer 423, the variable resistance layer 424, the sidewall protection layer 425, and the upper electrode layer 426.
[0093] Here, the patterning process can be performed by, for example, an IBE process.
[0094] During the patterning process, the TDMIT material is re-deposited on the sidewalls of the resistance variable layer 424 by etching the upper electrode layer material layer 426A, thereby forming the sidewall protection layer 425.
[0095] The sidewall protection layer 425 may be formed to a thickness that allows the TDMIT material to exhibit insulating properties. Thus, the thickness of the sidewall protection layer 425 may be determined depending on the TDMIT material included. Since the material layer redeposited by the IBE process is formed to a thin thickness, the sidewall protection layer 425 may be formed to a thickness that allows the TDMIT material to exhibit insulating properties.
[0096] The sidewall protection layer 425 can significantly reduce the SFR and process TAT of the variable resistance layer 424, and can eliminate an additional process for removing redeposited materials.
[0097] As shown in FIG. 4C, a second interconnect 430 can be formed on the top electrode layer 426.
[0098] 4A to 4C may include a substrate 400, a first interconnection 410, a memory cell 420, and a second interconnection 430. The memory cell 420 may include a lower electrode layer 421, a selection element layer 422, an intermediate electrode layer 423, a variable resistance layer 424, a sidewall protection layer 425, and an upper electrode layer 426. The upper electrode layer 426 may include a TDMIT material and may be formed to a thickness that allows the TDMIT material to exhibit conductivity. The sidewall protection layer 425 may include a redeposited TDMIT material derived from the upper electrode layer 426 and may be formed to a thickness that allows the TDMIT material to exhibit insulation.
[0099] In this embodiment, the upper electrode layer 426 is formed of a TDMIT material, but in other embodiments, the middle electrode layer 423, or the middle electrode layer 423 and the upper electrode layer 426, may be formed of a TDMIT material.
[0100] Furthermore, although the semiconductor device according to this embodiment includes all of the lower electrode layer 421, the intermediate electrode layer 423, and the upper electrode layer 426, in other embodiments, at least one of the intermediate electrode layer 423 or the lower electrode layer 421 may be omitted.
[0101] In addition, although the variable resistance layer 424 is located on the upper side of the selection element layer 422 in this embodiment, the variable resistance layer 424 may be located on the lower side of the selection element layer 422 in other embodiments.
[0102] The semiconductor device according to the above-described embodiments has a structure in which the selection element layer 122, 222, 322, 422 and the variable resistance layer 124, 224, 324, 424 are stacked above and below the same element to form a high-density cross-point array. However, the embodiments of the present invention can also be applied to a semiconductor device having a structure in which only a variable resistance layer, for example, a magnetic tunnel junction (MTJ), is formed on one element. This will be described with reference to FIGS. 5A to 5D and 6A to 6C.
[0103] 5A to 5D are cross-sectional views illustrating steps in a method for forming a semiconductor device according to another embodiment of the present invention. Detailed descriptions of content similar to the embodiments illustrated in FIGS. 1A and 1B, 2A to 2D, 3A to 3E, and 4A to 4C will be omitted.
[0104] 5D , a semiconductor device according to an embodiment of the present invention may include a first wiring 510 formed on a substrate 500 and extending in a first direction, a second wiring 530 located on the first wiring 510 and extending in a second direction intersecting the first direction, and a variable resistance element 520 disposed at each intersection between the first wiring 510 and the second wiring 530. The variable resistance element 520 may include an MTJ structure including a free layer 504 having a changeable magnetization direction, a fixed layer 506 having a fixed magnetization direction, and a tunnel barrier layer 505 interposed between the free layer 504 and the fixed layer 506.
[0105] The free layer 504, which can store different data by having a changeable magnetization direction, may also be referred to as a storage layer. The free layer 504 may have one of different magnetization directions or one of different electron spin directions, and the resistance value may be changed by switching the polarity of the free layer 504 in the MTJ structure. In some embodiments, the polarity of the free layer 504 is changed or reversed when a voltage or current signal (e.g., a drive current above a certain threshold) is applied to the MTJ structure. By changing the polarity of the free layer 504, the free layer 504 and the fixed layer 506 have different magnetization directions or different electron spin directions, allowing the variable resistance element 500 to store different data or represent different data bits. The magnetization direction of the free layer 504 may be substantially perpendicular to the surfaces of the free layer 504, the tunnel barrier layer 505, and the fixed layer 506. That is, the magnetization direction of the free layer 504 can be substantially parallel to the stacking direction of the free layer 504, the tunnel barrier layer 505, and the fixed layer 506. Therefore, the magnetization direction of the free layer 504 can be changed between a top-to-bottom direction and a bottom-to-top direction. Such a change in the magnetization direction of the free layer 504 can be induced by a spin transfer torque generated by an applied current or voltage.
[0106] The free layer 504 may have a single layer or a multi-layer structure containing a ferromagnetic material. For example, the free layer 504 may include an alloy mainly composed of Fe, Ni, or Co, such as an Fe-Pt alloy, an Fe-Pd alloy, a Co-Pd alloy, a Co-Pt alloy, an Fe-Ni-Pt alloy, a Co-Fe-Pt alloy, a Co-Ni-Pt alloy, or a Co-Fe-B alloy, or may include a metal layer structure, such as a Co / Pt or Co / Pd layer structure.
[0107] The tunnel barrier layer 505 can allow tunneling of electrons during both data read and data write operations. During a write operation to store new data, a high write current flows through the tunnel barrier layer 505, which can change the resistance state of the MTJ to change the magnetization direction of the free layer 504 and write a new data bit. During a read operation, a low read current flows through the tunnel barrier layer 505, which can measure the existing resistance state of the MTJ according to the existing magnetization direction of the free layer 504 without changing the magnetization direction of the free layer 504, thereby reading the data bit stored in the MTJ. The tunnel barrier layer 505 can include an insulating oxide, such as MgO, CaO, SrO, TiO, VO, NbO, Al2O3, TiO2, Ta2O5, RuO2, or BO3.
[0108] The pinned layer 506 can have a fixed magnetization direction, and such fixed magnetization direction does not change while the magnetization direction of the free layer 504 changes. The pinned layer 506 can also be referred to as a reference layer, etc. In some embodiments, the pinned layer 506 can be pinned with a magnetization direction that points from top to bottom. In some embodiments, the pinned layer 506 can be pinned with a magnetization direction that points from bottom to top.
[0109] The pinned layer 506 may have a single layer or a multi-layer structure containing a ferromagnetic material. For example, the pinned layer 506 may include an alloy mainly composed of Fe, Ni, or Co, such as an Fe-Pt alloy, an Fe-Pd alloy, a Co-Pd alloy, a Co-Pt alloy, an Fe-Ni-Pt alloy, a Co-Fe-Pt alloy, a Co-Ni-Pt alloy, or a Co-Fe-B alloy, or may include a laminate structure made of metal, such as a laminate structure of Co / Pt or Co / Pd.
[0110] When a voltage or current is applied to the variable resistance element 520, the magnetization direction of the free layer 504 can be changed by a spin transfer torque. When the magnetization directions of the free layer 504 and the fixed layer 506 are parallel to each other, the variable resistance element 520 can be in a low resistance state, representing, for example, a digital data bit "0." Conversely, when the magnetization directions of the free layer 504 and the fixed layer 506 are antiparallel to each other, the variable resistance element 520 can be in a high resistance state, representing, for example, a digital data bit "1." In some embodiments, the variable resistance element 520 can be configured to store a data bit "1" when the magnetization directions of the free layer 504 and the fixed layer 506 are parallel to each other and to store a data bit "0" when the magnetization directions of the free layer 504 and the fixed layer 506 are antiparallel to each other.
[0111] In addition to the MTJ structure, the variable resistance element 520 may further include layers having various uses for improving the characteristics and process of the MTJ structure. For example, the variable resistance element 520 may further include a bottom electrode layer 501, a buffer layer 502, a bottom layer 503, a spacer layer 507, a magnetic correction layer 508, a capping layer 509, and a sidewall protection layer 511.
[0112] In this embodiment, the lower electrode layer 501 may include a TDMIT material. For example, the lower electrode layer 501 may include at least one of, but is not limited to, V2O3, LaNiO3, SrRuO3, NdNiO3, PrNiO3, SnO2:Sb, or a combination thereof. In addition, the lower electrode layer 501 may be formed to a thickness that allows the TDMIT material to exhibit conductivity.
[0113] The sidewall protective layer 511 may be formed by redepositing a TDMIT material on the sidewall of the variable resistance element 520 when the lower electrode layer 501 is formed. The sidewall protective layer 511 may be formed to a thickness that allows the TDMIT material to exhibit insulating properties. Thus, the thickness of the sidewall protective layer 511 may be determined depending on the TDMIT material included. Typically, the variable resistance element 520 including an MTJ structure is formed by an IBE process, and the material layer redeposited by the IBE process is formed to a thin thickness, so the sidewall protective layer 511 may be formed to a thickness that allows the TDMIT material to exhibit insulating properties.
[0114] The buffer layer 502 is formed under the lower layer 503 to aid in the crystal growth of the layers located above, thereby further improving the perpendicular magnetic anisotropy of the free layer 504. The buffer layer 502 may have a single-layer structure or a multi-layer structure including various conductive materials such as a single metal, a metal alloy, a metal nitride, or a metal oxide. The buffer layer 502 may also be formed of a material that is highly compatible with the lower electrode layer 501 to eliminate the lattice constant mismatch between the lower electrode layer 501 and the lower layer 503. For example, the buffer layer 502 may include tantalum (Ta).
[0115] The lower layer 503 may be in direct contact with the bottom surface of the free layer 1504 below the free layer 504 and may serve to improve the perpendicular magnetic anisotropy of the free layer 504. The lower layer 503 may have a single-layer structure or a multi-layer structure including one or more of a metal, a metal alloy, a metal nitride, or a metal oxide. In one embodiment, the lower layer 503 may have a single-layer structure or a multi-layer structure including a metal nitride. For example, the lower layer 503 may include one or more of TaN, AlN, SiN, TiN, VN, CrN, GaN, GeN, ZrN, NbN, MoN, or HfN.
[0116] The spacer layer 507 is interposed between the pinned layer 506 and the magnetic correction layer 508 to act as a buffer between them and improve the characteristics of the magnetic correction layer 508. The spacer layer 507 may include a noble metal such as Ru.
[0117] The magnetic correction layer 508 can function to cancel or reduce the influence of the stray magnetic field generated by the pinned layer 506. In such a case, the influence of the stray magnetic field generated by the pinned layer 506 on the free layer 504 is reduced, thereby reducing the deflection magnetic field in the free layer 504. In other words, the magnetic correction layer 508 can nullify the shift in the magnetization reversal characteristic (hysteresis curve) of the free layer 504 caused by the stray magnetic field from the pinned layer 506. For this purpose, the magnetic correction layer 508 can have a magnetization direction antiparallel to the magnetization direction of the pinned layer 506. In this embodiment, if the pinned layer 506 has a magnetization direction from top to bottom, the magnetic correction layer 508 can have a magnetization direction from bottom to top. Conversely, if the pinned layer 506 has a magnetization direction from bottom to top, the magnetic correction layer 508 can have a magnetization direction from top to bottom. The magnetic correction layer 508 can form a synthetic anti-ferromagnet (SAF) structure by being diamagnetically exchange coupled to the pinned layer 506 via the spacer layer 507. The magnetic correction layer 508 can have a single-layer structure or a multi-layer structure containing a ferromagnetic material.
[0118] In this embodiment, the magnetic correction layer 508 is located above the pinned layer 506, but the location of the magnetic correction layer 508 can be varied. For example, the magnetic correction layer 508 can be located below the MTJ structure. Alternatively, for example, the magnetic correction layer 508 can be patterned separately from the MTJ structure and disposed above, below, or to the side of the MTJ structure.
[0119] The capping layer 509 may protect the variable resistance element 520 and, in some cases, may function as a hard mask when patterning the variable resistance element 520. The capping layer 509 may include various conductive materials, such as metal, or oxide. In particular, the capping layer 509 may be formed of a metal-based material that has few pinholes within the layer and is highly resistant to wet and / or dry etching. For example, the capping layer 509 may include a noble metal, such as Ru.
[0120] The capping layer 509 may have a single layer structure or a multi-layer structure. In one embodiment, the capping layer 509 may have a multi-layer structure including oxide, metal, and combinations thereof, for example, a multi-layer structure consisting of an oxide layer / a first metal layer / a second metal layer.
[0121] In one embodiment, a material layer (not shown) for eliminating the lattice structure difference and lattice mismatch between the pinned layer 506 and the magnetic correction layer 508 may be interposed between the pinned layer 506 and the magnetic correction layer 508. For example, such a material layer may be amorphous and may further include a conductive material such as a metal, a metal nitride, or a metal oxide.
[0122] Next, a method for forming the semiconductor device shown in FIG. 5D will be described.
[0123] As shown in FIG. 5A, a first wiring 510 may be formed on a substrate 500 on which a predetermined substructure (not shown) is formed.
[0124] Next, a lower electrode layer material layer 501A may be formed on the first wiring 510.
[0125] The lower electrode layer material layer 501A may include a TDMIT material, such as, but not limited to, at least one of V2O3, LaNiO3, SrRuO3, NdNiO3, PrNiO3, SnO2:Sb, or a combination thereof.
[0126] The lower electrode layer material layer 501A may be formed to a thickness that allows the TDMIT material to exhibit conductivity, and thus the thickness of the lower electrode layer material layer 501A may be determined depending on the TDMIT material included therein.
[0127] As shown in FIG. 5B, a buffer layer material layer 502A, a lower layer material layer 503A, a free layer material layer 504A, a tunnel barrier layer material layer 505A, a fixed layer material layer 506A, a spacer layer material layer 507A, a magnetic correction layer material layer 508A, and a capping layer material layer 509A may be sequentially formed on a lower electrode layer material layer 501A.
[0128] As shown in FIG. 5C , the capping layer material layer 509A, the magnetic correction layer material layer 508A, the spacer layer material layer 507A, the fixed layer material layer 506A, the tunnel barrier layer material layer 505A, the free layer material layer 504A, the lower layer material layer 503A, the buffer layer material layer 502A, and the lower electrode layer material layer 501A are sequentially etched by a patterning process using a mask pattern (not shown), thereby forming the lower electrode layer 501, the buffer layer 502, the lower layer 503, the free layer 504, the tunnel barrier layer 505, the fixed layer 506, the spacer layer 507, the magnetic correction layer 508, the capping layer 509, and the sidewall protection layer 511.
[0129] Here, the patterning process can be performed by, for example, an IBE process.
[0130] During the patterning process, the TDMIT material is re-deposited on the sidewalls of the variable resistance element 520 by etching the lower electrode layer material layer 501A, thereby forming the sidewall protection layer 511.
[0131] The sidewall protection layer 511 may be formed to a thickness that allows the TDMIT material to exhibit insulating properties. Thus, the thickness of the sidewall protection layer 511 may be determined depending on the TDMIT material included. Since the material layer redeposited by the IBE process is formed to a thin thickness, the sidewall protection layer 511 may be formed to a thickness that allows the TDMIT material to exhibit insulating properties.
[0132] The sidewall protection layer 511 can significantly reduce the SFR and process TAT of the variable resistance element 520, and can omit an additional process for removing redeposited materials.
[0133] A second interconnect 530 can be formed on the capping layer 509, as shown in FIG. 5D.
[0134] 5A to 5D may include a substrate 500, a first interconnection 510, a variable resistance element 520, and a second interconnection 530. The variable resistance element 520 may include a bottom electrode layer 501, a buffer layer 502, a bottom layer 503, a free layer 504, a tunnel barrier layer 505, a fixed layer 506, a spacer layer 507, a magnetic correction layer 508, a capping layer 509, and a sidewall protection layer 511. The bottom electrode layer 501 may include a TDMIT material and may be formed to a thickness that allows the TDMIT material to exhibit conductivity. The sidewall protection layer 511 may include a redeposited TDMIT material derived from the bottom electrode layer 501 and may be formed to a thickness that allows the TDMIT material to exhibit insulation.
[0135] In this embodiment, the buffer layer 502, the underlayer 503, the spacer layer 507, the magnetic correction layer 508, and the capping layer 509 are all included, but in other embodiments, at least one of these layers may be omitted.
[0136] In this embodiment, the upper electrode layer is omitted, and the second wiring 530 can also function as the upper electrode layer.
[0137] 6A to 6C are cross-sectional views illustrating steps in a method for forming a semiconductor device according to another embodiment of the present invention, and detailed descriptions of the same aspects as those of the embodiment shown in FIGS.
[0138] As shown in FIG. 6A, a first wiring 610 may be formed on a substrate 600 on which a predetermined substructure (not shown) is formed.
[0139] Next, on the first wiring 610, a material layer 601A for a lower electrode layer, a material layer 602A for a buffer layer, a material layer 603A for a lower layer, a material layer 604A for a free layer, a material layer 605A for a tunnel barrier layer, a material layer 606A for a fixed layer, a material layer 607A for a spacer layer, a material layer 608A for a magnetic correction layer, a material layer 609A for a capping layer, and a material layer 612A for an upper electrode layer may be sequentially formed.
[0140] The lower electrode material layer 601A may have a single layer structure or a multi-layer structure including various conductive materials, such as metals, metal nitrides, conductive carbon materials, or combinations thereof.
[0141] The upper electrode layer material layer 612A may include a TDMIT material, such as, but not limited to, at least one of V2O3, LaNiO3, SrRuO3, NdNiO3, PrNiO3, SnO2:Sb, or a combination thereof.
[0142] The upper electrode layer material layer 612A may be formed to a thickness that allows the TDMIT material to exhibit conductivity, and thus the thickness of the upper electrode layer material layer 612A may be determined depending on the TDMIT material included.
[0143] As shown in FIG. 6B , a material layer 612A for an upper electrode layer, a material layer 609A for a capping layer, a material layer 608A for a magnetic correction layer, a material layer 607A for a spacer layer, a material layer 606A for a fixed layer, a material layer 605A for a tunnel barrier layer, a material layer 604A for a free layer, a material layer 603A for a lower layer, a material layer 602A for a buffer layer, and a material layer 601A for a lower electrode layer are sequentially etched by a patterning process using a mask pattern (not shown), thereby forming a lower electrode layer 601, a buffer layer 602, a lower layer 603, a free layer 604, a tunnel barrier layer 605, a fixed layer 606, a spacer layer 607, a magnetic correction layer 608, a capping layer 609, an upper electrode layer 612, and a sidewall protection layer 611.
[0144] Here, the patterning process can be performed by, for example, an IBE process.
[0145] During the patterning process, the TDMIT material is re-deposited on the sidewalls of the variable resistance element 620 by etching the upper electrode layer material layer 612A, thereby forming the sidewall protection layer 611.
[0146] The sidewall protection layer 611 may be formed to a thickness that allows the TDMIT material to exhibit insulating properties. Thus, the thickness of the sidewall protection layer 611 may be determined depending on the TDMIT material included. Since the material layer redeposited by the IBE process is formed to a thin thickness, the sidewall protection layer 611 may be formed to a thickness that allows the TDMIT material to exhibit insulating properties.
[0147] The sidewall protection layer 611 can significantly reduce the SFR and process TAT of the variable resistance element 620, and can omit an additional process for removing redeposited materials.
[0148] As shown in FIG. 6C, a second interconnect 630 can be formed on the top electrode layer 612.
[0149] 6A to 6C may include a substrate 600, a first interconnection 610, a variable resistance element 620, and a second interconnection 630. The variable resistance element 620 may include a lower electrode layer 601, a buffer layer 602, a lower layer 603, a free layer 604, a tunnel barrier layer 605, a fixed layer 606, a spacer layer 607, a magnetic correction layer 608, a capping layer 609, an upper electrode layer 612, and a sidewall protection layer 611. The upper electrode layer 612 may include a TDMIT material and may be formed to a thickness that allows the TDMIT material to exhibit conductivity. The sidewall protection layer 611 may include a redeposited TDMIT material derived from the upper electrode layer 612 and may be formed to a thickness that allows the TDMIT material to exhibit insulation.
[0150] In this embodiment, the upper electrode layer 612 is formed of a TDMIT material, but in other embodiments, the lower electrode layer 601, or the lower electrode layer 601 and the upper electrode layer 612 may be formed of a TDMIT material.
[0151] Furthermore, although the semiconductor device according to this embodiment includes both the lower electrode layer 601 and the upper electrode layer 612, in other embodiments, the lower electrode layer 601 may be omitted. When the lower electrode layer 601 is omitted, the first wiring 610 may perform the function of the lower electrode layer 601.
[0152] Also, in this embodiment, the buffer layer 602, the lower layer 603, the spacer layer 607, the magnetic correction layer 608, and the capping layer 609 are all included, but in other embodiments, at least one of these layers may be omitted.
[0153] As mentioned above, various embodiments for solving the problems to be solved have been described, but it is clear that a person having ordinary knowledge in the technical field to which the present invention pertains can make various changes and modifications within the scope of the technical concept of the present invention. [Explanation of symbols]
[0154] 100, 200, 300, 400, 500, 600 boards 110, 210, 310, 410, 510, 610 First wiring 120, 220, 320, 420 memory cells 121, 221, 321, 421, 501, 601 Lower electrode layer 122, 222, 322, 422 Selective element layer 123, 223, 323, 423 intermediate electrode layer 124, 224, 324, 424 variable resistance layer 520, 620 variable resistance element 125, 225, 325, 425, 511, 611 Sidewall protection layer 126, 226, 326, 426, 612 Upper electrode layer 130, 230, 330, 430, 530, 630 Second wiring
Claims
1. A first wiring; a second wiring arranged apart from the first wiring; a variable resistance layer disposed between the first wiring and the second wiring; an electrode layer disposed at at least one of a first position between the first wiring and the variable resistance layer or a second position between the variable resistance layer and the second wiring, the electrode layer including a thickness-dependent metal-insulator transition (TDMIT) material whose electrical resistance varies depending on its thickness; A semiconductor device comprising:
2. 2. The semiconductor device of claim 1, wherein the TDMIT material of the electrode layer is configured to a first thickness exhibiting electrical conductivity.
3. The semiconductor device according to claim 2 , further comprising a sidewall protection layer disposed on a sidewall of the variable resistance layer and containing the same TDMIT material as the TDMIT material of the electrode layer.
4. 4. The semiconductor device of claim 3, wherein the TDMIT material of the sidewall protection layer is configured to a second thickness that exhibits electrical insulation.
5. The TDMIT material is V ２ O ３ , LaNiO ３ , SrRuO ３ , NdNiO ３ , PrNiO ３ , SnO ２ 2. The semiconductor device according to claim 1, further comprising at least one of Sb, Sb, Sb+, Sb- ...
6. The semiconductor device according to claim 4 , wherein the first thickness is greater than the second thickness.
7. The semiconductor device according to claim 1 , wherein the electrode layer is disposed either above or below the variable resistance layer while being in contact with the variable resistance layer.
8. The semiconductor device according to claim 1 , wherein the electrode layers are arranged on both the upper and lower sides of the variable resistance layer while being in contact with the variable resistance layer.
9. The semiconductor device according to claim 1 , further comprising a selection element layer disposed above or below the variable resistance layer with the electrode layer interposed therebetween, the selection element layer being configured to control electrical access to the variable resistance layer.
10. A method of forming a thickness-dependent metal-insulator transition (TDMIT) material layer having electrical resistance that varies with thickness; forming a variable resistance layer on or under the TDMIT material layer; performing a patterning process on the TDMIT material layer and the resistance variable layer to form an electrode layer and a resistance variable layer pattern; A method for manufacturing a semiconductor device comprising:
11. A method for manufacturing a semiconductor device as described in Claim 10, wherein the step of performing the patterning process includes a step of forming the TDMIT material of the electrode layer to have a first thickness that exhibits electrical conductivity.
12. The method of claim 10 , further comprising forming a sidewall protection layer containing the TDMIT material on a sidewall of the variable resistance layer pattern.
13. The method of claim 12 , wherein the step of forming the sidewall protection layer includes the step of re-depositing atoms of the TDMIT material on the sidewalls of the variable resistance layer pattern.
14. The method for manufacturing a semiconductor device as described in claim 12, wherein the sidewall protection layer is formed to have a second thickness that causes the TDMIT material of the sidewall protection layer to exhibit electrical insulation properties.
15. The TDMIT material layer is V ２ O ３ , LaNiO ３ , SrRuO ３ , NdNiO ３ , PrNiO ３ , SnO ２ 11. The method for manufacturing a semiconductor device according to claim 10, wherein the material contains at least one selected from the group consisting of Sb, Sb, Sb, and a combination thereof.
16. The method for manufacturing a semiconductor device according to claim 12 , wherein the electrode layer is formed to have a thickness greater than that of the sidewall protection layer.
17. The method for manufacturing a semiconductor device as described in claim 10, further comprising the step of forming a selection element layer on top or bottom of the electrode layer.
18. A method for manufacturing a semiconductor device as described in Claim 10, wherein the step of performing the patterning process forms the electrode layer so that it is positioned above or below the variable resistance layer pattern.
19. A method for manufacturing a semiconductor device as described in claim 10, further comprising a step of forming the additional electrode layer so that the variable resistance layer is positioned between the electrode layer and the additional electrode layer containing the TDMIT material.