Semiconductor device

Abstract

To provide a semiconductor device that increases an area of an active region while reducing a reverse recovery loss.SOLUTION: In a semiconductor device 100, a transistor part 70 comprises: a first transistor region 72 that is provided with an emitter region 12, a contact region 15 and a first base region 14; a second transistor region 73 that is provided with the emitter region and the contact region 15 and provided between the first transistor region 72 and a diode part 80; and a boundary region 74 that is provided between the diode part 80 and the second transistor region 73 including a second base region 84. On the front side of a semiconductor substrate, an area of the contact region 15 in the second transistor region 73 is smaller than an area of the contact region 15 in the first transistor region 72.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 describes that providing a carrier injection suppression layer in an insulated gate bipolar transistor region suppresses the flow of holes into a diode region and improves breakdown resistance during recovery operation. Patent Document 2 describes that a carrier suppression region exposed from one surface of a semiconductor substrate is formed, and a first electrode is connected to the carrier suppression region by a Schottky junction. [Prior art document] [Patent documents] [Patent Document 1] JP 2021-158199 A [Patent Document 2] JP 2021-144998 A Summary of the Invention [Problem to be solved by the invention]

[0003] A semiconductor device is provided in which the area of ​​an active region is increased while the reverse recovery loss is reduced. [Means for solving the problem]

[0004] A first aspect of the present invention is a semiconductor device having a transistor portion and a diode portion, and including a semiconductor substrate provided with a plurality of trench portions, the semiconductor substrate including a drift region of a first conductivity type, a first base region of a second conductivity type provided above the drift region, a second base region of the second conductivity type provided above the drift region and having a lower doping concentration than the first base region, an emitter region of the first conductivity type provided above the first base region and having a higher doping concentration than the drift region, and a second base region provided above the first base region and the second base region and having a higher doping concentration than the first base region. and a contact region of a different conductivity type, the transistor section having a first transistor region in which the emitter region, the contact region, and the first base region are provided, a second transistor region in which the emitter region and the contact region are provided and which is provided between the first transistor region and the diode section, and a boundary region including the second base region and which is provided between the second transistor region and the diode section, and on the front surface of the semiconductor substrate, an area of ​​the contact region in the second transistor region is smaller than an area of ​​the contact region in the first transistor region.

[0005] In the first transistor region, the first base region may not be exposed on the front surface of the semiconductor substrate.

[0006] In the first transistor region, the first base region may be exposed on the front surface of the semiconductor substrate.

[0007] The contact region may be sandwiched between the first base regions on the front surface of the semiconductor substrate in the first transistor region.

[0008] The length of the contact region in the second transistor region in the trench extension direction may be shorter than the length of the contact region in the first transistor region aligned in the trench arrangement direction in the trench extension direction.

[0009] The first base region may be provided in the first transistor region and the second transistor region, and the second base region may be provided in the boundary region and the diode portion.

[0010] In the trench arrangement direction, the width of the second transistor region may be narrower than the width of the boundary region.

[0011] The semiconductor substrate may have an accumulation region of a first conductivity type that is more highly doped than the drift region.

[0012] The accumulation region may be provided in the transistor portion.

[0013] The accumulation region may be provided in the second transistor region but not in the boundary region.

[0014] The plurality of trench portions may include gate trench portions and dummy trench portions, and at least one of the gate trench portions may be provided in the second transistor region.

[0015] The boundary region and the diode portion may have a lifetime control region including a lifetime killer on the front surface side of the semiconductor substrate.

[0016] the diode portion has the contact region and the second base region, In the boundary region and the diode portion, the contact region may be provided between the second base regions.

[0017] The transistor portion may further have a collector region of a second conductivity type provided on the back surface of the semiconductor substrate, and the diode portion may further have a first cathode region of a first conductivity type provided on the back surface of the semiconductor substrate, and a second cathode region of a second conductivity type provided on the back surface of the semiconductor substrate and having an area smaller than that of the first cathode region.

[0018] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0019] [Figure 1] 1 shows an example of a top view of a semiconductor device 100 according to a first embodiment. [Figure 2] 2 shows an example of an enlarged view of region A in FIG. [Figure 3] FIG. 3 is a diagram showing an example of a cross section taken along line aa' in FIG. [Figure 4] 1 shows an example of a bottom view of the semiconductor device 100. FIG. [Figure 5] 1 shows another example of a bottom view of the semiconductor device 100. FIG. [Figure 6] 1 shows an example of an enlarged view of the top surface of a semiconductor device 1100 according to a comparative example. [Figure 7] FIG. 7 is a diagram showing an example of a cross section taken along line aa' in FIG. [Figure 8] 10 shows an example of a top view of a semiconductor device 200 according to a second embodiment. [Figure 9] 10 shows an example of a top view of a semiconductor device 300 according to a third embodiment. [Figure 10] 10 is a graph showing the change over time in collector current Ic during reverse recovery. DETAILED DESCRIPTION OF THE INVENTION

[0020] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0021] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "top" and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the top surface and the other surface is referred to as the bottom surface. The directions of "top," "bottom," "front," and "back" are not limited to the direction of gravity or the direction in which the semiconductor device is attached to a substrate or the like when mounted.

[0022] In this specification, technical matters may be explained using orthogonal coordinate axes of X, Y, and Z. In this specification, a plane parallel to the front surface of a semiconductor substrate is defined as the XY plane, and the depth direction of the semiconductor substrate is defined as the Z axis. In this specification, the view of the semiconductor substrate in the Z axis direction is referred to as a top view.

[0023] In each embodiment, an example is shown in which the first conductivity type is N-type and the second conductivity type is P-type, but the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment will be opposite polarities.

[0024] In this specification, layers and regions marked with N or P have majority carriers of electrons or holes, respectively. In addition, + and - attached to N or P indicate higher and lower doping concentrations than layers and regions without that designation, respectively. ++ indicates a higher doping concentration than +, and -- indicates a lower doping concentration than -.

[0025] In this specification, the doping concentration refers to the concentration of a dopant converted into a donor or acceptor. Therefore, the unit is / cm 3In this specification, the difference in concentration between the donor and the acceptor (i.e., the net doping concentration) may be referred to as the doping concentration. In this case, the doping concentration can be measured by the SR method. Alternatively, the chemical concentration of the donor and the acceptor may be referred to as the doping concentration. In this case, the doping concentration can be measured by the SIMS method. Unless otherwise specified, any of the above may be used as the doping concentration. Unless otherwise specified, the peak value of the doping concentration distribution in the doping region may be referred to as the doping concentration in the doping region.

[0026] In this specification, the dose refers to the number of ions implanted into a wafer per unit area during ion implantation. Therefore, the unit is / cm 2 The dose of a semiconductor region can be expressed as an integral concentration obtained by integrating the doping concentration over the depth direction of the semiconductor region. The unit of the integral concentration is / cm 2 Therefore, the dose amount and the integrated concentration may be treated as the same thing. The integrated concentration may be the integral value up to the half-width, and when the spectrum overlaps with that of another semiconductor region, the influence of the other semiconductor region may be excluded from the calculation.

[0027] Therefore, in this specification, the high or low doping concentration can be interpreted as the high or low dose amount. That is, when the doping concentration of one region is higher than the doping concentration of another region, it can be understood that the dose amount of the one region is higher than the dose amount of the other region.

[0028] Fig. 1 shows an example of a top view of a semiconductor device 100 according to an embodiment. Fig. 1 shows the positions of each component projected onto the front surface of a semiconductor substrate 10. Fig. 1 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0029] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 has edges 102 in a top view. In this example, the semiconductor substrate 10 has two pairs of edges 102 that face each other in a top view. The X-axis and Y-axis are parallel to either of the edges 102. In this specification, the arrangement direction of the transistor section 70 and the diode section 80 (described later) is referred to as the X-axis, and the extension direction perpendicular to the arrangement direction in a top view is referred to as the Y-axis. The Z-axis is perpendicular to the front surface of the semiconductor substrate 10.

[0030] An active region 160 is provided in the semiconductor substrate 10. The active region 160 is a region through which a main current flows in the depth direction between the front and back surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode 52 is provided above the active region 160, but is omitted in FIG. 1 .

[0031] In FIG. 1, the active region 160 is divided by a gate wiring layer 50, which will be described later. In this example, the active region 160 may be divided into two regions in the X-axis direction and three regions in the Y-axis direction. These active regions 160 are electrically connected to each other by an emitter electrode 52, which will be described later. The number of active regions 160 divided by the gate wiring layer 50 may be changed as appropriate.

[0032] The active region 160 is provided with a transistor section 70 and a diode section 80. For example, the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT) in which an insulated gate bipolar transistor (IGBT) is provided in the transistor section 70 and a free wheeling diode (FWD) is provided in the diode section 80. The semiconductor device 100 may be an IGBT or a MOS transistor.

[0033] In this example, the transistor sections 70 and the diode sections 80 are alternately arranged on the front surface of the semiconductor substrate 10 along the arrangement direction (X-axis direction).

[0034] In FIG. 1, the region where the transistor section 70 is disposed is marked with the symbol "I," and the region where the diode section 80 is disposed is marked with the symbol "F." The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than the width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section, which will be described later.

[0035] 1, the end of the transistor section 70 in the Y-axis direction is located closer to the outer periphery of the active region 160 than the end of the diode section 80 in the Y-axis direction. In addition, the width of the transistor section 70 in the X-axis direction is wider than the width of the diode section 80 in the X-axis direction.

[0036] The diode section 80 has an N+ type cathode region on the back surface side of the semiconductor substrate 10. In this specification, the region where the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A P+ type collector region may be provided on the back surface of the semiconductor substrate 10 in a region other than the cathode region.

[0037] The transistor section 70 has a P+ type collector region on the back surface side of the semiconductor substrate 10. In addition, the transistor section 70 has an N type emitter region, a P type base region, a gate conductive portion, and a gate trench portion having a gate insulating film periodically arranged on the front surface side of the semiconductor substrate 10.

[0038] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. As an example, the semiconductor device 100 may include a pad region 163. The pad region 163 may include pads such as a gate pad, an anode pad and a cathode pad of a temperature detection diode (not shown), and a current detection pad of a current sense (not shown). The pad region 163 is disposed between the active region 160 and an edge termination structure 162, which will be described later. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0039] The gate wiring layer 50 electrically connects a gate conductive portion 44 provided in a gate trench portion, which will be described later, to a gate pad. The gate wiring layer 50 of this example surrounds the active region 160 in a top view.

[0040] In the semiconductor device 100 of this example, the active region 160 and the pad region 163 adjacent to the active region 160 are surrounded by an edge termination structure 162. The edge termination structure 162 reduces electric field concentration on the front surface side of the semiconductor substrate 10. The edge termination structure 162 may include multiple guard rings. The guard rings are P-type regions that contact the front surface of the semiconductor substrate 10. By providing multiple guard rings, the depletion layer on the upper surface side of the active region 160 can be extended outward, improving the breakdown voltage of the semiconductor device 100. The edge termination structure 162 may further include at least one of a field plate and a resurf annularly arranged to surround the active region 160 and the pad region 163.

[0041] Fig. 2 is an enlarged view showing an example of region A in Fig. 1. Region A is around the boundary between the transistor section 70 and the diode section 80 and the pad region 163 on the negative side of the Y axis direction of the semiconductor device 100 in a top view.

[0042] The transistor section 70 is a region obtained by projecting a collector region 22 provided on the back side of the semiconductor substrate 10 onto the front surface of the semiconductor substrate 10. In this example, the collector region 22 is, for example, a P+ type. The transistor section 70 includes a transistor such as an IGBT.

[0043] The diode section 80 is a region obtained by projecting a cathode region 82 provided on the back surface side of the semiconductor substrate 10 onto the front surface of the semiconductor substrate 10. In this example, the cathode region 82 is, for example, an N+ type. The diode section 80 includes a diode such as a free wheel diode (FWD) provided adjacent to the transistor section 70 on the front surface of the semiconductor substrate 10.

[0044] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, etc. The semiconductor substrate 10 in this example is a silicon substrate.

[0045] The semiconductor device 100 of this example includes, on the front surface of the semiconductor substrate 10, a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a first base region 14, a second base region 84, a contact region 15, and a well region 17. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate wiring layer 50 provided above the front surface of the semiconductor substrate 10.

[0046] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the first base region 14, the second base region 84, the contact region 15, and the well region 17. The gate wiring layer 50 is provided above the gate trench portion 40 and the well region 17.

[0047] The emitter electrode 52 and the gate wiring layer 50 are made of a material containing metal. At least a portion of the emitter electrode 52 may be made of aluminum or an alloy containing aluminum as a main component (e.g., an aluminum-silicon alloy, an aluminum-silicon-copper alloy, etc.). At least a portion of the gate wiring layer 50 may be made of aluminum or an alloy containing aluminum as a main component (e.g., an aluminum-silicon alloy, an aluminum-silicon-copper alloy, etc.). The emitter electrode 52 and the gate wiring layer 50 may have a barrier metal made of titanium, a titanium compound, etc. below the region made of aluminum, etc. The emitter electrode 52 and the gate wiring layer 50 are provided so as to be electrically isolated from each other.

[0048] The emitter electrode 52 and the gate wiring layer 50 are provided above the semiconductor substrate 10, with an interlayer insulating film 38 sandwiched therebetween. The interlayer insulating film 38 is omitted in Fig. 2. A contact hole 54, a contact hole 55, and a contact hole 56 are provided to penetrate the interlayer insulating film 38.

[0049] The contact hole 55 connects the gate conductive portion 44 in the gate trench portion 40 of the transistor section 70 to the gate wiring layer 50. A plug made of tungsten or the like may be provided inside the contact hole 55 via a barrier metal.

[0050] The contact hole 56 connects the emitter electrode 52 to a dummy conductive portion 34 in a dummy trench portion 30 (described later) provided in the transistor portion 70 and the diode portion 80. A plug made of tungsten or the like may be provided inside the contact hole 56 via a barrier metal.

[0051] At the connection portion 25a, the gate wiring layer 50 is electrically connected to the semiconductor substrate 10 through a contact hole 55. At the connection portion 25b, the emitter electrode 52 is electrically connected to the semiconductor substrate 10 through a contact hole 56.

[0052] In one example, the connection portion 25a is provided in a region between the gate wiring layer 50 and the gate conductive portion 44, including the inside of the contact hole 55. The connection portion 25b is provided in a region between the emitter electrode 52 and the dummy conductive portion 34, including the inside of the contact hole 56.

[0053] The connecting portions 25a and 25b are made of a conductive material such as a metal such as tungsten or polysilicon doped with impurities. The connecting portions 25a and 25b may also have a barrier metal such as titanium nitride. Here, the connecting portions 25a and 25b are made of polysilicon (N+) doped with N-type impurities. The connecting portions 25a and 25b are provided above the front surface of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0054] The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The gate trench portions 40 in this example may have two extension portions 39 that extend parallel to the front surface of the semiconductor substrate 10 and along an extension direction perpendicular to the arrangement direction (in this example, the Y-axis direction), and a connection portion 41 that connects the two extension portions 39.

[0055] It is preferable that at least a portion of the connection portion 41 is formed in a curved shape. By connecting the ends of the two extension portions 39 of the gate trench portion 40, it is possible to alleviate electric field concentration at the ends of the extension portions 39. At the connection portion 41 of the gate trench portion 40, the gate wiring layer 50 may be connected to the gate conductive portion 44.

[0056] The dummy trench portion 30 is a trench portion in which a dummy conductive portion 34 provided therein is electrically connected to the emitter electrode 52. Like the gate trench portion 40, the dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example). Like the gate trench portion 40, the dummy trench portion 30 of this example may have a U-shape on the front surface of the semiconductor substrate 10. That is, the dummy trench portion 30 may have two extension portions 29 extending along the extension direction and a connection portion 31 connecting the two extension portions 29.

[0057] In this example, the contact holes 54 are provided above the emitter region 12 and the contact region 15 in the transistor section 70. The contact holes 54 are provided above the contact region 15 and the second base region 84 in the diode section 80. None of the contact holes 54 are provided above the well regions 17 provided at both ends in the Y-axis direction. In this manner, one or more contact holes 54 are provided in the interlayer insulating film. The one or more contact holes 54 may be provided extending in the extension direction.

[0058] Mesa portion 71 and mesa portion 81 are mesa portions provided adjacent to trench portions in a plane parallel to the front surface of semiconductor substrate 10. A mesa portion is a portion of semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be a portion extending from the front surface of semiconductor substrate 10 to the deepest bottom of each trench portion. An extension portion of each trench portion may be considered as one trench portion. In other words, the region sandwiched between the two extension portions may be considered as a mesa portion.

[0059] The mesa portion 71 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 and the gate trench portion 40 .

[0060] The mesa portion 81 is provided in a region of the diode portion 80 that is sandwiched between adjacent dummy trench portions 30. The mesa portion 81 of this example has a second base region 84 on the front surface of the semiconductor substrate 10, and has a well region 17 on the negative side in the Y-axis direction. The mesa portion 81 may have a contact region 15 provided on the front surface of the second base region 84.

[0061] The transistor section 70 has a first transistor region 72, a second transistor region 73 provided between the first transistor region 72 and the diode section 80, and a boundary region 74 provided between the second transistor region 73 and the diode section 80.

[0062] The first transistor region 72 and the second transistor region 73 each have an emitter region 12, a contact region 15, and a first base region 14. The mesa portion 71 of the first transistor region 72 and the second transistor region 73 has, on the front surface of the semiconductor substrate 10, a well region 17, the emitter region 12, the first base region 14, and the contact region 15.

[0063] The first transistor region 72 and the second transistor region 73 have a structure in which one gate trench portion 40 and two dummy trench portions 30 are repeatedly arranged. That is, in this example, the first transistor region 72 and the second transistor region 73 have the gate trench portion 40 and the dummy trench portion 30 in a ratio of 1:2. For example, the transistor region 70 has two extension portions 29 between two extension portions 39.

[0064] However, the ratio of the gate trench portions 40 to the dummy trench portions 30 is not limited to this example. The ratio of the gate trench portions 40 to the dummy trench portions 30 may be 1:1 or 2:3. Furthermore, the transistor portion 70 may not be provided with dummy trench portions 30, and may be entirely made up of gate trench portions 40.

[0065] The first base region 14 is a region provided on the front surface side of the semiconductor substrate 10 in the transistor portion 70. The first base region 14 is, for example, a P-type. The first base region 14 may be provided on the front surface of the semiconductor substrate 10 at both ends in the Y-axis direction of the mesa portion 71 of the first transistor region 72 and the second transistor region 73. Note that FIG. 2 shows only the end of the first base region 14 on the negative side in the Y-axis direction.

[0066] The second base region 84 is a region provided on the front surface side of the semiconductor substrate 10 in the boundary region 74 and the diode section 80. The second base region 84 is, for example, P-- type. The doping concentration of the second base region 84 is lower than the doping concentration of the first base region 14. The second base region 84 may be provided on the front surface of the semiconductor substrate 10 at both ends in the Y-axis direction of the mesa section 71 and the mesa section 81 in the boundary region 74. Note that FIG. 2 shows only the end on the negative side in the Y-axis direction of the second base region 84. Here, in the diode section 80, the second base region 84 corresponds to an anode layer.

[0067] The emitter region 12 is a region of the same conductivity type as the drift region 18 but with a higher doping concentration than the drift region 18. In this example, the emitter region 12 is, for example, N+ type. An example of a dopant for the emitter region 12 is arsenic (As). In the first transistor region 72 and the second transistor region 73, the emitter region 12 is provided in contact with the gate trench portion 40. In the first transistor region 72 and the second transistor region 73, the emitter region 12 may be provided extending in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The emitter region 12 is also provided below the contact hole 54.

[0068] Furthermore, the emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30. The emitter region 12 does not have to be provided in the boundary region 74 and the mesa portion 81.

[0069] The contact region 15 has the same conductivity type as the first base region 14 but has a higher doping concentration than the first base region 14. In this example, the contact region 15 is, for example, a P+ type. The contact region 15 in this example is provided on the front surface of the mesa portion 71. In the first transistor region 72 and the second transistor region 73, the contact region 15 may be provided extending in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. Meanwhile, in the boundary region 74, the X-axis end of the contact region 15 is spaced apart from the adjacent trench portion. Furthermore, in the boundary region 74, the contact region 15 is selectively provided in the Y-axis direction.

[0070] The contact region 15 may or may not be in contact with the gate trench portion 40. Furthermore, the contact region 15 may or may not be in contact with the dummy trench portion 30. In the first transistor region 72 and the second transistor region 73, the contact region 15 is in contact with the dummy trench portion 30 and the gate trench portion 40. On the other hand, in the boundary region 74, the contact region 15 is separated from the dummy trench portion 30. The contact region 15 is also provided below the contact hole 54.

[0071] In this example, emitter regions 12 and contact regions 15 are alternately provided in the extension direction (Y-axis direction) in the mesa portions 71 of the first transistor region 72 and the second transistor region 73. In the first transistor region 72 and the second transistor region 73 of this example, the first base regions 14 are not exposed on the front surface of the semiconductor substrate 10.

[0072] On the front surface of the semiconductor substrate 10, the area of ​​the contact region 15 in the second transistor region 73 is smaller than the area of ​​the contact region 15 in the first transistor region 72. That is, in the second transistor region 73, the ratio of the Y-axis direction length of the emitter region 12 to the Y-axis direction length of the contact region 15 is larger than that in the first transistor region 72.

[0073] In this example, if the length in the extension direction (Y-axis direction) of one contact region 15 of the first transistor region 72 is L1 and the length in the extension direction (Y-axis direction) of the contact region 15 of the second transistor region 73 that is aligned with the contact region 15 in the arrangement direction (X-axis direction) is L2, then L2 = L1 or L2 = 0. That is, in the second transistor region 73, a contact region 15 or emitter region 12 having the same extension direction length L2 as L1 is provided at a position aligned with the contact region 15 of the first transistor region 72 in the arrangement direction. The width of the second transistor region 73 in the arrangement direction (X-axis direction) may be narrower than the width of the boundary region 74.

[0074] When the transistor section 70 is turned off and the diode section 80 becomes conductive, an electron current flows from the cathode region 82 to the second base region 84, which acts as an anode layer, generating a reverse recovery current. When the electron current reaches the second base region 84, conductivity modulation occurs, causing a hole current to flow from the anode layer.

[0075] At this time, the electron current also diffuses from the cathode region 82 to the first base region 14 of the transistor section 70. The electron current diffusing toward the transistor section 70 promotes hole injection from the contact region 15, which has a higher doping concentration than the first base region 14, and increases the hole density in the semiconductor substrate 10. Therefore, it takes time for the holes to disappear when the diode section 80 is turned off. As a result, the reverse recovery peak current increases and the reverse recovery loss also increases.

[0076] In the second transistor region 73 of this example, the area ratio of the contact region 15 is made smaller than that of the first transistor region 72, thereby suppressing hole injection and reducing reverse recovery loss.

[0077] The boundary region 74 is a region that does not function as a transistor and is adjacent to the diode portion 80 within the transistor portion 70. The mesa portion 71 of the boundary region 74 has, on the front surface of the semiconductor substrate 10, a well region 17, an emitter region 12, a second base region 84, and a contact region 15.

[0078] In the diode section 80 of this example, the contact region 15 is not in contact with the dummy trench section 30, and is sandwiched between the second base regions 84 in the extension direction (Y-axis direction) and arrangement direction (X-axis direction). In the diode section 80, the X-axis direction end of the contact region 15 is spaced apart from the adjacent dummy trench section 30 in a plan view, and the contact region 15 is selectively provided in the Y-axis direction.

[0079] Similarly, in the boundary region 74 of this example, the contact region 15 is not in contact with the dummy trench portion 30, and is sandwiched between the second base regions 84 in the extension direction and arrangement direction. In other words, the boundary region 74 is a part of the transistor portion 70, but has the same front surface structure as the diode portion 80.

[0080] In this way, by providing the boundary region 74 having the second base region 84 with a low doping concentration on the diode section 80 side of the transistor section 70, hole injection can be suppressed and reverse recovery loss can be reduced.

[0081] The well region 17 is provided closer to the front surface of the semiconductor substrate 10 than the drift region 18, which will be described later. The well region 17 is an example of a well region provided on the edge side of the semiconductor device 100. The well region 17 is, for example, P+ type. The well region 17 is provided within a predetermined range from the end of the active region on the side where the gate wiring layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. Part of the regions of the gate trench portion 40 and the dummy trench portion 30 on the gate wiring layer 50 side are provided in the well region 17. The bottoms of the ends of the gate trench portion 40 and the dummy trench portion 30 in the extension direction may be covered by the well region 17.

[0082] 3 is a diagram showing an example of the a-a' cross section in FIG. 2. The a-a' cross section is an XZ plane passing through the contact region 15 in the transistor section 70. In the a-a' cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, a contact region 15, and a collector electrode 24. An emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0083] The drift region 18 is a region provided in the semiconductor substrate 10. In this example, the drift region 18 is, for example, N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein. That is, the doping concentration of the drift region 18 may be the same as the doping concentration of the semiconductor substrate 10.

[0084] The buffer region 20 is a region provided below the drift region 18. In this example, the buffer region 20 has the same conductivity type as the drift region 18, for example, N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower surface sides of the first base region 14 and the second base region 84 from reaching the collector region 22 and the cathode region 82.

[0085] The collector region 22 is a region of a different conductivity type from the drift region 18, provided below the buffer region 20 in the transistor section 70. The cathode region 82 is a region of the same conductivity type as the drift region 18, provided below the buffer region 20 in the diode section 80. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80.

[0086] The collector electrode 24 is formed on the rear surface 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a conductive material such as a metal or by laminating conductive materials such as metals.

[0087] The first base region 14 is a region of a different conductivity type from the drift region 18, provided above the drift region 18 in the mesa portion 71 of the first transistor region 72 and the second transistor region 73. The second base region 84 is a region of a different conductivity type from the drift region 18, provided above the drift region 18 in the mesa portion 71 and the mesa portion 81 of the boundary region 74. The first base region 14 in this example is P-type, for example. The second base region 84 in this example is P--type, for example. The doping concentration of the second base region 84 is lower than the doping concentration of the first base region 14. The first base region 14 is provided in contact with the gate trench portion 40. The first base region 14 may be provided in contact with the dummy trench portion 30. On the other hand, the second base region 84 in this example is provided in contact with the dummy trench portion 30, but is not in contact with the gate trench portion 40.

[0088] The emitter region 12 is provided between the first base region 14 and the front surface 21 of the semiconductor substrate 10. In other cross sections, the emitter region 12 may be provided on the front surface of the mesa portion 71 in the first transistor region 72 and the second transistor region 73. In this example, the emitter region 12 is not provided in the mesa portion 71 and the mesa portion 81 in the boundary region 74. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0089] The accumulation region 16 is a region provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18. In this example, the accumulation region 16 has the same conductivity type as the drift region 18, and is, for example, N-type. The accumulation region 16 is provided in the transistor section 70. In this example, the accumulation region 16 is provided in the first transistor region 72 and the second transistor region 73, but is not provided in the boundary region 74. The accumulation region 16 may also be provided in the boundary region 74 and the diode section.

[0090] The accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage of the transistor portion 70 can be reduced.

[0091] In this example, a first-stage accumulation region 16 is provided on the lower surface of the first base region 14, and a second-stage accumulation region 16 is further provided across a drift region 18 provided on the lower surface of the first-stage accumulation region 16. The number of stages of the accumulation region 16 may be changed as appropriate depending on the desired carrier injection enhancement effect.

[0092] One or more gate trenches 40 and one or more dummy trenches 30 are provided in the front surface 21 of the semiconductor substrate 10. Each trench extends from the front surface 21 to the drift region 18. In regions where at least one of the emitter region 12, the first base region 14, the second base region 84, the contact region 15, and the accumulation region 16 is provided, each trench also penetrates these regions to reach the drift region 18. The trenches penetrating the doped regions are not limited to those formed in the order of forming the doped regions and then the trenches. The trenches penetrating the doped regions also include those formed after the trenches are formed.

[0093] The gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 provided on the front surface 21 of the semiconductor substrate 10. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench, further inward than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is made of a conductive material such as polysilicon. The gate trench portion 40 is covered with an interlayer insulating film 38 on the front surface 21 of the semiconductor substrate 10.

[0094] The gate conductive portion 44 includes a region facing the adjacent first base region 14 on the mesa portion 71 side, across the gate insulating film 42, in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the first base region 14 that contacts the gate trench.

[0095] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side of the semiconductor substrate 10. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided more inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the front surface 21 with an interlayer insulating film 38.

[0096] The interlayer insulating film 38 is provided on the front surface 21 of the semiconductor substrate 10. An emitter electrode 52 is provided above the interlayer insulating film 38. One or more contact holes 54 are provided in the interlayer insulating film 38 to electrically connect the emitter electrode 52 to the semiconductor substrate 10. Contact holes 55 and 56 may also be provided so as to penetrate the interlayer insulating film 38.

[0097] A known technique for promoting carrier annihilation and reducing reverse recovery loss during turn-off is to provide a lifetime control region including a lifetime killer in the drift region 18. A lifetime killer is a crystal defect formed at a predetermined depth in the semiconductor substrate by implanting, for example, helium ions, hydrogen ions (protons), or deuterium ions. The lifetime control region promotes recombination between holes generated in the base region and electrons injected from the cathode region when the diode section is turned off, thereby suppressing the peak current during reverse recovery.

[0098] A lifetime control region may be provided continuously from the diode portion 80 to at least a part of the boundary region 74 on the front surface 21 side of the semiconductor substrate 10. As a result, when the diode portion is conductive, a hole current is generated not only in the second base region 84 of the diode portion 80 but also from the first base region 14 of the transistor portion 70 toward the cathode region 82, and the lifetime control region 85 provided in the boundary region 74 promotes carrier annihilation and reduces reverse recovery loss at turn-off. The lifetime control region 85 may be provided so that the concentration distribution of the lifetime killer has multiple peaks in the Z-axis direction.

[0099] Here, an example of an impurity implantation process for the semiconductor device 100 according to this example will be described. In the semiconductor substrate 10, impurities for forming the accumulation region 16 are implanted using a mask into the regions for forming the first transistor region 72 and the second transistor region 73, and then impurities for forming the second base region 84 are implanted over the entire surface. Next, impurities for forming the first base region 14 are implanted using a mask into the regions for forming the first transistor region 72 and the second transistor region 73. Thereafter, a plurality of trenches are formed in the front surface 21 of the semiconductor substrate 10 by etching.

[0100] Next, impurities for forming emitter region 12 are implanted using a mask into the regions for forming first transistor region 72 and second transistor region 73. Next, impurities for forming contact region 15 are implanted using a mask into the regions for forming first transistor region 72 and second transistor region 73, and are implanted using another mask into boundary region 74 and diode section 80. Thereafter, front surface metal layers such as interlayer insulating film 38 and emitter electrode 52 are formed on front surface 21 of semiconductor substrate 10.

[0101] 4 shows an example of a bottom view of semiconductor device 100. Here, only a portion of active region 160 on back surface 23 of semiconductor substrate 10 is shown, and edge termination structure 162 is omitted. Collector electrode 24 provided on back surface 23 of semiconductor substrate 10 is also omitted.

[0102] The collector region 22 is a region of a different conductivity type from the drift region 18, provided below the buffer region 20 in the transistor section 70. The cathode region 82 is a region of the same conductivity type as the drift region 18, provided below the buffer region 20 in the diode section 80. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80. The collector region 22 may be provided between the end of the active region 160 and the end of the cathode region 82 in the extension direction.

[0103] Fig. 5 shows another example of a bottom view of the semiconductor device 100. Here, explanations common to Fig. 4 will be omitted. The cathode region of this example has a first cathode region 82 of a first conductivity type corresponding to the cathode region 82 of Fig. 4, and a second cathode region 83 of a second conductivity type having an area smaller than that of the first cathode region 82.

[0104] As an example, the second cathode region 83 is a region that is evenly provided in a portion of the first cathode region 82. In this example, the second cathode region 83 may be provided extending in the arrangement direction. In the extension direction, the first cathode region 82 is longer than the second cathode region 83. The second cathode region 83 may have the same doping concentration as the collector region 22. The second cathode region 83 may be in contact with the collector region 22 at an end portion in the arrangement direction. The second cathode region 83 suppresses surge voltage during reverse recovery and improves the characteristics of the diode section 80.

[0105] Fig. 6 shows an example of an enlarged view of the top surface of a semiconductor device 1100 according to a comparative example. Fig. 7 is a diagram showing an example of a-a' cross section in Fig. 6. Here, explanations of members common to Fig. 2 will be omitted, and differences will be mainly described.

[0106] The transistor section 70 of the semiconductor device 1100 of the comparative example has a first transistor region 72 and a boundary region 74, but unlike the transistor section 70 of the semiconductor device 100, a second transistor region 73 is not provided between the first transistor region 72 and the boundary region 74.

[0107] In the arrangement direction (X-axis direction), the width of the boundary region 74 in the semiconductor device 1100 is narrower than the sum of the widths of the second transistor region 73 and the boundary region 74 in the semiconductor device 100. In addition, the width of the boundary region 74 in the semiconductor device 1100 is wider than the width of the boundary region 74 in the semiconductor device 100.

[0108] That is, in the semiconductor device 1100, the distance between the first transistor region 72 and the diode section 80 is shorter than in the semiconductor device 100. Therefore, when the diode section 80 is conductive, a hole current flows from the first base region 14 of the first transistor region 72 to the cathode region 82, and the hole density in the semiconductor substrate 10 increases, so it takes time for the holes to disappear when the diode section 80 is turned off. Therefore, in the semiconductor device 1100, the peak current during reverse recovery is larger than in the semiconductor device 100, and the reverse recovery loss is larger.

[0109] In the semiconductor device 100, the second transistor region 73, whose contact region 15 has a smaller area than the first transistor region 72, is provided between the first transistor region 72 and the boundary region 74, thereby reducing the hole current flowing toward the cathode region 82 when the diode section 80 is conductive. Therefore, in the semiconductor device 100, the peak current during reverse recovery is smaller than in the semiconductor device 1100, and reverse recovery loss can be reduced.

[0110] Furthermore, the width of the boundary region 74 in the semiconductor device 100 is shorter than the width of the boundary region 74 in the semiconductor device 1100, and instead a second transistor region 73 is provided, thereby reducing the ineffective region that does not contribute to transistor operation.

[0111] 8 shows an example of a top view of a semiconductor device 200 according to Example 2. Here, a description of the configuration common to the semiconductor device 100 shown in FIG. 2 will be omitted, and differences will be mainly described.

[0112] In the first transistor region 72 and the second transistor region 73 of this example, the first base region 14 is exposed on the front surface 21 of the semiconductor substrate 10. In the first transistor region and the second transistor region 73 of this example, the contact region 15 is sandwiched between the first base regions 14 on the front surface 21 of the semiconductor substrate 10 in the extension direction (Y-axis direction). That is, in this example, the first base region 14 is exposed between the emitter region 12 and the contact region 15 on the front surface 21 of the semiconductor substrate 10.

[0113] In one example of a process for forming the first transistor region 72 and the second transistor region 73, after the first base region 14 is formed in the semiconductor substrate 10, the emitter region 12 is formed on the front surface 21 of the semiconductor substrate 10, and then the contact region 15 is formed. The first base region 14 exposed on the front surface 21 of the semiconductor substrate 10 may be a region in which the impurities implanted to form the contact region 15 remain without diffusing to the end of the emitter region 12. Note that the order in which the emitter region 12 and the contact region 15 are formed may be reversed.

[0114] In this way, the semiconductor device 200 according to the second embodiment can also reduce reverse recovery loss by providing the second transistor region 73 between the first transistor region 72 and the boundary region 74, thereby achieving the same effect as the semiconductor device 100 according to the first embodiment.

[0115] Fig. 9 shows an example of a top view of a semiconductor device 300 according to Example 3. Here, a description of the configuration common to the semiconductor device 200 shown in Fig. 8 will be omitted, and differences will be mainly described.

[0116] In the second transistor region 73 of this example, the length L2 in the extension direction (Y-axis direction) of the contact region 15 is shorter than the length L1 in the extension direction (Y-axis direction) of the contact region 15 in the first transistor region 72 aligned in the arrangement direction (X-axis direction).

[0117] That is, in this example, the area ratio of the contact region 15 in the second transistor region 73 is further reduced, so that the reverse recovery loss can be further reduced.

[0118] Furthermore, as described in Example 2, in one example of the process for forming the first transistor region 72 and the second transistor region 73, after the first base region 14 is formed in the semiconductor substrate 10, the emitter region 12 is formed on the front surface 21 of the semiconductor substrate 10, and then the contact region 15 is formed. In this example, since the length L2 in the extension direction (Y-axis direction) of the contact region 15 is short, even if the mask position is shifted during impurity implantation, the impurities are unlikely to diffuse into the range of the emitter region 12, and the contact region 15 can be formed with a predetermined length in the extension direction (Y-axis direction).

[0119] Fig. 10 is a graph showing the change over time in collector current Ic during reverse recovery. In the graph of Fig. 10, the solid line shows the behavior of collector current Ic in a semiconductor device according to a comparative example (e.g., semiconductor device 1100) that does not have second transistor region 73, and the dashed line shows the behavior of collector current Ic in a semiconductor device according to an example (e.g., any of semiconductor device 100, semiconductor device 200, and semiconductor device 300) that has second transistor region 73.

[0120] At time t1, the transistor section is turned off, and the diode section 80 becomes conductive. An electron current flows from the cathode region 82 to the second base region 84, which acts as an anode layer, generating a reverse recovery current. When the electron current reaches the second base region 84, conductivity modulation occurs, and a hole current flows from the anode layer. Furthermore, the electron current also diffuses from the cathode region 82 to the first base region 14 of the transistor section 70.

[0121] The electron current diffused toward the transistor section 70 promotes hole injection from the contact region 15, which has a higher doping concentration than the first base region 14, and increases the hole density in the semiconductor substrate 10, so it takes time for the holes to disappear when the diode section 80 is turned off. As a result, the reverse recovery peak current Irp increases and the reverse recovery loss also increases.

[0122] Here, the collector current Ic in the semiconductor device according to the comparative example gradually decreases after reaching the reverse recovery peak current Irp at time t2 and becomes almost zero around time t3. If the reverse recovery peak current Irp is large, it takes a long time for the current to become zero, which increases heat generation and reverse recovery loss.

[0123] On the other hand, the semiconductor device 100 according to the embodiment has a second transistor region 73 between the first transistor region 72 and the boundary region 74 of the transistor section 70 .

[0124] The second transistor region 73 and the boundary region 74 are interposed between the first transistor region 72 and the diode section 80, thereby increasing the distance between the first transistor region 72 and the diode section 80 and suppressing hole injection from the first transistor region 72 to the diode section 80. As described above, the semiconductor device according to the example has a smaller reverse recovery peak current Irp and a shorter time until the current reaches zero than the semiconductor device according to the comparative example, thereby reducing reverse recovery loss.

[0125] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0126] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0127] 10 semiconductor substrate, 12 emitter region, 14 first base region, 15 contact region, 16 accumulation region, 17 well region, 18 drift region, 20 buffer region, 21 front surface, 22 collector region, 23 back surface, 24 collector electrode, 25a connection portion, 25b connection portion, 29 extension portion, 30 dummy trench portion, 31 connection portion, 32 dummy insulating film, 34 dummy conductive portion, 38 interlayer insulating film, 39 extension portion, 40 gate trench portion, 41 connection portion, 42 gate insulating film, 44 gate Conductive portion, 50... gate wiring layer, 52... emitter electrode, 54... contact hole, 55... contact hole, 56... contact hole, 70... transistor portion, 71... mesa portion, 72... first transistor region, 73... second transistor region, 74... boundary region, 80... diode portion, 81... mesa portion, 82... cathode region, 83... second cathode region, 84... second base region, 100... semiconductor device, 160... active region, 162... edge termination structure portion, 163... pad region, 200... semiconductor device, 300... semiconductor device, 1100... semiconductor device

Claims

1. A semiconductor device including a semiconductor substrate having a transistor portion and a diode portion and having a plurality of trench portions, The semiconductor substrate is a drift region of a first conductivity type; a second conductivity type base region provided above the drift region; an emitter region of a first conductivity type provided above the base region and having a doping concentration higher than that of the drift region; a second conductivity type contact region provided above the base region and having a doping concentration higher than that of the base region; and The transistor section a first transistor region; a second transistor region provided between the first transistor region and the diode portion; and On the front surface of the semiconductor substrate, the area of ​​the contact region in the second transistor region is smaller than the area of ​​the contact region in the first transistor region. Semiconductor device.

2. In the first transistor region, the base region is not exposed on the front surface of the semiconductor substrate. The semiconductor device according to claim 1 .

3. The area of ​​the emitter region in the second transistor region is larger than the area of ​​the emitter region in the first transistor region. The semiconductor device according to claim 1 .

4. A semiconductor device having a transistor portion and a diode portion, and including a semiconductor substrate on which a plurality of trench portions are provided, The semiconductor substrate is a drift region of a first conductivity type; a second conductivity type base region provided above the drift region; an emitter region of a first conductivity type provided above the base region and having a doping concentration higher than that of the drift region; a second conductivity type contact region provided above the base region and having a doping concentration higher than that of the base region; and The transistor section a first transistor region; a second transistor region provided between the first transistor region and the diode portion; and The area of ​​the emitter region in the second transistor region is larger than the area of ​​the emitter region in the first transistor region. Semiconductor device.

5. In the first transistor region, the base region is exposed on the front surface of the semiconductor substrate. The semiconductor device according to claim 1 .

6. The contact region is sandwiched between the base regions on the front surface of the semiconductor substrate in the first transistor region. The semiconductor device according to claim 3 .

7. The length of the contact region in the second transistor region in the trench extension direction is shorter than the length of the contact region in the first transistor region aligned in the trench arrangement direction in the trench extension direction. The semiconductor device according to claim 1 .

8. A semiconductor device having a transistor portion and a diode portion, and including a semiconductor substrate on which a plurality of trench portions are provided, The semiconductor substrate is a drift region of a first conductivity type; a second conductivity type base region provided above the drift region; an emitter region of a first conductivity type provided above the base region and having a doping concentration higher than that of the drift region; a second conductivity type contact region provided above the base region and having a doping concentration higher than that of the base region; and The transistor section a first transistor region; a second transistor region provided between the first transistor region and the diode portion; and The length of the contact region in the second transistor region in the trench extension direction is shorter than the length of the contact region in the first transistor region aligned in the trench arrangement direction in the trench extension direction. Semiconductor device.

9. The diode portion has a mesa portion on the front surface of the semiconductor substrate, the contact region having an area smaller than the first transistor region and the second transistor region.

9. The semiconductor device according to claim 1.

10. The base region has a first base region provided in the first transistor region and a second base region having a doping concentration lower than that of the first base region. The semiconductor device according to claim 1 .

11. The transistor portion has a boundary region provided between the second transistor region including the second base region and the diode portion. The semiconductor device according to claim 10.

12. the first base region is provided in the first transistor region and the second transistor region; The second base region is provided in the boundary region and the diode portion. The semiconductor device according to claim 11.

13. In the trench arrangement direction, the width of the second transistor region is narrower than the width of the boundary region. The semiconductor device according to claim 11.

14. The semiconductor substrate has an accumulation region of a first conductivity type that is more highly doped than the drift region. The semiconductor device according to claim 11.

15. The accumulation region is provided in the transistor portion. The semiconductor device according to claim 14.

16. The accumulation region is provided in the second transistor region but not in the boundary region. The semiconductor device according to claim 15.

17. the plurality of trench portions include gate trench portions and dummy trench portions; At least one gate trench portion is provided in the second transistor region. The semiconductor device according to claim 1 .

18. The boundary region and the diode portion have a lifetime control region including a lifetime killer on the front surface side of the semiconductor substrate. The semiconductor device according to claim 11.

19. the diode portion has the contact region and the second base region, In the boundary region and the diode portion, the contact region is provided between the second base regions. The semiconductor device according to claim 11.

20. the transistor portion further includes a collector region of a second conductivity type provided on a rear surface of the semiconductor substrate, The diode section a first cathode region of a first conductivity type provided on a rear surface of the semiconductor substrate; a second cathode region of a second conductivity type provided on the rear surface of the semiconductor substrate and having an area smaller than that of the first cathode region; Further having The semiconductor device according to claim 1 .

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