Image sensor

Abstract

To provide an image sensor.SOLUTION: An image sensor includes: a dual vertical gate including two vertical portions apart from each other by an isolation area in a first direction and vertically extending into a substrate, and a connection portion located on the upper parts of the two vertical portions and configured to connect the two vertical portions to each other; and a device isolation film disposed on side surfaces of the vertical portions in the first direction. Each of the two vertical portions includes an upper vertical portion and a lower vertical portion. A sidewall of the upper vertical portion forms a first inclination angle with a line extending in the first direction. A sidewall of the lower vertical portion forms a second inclination angle with the line extending in the first direction. The first inclination angle is different from the second inclination angle.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to image sensors, and more particularly to image sensors including dual vertical gates. [Background technology]

[0002] An image sensor converts an optical image into an electrical signal. Commonly used image sensors include a charge coupled device (CCD) type image sensor and a complementary metal oxide semiconductor (CMOS) type image sensor (CIS). Such an image sensor includes a plurality of pixels arranged in a two-dimensional matrix form, and each pixel outputs an image signal from optical energy. Each of the plurality of pixels accumulates photoelectric charges corresponding to the amount of light incident through a photoelectric conversion element, and outputs a pixel signal based on the accumulated photoelectric charges. Recently, as the integration degree of image sensors has increased significantly, the size of pixels has become smaller, and the size of components of pixel circuits has also become smaller. Accordingly, image sensors including a vertical gate structure have been developed. Summary of the Invention [Problem to be solved by the invention]

[0003] The problem to be solved by the present invention is to provide an image sensor including a dual vertical gate that can be formed in a fine pixel area, has improved interface characteristics and noise characteristics, and can prevent misalignment. [Means for solving the problem]

[0004] In order to solve the above-mentioned problems, the technical idea of ​​the present invention provides an image sensor including: two vertical portions spaced from each other in a first direction by an isolation region and extending into a substrate along a second direction perpendicular to the first direction; a dual vertical gate including a connecting portion located on top of the two vertical portions and connecting the two vertical portions to each other; and an isolation layer disposed on a side of the vertical portions in the first direction, each of the two vertical portions including an upper vertical portion and a lower vertical portion, a sidewall of the upper vertical portion and a line extending along the first direction form a first inclination angle, and a sidewall of the lower vertical portion and a line extending along the first direction form a second inclination angle, the first inclination angle and the second inclination angle being different from each other.

[0005] In order to achieve the above object, a technical idea of ​​the present invention provides an image sensor including: a substrate; a dual vertical gate disposed in an upper portion of the substrate; a photoelectric conversion element disposed inside the substrate and below the dual vertical gate; an isolation layer disposed adjacent to the dual vertical gate in a first direction parallel to an upper surface of the substrate; and a floating diffusion region disposed in an upper portion of the substrate adjacent to the dual vertical gate, wherein the dual vertical gate includes two vertical portions spaced apart from each other in the first direction by an isolation region and extending into the substrate along a second direction perpendicular to the first direction, and a connecting portion connecting the two vertical portions to each other at upper portions of the two vertical portions, each of the two vertical portions including an upper vertical portion and a lower vertical portion, a sidewall of the upper vertical portion and a line extending along the first direction form a first inclination angle, and a sidewall of the lower vertical portion and a line extending along the first direction form a second inclination angle, the first inclination angle and the second inclination angle being different from each other.

[0006] In order to achieve the above object, the technical idea of ​​the present invention includes a substrate, a dual vertical gate disposed in an upper portion of the substrate, a gate insulating film surrounding at least a portion of the dual vertical gate, a photoelectric conversion element disposed in the substrate below the dual vertical gate, an element isolation film disposed in the upper portion of the substrate adjacent to the dual vertical gate in a first direction parallel to an upper surface of the substrate, and a floating diffusion region disposed in the upper portion of the substrate adjacent to the dual vertical gate, the dual vertical gates being spaced apart from each other in the first direction by an isolation film and extending in the substrate along a second direction perpendicular to the first direction. a connecting portion connecting the two vertical portions to each other at an upper portion of the device isolation layer, each of the two vertical portions including an upper vertical portion and a lower vertical portion, a sidewall of the upper vertical portion and a line extending in the first direction form a first inclination angle, a sidewall of the lower vertical portion and a line extending in the first direction form a second inclination angle different from the first inclination angle, an upper surface of the upper vertical portion is located at the same vertical level as an upper surface of the device isolation layer, a lower surface of the upper vertical portion is located at the same vertical level as a lower surface of the device isolation layer, and the upper vertical portion is in contact with the device isolation layer. [Brief description of the drawings]

[0007] [Figure 1] 1 is a block diagram illustrating an image sensor according to an exemplary embodiment of the present invention; [Diagram 2] 1 is a circuit diagram of a pixel array of an image sensor according to an exemplary embodiment of the present invention. [Diagram 3] FIG. 2 is a plan view illustrating a pixel of an image sensor according to an exemplary embodiment of the invention. [Figure 4] FIG. 4 is a cross-sectional view taken along line AA' in FIG. [Figure 5A] FIG. 1 illustrates a cross-sectional view of a dual vertical gate according to an exemplary embodiment of the present invention. [Figure 5B] FIG. 1 illustrates a cross-sectional view of a dual vertical gate according to an exemplary embodiment of the present invention. [Figure 5C] FIG. 1 illustrates a cross-sectional view of a dual vertical gate according to an exemplary embodiment of the present invention. [Figure 5D] FIG. 1 illustrates a cross-sectional view of a dual vertical gate according to an exemplary embodiment of the present invention. [Figure 5E] FIG. 1 illustrates a cross-sectional view of a dual vertical gate according to an exemplary embodiment of the present invention. [Figure 6A] FIG. 2 is a plan view illustrating a pixel of an image sensor according to an exemplary embodiment of the invention. [Figure 6B] FIG. 2 is a plan view illustrating a pixel of an image sensor according to an exemplary embodiment of the invention. [Figure 6C] FIG. 2 is a plan view illustrating a pixel of an image sensor according to an exemplary embodiment of the invention. [Figure 7A] 1A-1D are cross-sectional views illustrating stages in a method for fabricating a dual vertical gate according to an exemplary embodiment of the present invention. [Figure 7B] 1A-1D are cross-sectional views illustrating stages in a method for fabricating a dual vertical gate according to an exemplary embodiment of the present invention. [Figure 7C] 1A-1D are cross-sectional views illustrating stages in a method for fabricating a dual vertical gate according to an exemplary embodiment of the present invention. [Figure 7D] 1A-1D are cross-sectional views illustrating stages in a method for fabricating a dual vertical gate according to an exemplary embodiment of the present invention. [Figure 7E] 1A-1D are cross-sectional views illustrating stages in a method for fabricating a dual vertical gate according to an exemplary embodiment of the present invention. [Figure 7F] 1A-1D are cross-sectional views illustrating stages in a method for fabricating a dual vertical gate according to an exemplary embodiment of the present invention. [Figure 7G] 1A-1D are cross-sectional views illustrating stages in a method for fabricating a dual vertical gate according to an exemplary embodiment of the present invention. [Figure 8A] FIG. 1 is a block diagram illustrating an electronic system according to an exemplary embodiment of the present invention. [Figure 8B] FIG. 8B is a detailed block diagram showing a camera module included in the electronic system of FIG. 8A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to refer to the same components, and redundant description thereof will be omitted.

[0009] FIG. 1 is a block diagram illustrating an image sensor according to an exemplary embodiment of the present invention.

[0010] 1, an image sensor 100 according to an exemplary embodiment of the present invention may include a pixel array 10 and a circuit for controlling the pixel array 10. In an exemplary embodiment, the circuit for controlling the pixel array 10 may include a column driver 20, a row driver 30, a timing controller 40, and a readout circuit 50.

[0011] The image sensor 100 may be operated according to a control command received from the image processor 70, and may convert light transmitted from an external object into an electrical signal and output the electrical signal to the image processor 70. The image sensor 100 may be a CMOS image sensor.

[0012] The pixel array 10 includes a plurality of unit pixels PXU having a two-dimensional array structure arranged in a matrix form along a plurality of row lines and a plurality of column lines.

[0013] Each of the unit pixels PXU includes a photoelectric conversion element. The photoelectric conversion element may receive light transmitted from the object and generate an electric charge. The image sensor 100 may perform an autofocus function using a phase difference between pixel signals generated from the photoelectric conversion elements included in the unit pixels PXU. Each of the unit pixels PXU may include a pixel circuit for generating a pixel signal from an electric charge generated in the photoelectric conversion element.

[0014] The column driver 20 includes a correlated double sampler (CDS), an analog-to-digital converter (ADC), etc. The correlated double sampler is connected to a unit pixel PXU included in a row selected by a row selection signal supplied by the row driver 30 through a column line, and performs correlated double sampling to detect a reset voltage and a pixel voltage. The analog-to-digital converter converts the reset voltage and the pixel voltage detected by the correlated double sampler into digital signals and transmits them to a readout circuit 50.

[0015] The readout circuit 50 includes a latch or buffer circuit capable of temporarily storing a digital signal, an amplifier circuit, etc., and can temporarily store or amplify the digital signal received from the column driver 20 to generate image data. The operation timing of the column driver 20, the row driver 30, and the readout circuit 50 is determined by the timing controller 40, and the timing controller 40 can operate according to a control command transmitted by the image processor 70.

[0016] The image processor 70 may process the image data output by the readout circuit 50 and output it to a display device or store it in a storage device such as a memory. When the image sensor 100 is mounted on an autonomous vehicle, the image processor 70 may process the image data and transmit it to a main controller that controls the autonomous vehicle.

[0017] FIG. 2 is a circuit diagram of a pixel array of an image sensor in accordance with an exemplary embodiment of the invention.

[0018] Referring to FIG. 2, a unit pixel PXU including a transfer transistor TX and logic transistors RX, SX, and SFX is shown in the form of an array.

[0019] A plurality of unit pixels PXU may be arranged. In an exemplary embodiment, a plurality of unit pixels PXU may be arranged in a matrix form. Here, the logic transistor may include a reset transistor RX, a selection transistor SX, and a source follower transistor SFX. The reset transistor RX includes a reset gate RG, and the selection transistor SX includes a selection gate SG. In addition, in an exemplary embodiment of the present invention, the transfer transistor TX may include a dual vertical gate 110 (see FIG. 3). The transfer transistor TX and the dual vertical gate 110 will be described in more detail below with reference to FIGS. 3 and 4.

[0020] The unit pixel PXU includes a photoelectric conversion element PD and a floating diffusion region FD. The photoelectric conversion element PD can generate and accumulate photocharges in proportion to the amount of light incident from the outside, and can be a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), or a combination thereof.

[0021] The transfer transistor TX can transfer the photocharge generated in the photoelectric conversion element PD to the floating diffusion region FD. The floating diffusion region FD can receive the photocharge generated in the photoelectric conversion element PD and store it cumulatively. The source follower transistor SFX is controlled by the amount of the photocharge accumulated in the floating diffusion region FD.

[0022] The reset transistor RX can periodically reset the photocharges accumulated in the floating diffusion region FD. A drain electrode of the reset transistor RX is connected to the floating diffusion region FD, and a source electrode of the reset transistor RX is connected to a power supply voltage V DD can be linked to

[0023] When the reset transistor RX is turned on, the power supply voltage V DD may be transferred to the floating diffusion region FD. When the reset transistor RX is turned on, photocharges accumulated in the floating diffusion region FD may be discharged and the floating diffusion region FD may be reset.

[0024] The source follower transistor SFX is connected to a current source (not shown) located outside the unit pixel PXU and can function as a source follower buffer amplifier, amplifying the potential change in the floating diffusion region FD and outputting it to the output line V OUT can be output to.

[0025] The selection transistor SX can select a plurality of unit pixels PXU in units of a row. When the selection transistor SX is turned on, a power supply voltage V DD can be transmitted to the source electrode of the source follower transistor SFX.

[0026] 3 is a plan view of a pixel of an image sensor according to an exemplary embodiment of the present invention, and FIG 4 is a cross-sectional view taken along line AA' of FIG 3.

[0027] 3 and 4, the image sensor 100 includes a substrate 101 having a pixel region PX. Although one pixel region PX is illustrated in FIG. 3, the substrate 101 may include a plurality of pixel regions PX. In the substrate 101, the pixel region PX may be defined by a pixel isolation film 130. The pixel region PX may include a photoelectric conversion element PD formed in the substrate 101. The pixel region PX may be a region that senses light incident from the outside.

[0028] The substrate 101 includes a semiconductor layer. In an exemplary embodiment, the substrate 101 may include a semiconductor layer doped with a P-type impurity. For example, the substrate 101 may include a semiconductor layer made of Si, Ge, SiGe, a II-VI compound semiconductor, a III-V compound semiconductor, or a combination thereof, or a silicon on insulator (SOI) substrate. In an exemplary embodiment, the substrate 101 may also include a P-type epitaxial semiconductor layer epitaxially grown from a P-type bulk silicon substrate. The substrate 101 may include a front surface 101A and a back surface 101B opposite the front surface 101A.

[0029] The pixel isolation film 130 may have a planar structure surrounding the photoelectric conversion element PD. The pixel isolation film 130 extends in the thickness direction of the substrate 101 from the front surface 101A to the rear surface 101B of the substrate 101. In an exemplary embodiment, the pixel isolation film 130 may include silicon oxide, silicon nitride, SiCN, SiON, SiOC, polysilicon, metal, metal nitride, metal oxide, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma enhanced tetraethyl orthosilicate (PE-TEOS), fluoride silicate glass (FSG), carbon doped silicon oxide (CDO), organosilicate glass (OSG), air, or a combination thereof. For example, the metal included in the pixel isolation film 130 may be tungsten (W), copper (Cu), or a combination thereof. The metal nitride included in the pixel isolation film 130 may be TiN, TaN, or a combination thereof. The metal oxide contained in the pixel separation film 130 is ITO (indium tin oxide), aluminum oxide (Al 2 O 3 ) or a combination thereof.

[0030] The pixel isolation layer 130 may have various shapes. For example, the pixel isolation layer 130 may not completely penetrate the substrate 101. In addition, the pixel isolation layer 130 may have a structure penetrating the device isolation layer 120, or may have a structure contacting the lower surface of the device isolation layer 120 without penetrating the device isolation layer 120.

[0031] An isolation layer 120 defining a plurality of active regions AC1, AC2, and AC3 may be disposed on the front surface 101A of the substrate 101. The plurality of active regions AC1, AC2, and AC3 may include a first active region AC1, a second active region AC2, and a third active region AC3. A lower surface of the isolation layer 120 may be vertically spaced apart from the photoelectric conversion element PD. A depth of the isolation layer 120 is shallower than a depth of the pixel isolation layer 130. In an exemplary embodiment, the isolation layer 120 may be an insulating layer including a silicon oxide layer, a silicon nitride layer, or a combination thereof.

[0032] In a plan view (XY plane), the first active region AC1 may have a T-shape, the second active region AC2 may have an L-shape, and the third active region AC3 may have a rectangular shape. However, the shapes are not limited thereto, and the first to third active regions AC1, AC2, and AC3 may have various shapes. For example, the second active region AC2 may have a rectangular shape extending long along one horizontal direction.

[0033] A transfer transistor TX (see FIG. 2) and a floating diffusion region FD may be disposed in the first active region AC1. The transfer transistor TX may include a dual vertical gate 110.

[0034] The dual vertical gate 110 may include a connecting portion 111 and two vertical portions 113. The dual vertical gate 110 may have different shapes depending on the vertical level on the XY plane. Specifically, on the XY plane, the dual vertical gate 110 may have one rectangular shape at a vertical level higher than the top surface of the isolation region SA1, and may have two rectangular shapes spaced apart from each other in a first direction (X direction) at a vertical level lower than the top surface of the isolation region SA1.

[0035] The two vertical portions 113 may each extend vertically into the substrate 101 and be separated from each other in a first direction (X-direction) by an isolation region SA1, where vertical means a second direction (Z-direction) perpendicular to the top surface of the substrate 101. The isolation region SA1 refers to a portion of the semiconductor substrate 101 that is covered by the dual vertical gate 110 and is disposed between the two vertical portions 113.

[0036] Two trenches 113T may be disposed in the semiconductor substrate 101, spaced apart from each other with an isolation region SA1 therebetween, and two vertical portions 113 may be disposed in each of the two trenches 113T. The isolation region SA1 of the semiconductor substrate 101 may be exposed at first sidewalls facing each other of the two trenches 113T, and the device isolation film 120 may be exposed at least in a portion of a second sidewall opposite to the first sidewall of the two trenches (e.g., on an upper side of the second sidewall).

[0037] Each of the two vertical portions 113 may include an upper vertical portion 113U and a lower vertical portion 113D. The upper vertical portion 113U is disposed on the lower vertical portion 113D, and the upper vertical portion 113U and the lower vertical portion 113D may be in contact with each other. That is, the lower surface of the upper vertical portion 113U may be in contact with the upper surface of the lower vertical portion 113D. The length h2 of the upper vertical portion 113U in the second direction may be substantially equal to the length h1 of the device isolation film 120 in the second direction. That is, the upper surface of the upper vertical portion 113U may be located at the same vertical level as the upper surface of the device isolation film 120, and the lower surface of the upper vertical portion 113U may be located at the same vertical level as the lower surface of the device isolation film 120. In an exemplary embodiment, the upper surface of the lower vertical portion 113D may be located at the same vertical level as the lower surface of the device isolation film 120.

[0038] A sidewall of the upper vertical portion 113U may form a first inclination angle θ1 with a virtual line parallel to the first direction (x direction). A sidewall of the lower vertical portion 113D may form a second inclination angle θ2 with a virtual line parallel to the first direction (x direction). In this case, the first inclination angle θ1 and the second inclination angle θ2 are different from each other. Such a difference in inclination angle may occur because the dual vertical gate 110 is formed by performing two etching processes, as described below with reference to FIGS. 7A and 7G. In an exemplary embodiment, the first inclination angle θ1 is 90°, and the second inclination angle θ2 is smaller than the first inclination angle θ1. Such a difference in inclination angle can occur by first forming the upper side of a rectangular trench 113T having sidewalls that form a first inclination angle θ1 with an imaginary line parallel to the first direction (x direction) through a precision etching process, and then forming the lower side of trench 113T, which becomes narrower toward the bottom, having sidewalls that form a second inclination angle θ2 with an imaginary line parallel to the first direction (x direction) through a general etching process.

[0039] The connecting portion 111 may connect the two vertical portions 113 at the top of the two vertical portions 113. The connecting portion 111 may include a first region S1 overlapping with the vertical portion 113 in a second direction (z direction) and a second region S2 which is a remaining region excluding the first region. In an exemplary embodiment, an upper surface of the connecting portion 111 may be located at a higher level than an upper surface of the isolation film 120. In an exemplary embodiment, a lower surface of the second region S2 of the connecting portion 111 may be located at a higher vertical level than a lower surface of the first region S1 of the connecting portion 111.

[0040] Various embodiments of the dual vertical gate 110 will now be described in more detail with reference to FIGS. 5A-5E.

[0041] 5A to 5E are cross-sectional views showing a dual vertical gate according to an exemplary embodiment of the present invention. Specifically, FIG. 5A to 5E are enlarged cross-sectional views of a region corresponding to region B in FIG. 4. Each configuration in FIG. 5A to 5E is similar to each configuration of image sensor 100 described with reference to FIG. 4, so the following description will focus on the differences.

[0042] 5A, the dual vertical gate 110a also includes a connecting portion 111a and a vertical portion 113a. The vertical portion 113a may include an upper vertical portion 113Ua and a lower vertical portion 113Da. A sidewall of the upper vertical portion 113Ua may form a first tilt angle θ1a with a virtual line parallel to a first direction (x direction). A sidewall of the lower vertical portion 113Da may form a second tilt angle θ2a with a virtual line parallel to the first direction (x direction). In an exemplary embodiment, the second tilt angle θ2a is 90°, and the first tilt angle θ1a is smaller than the second tilt angle θ2a. Such a difference in the inclination angle may occur by first forming a trench having a shape that narrows toward the bottom and has sidewalls that form a first inclination angle θ1 with an imaginary line parallel to the first direction (x direction) through a general etching process, and then forming a rectangular trench having sidewalls that form a second inclination angle θ2 with an imaginary line parallel to the first direction (x direction) through a precision etching process. The shape of the isolation region SA1a is different from that of the isolation region SA1 shown in FIG. 4 due to the first inclination angle θ1a and the second inclination angle θ2a.

[0043] 5B, the dual vertical gate 110b may include a connecting portion 111b and a vertical portion 113b. The vertical portion 113b may include an upper vertical portion 113Ub and a lower vertical portion 113Db. A sidewall of the upper vertical portion 113Ub may form a first inclination angle θ1b with a virtual line parallel to the first direction (x direction). A sidewall of the lower vertical portion 113Db may form a second inclination angle θ2b with a virtual line parallel to the first direction (x direction). In an exemplary embodiment, the first inclination angle θ1b is greater than the second inclination angle θ2b. Due to the first inclination angle θ1b and the second inclination angle θ2b, the shape of the separation region SA1b is different from that of the separation region SA1 shown in FIG. 4.

[0044] 5C, the dual vertical gate 110c may include a connecting portion 111c and a vertical portion 113c. The vertical portion 113c may include an upper vertical portion 113Uc and a lower vertical portion 113Dc. A sidewall of the upper vertical portion 113Uc may form a first inclination angle θ1c with a virtual line parallel to the first direction (x direction). A sidewall of the lower vertical portion 113Dc may form a second inclination angle θ2c with a virtual line parallel to the first direction (x direction). In an exemplary embodiment, the first inclination angle θ1c is smaller than the second inclination angle θ2c. Due to the first inclination angle θ1c and the second inclination angle θ2c, the shape of the separation region SA1c is different from that of the separation region SA1 shown in FIG. 4.

[0045] 5D, the dual vertical gate 110d may include a connection portion 111d and a vertical portion 113d. The vertical portion 113d may include an upper vertical portion 113Ud and a lower vertical portion 113Dd. Of the sidewalls of the upper vertical portion 113Ud, a sidewall adjacent to the isolation film 120 may form a first inclination angle θ1d with an imaginary line parallel to the first direction (X direction), and of the sidewalls of the upper vertical portion 113Ud, a sidewall adjacent to the isolation region SA1d may form a third inclination angle θ3d with an imaginary line parallel to the first direction (X direction). Among the sidewalls of the lower vertical portion 113Dd, a sidewall adjacent to the isolation film 120 may form a second inclination angle θ2d with a virtual line parallel to the first direction (X direction), and among the sidewalls of the lower vertical portion 113Dd, a sidewall adjacent to the isolation region SA1d may form a fourth inclination angle θ4d with a virtual line parallel to the first direction (X direction). In an exemplary embodiment, the first inclination angle θ1d and the third inclination angle θ3d may be different from each other, and the second inclination angle θ2d and the fourth inclination angle θ4d may be the same from each other. In another exemplary embodiment, the first inclination angle θ1d and the third inclination angle θ3d may be the same from each other, and the second inclination angle θ2d and the fourth inclination angle θ4d may be different from each other. The shape of the separation region SA1d is different from that of the separation region SA1 shown in FIG. 4 due to the first inclination angle θ1d, the second inclination angle θ2d, the third inclination angle θ3d, and the fourth inclination angle θ4d.

[0046] 5E, the dual vertical gate 110e may include a connecting portion 111e and a vertical portion 113e. The vertical portion 113e may include an upper vertical portion 113Ue and a lower vertical portion 113De. Of the sidewalls of the upper vertical portion 113Ue, a sidewall adjacent to the isolation film 120 may form a first inclination angle θ1e with an imaginary line parallel to the first direction (X direction), and of the sidewalls of the upper vertical portion 113Ue, a sidewall adjacent to the isolation region SA1e may form a third inclination angle θ3e with an imaginary line parallel to the first direction (X direction). Among the sidewalls of the lower vertical portion 113De, a sidewall adjacent to the isolation film 120 may form a second inclination angle θ2e with a virtual line parallel to the first direction (X direction), and among the sidewalls of the lower vertical portion 113De, a sidewall adjacent to the isolation region SA1e may form a fourth inclination angle θ4e with a virtual line parallel to the first direction (X direction). In an exemplary embodiment, the first inclination angle θ1e and the third inclination angle θ3e may be different from each other, and the second inclination angle θ2e and the fourth inclination angle θ4e may also be different from each other. Due to the first inclination angle θ1e, the second inclination angle θ2e, the third inclination angle θ3e, and the fourth inclination angle θ4e, the shape of the isolation region SA1e is different from that of the isolation region SA1 shown in FIG.

[0047] In FIGS. 4 and 5A to 5E, the connecting portions 111a to 111e and the vertical portions 113a to 113e may be formed of the same material and may be integrally joined together.

[0048] Each of the image sensors 100, 100a, 100b, 100c, 100d, and 100e according to the exemplary embodiment of the present invention includes a dual vertical gate 110, 110a, 110b, 110c, 110d, and 110e including upper and lower vertical portions whose sidewalls have different inclination angles with respect to a line extending along a first direction (X direction). As described below with reference to Figures 7A and 7G, the dual vertical gate 110 is formed using a photoresist pattern PR2 having only one opening, so that a smaller dual vertical gate can be formed compared to a case where the dual vertical gate is formed using a photoresist pattern having two openings, and therefore, the pixel area can be miniaturized. In addition, since trenches T1 and T2 are formed in the process of forming the device isolation film 120 through a dual STI (shallow trench isolation) process, etching of the substrate 101 can be minimized compared to the conventional method, and interface characteristics and noise of the dual vertical gate 110 can be improved.

[0049] 3 and 4, the isolation region SA1 may be disposed between two vertical portions 113. In an exemplary embodiment, the top surface of the isolation region SA1 may be located at the same vertical level as the top surface of the device isolation film 120. In the XZ plane, the shape of the isolation region SA1 may vary depending on a first tilt angle θ1 and a second tilt angle θ2. The isolation region SA1 also extends in a third direction (Y direction) perpendicular to the first direction (X direction) and the second direction (Z direction). In this case, in the XY plane, the shape of the isolation region SA1 may be rectangular. Hereinafter, various embodiments of the isolation region will be described with reference to FIGS. 6A to 6C.

[0050] 6A to 6C are plan views showing pixels of an image sensor according to an exemplary embodiment of the present invention. Since the configurations of Fig. 6A to 6C are similar to the configurations of the image sensor 100 described with reference to Fig. 3, the following description will focus on the differences.

[0051] 6A, in an exemplary embodiment, the isolation region SA2 may have a T-shape on the XY plane, in which case the area between the dual vertical gate 110 and the semiconductor substrate 101 in the first active region AC1, i.e., the area of ​​the channel region, may be increased, and the transfer characteristics of the image sensor 100f may be improved.

[0052] 6B, in another exemplary embodiment, the isolation region SA3 may have a trapezoidal shape on the XY plane. Similarly, in this case, the area between the dual vertical gate 110 and the semiconductor substrate 101 in the first active region AC1, i.e., the area of ​​the channel region, may be increased, and the transfer characteristics of the image sensor 100g may be improved.

[0053] In yet another exemplary embodiment, referring to FIG. 6C, the isolation region SA4 may have a rectangular shape on the XY plane. Unlike the isolation region SA1 shown in FIG. 3, the length of the isolation region SA4 shown in FIG. 6C in the third direction (Y direction) is shorter than the length of the dual vertical gate 110 in the third direction (Y direction). In this case, unlike the image sensor 100 shown in FIG. 3, the number of contact surfaces between the dual vertical gate 110 and the semiconductor substrate 101 in the first active region AC1 of the image sensor 100h in FIG. 6 is three. Therefore, the area between the dual vertical gate 110 and the semiconductor substrate 101 in the first active region AC1, i.e., the area of ​​the channel region, is increased, and the transfer characteristics of the image sensor 100g may be improved.

[0054] 4, on the other hand, a gate insulating layer 115 is disposed between the isolation region SA1 and the dual vertical gate 110. The gate insulating layer 115 may be, for example, silicon oxide.

[0055] A logic transistor may be disposed in the second active region AC2. For example, at least one of a reset transistor RX, a source follower transistor SFX, and a selection transistor SX may be disposed in the second active region AC2. In another example, all three transistors may be disposed in the second active region AC2. Also, according to an embodiment, a source follower transistor SFX and a selection transistor SX may be disposed in the second active region AC2 of one pixel region PX, and a reset transistor RX may be disposed in the second active region AC2 of another adjacent pixel region PX. In such a structure, two adjacent pixel regions PX can share a logic transistor. A pixel gate PXG may be disposed in the second active region AC2. The pixel gate PXG may be, for example, a reset gate RG (see FIG. 2) or a selection gate SG (see FIG. 2). A contact plug 141 may be disposed in the second active region AC2. The contact plug 141 may be a power supply voltage contact plug.

[0056] The third active region AC3 includes an impurity region (not shown), and the impurity region of the third active region AC3 is connected to a contact plug 143. The impurity region of the third active region AC3 may be a ground region, and the contact plug 143 connected to the impurity region may be a ground contact plug.

[0057] On the front surface 101A of the substrate 101, the plurality of transistors TX, RX, SX, SFX and the element isolation film 120 may be covered by a wiring structure 150. An electrical signal converted by the photoelectric conversion element PD may be processed in the plurality of transistors TX, RX, SX, SFX and the wiring structure 150 arranged on the front surface 101A of the substrate 101. The wiring structure 150 may include a plurality of contact plugs 161 selectively connected to the plurality of transistors TX, RX, SX, SFX including the transfer transistor TX, a plurality of conductive lines 163, 165 configured to be selectively connected to the plurality of transistors via the contact plugs 161, and a plurality of interlayer insulating films 151, 153, 155 covering the plurality of conductive lines 163, 165.

[0058] The contact plugs 161 and the conductive lines 163, 165 may each include a metal, a conductive metal nitride, or a combination thereof. For example, the contact plugs 161 and the conductive lines 163, 165 may each include, but are not limited to, Cu, Al, W, Ti, Mo, Ta, TiN, TaN, ZrN, WN, or a combination thereof. The interlayer insulating films 151, 153, 155 may each include an oxide film, a nitride film, or a combination thereof.

[0059] The number and arrangement of the interlayer insulating films 151, 153, 155 and the conductive lines 163, 165 are not limited to those shown in Fig. 4 and may be modified or changed in various ways as necessary. The conductive lines 163, 165 included in the wiring structure 150 may include wiring connected to a plurality of transistors electrically connected to the photoelectric conversion elements PD formed in the pixel region PX. The conductive lines 163, 165 may be freely arranged regardless of the arrangement of the photoelectric conversion elements PD (e.g., photodiodes).

[0060] On the rear surface 101B of the substrate 101, an anti-reflection film 170, a color filter CF, and a microlens ML may be laminated in this order.

[0061] The anti-reflection film 170 may prevent incident light passing through the color filter CF from being reflected or scattered to the side. The anti-reflection film 170 may include a metal. For example, the anti-reflection film 170 may include W, Al, Cu, or a combination thereof. Unlike the example shown in FIG. 4, the anti-reflection film 170 may include a plurality of layers. For example, the anti-reflection film 170 may include a first anti-reflection layer (not shown), a second anti-reflection layer (not shown), and a third anti-reflection layer (not shown). The first anti-reflection layer, the second anti-reflection layer, and the third anti-reflection layer may each include the same metal. For example, the first anti-reflection layer, the second anti-reflection layer, and the third anti-reflection layer may each include W. However, the present invention is not limited thereto, and the first anti-reflection layer, the second anti-reflection layer, and the third anti-reflection layer may each include different metals.

[0062] The color filter CF can filter the collected light and provide it to the pixel region PX. In an exemplary embodiment, the color filter CF can include a red color filter, a green color filter, a blue color filter, or a white color filter. The white color filter can be a transparent color filter that transmits light in the visible light wavelength band. In other exemplary embodiments, the color filter CF can have other colors such as cyan, magenta, or yellow.

[0063] The microlens ML can condense incident light. The microlens ML is disposed to correspond to the photoelectric conversion element PD. The microlens ML can have an outwardly bulging shape so as to condense light incident on the photoelectric conversion element PD. The microlens ML can be transparent. For example, the microlens ML can have a transmittance of 90% or more for light in the visible light range. The microlens ML can be formed of a material such as a styrene-based resin, an acrylic-based resin, a styrene-acrylic copolymer-based resin, or a siloxane-based resin.

[0064] The substrate 101 of the image sensor 100 may further include a region in which a plurality of unit pixels PXU described with reference to FIG. 1 are arranged, a peripheral circuit region (not shown) arranged around the unit pixels PXU, and a pad region (not shown). The peripheral circuit region may be a region including various types of circuits for controlling a plurality of unit pixels PXU (see FIG. 1). For example, the peripheral circuit region may include a plurality of transistors. The plurality of transistors arranged in the peripheral circuit region may be driven to provide a certain signal to a photoelectric conversion element PD formed in the pixel region PX or to control an output signal from the photoelectric conversion element PD. For example, the plurality of transistors arranged in the peripheral circuit region may constitute various types of logic circuits such as a timing generator, a row decoder, a row driver, a CDS, an ADC, a latch unit, and a column decoder. The pad region may include conductive pads electrically connected to a plurality of unit pixels PXU and a circuit in the peripheral circuit region. The conductive pads can function as connection terminals for providing power and signals from the outside to a plurality of unit pixels PXU (see FIG. 1) and circuits in the peripheral circuit region.

[0065] 7A to 7G are cross-sectional views showing steps of a method for manufacturing a dual vertical gate according to an exemplary embodiment of the present invention. Although FIG. 7A to 7G describe a method for manufacturing a dual vertical gate based on the dual vertical gate 110 shown in FIG. 4, it will be apparent to those skilled in the art that various modifications and variations can be made within the scope of the technical concept of the present invention to manufacture the dual vertical gates 110a, 110b, 110c, 110d, and 110e described with reference to FIG. 5A to 5E.

[0066] 7A, an oxide film OL and a nitride film NL are sequentially formed on a substrate 101, and a photoresist pattern PR1 is formed on the nitride film NL. The photoresist pattern PR1 may have two openings.

[0067] Referring to FIG. 7B, a first etching process is then performed using a photoresist pattern PR1 (FIG. 7A) having two openings, to form a first trench T1 in the substrate 101. A sidewall of the first trench T1 may form a first inclination angle θ1 (see FIG. 4) with a line extending along a first direction (X direction). The first etching process may be, for example, a precision etching process. In this case, the first trench T1 may have a rectangular cross section with the first inclination angle θ1 of 90°.

[0068] 7C, a second photoresist pattern PR2 may be formed on the substrate 101. The second photoresist pattern PR2 may have only one opening. The opening may expose a portion of the two first trenches T1 and the substrate 101 located between the two first trenches T1. Even if the second photoresist pattern PR2 has only one opening, the oxide film OL and the nitride film NL remain on the substrate 101 located between the two first trenches T1, and the substrate 101 located between the two first trenches T1 may be protected in a second etching process described below with reference to FIG. 7D.

[0069] Referring to FIG. 7D, a second etching process may be performed using the second photoresist pattern PR2 to form a second trench T2. The second trench T2 may penetrate the substrate 101 deeper than the first trench T1. A sidewall of the second trench T2 may form a second inclination angle θ2 (see FIG. 4) with a line extending along the first direction (X direction). The second etching process may be, for example, a general etching process. In this case, the second trench T2 may have a trapezoidal cross section with the second inclination angle θ2 less than 90°.

[0070] 7E, the first trench T1 and the second trench T2 may be filled with an insulating material and then a portion of the insulating material may be etched to form an isolation layer 120. The insulating material may be, for example, silicon oxide.

[0071] 7F, a gate insulating film 115 may be formed on the inner walls of the trenches T1 and T2 on the substrate 101. The gate insulating film 115 may be, for example, silicon oxide.

[0072] Referring to FIG. 7G, the vertical portions 113U and 113D filling the trenches T1 and T2 and the connecting portion 111 connecting the vertical portions 113U and 113D at the top thereof may be formed to form a dual vertical gate 110.

[0073] When the dual vertical gate is formed using the photoresist pattern PR2 having only one opening, the dual vertical gate can be formed in a finer pixel region than when the dual vertical gate is formed using a photoresist pattern having two openings. This allows the pixel region to be miniaturized. In addition, since the trenches T1 and T2 are formed in the process of forming the device isolation film 120 using the dual STI process, etching of the substrate 101 is minimized compared to the conventional method, and the interface characteristics and noise of the dual vertical gate 110 can be improved. In addition, as described with reference to FIGS. 7C and 7D, when the second etching process is performed, the oxide film OL and the nitride film NL on the substrate 101 protect the substrate 101 located between the first trenches T1, so that the second trenches T2 are formed in a part of the first trenches T1 by a self-alignment method. This allows the misalignment problem occurring when performing the etching process to be improved.

[0074] FIG. 8A is a block diagram illustrating an electronic system according to an exemplary embodiment of the invention, and FIG. 8B is a detailed block diagram illustrating a camera module included in the electronic system of FIG. 8A.

[0075] Referring to FIG. 8A, the electronic system 1000 also includes a camera module group 1100, an application processor 1200, a power management integrated circuit (PMIC) 1300 and an external memory 1400.

[0076] The camera module group 1100 may include a plurality of camera modules 1100a, 1100b, and 1100c. Although the drawings show an embodiment in which three camera modules 1100a, 1100b, and 1100c are arranged, the technical idea of ​​the present invention is not limited thereto. In some embodiments, the camera module group 1100 may be modified to include only two camera modules. In some embodiments, the camera module group 1100 may be modified to include n camera modules (n is a natural number equal to or greater than 4).

[0077] The detailed configuration of camera module 1100b will be described in more detail below with reference to FIG. 8B, but the following description can also be similarly applied to other camera modules 1100a and 1100c depending on the embodiment.

[0078] Referring to FIG. 8B, the camera module 1100b also includes a prism 1105, an optical path folding element (OPFE) 1110, an actuator 1130, an image sensing device 1140 and a storage unit 1150.

[0079] The prism 1105 includes a reflecting surface 1107 made of a light reflecting material, and is capable of changing the path of light L incident from the outside.

[0080] In some embodiments, the prism 1105 can change the path of the light L incident in a first direction (X direction in FIG. 8B) to a third direction (Y direction in FIG. 8B) perpendicular to the first direction. The prism 1105 can rotate in the A direction about a central axis 1106 of a reflecting surface 1107 of a light reflecting material, or rotate the central axis 1106 in the B direction, to change the path of the light L incident in the first direction (X direction) to a perpendicular third direction (Y direction). At this time, the OPFE 1110 can also move in a second direction (Z direction in FIG. 8B) perpendicular to the first direction (X direction) and the third direction (Y direction).

[0081] In some embodiments, as shown in FIG. 8B, the maximum rotation angle of prism 1105 in the A direction is less than or equal to 15° in the positive (+) A direction and greater than 15° in the negative (-) A direction, although the technical concept of the present invention is not limited thereto.

[0082] In some embodiments, the prism 1105 can rotate in the plus (+) or minus (-) B direction by around 20°, or in a range of 10° to 20°, or 15° to 20°, where the rotation angle can be the same angle in the plus (+) or minus (-) B direction, or a similar angle in a range of around 1°.

[0083] In some embodiments, the prism 1105 can move the reflective surface 1107 of the light-reflective material in a second direction (eg, Z direction) parallel to the extension direction of the central axis 1106 .

[0084] The OPFE 1110 also includes optical lenses consisting of, for example, m groups (where m is a natural number). The m lenses can move in a third direction (Y direction) to change the optical zoom ratio of the camera module 1100b. For example, when the basic optical zoom ratio of the camera module 1100b is Z, when the m optical lenses included in the OPFE 1110 are moved, the optical zoom ratio of the camera module 1100b can be changed to an optical zoom ratio of 3Z, 5Z, or more.

[0085] The actuator 1130 can move the OPFE 1110 or an optical lens (hereinafter, referred to as the optical lens) to a specific position. For example, the actuator 1130 can adjust the position of the optical lens so that the image sensor 1142 is located at the focal length of the optical lens for accurate sensing.

[0086] The image sensing device 1140 also includes an image sensor 1142, a control logic 1144, and a memory 1146. The image sensor 1142 can sense an image of a sensing target using light L provided through an optical lens. The control logic 1144 can control the overall operation of the camera module 1100b. For example, the control logic 1144 can control the operation of the camera module 1100b according to a control signal provided via a control signal line CSLb.

[0087] The memory 1146 may store information required for the operation of the camera module 1100b, such as calibration data 1147. The calibration data 1147 may include information required for the camera module 1100b to generate image data using light L provided from the outside. The calibration data 1147 may include, for example, information related to the degree of rotation, information related to a focal length, information related to an optical axis, etc. If the camera module 1100b is embodied in the form of a multi-state camera in which the focal length changes depending on the position of an optical lens, the calibration data 1147 may include a focal length value for each position (or state) of the optical lens and information related to auto-focusing.

[0088] The storage unit 1150 may store image data sensed through the image sensor 1142. The storage unit 1150 may be disposed outside the image sensing device 1140 and may be implemented in a stacked form with a sensor chip constituting the image sensing device 1140. In some embodiments, the storage unit 1150 may be implemented using an Electrically Erasable Programmable Read-Only Memory (EEPROM), but the technical spirit of the present invention is not limited thereto.

[0089] The image sensor 1142 may include the image sensors 100a, 100b, 100c, 100d, 100e, 100f, and 100g described with reference to Figures 1 to 6B, or image sensors variously modified and altered therefrom within the scope of the technical concept of the present invention.

[0090] 8A and 8B, in some embodiments, each of the camera modules 1100a, 1100b, 1100c also includes an actuator 1130. As such, each of the camera modules 1100a, 1100b, 1100c includes the same or different calibration data 1147 due to the operation of the actuator 1130 included therein.

[0091] In some embodiments, one of the multiple camera modules 1100a, 1100b, and 1100c (e.g., camera module 1100b) is a folded lens type camera module including the above-mentioned prism 1105 and OPFE 1110, and the remaining camera modules (e.g., camera modules 1100a and 1100c) are vertical type camera modules that do not include the prism 1105 and the OPFE 1110, but the technical idea of ​​the present invention is not limited thereto.

[0092] In some embodiments, one of the camera modules 1100a, 1100b, and 1100c (e.g., camera module 1100c) may be a vertical depth camera that extracts depth information using infrared rays (IR). In this case, the application processor 1200 may merge image data provided from the vertical depth camera with image data provided from another camera module (e.g., camera module 1100a or 1100b) to generate a 3D depth image.

[0093] In some embodiments, at least two of the camera modules 1100a, 1100b, and 1100c (e.g., camera modules 1100a and 1100b) may have different fields of view (fields of view) from each other, for example, but not limited to, at least two of the camera modules 1100a, 1100b, and 1100c (e.g., camera modules 1100a and 1100b) may have different optical lenses from each other.

[0094] In some embodiments, the camera modules 1100a, 1100b, and 1100c each have a different viewing angle, and the optical lenses included in the camera modules 1100a, 1100b, and 1100c are also different from each other, but are not limited thereto.

[0095] In some embodiments, the multiple camera modules 1100a, 1100b, and 1100c may be arranged to be physically separated from one another. That is, the multiple camera modules 1100a, 1100b, and 1100c do not share the sensing area of ​​one image sensor 1142, but an independent image sensor 1142 may be arranged inside each of the multiple camera modules 1100a, 1100b, and 1100c.

[0096] 8A, the application processor 1200 also includes an image processing unit 1210, a memory controller 1220, and an internal memory 1230. The application processor 1200 may be implemented separately from the camera modules 1100a, 1100b, and 1100c. For example, the application processor 1200 and the camera modules 1100a, 1100b, and 1100c may be implemented separately from each other by using separate semiconductor chips.

[0097] The image processing device 1210 also includes a number of sub-processors 1212a, 1212b, 1212c, an image generator 1214, and a camera module controller 1216. The image processing device 1210 may also include a number of sub-processors 1212a, 1212b, 1212c corresponding to the number of camera modules 1100a, 1100b, 1100c.

[0098] The image data generated from each of the camera modules 1100a, 1100b, and 1100c are also provided to the corresponding sub-processors 1212a, 1212b, and 1212c through mutually separated image signal lines ISLa, ISLb, and ISLc. For example, the image data generated from the camera module 1100a is provided to the sub-processor 1212a through the image signal line ISLa, the image data generated from the camera module 1100b is provided to the sub-processor 1212b through the image signal line ISLb, and the image data generated from the camera module 1100c is provided to the sub-processor 1212c through the image signal line ISLc. Such image data transmission is performed, for example, using a CSI (Camera Serial Interface) based on a MIPI (Mobile Industry Processor Interface), but the technical idea of ​​the present invention is not limited thereto.

[0099] Meanwhile, in some embodiments, one sub-processor may be arranged to correspond to a plurality of camera modules. For example, sub-processor 1212a and sub-processor 1212c may not be implemented separately from each other as shown in the figure, but may be implemented as an integrated sub-processor, and image data provided from camera module 1100a and camera module 1100c may be selected via a selection element (e.g., a multiplexer) and then provided to the integrated sub-processor.

[0100] The image data provided to each of the sub-processors 1212a, 1212b, and 1212c is also provided to an image generator 1214. The image generator 1214 can generate an output image using the image data provided from each of the sub-processors 1212a, 1212b, and 1212c according to image generation information or a mode signal.

[0101] Specifically, the image generator 1214 may merge at least a portion of the image data generated from the camera modules 1100a, 1100b, and 1100c having different viewing angles according to the image generation information or the mode signal to generate an output image. Also, the image generator 1214 may select one of the image data generated from the camera modules 1100a, 1100b, and 1100c having different viewing angles according to the image generation information or the mode signal to generate an output image.

[0102] In some embodiments, the image generation information may also include a zoom signal or zoom factor, and in some embodiments the mode signal may also be based on a mode selected by a user, for example.

[0103] When the image generation information is a zoom signal (zoom factor) and each of the camera modules 1100a, 1100b, and 1100c has a different observation field of view (viewing angle), the image generator 1214 may perform different operations according to the type of zoom signal. For example, when the zoom signal is a first signal, the image generator 1214 may merge the image data output from the camera module 1100a and the image data output from the camera module 1100c, and then generate an output image using the merged image signal and the image data output from the camera module 1100b that is not used for merging. When the zoom signal is a second signal different from the first signal, the image generator 1214 may not merge the image data, but may select one of the image data output from each of the camera modules 1100a, 1100b, and 1100c to generate an output image. However, the technical idea of ​​the present invention is not limited thereto, and the method of processing image data may be modified and implemented at any time as necessary.

[0104] In some embodiments, the image generator 1214 can receive multiple image data having different exposure times from at least one of the multiple sub-processors 1212a, 1212b, 1212c, and perform HDR (high dynamic range) processing on the multiple image data to generate merged image data with an increased dynamic range.

[0105] The camera module controller 1216 can provide control signals to each of the camera modules 1100a, 1100b, 1100c. The control signals generated from the camera module controller 1216 are also provided to the corresponding camera modules 1100a, 1100b, 1100c via separate control signal lines CSLa, CSLb, CSLc.

[0106] One of the multiple camera modules 1100a, 1100b, 1100c, for example, the camera module 1100b, is designated as a master camera module by image generation information including a zoom signal or a mode signal, and the remaining camera modules, for example, the camera modules 1100a, 1100c, are also designated as slave cameras. Such information is included in a control signal and is also provided to the corresponding camera modules 1100a, 1100b, 1100c via mutually separated control signal lines CSLa, CSLb, CSLc.

[0107] The camera modules operating as the master and the slave may be changed depending on the zoom factor or the operation mode signal. For example, when the viewing angle of the camera module 1100a is wider than that of the camera module 1100b and the zoom factor indicates a low zoom ratio, the camera module 1100b may operate as the master and the camera module 1100a may operate as the slave. On the other hand, when the zoom factor indicates a high zoom ratio, the camera module 1100a may operate as the master and the camera module 1100b may operate as the slave.

[0108] In some embodiments, the control signals provided from the camera module controller 1216 to each of the camera modules 1100a, 1100b, 1100c also include a sync enable signal. For example, if the camera module 1100b is a master camera and the camera modules 1100a, 1100c are slave cameras, the camera module controller 1216 can transmit a sync enable signal to the camera module 1100b. The camera module 1100b provided with such a sync enable signal can generate a sync signal based on the provided sync enable signal and provide the generated sync signal to the camera modules 1100a, 1100c via a sync signal line SSL. The camera modules 1100b and the camera modules 1100a, 1100c can be synchronized to such a sync signal and transmit image data to the application processor 1200.

[0109] In some embodiments, the control signals provided by the camera module controller 1216 to the camera modules 1100a, 1100b, 1100c also include mode information via a mode signal, such that the camera modules 1100a, 1100b, 1100c can operate in a first operational mode and a second operational mode associated with a sensing speed.

[0110] In a first operation mode, the camera modules 1100a, 1100b, 1100c can generate image signals at a first rate (e.g., generate image signals at a first frame rate), encode the image signals at a second rate higher than the first rate (e.g., encode image signals at a second frame rate higher than the first frame rate), and transmit the encoded image signals to the application processor 1200. In this case, the second rate is less than or equal to 30 times the first rate.

[0111] The application processor 1200 stores the received image signal, i.e., the encoded image signal, in the internal memory 1230 or the external memory 1400 outside the application processor 1200, and thereafter reads and decodes the encoded image signal from the internal memory 1230 or the external memory 1400, and can display image data generated based on the decoded image signal. For example, a corresponding sub-processor among a plurality of sub-processors 1212a, 1212b, and 1212c of the image processing device 1210 can perform decoding and image processing on the decoded image signal.

[0112] In the second operation mode, the camera modules 1100a, 1100b, 1100c can generate image signals at a third rate lower than the first rate (e.g., generate image signals at a third frame rate lower than the first frame rate) and transmit the image signals to the application processor 1200. The image signals provided to the application processor 1200 are also unencoded signals. The application processor 1200 performs image processing on the received image signals and stores the image signals in the internal memory 1230 or the external memory 1400.

[0113] The PMIC 1300 can supply power, e.g., a power supply voltage, to each of the multiple camera modules 1100a, 1100b, and 1100c. For example, under the control of the application processor 1200, the PMIC 1300 can supply a first power to the camera module 1100a via a power signal line PSLa, supply a second power to the camera module 1100b via a power signal line PSLb, and supply a third power to the camera module 1100c via a power signal line PSLc.

[0114] The PMIC 1300 can generate power corresponding to each of the camera modules 1100a, 1100b, and 1100c and adjust the power level in response to a power control signal PCON from the application processor 1200. The power control signal PCON can also include a power adjustment signal for each operation mode of the camera modules 1100a, 1100b, and 1100c. For example, the operation mode can include a low power mode, and the power control signal PCON can include information related to a camera module operating in the low power mode and a power level to be set. The levels of power provided to each of the camera modules 1100a, 1100b, and 1100c can be the same or different from each other. Also, the power level can be dynamically changed.

[0115] As described above, exemplary embodiments have been disclosed in the drawings and the specification. In this specification, specific terms are used to describe the embodiments, but they are used only for the purpose of describing the technical idea of ​​the present invention, and are not used to limit the meaning or the scope of the present invention described in the claims. Therefore, a person having ordinary skill in the art can understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical scope of protection of the present invention should be determined by the technical idea of ​​the claims. [Explanation of symbols]

[0116] 101 Substrate 101A Front 101B Back 110 Dual Vertical Gate 111 Connecting part 113 Vertical section 113D Lower vertical section 113U upper vertical section 113T Trench 115 Gate insulating film 120 Element isolation film 150 Wiring structures 151, 153, 155 Interlayer insulating film 161 Contact plug 163,165 Conductive line 170 Anti-reflection coating CF Color Filter ML Micro Lens PD photoelectric conversion element SA1 separation area

Claims

1. A substrate having a first surface and a second surface opposite to the first surface, The photoelectric conversion element (PD) in the substrate, Includes a dual vertical gate that overlaps the PD in the vertical direction, The dual vertical gates are In a vertical view, the connecting portion has a first region, a second region, and a third region between the first region and the second region, A first vertical portion including a first upper vertical portion, wherein the first upper vertical portion is located on the first region, A second vertical portion including a second upper vertical portion, wherein the second upper vertical portion is located on the second region, and includes a second vertical portion, The lower surface of the first region is in direct contact with the upper surface of the first vertical portion. The lower surface of the second region is in direct contact with the upper surface of the second vertical portion. In a vertical view, the width of the lower surface of the first region along a first direction parallel to the first surface is the same as the width of the upper surface of the first vertical portion along the first direction. In a vertical view, the width of the lower surface of the second region along the first direction is the same as the width of the upper surface of the second vertical portion along the first direction. The width of the lower surface of the connecting portion along the first direction is equal to the sum of the width of the lower surface of the first region along the first direction, the width of the lower surface of the second region along the first direction, and the width of the lower surface of the third region along the first direction. The first vertical portion and the second vertical portion extend from the first surface into the substrate. Image sensor.

2. The image sensor according to claim 1, wherein the width of the lower surface of the first region along the first direction is greater than the width of the lower surface of the third region along the first direction.

3. The image sensor according to claim 1, wherein the width of the upper surface of the first vertical portion along the first direction is greater than the width of the lower surface of the first vertical portion along the first direction.

4. The image sensor according to claim 1, wherein the height of the third region along the second direction perpendicular to the first direction is shorter than the width of the lower surface of the third region along the first direction.

5. First contact plug and Further including a second contact plug, The first contact plug and the second contact plug are connected to the connecting portion. The image sensor according to claim 1.

6. The image sensor according to claim 5, wherein the first contact plug is connected to the first region.

7. The image sensor according to claim 6, wherein the second contact plug is connected to the second region.

8. First conductive line and The present invention further includes a second conductive line that is separated from the first conductive line in the first direction when viewed in the vertical direction, The first contact plug is connected to the first conductive line, The second contact plug is connected to the second conductive line. The image sensor according to claim 5.

9. The first vertical portion further includes a first lower vertical portion on the first upper vertical portion, The width of the lower surface of the first lower vertical portion along the first direction in a vertical view is smaller than the width of the upper surface of the first upper vertical portion along the first direction in a vertical view. The image sensor according to claim 1.

10. The image sensor according to claim 9, wherein the width of the lower surface of the first lower vertical portion along the first direction in a vertical view is smaller than the width of the lower surface of the first upper vertical portion along the first direction in a vertical view.

11. The image sensor according to claim 9, wherein the height of the first upper vertical portion along the second direction in the vertical view is greater than the height of the first lower vertical portion along the second direction in the vertical view.

12. The image sensor according to claim 9, wherein the height of the second upper vertical portion along the second direction in an up-and-down view is greater than the height of the first lower vertical portion along the second direction in an up-and-down view.

13. A substrate having a first surface and a second surface opposite to the first surface, The photoelectric conversion element (PD) in the substrate, Includes a dual vertical gate that overlaps the PD in the vertical direction, The dual vertical gates are In a vertical view, the connecting portion has a first region, a second region, and a third region between the first region and the second region, A first vertical portion including a first upper vertical portion, wherein the first upper vertical portion is located on the first region, A second vertical portion including a second upper vertical portion, wherein the second upper vertical portion is located on the second region, and includes a second vertical portion, The first region, when viewed in the vertical direction, has a left surface and a right surface opposite to the left surface. The first vertical portion, in a view in the vertical direction, has a left surface and a right surface opposite to the left surface. The left surface of the first region, in a vertical view, is in contact with the first vertical portion on the left surface of the first vertical portion, The first vertical portion and the second vertical portion extend from the first surface into the substrate. Image sensor.

14. The image sensor according to claim 13, wherein the right surface of the first region is in contact with the first vertical portion on the right surface of the first vertical portion when viewed in the vertical direction.

15. The image sensor according to claim 14, wherein, in a vertical view, the width of the first region from the left surface to the right surface of the first region along a first direction parallel to the first surface is the same as the maximum width of the first vertical portion from the left surface to the right surface of the first vertical portion along the first direction.

16. First contact plug and Further including a second contact plug, The first contact plug and the second contact plug are connected to the connecting portion. The image sensor according to claim 15.

17. The image sensor according to claim 16, wherein the first contact plug is connected to the first region.

18. The image sensor according to claim 17, wherein the second contact plug is connected to the second region.

19. The second region, when viewed in the vertical direction, has a left surface and a right surface opposite to the left surface. The second vertical portion has a left surface and a right surface opposite to the left surface when viewed in the vertical direction. The right surface of the second region, in a vertical view, is in contact with the second vertical portion on the right surface of the second vertical portion. The image sensor according to claim 15.

20. A substrate having a first surface and a second surface opposite to the first surface, The photoelectric conversion element (PD) in the substrate, A dual vertical gate that overlaps the PD in the vertical direction, First conductive line and A second conductive line separated from the first conductive line in the first direction when viewed in the vertical direction, The first contact plug on the first conductive line, The second contact plug on the second conductive line, The first contact plug is connected to the first conductive line, The second contact plug is connected to the second conductive line, The dual vertical gates are In a vertical view, the connecting portion has a first region, a second region, and a third region between the first region and the second region, A first vertical portion including a first upper vertical portion, wherein the first upper vertical portion is located on the first region, A second vertical portion including a second upper vertical portion, wherein the second upper vertical portion is located on the second region, and includes a second vertical portion, The first contact plug and the second contact plug are connected to the connecting portion, The first vertical portion and the second vertical portion extend from the first surface into the substrate. Image sensor.

Images