Power mosfet device with improved isolated gate structure and manufacturing process thereof

Abstract

To provide a power MOSFET device with an improved isolated-gate structure and a manufacturing process thereof.SOLUTION: A power MOSFET device (1) includes an isolated-gate structure (15). The isolated-gate structure extends over an active area (7) and includes a gate-oxide layer (12) made of an insulating material and extending over a first main surface (3a), and a gate region (24) is buried in the gate-oxide layer (12) so as to be electrically insulated from a semiconductor body (3). The gate region (24) includes a gate layer (14) of polysilicon, and at least one first silicide electrical-modulation region (25a) and one second silicide electrical-modulation region (25b). The regions extend in the gate layer (14) so as to face a top surface (14a) of the gate layer (14) and to be arranged alongside one another and spaced apart from one another in a first plane (XY).SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a power MOSFET device having an improved insulated gate structure and a process for fabricating the same, particularly the insulated gate structure having a gate region embedded in a gate oxide layer, the gate region having a polysilicon gate layer and a plurality of silicide electrically modulated regions which allow localized modification of the electrical resistance of the gate region. [Background technology]

[0002] As is known, power devices are electronic devices designed to operate at high voltages and currents, for example voltages reaching 1700 V in the inhibited state and currents of at most tens or hundreds of amperes in the conducting state. In particular, semiconductor devices are known that are based on, for example, silicon, gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), etc. For example, due to its high thermal mass, SiC can operate at temperatures up to about 440° C. and has the ability to withstand high powers (hundreds of watts) and can also operate at high frequencies (hundreds of MHz).

[0003] Power devices are used in many applications, for example, they are commonly used as switched-mode power supplies (SMPS), audio amplifiers, engine controls, energy conversion devices, and in the automotive sector for hybrid and electric vehicles.

[0004] For example, the power devices include power diodes, power transistors with finger electrode structures, thyristors, MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors), and SJ-MOSFETs (Superjunction MOSFETs).

[0005] However, it is known that the electrical control of power devices may present critical aspects, for example due to the wide spread of the active area of ​​the power devices or due to the particular layout of the power devices, which may cause delays in the propagation of control signals (e.g. source voltages) and therefore in the switching of the states (e.g. on / off states) of the power devices.

[0006] In particular, it is known that power devices may switch locally at different times (i.e., some areas of the power device switch on / off before others), which may lead to degradation of electrical performance and risk of damage to the power devices. Indeed, if the switching of the states of the power devices occurs at different times rather than in a uniform and simultaneous manner in all power devices, high current densities (typically higher than what was considered and planned for in the design phase) may occur in certain localized areas of the power devices, which may cause excessive heating of these areas, which may cause damage to the power devices due to the Joule effect.

[0007] Thus, currently known power devices impose limitations in the transmission of control signals that reduce reliability and degrade operational and electrical performance.

[0008] Furthermore, currently there is no known simple, low-cost solution that allows for localized control of the propagation of control signals based on the design conditions of the power device, for example by deliberately delaying or accelerating control signals in predefined regions of the power device to allow shifted (e.g., postponed or preempted) switching with respect to other regions of the power device, or otherwise to allow simultaneous and uniform switching throughout the power device. As a result, based on the application and desired conditions of use, it is not possible to effectively control the power devices in such a way that they switch at all points substantially simultaneously (e.g., at time intervals of less than about 50 ns), or otherwise have some regions switch before other regions. Summary of the Invention [Problem to be solved by the invention]

[0009] SUMMARY OF THE PRESENT EMBODIMENT It is an object of the present invention to provide a power MOSFET device having an improved insulated gate structure and method for fabricating the same which overcomes the shortcomings of the prior art. [Means for solving the problem]

[0010] According to the present invention, as defined in the claims, there is provided a power MOSFET device with an improved insulated gate structure, and a method for fabricating the same.

[0011] In order that the invention may be better understood, preferred embodiments will now be described, purely by way of non-limiting example, with reference to the accompanying drawings, in which: [Brief description of the drawings]

[0012] [Figure 1] 3 is a cross-sectional view of a power device according to one embodiment taken along section line II in FIG. 2. [Diagram 2] 2 is a plan view, with parts removed, of the power unit of FIG. 1 taken along section line AA of FIG. 1 according to one embodiment. [Figure 3A]2A-2C are respective plan views of the power device of FIG. 1 according to respective embodiments, taken along section line AA of FIG. 1, with parts removed; [Figure 3B] 2A-2C are respective plan views of the power device of FIG. 1 according to respective embodiments, taken along section line AA of FIG. 1, with parts removed; [Figure 4] 4 is a longitudinal cross-sectional view, with parts removed, of the power unit of FIG. 1 according to one embodiment, taken along section line IV-IV of FIG. 1; [Diagram 5] FIG. 2 is a top view of a gate structure of the power device of FIG. 1 according to one embodiment. [Figure 6] 2 is a plan view of the power device of FIG. 1 with parts removed according to a further embodiment; FIG. [Figure 7A] 5A-5C are longitudinal cross-sectional views illustrating steps in the manufacture of the power device of FIG. 4 according to one embodiment. [Figure 7B] 5A-5C are longitudinal cross-sectional views illustrating steps in the manufacture of the power device of FIG. 4 according to one embodiment. [Figure 7C] 5A-5C are longitudinal cross-sectional views illustrating steps in the manufacture of the power device of FIG. 4 according to one embodiment. [Figure 7D] 5A-5C are longitudinal cross-sectional views illustrating steps in the manufacture of the power device of FIG. 4 according to one embodiment. [Figure 7E] 5A-5C are longitudinal cross-sectional views illustrating steps in the manufacture of the power device of FIG. 4 according to one embodiment. [Figure 7F] 5A-5C are longitudinal cross-sectional views illustrating steps in the manufacture of the power device of FIG. 4 according to one embodiment. [Figure 7G] 5A-5C are longitudinal cross-sectional views illustrating steps in the manufacture of the power device of FIG. 4 according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] In particular, the examples in the drawings are illustrated with reference to a three-axis Cartesian system defined by mutually orthogonal axes X, Y and Z.

[0014] In the following description, elements common between various embodiments are designated by the same reference numerals.

[0015] Fig. 1 shows a power device (in particular of the power MOSFET type) 1 according to one embodiment provided and described by way of example. In particular, Fig. 1 shows, by way of example, a basic cell 1' of the power device 1, but in a manner known to those skilled in the art, the power device 1 may include a number of basic cells 1' electrically connected to one another, for example in parallel.

[0016] The elementary cell 1' of the power device 1 has a main direction of extension parallel to the axis Y, and FIG. 1 shows a cross-section of the elementary cell 1' in a plane XZ defined by the axes X and Z, thus perpendicular to said main direction of extension.

[0017] The elementary cells 1' include a semiconductor body 3 made of a semiconductor material, for example SiC or silicon, which has a front surface (or first main surface) 3a and a rear surface (or second main surface) 3b. The semiconductor body 3 is common to all elementary cells 1' and comprises a drain region 5, which has a first conductivity type (for example N-type) and a first conductivity type value and which extends in the semiconductor body 3 starting from the rear surface 3b towards the front surface 3a. A drain metallization 6 extends on the rear surface 3b in direct electrical contact with the drain region 5 and forms an electrical drain terminal.

[0018] A first body region 9a and a second body region 9b extend within the semiconductor body 3 starting from the front surface 3a towards the rear surface 3b without reaching the rear surface 3b and are physically separated from each other (in a direction parallel to the axis X) and from the rear surface 3b (in a direction parallel to the axis Z) via the drain region 5. Both the first body region 9a and the second body region 9b have a second conductivity type (here, P-type) and a second conductivity type value.

[0019] The first and second source regions 13a, 13b have a first conductivity type (here, N-type) and a third conductivity type value higher than the first conductivity type value, and extend starting from the front surface 3a into the first and second body regions 9a, 9b, respectively. In a direction parallel to the axis X, each source region 13a, 13b is physically separated (i.e. located at a distance) from the drain region 5 via a respective part of the first and second body regions 9a, 9b forming a first channel region 17a and a second channel region 17b, respectively (therefore, they have a second conductivity type value).

[0020] By way of purely non-limiting example, the elementary cell 1′ has a channel length L of the body regions 9a, 9b, for example between 150 nm and 1000 nm, in particular about 500 nm. ch For example, measured parallel to the axis X) and 1 x 10 15 Number of turns / cm 3 5×10 17 Number of turns / cm 3 For example, about 2 x 10 16 Number of turns / cm 3 The first doping value of the drain region 5 is approximately 1×10 13 Number of turns / cm 3 5×10 15 Number of turns / cm 3 and a second doping value for the implantation of the body regions 9a, 9b between 1×10 15 Number of turns / cm 3 5×10 16 Number of turns / cm 3 For example, between about 1×10 16 Number of turns / cm 3a third doping value for the implantation of the source regions 13a, 13b.

[0021] The power device 1 further includes a gate structure (also referred to as an "insulated gate structure") 15 which, in the embodiment illustrated by way of example in FIG. 1, is located along axis Z above the channel regions 17a, 17b of the body regions 9a, 9b and the portion of the drain region 5 that is disposed along axis X between the body regions 9a, 9b.

[0022] The gate structure 15 comprises an oxide layer (or gate oxide layer) 12 on the front surface 3a and a gate region 24 embedded within the oxide layer 12 so as to be physically and electrically isolated from the semiconductor body 3 (in particular from the front surface 3a of the semiconductor body 3). The gate region 24 is electrically connected to a gate metallization (not shown) in a manner known per se to a person skilled in the art.

[0023] The oxide layer 12 is made of an insulating material, such as an oxide, for example silicon dioxide (SiO2).

[0024] 1, is located along axis Z above the channel regions 17a, 17b of the body regions 9a, 9b and the portion of the drain region 5 that is located along axis X between the body regions 9a, 9b. In particular, the gate layer 14 is made of doped polysilicon, for example of a first electrical conductivity type (here, N-type) and, purely by way of example, of about 5×10 18 Number of turns / cm 3 Approximately 1×10 21 Number of turns / cm 3 For example, between about 5 x 10 19 Number of turns / cm 3 The second doping value has a fourth doping value.

[0025] The gate region 24 further includes a plurality of electrically modulating regions (or islands) 25 made of the silicide TiSi2CoSi2NiSi, WSi2. In the following description, the electrically modulating regions 25 are considered to be made of TiSi2 as an example, although other silicides (i.e., binary chemical compounds formed by a metal or metalloid and silicon) can be used as well. The electrically modulating regions 25 are contained within the gate layer 14, for example, and are described in more detail below with reference to FIG. 4.

[0026] A source metallization 16 (defining an electrical source terminal of a conductive material such as a metal) extends over the oxide layer 12 and over the front surface 3a in those areas not covered by the oxide layer 12, and is in direct electrical contact with the source regions 13a, 13b and body regions 9a, 9b, so that they are electrically coupled to one another.

[0027] Optionally, and in a manner not further shown or described, one or more passivation layers may extend over the source metallization 16 .

[0028] In practice, the drain metallization 6, the drain region 5, the first body region 9a, the first source region 13a, the gate layer 14, the oxide layer 12 and the source metallization 16 form the first device part 1a, while the drain metallization 6, the drain region 5, the second body region 9b, the second source region 13b, the gate layer 14, the oxide layer 12 and the source metallization 16 form the second device part 1b.

[0029] FIG. 2 shows the power device 1 in a plan view parallel to a plane XY (also called the "first plane XY") defined by axes X and Y, and for simplicity, the gate structures 15 and the source metallization 16 are not shown.

[0030] As can be seen from FIG. 2, the channel regions 17a, 17b of the device portions 1a, 1b have a channel extension W, e.g., equal to each other and between about 100 nm and about 1 μm, in a direction parallel to the first axis Y. ch Channel Length W ch The axial length of the axial groove is equal to the width of the axial groove (also called the axial groove).

[0031] 2, the elementary cell 1' extends into the active area 7 of the power device 1, and in the case of a plurality of elementary cells 1', they also extend into the active area 7 and share a gate structure 15. In particular, the semiconductor body 3 includes a field isolation region 11 (made of insulating material SiO2) which has a closed shape and which defines the boundary of the active area 7 of the power device 1. The isolation region 11 has the function of electrically isolating the active area 7 (and thus the one or more elementary cells 1') from the remainder of the semiconductor body 3. The active area 7 and the one or more elementary cells 1' contained therein are therefore galvanically isolated with respect to further devices contained in the semiconductor body 3 but which may be provided outside the active area 7.

[0032] In particular, in the case of multiple basic cells 1', each of them shares a drain region 5, a drain metallization 6, and a source metallization 16. Furthermore, the basic cells 1' share a common gate layer 14 for all the basic cells 1'.

[0033] For example, Figure 3A shows one embodiment of a power device 1 in plan view where, for simplicity, source metallization 16 and gate regions 24 are not shown. In Figure 3A, the power device 1 includes multiple base cells 1' electrically connected together.

[0034] 3A, the elementary cells 1' can be aligned with each other along an alignment axis 20 parallel to the axis Y and to the main extension direction of each elementary cell 1' to form an array of elementary cells 1'. That is, the first and second source regions 13a and 13b of each elementary cell 1' are aligned with each other in a direction perpendicular to the alignment axis 20. The gate structures 15 are located above each elementary cell 1' and have respective main extension directions 19 parallel to the alignment axis 20. For example, the gate structures 15 are here strip-shaped and have a main extension in the main extension direction.

[0035] Figure 3B shows a different embodiment of the power device 1 in plan view, where for simplicity the source metallization 16 and the gate regions 24 are not shown. In Figure 3B the power device 1 includes a number of elementary cells 1' which are electrically connected to each other.

[0036] As shown in FIG. 3B , the gate structure 15 may have a main portion 15′ having a main extension direction that is, for example, parallel to the axis X, and a plurality of secondary portions (i.e., gate fingers) 15″ extending from the main portion 15′ in a transverse manner to the main portion 15′, i.e., each secondary portion 15″ has a respective main extension that is transverse to the main extension direction 19, here, for example, parallel to the axis Y. For example, the main portion 15′ may be strip-shaped having the aforementioned main extension direction 19, while the secondary portions 15″ may extend two on either side of the main portion 15′ that are opposite each other along the axis Y, with each pair of secondary portions 15″ having respective coaxial secondary portions 15″ (i.e., the respective main portions are aligned with each other in a direction parallel to the axis Y).

[0037] Each secondary portion 15" can be, for example, above a respective one of the elementary cells 1' along the axis Z. As a result, each elementary cell 1' has first and second source regions 13a and 13b, which are aligned with each other, for example, in a direction parallel to the main extension direction 19.

[0038] Figure 4 shows a longitudinal cross-sectional view of the power device 1 taken along the section line IV-IV shown in Figure 1 and in an area corresponding to the gate layer 14 and the electrical modulation region 25. In particular, the view is in the plane YZ defined by the axes Y and Z. For ease of illustration, Figure 4 does not show the source metallization 16 and the drain metallization 6.

[0039] Figure 4 illustrates electrically modulated regions 25. Purely by way of non-limiting example, Figure 4 illustrates a first electrically modulated region 25a, a second electrically modulated region 25b, and a third electrically modulated region 25c, although the number of electrically modulated regions can vary, for example, to more than two or three.

[0040] In particular, the gate layer 14 has a top surface 14a and a bottom surface 14b that are opposed to each other along the axis Z. The top surface 14a faces an upper portion 12a of the oxide layer 12 that is disposed along the axis Z between the source layer 14 and the source metallization 16, while the bottom surface 14b faces a bottom portion 12b of the oxide layer 12 that is disposed along the axis Z between the gate layer 14 and the drain region 5.

[0041] The electrically modulating regions 25 extend within the gate layer 14 at the upper surface 14a of the gate layer 14 so as to face the upper surface 14a and to be spaced apart and disposed next to each other (ie, disposed next to each other) in the plane XY.

[0042] In particular, the electrically modulating regions 25 are at a distance from one another in a direction parallel to the plane XY, e.g., they are aligned with one another along the axis X and / or axis Y to form an array and / or matrix pattern, and purely by way of example, Figure 4 illustrates electrically modulating regions 25a, 25b, 25c aligned along the axis Y. The electrically modulating regions 25 are spaced apart from one another in a direction parallel to the plane XY by the gate layer 14.

[0043] In particular, the electrically modulated region 25 extends within the gate layer 14 from the top surface 14a to the bottom surface 14b. The electrically modulated region 25 may reach the bottom surface 14b or may extend a distance along the axis Z from the bottom surface 14b. Additionally, the electrically modulated region 25 may protrude outside the gate layer 14 and extend partially into the upper portion 12a of the oxide layer 12.

[0044] The electrically modulating region 25 has a shape (i.e., a cross section) in a plane parallel to the plane XY that is a closed polygon, such as a square, a triangle, a rectangle, a hexagon, etc. In the following description, as an example, the electrically modulating region 25 is considered to have a square shape, but other shapes are also possible.

[0045] Each electrically modulated region 25 has a thickness t silic 3, the electrical modulation regions 25 have an extended area A, measured in a plane parallel to the plane XY, the extended area A being a maximum thickness, measured, for example, between the top and bottom surfaces of the electrically modulating regions 25 that are opposed to each other along the axis Z. silic For example, a maximum expansion area. Furthermore, for more than two electrically modulated regions 25, each pair of electrically modulated regions 25 adjacent to each other in a direction parallel to the plane XY has a minimum distance D silic , which is the minimum distance between electrically modulating regions 25 measured along axis X or axis Y.

[0046] The shape and thickness t of the electrically modulated region 25 in a plane parallel to the plane XY silic Expansion Area A silic and the minimum distance D silic In the following description, these are also referred to as the structural parameters of the electrically modulating region 25.

[0047] The electrically modulating regions 25 have structural parameters that may differ from one another. That is, at least one of the electrically modulating regions 25 has structural parameters (shape, thickness, t silic Expansion Area A silic and minimum distance Dsilic Alternatively, all of the electrically modulating regions 25 may have the same structural parameters.

[0048] In the embodiment considered by way of example in FIG. 4, the electrically modulating regions 25a, 25b, and 25c have the same shape and expansion area A silic and the minimum distance D silic However, the thickness t silic It's different.

[0049] In particular, the structural parameters of the electrical modulation region 25 are heuristically selected during the design stage of the power device 1 to achieve predefined specific targets for the application in which the power device 1 is to be used.

[0050] In fact, silicides typically have a much lower electrical resistivity than that of the polysilicon of the gate layer 14, e.g., about two orders of magnitude lower. For example, the electrical resistivity of polysilicon is between about 1 Ω·m and about 100 Ω·m, and the electrical resistivity of TiSi2 is between about 0.01 Ω·m and about 1 Ω·m. As a result, the presence of the electrical modulation region 25 reduces the overall electrical resistance of the gate region 24 compared to the absence of the electrical modulation region 25, and among other things, allows for localized modulation of the electrical resistance of the gate region 24, allowing for localized and selective change of the electrical characteristics of the power device 1 (e.g., the speed of switching from an on state to an off state and vice versa in a given region of the power device 1).

[0051] In particular, in some applications it may be useful to have one or more first portions of gate region 24 at a lower electrical resistance and one or more second portions of gate region 24 at a higher electrical resistance disposed alongside the one or more first portions of gate region 24. In this case, the one or more first portions of gate region 24 include an electrically modulating region 25, while the one or more second portions of gate region 24 do not.

[0052] Furthermore, the possibility of varying the structural parameters of the electrically modulating regions 25 and the number of electrically modulating regions 25 in the gate structure 15 allows for more precise control of the electrical resistance of the gate region 24 at the design stage. For example, a larger number of electrically modulating regions 25, a larger thickness t, of one or more first sub-portions of the one or more first portions of the gate region 24, relative to one or more second sub-portions of the one or more gate regions 24 (which are arranged side-by-side with the one or more first sub-portions and have a higher electrical resistance than the one or more first sub-portions), may be achieved. silic Larger expansion area A silic and the smaller minimum distance D silic It is possible to provide at least one of the following:

[0053] Purely by way of example, considering now the embodiment of FIG. 3A, the gate structure 15 is strip-shaped and has a main extension direction 19. As a result, the gate layer 14 also has its main extension in the main extension direction 19 and has a first end 14' and a second end 14" opposite each other in the main extension direction 19 (FIG. 4). For example, it is required that the electrical resistance of the gate region 24 increases from the first end 14' to the second end 14". In this case, from the first end 14' to the second end 14", the gate region 24 is reduced in accordance with the following criteria: the number of electrically modulating regions 25 decreases, the thickness t silic Decrease, expansion area A silic Reduction and minimum distance D silic For example, FIG. 4 shows that the electrical resistance of the gate region 24 increases from the first end 14' to the second end 14" via a decrease in thickness tsilic from the first end 14' to the second end 14".

[0054] Figure 5 shows a plan view of the gate structure 15 of Figure 4. In the embodiment shown as an example in Figure 5, the electrically modulating regions 25 have a square shape with a side P (e.g., greater than about 0.2 μm and, for example, equal to about 1 μm) in a plane parallel to the plane XY. Furthermore, the electrically modulating regions 25 are, for example, equidistantly spaced from each other in the main extension direction 19.

[0055] FIG. 6 is a schematic illustration in plan view of a further example of a gate region 24, and in particular the arrangement of an electrically modulating region 25 in the gate layer 14.

[0056] In particular, Figure 6 shows a further embodiment of a power device 1 in plan view, where, for simplicity of illustration, the source metallization 16 and the oxide layer 12 are not shown. In Figure 6, the power device 1 includes, by way of example, a number of elementary cells 1' electrically connected together.

[0057] As shown in FIG. 6, the gate region 24 may provide a main portion 24' that acts as a gate bus and is coupled to a gate pad 24''' to which, for example, a gate metallization may be coupled. For example, the main portion 24' may have the shape of a polygonal frame, for example a square frame, and may define an interior region that extends inside (i.e., defines externally) the polygonal frame. Within this interior region extend secondary portions 24'' of the gate region 24, each secondary portion 24'' forming part of a respective elementary cell 1' (i.e., overlying a respective first device portion 1a and a respective second device portion 1b along axis Z, as shown in FIG. 1) and forming a respective gate finger. Each secondary portion 24'' has a respective end (e.g., opposite each other along axis Y) that is coupled to the main portion 24'. For example, the secondary portions 24'' extend between opposite sides of the square frame along axis Y so as to be parallel to each other and to axis Y.

[0058] The electrically modulated region 25 may extend over some of the secondary portions 24'' (optionally over a portion of the main portion 24') and / or over only predetermined areas of the secondary portions 24''.

[0059] For example, the electrically modulating region 25 may extend in a first set of secondary portions 24" but not in a second set of secondary portions 24". By way of example and as shown in FIG. 6, the first set extends on opposite sides of the gate region 24 with respect to the gate pad 24"', e.g., along axis X, while the second set extends between the gate pad 24'" and the first set. As a result, the first set of secondary portions 24" forms a first portion of the gate region 24 having a lower electrical resistance, and the second set of secondary portions 24" forms a second portion of the gate region 24 having a higher electrical resistance. For example, about half of the secondary portions 24" belong to the first set, and about half of the secondary portions 24" belong to the second set. Optionally, the electrically modulating region 25 also extends within the main portion 24', e.g., in the first set of secondary portions 24".

[0060] Furthermore, the electrical modulation region 25 may extend within a central region of the secondary portion 24" rather than in the end regions of the secondary portion 24". In particular, the central region of the secondary portion 24" is a region of the secondary portion 24" that is centrally disposed along the axis Y and is disposed between the end regions of the secondary portion 24" (e.g., disposed such that they are equidistant from the ends of the secondary portion 24" that are coupled to the main portion 24'), while the end regions of the secondary portion 24" are disposed alongside the central region of the secondary portion 24" and define the ends of the secondary portion 24" that are coupled to the main portion 24'. Thus, for each secondary portion 25 provided with an electrical modulation region 25, the end regions of the secondary portion 24" form a second portion of the gate region 24 having a higher electrical resistance.

[0061] In a known manner, during use, the power device 1 applies a source voltage V SFor example, the drain voltage V D A gate voltage V 1 is applied to the drain metallization 6. Furthermore, a gate voltage V 2 is applied to the gate region 24 via the gate metallization 6 in order to generate a respective flow of charge carriers (here electrons) through the channel regions 17a, 17b, respectively (as shown in FIG. 2). G When biased, the power device is in a conducting state (ON state), otherwise the power device is in an inhibited state (OFF state). Thus, in use, the overall conduction of the power device 1 is a function of both the flows of electrons 18a, 18b (each corresponding to a respective device portion 1a, 1b).

[0062] 7A-7G show various stages in a process for manufacturing the power device 1, particularly the embodiment of FIG. 4. The manufacturing process of FIGS. 7A-7G is similar to that of FIG. 4, in that the power device 1 (e.g., the electrically modulating region 25 has different thicknesses t silic Although the present invention is illustrated with reference to an embodiment in which the power units 1 and 2 are equidistantly spaced apart along the axis Y, the manufacture of the other embodiments of the power unit 1 described above is similar and will be obvious to those skilled in the art from the following description, and therefore will not be described further.

[0063] With reference to Figure 7A, firstly a semiconductor body 3 is formed in a manner known per se. For ease of illustration, Figures 7A to 7G do not show the drain region 5, the body regions 9a, 9a or the source regions 13a, 13b.

[0064] In particular, a substrate of semiconductor material (which in the context of the present description consists, for example, of SiC and has a first conductivity type of N-type) is provided on which a number of epitaxial layers (not shown) are formed, the drain region 5 being formed as a result of epitaxial growth on the substrate.

[0065] Then, by techniques known per se and starting from the front face 3 a , isolation regions 11 are formed in the semiconductor body 3 , which define the delimitation of the active area 7 of the power device 1 .

[0066] This is then followed in a manner known per se and via lithographic techniques by the formation of the body regions 9a, 9b and then the formation of source regions 13a, 13b in the body regions 9a, 9b. However, it will be obvious to a person skilled in the art that the formation of the source regions 13a, 13b can also be carried out in a manner known per se prior to or simultaneously with the formation of the body regions 9a, 9b. For example, the formation of the body regions 9a, 9b can be carried out by doping with a first dopant having a second conductivity type (here, for example, P-type via ions of boron, indium and aluminium) and a second doping value (approximately 1×10 12 Number of turns / cm 2 1×10 13 Number of turns / cm 2 Instead, the formation of source regions 13a, 13b in body regions 9a, 9b is performed by a first implantation with a concentration equal to the first dopant concentration (about 5×10 ions) followed by a thermal annealing step (for example at temperatures between 900° C. and 1100° C. for a period between a few tens of seconds in the case of rapid thermal annealing, RTA, and a few hours in the case of a furnace, in a protected environment, for example in a nitrogen or argon atmosphere) allowing the redistribution and activation of the first dopant. 15 Number of turns / cm 2 5×10 16 Number of turns / cm 2 This is accomplished by a second implantation of a second dopant having a concentration equal to that of the first dopant (during implantation), followed by a thermal annealing step allowing redistribution and activation of the second dopant.

[0067] In this way a semiconductor body 3 is obtained as shown in FIG.

[0068] 7A again, a first oxide layer 50 is formed on the front surface 3a of the semiconductor body 3. The first oxide layer 50 of an insulating material such as an oxide (e.g., silicon oxide) is for forming the bottom portion 12b of the oxide layer 12. For example, the first oxide layer 50 extends in a uniform manner across the front surface 3a of the semiconductor body 3. In particular, the first oxide layer 50 is formed via techniques such as thermal oxidation, wet anodization, chemical vapor deposition (CVD), and plasma anodization. For example, the first oxide layer 50 is formed by performing a thermal process in an oxygen atmosphere to obtain oxygen that reacts with the silicon of the semiconductor body 3 to form silicon oxide on the front surface 3a of the semiconductor body 3.

[0069] The gate layer 14 is then formed on the first oxide layer 50 (i.e. on the top surface of the first oxide layer 50 opposite to the bottom surface of the first oxide layer 50 facing the semiconductor body 3). For example, the gate layer 14 extends in a uniform manner on the first oxide layer 50. In particular, the gate layer 14 is made of polysilicon (in particular, here of N-type, for example, about 5×10 18 Number of turns / cm 2 Approximately 1×10 21 Number of turns / cm 2 and is formed via techniques such as chemical vapor deposition of doped polysilicon or chemical vapor deposition of polysilicon followed by doping of said polysilicon via ion implantation of dopant species. For example, gate layer 14 is formed via low pressure chemical vapor deposition (LPCVD) in a manner known per se.

[0070] Referring to FIG. 7B, a first mask layer 52 is then formed on the gate layer 14, ie, on the upper surface 14a of the gate layer 14. As shown in FIG. In particular, the first mask layer 52 exposes first phase exposed regions 53' of the upper surface 14a of the gate layer 14 and covers first phase covered regions 53" of the upper surface 14a of the gate layer 14. In particular, the first phase exposed regions 53' are arranged side by side and spaced apart from one another in the plane XY, e.g., along the axis Y (i.e., laterally arranged at a distance), i.e., the first phase exposed regions 53' are offset from one another in plan view (i.e., parallel to the plane XY). In the embodiment considered as an example, the first phase exposed regions 53' are spaced apart at an equal distance along the axis Y. More particularly, the first mask layer 52 has a plurality of first phase openings 54 which extend through the first mask layer 52 to expose the first face exposed regions 53', the first phase openings 54 being arranged side by side and spaced apart from one another in the plane XY, e.g., spaced apart at an equal distance along the axis Y.

[0071] For example, and in the following, as an example, the first mask layer 52 is made of an oxide such as silicon oxide, although other materials such as nitrides or photoresists can also be used to produce the first mask layer 52. In particular, the first oxide mask layer 52 is formed through the deposition of a first intermediate oxide layer (not shown and made of an oxide such as silicon oxide) uniformly performed on the upper surface 14a of the gate layer 14. The deposition of the first intermediate oxide layer is performed in the same manner as that of the first oxide layer 50, and therefore a detailed description thereof will be omitted. Following the deposition of the first intermediate oxide layer, a first first phase etch is performed, which forms first phase openings 54 by removing corresponding portions of the first intermediate oxide layer to define the first mask layer 52. For example, the first first phase etch may be a wet etch (e.g., HF-based) or a plasma etch (e.g., XeF2 through a chlorine or fluorine compound of SF6) and is performed through a first etch mask (not shown) covering the first intermediate oxide layer while leaving exposed the portions of the first intermediate oxide layer to be removed (i.e., the portions along axis Z that form first phase openings 54 above first phase exposed regions 53'). More specifically, this is done by forming the first etch mask on the first intermediate oxide layer through known lithographic techniques, performing the first first phase etch through the first etch mask, and then removing the first etch mask (e.g., through the use of a suitable chemical solvent).

[0072] Referring to FIG. 7C, a first metal layer 56 is formed on the first mask layer 52 and on the first phase exposed areas 53' of the upper surface 14a of the gate layer 14. In particular, the first metal layer 56 is also formed in the first phase openings 54 in such a manner as to cover the first phase exposed areas 53'. The first metal layer 56 is made of a metal or semimetal, which is capable of forming a silicide by reacting with silicon. For example, the first metal layer 56 is made of Ti, Co, Ni, W, and in the case considered below by way of a non-limiting example, the first metal layer 56 is made of Ti. For example, the first metal layer 56 is formed in a manner known per se, such as by cathodic sputtering or electroplating.

[0073] 7D, first phase silicide regions 58 are formed in first phase exposed regions 53'. In particular, first phase silicide regions 58 are comprised of silicide formed starting from silicon present in gate layer 14 and titanium present in first metal layer 56 contained within respective electrically modulating regions 25. In the embodiment considered as an example, a first first phase silicide region 58a, a second first phase silicide region 58b, and a third first phase silicide region 58c are formed in areas corresponding to respective first phase exposed regions 53' and respective first phase openings 54, e.g., first, second, and third first phase silicide regions 58a, 58b, 58c are arranged one after the other along axis Y (e.g., from right to left in FIG. 7D), and first first phase silicide region 58a forms first electrically modulating region 25a.

[0074] In particular, the formation of the first phase silicide regions 58 is performed via one or more first thermal treatments that allow interdiffusion of silicon and titanium through the interface generated between the gate layer 14 and the first metal layer 56. For example, the one or more first thermal treatments are performed in a protective environment (e.g., in a nitrogen or argon atmosphere) at a temperature between 300° C. and 1100° C. for a time period between 10 s and 100 s. In effect, the one or more first thermal treatments allow diffusion of the silicon into and into the titanium, resulting in the formation of a silicide through the gradual consumption of the portions of the gate layer 14 and the first metal layer 56 that are in contact with each other at the first phase openings 54. As a result, first phase silicide region 58 extends partially into gate layer 14 (from top surface 14a to bottom surface 14b of gate layer 14) and partially into first metal layer 56 (from a bottom surface of first metal layer 56 facing gate layer 14 to a top surface of first metal layer 56 opposite the bottom surface along axis Z). In particular, increasing the time period for which the one or more first thermal treatments are performed increases the diffusion of silicon and titanium at the interface and therefore increases the thickness of first phase silicide region 58 as measured along axis Z. In the embodiment considered as an example, the time period for the one or more first thermal treatments increases the thickness t silic The thickness t of the first electrical modulation region 25a silic are determined to be equal.

[0075] Further details on the formation of silicides starting from the interface between silicon and metals / semimetals can be found in "Ti Nitrides and Ti Silicides", Isabelle Jauberteau, https: / / encyclopedia.pub / entry / 119 and "NiSi salicide technology for scaled CMOS", Iwaia, et al., This is described in prior art documents such as Microelectronic Engineering 60 (2002) 157-169.

[0076] Referring again to FIG. 7D, a step of removing titanium that did not react with silicon of the gate layer 14 is then performed. That is, the portions of the first metal layer 56 that did not react with the gate layer 14 to form a silicide are removed. In this manner, the first metal layer 56 is removed, leaving the first phase silicide regions 58 on the gate layer 14. For example, this is done by performing a second first phase etch that selectively removes the metal / metalloid of the first metal layer 56, without removing the oxide of the first metal layer 52 and the silicide of the first phase silicide regions 58. In particular, the second first phase etch is a wet etch with a base of hydrogen peroxide or a solution for etching metals.

[0077] Referring again to FIG. 7D, in a manner not shown, an optional step of removing the first mask layer 52 follows, exposing the first phase covered regions 53″ of the upper surface 14a of the gate layer 14. In particular, this is done by performing a third first phase etch that selectively removes the first mask layer 52 without removing the first phase silicide regions 58 and the gate layer 14. For example, the third first phase etch is a wet etch (e.g., HF-based) or a plasma etch (e.g., XeF2 or SF6 via chlorine or fluorine compounds).

[0078] The steps or process steps described with reference to Figures 7B-7D result in the formation of first phase silicide regions 58, and in particular, first electrically modulating regions 25a.

[0079] The steps described with reference to FIG. 7B to FIG. 7D have different thicknesses t silicThis process may be repeated one or more times to form additional silicide regions that overlap portions of first phase silicide region 58 (and, more particularly, do not overlap first phase silicide region 58a) to form electrical modulation region 25 having a first silicide region 58b, one example of which is described below with reference to Figures 7E-7G.

[0080] 7E, a second mask layer 62 is formed on the gate layer 14, i.e., on the upper surface 14a of the gate layer 14. In particular, the second mask layer 62 exposes second phase exposed regions 63′ of the upper surface 14a of the gate layer 14 and covers second phase covered regions 63″ of the upper surface 14a of the gate layer 14, and in particular, the second mask layer 62 covers the first first phase silicide regions 58a (i.e., the first electrically modulating regions 25a). In particular, the second phase exposed regions 63′ are arranged next to each other and at a distance apart from each other in the plane XY, e.g., along the axis Y, and are formed with a thickness t silic 5. The second phase exposed region 63' overlies the first phase silicide region 58 to be augmented. In the embodiment considered as an example, the second phase exposed region 63' overlies the second first phase silicide region 58b and the third first phase silicide region 58c, respectively, while the first first phase silicide region 58c is covered by the second mask layer 62. More specifically, the second mask layer 62 has a plurality of second phase openings 64 that extend through the second mask layer 62 to expose the second phase exposed region 63' (overlying a portion of the first phase exposed region 53' along axis Z).

[0081] Moreover, second mask layer 62 is comprised of a material and is obtained in a manner similar to that described above with respect to first mask layer 52. In particular, second mask layer 62 is formed via deposition of a second intermediate oxide layer (similar to the first intermediate oxide layer) followed by a first second phase etch (similar to the first first phase etch) that forms second phase openings 64.

[0082] 7F, a second metal layer 66 is formed on second mask layer 62 and on second first phase silicide region 58b and third first phase silicide region 58c (and thus within second phase opening 64 so as to cover second phase exposed region 63'). Second metal layer 66 is of a material and is obtained in a manner similar to that already described for first metal layer 56 and will not be described further.

[0083] 7G, second phase silicide regions 68 are formed in areas corresponding to second phase exposed regions 63'. In particular, second phase silicide regions 68 are themselves contained within respective electrically modulating regions 25 and are composed of silicide generated starting from silicon present in gate layer 14 and titanium present in second metal layer 66. In the illustrated and considered embodiment, a first second phase silicide region 68b and a second second phase silicide region 68c are formed, both of which extend along axis Z above and below second first phase silicide region 58b and third first phase silicide region 58c, respectively. First second phase silicide region 68b together with second first phase silicide region 58b form second electrically modulating region 25b.

[0084] Second phase silicide region 68 is comprised of a material and is obtained in a manner similar to that described above for first phase silicide region 58 (e.g., formed via one or more second thermal treatments similar to the one or more first thermal treatments, followed by a second second phase etch similar to the second first phase etch, and selective removal of second metal layer 66). In particular, the duration of the one or more second thermal treatments is determined by the thickness t of first phase silicide region 58. silic The thickness t of the second phase silicide region 68 silic The sum of these is the thickness t of the second electrically modulating region 25b. silic are defined in an equal manner.

[0085] Referring again to FIG. 7D, in a manner not shown, this is followed by the optional step of removing second mask layer 62 to expose second phase covered regions 63″ of upper surface 14a of gate layer 14. In particular, this is obtained by performing a third second phase step etch similar to the third first phase etch.

[0086] Through the steps described with reference to FIGS. 7E to 7G, the thickness t of the silicide region is increased to form the second electrically modulating region 25b. silic It is possible to increase the

[0087] Optionally, and in a manner not shown or described in detail again, the steps of Figures 7E-7G can be repeated as described above to form a third electrically modulating region 25c (in particular, to cover the first and second electrically modulating regions 25a, 25b through a third mask layer and to form a first third phase silicide region overlapping the second second phase silicide region 68c along axis Z), which allows the formation of gate region 24 as shown in Figure 4.

[0088] This is followed, in a manner not shown, by the formation of a second oxide layer along axis Z overlying gate layer 14 and electrically modulating region 25. The second oxide layer is formed to form upper portion 12a of oxide layer 12 and to merge with first oxide layer 50. That is, first oxide layer 50 and the second oxide layer form oxide layer 12 surrounding and embedding gate region 24 to electrically isolate gate region 24. The second oxide layer is composed of a material and is obtained in a manner similar to that described above for first oxide layer 50.

[0089] Several steps then follow leading to the formation of the power device 1 of FIG. 1, including the formation of source metallization 16 and drain metallization 6, which are known and will not be described further.

[0090] From a review of the features of the present invention provided in accordance with this disclosure, the advantages offered by the present invention are clear: In particular, the electrically modulated regions 25 allow a local and selective modulation of the electrical resistance of the gate region 24, i.e. the electrical resistance of the gate region 25 can be locally changed. This is obtained by the presence of the electrically modulated silicide regions 25, and more particularly, the number of electrically modulated regions 25 and their respective structural parameters (shape, thickness t silic Expansion Area A silic and the minimum distance D silic In this way, the gate voltage V , which may be present across different areas of the power device 1 in the absence of the electrical modulation region 25, is distributed in a synchronous and uniform manner across all the elementary cells 1′ (regardless of the extent of the power device 1 in a plane parallel to the plane XY). G 1, the gate voltage V G It is possible to provide a power supply with a MOSFET, which improves the switching control and electrical performance of the power device 1, and also improves the reliability of the power device 1 (more robust against thermal breakdown compared to known devices). Furthermore, it allows a specific design of the power device 1 based on the application and the corresponding design conditions.

[0091] Moreover, the manufacturing process described with reference to FIGS. 7A to 7G allows for a simplified and cost-effective manufacture of the power device 1, and in particular for the fabrication of the different thicknesses t silic This makes it possible to obtain an electrical modulation region 25 having the following characteristics.

[0092] Finally, it will be appreciated that various variations and modifications can be made to the invention as described and illustrated herein without departing from the spirit and scope of the invention as defined in the appended claims.

[0093] For example, different embodiments may be combined with each other to provide further solutions.

[0094] Additionally, other embodiments of the gate structure 15 are possible, one example of which is shown in FIG. 6, although further embodiments are possible as would be obvious to one skilled in the art. For example, the gate structure 15 shapes of FIGS. 3A and 3B can be combined together into multiple base cells 1' aligned with each other along their respective secondary portions 15", or the secondary portions 15" can be staggered in a direction parallel to the axis Y, or they can all be on the same side of one of the main portions 15'.

[0095] Furthermore, it is possible to design the electrical modulation regions 25 that enable the gate region 24 to have the required electrical performance according to the specific layout of the gate structure 15 and the design conditions imposed by the specific application (e.g. which areas of the power device 1 have to be switched before or after). This means that at the design stage, the number of electrical modulation regions 25 and their respective structural parameters (shape, thickness t silic Expansion Area A silic and the minimum distance D silic For example, it is possible to have more than three electrically modulated regions 25, each having the same thickness t silic It is possible to have multiple electrically modulated regions 25 having different minimum distances D silic It is possible to have electrically modulated regions 25 having M different thicknesses t silic For N number of electrically modulating regions 25 (where M≦N and M≧2), the steps described above with reference to FIGS. 7B to 7D are repeated M times. Alternatively, one electrically modulating region 25 having the same thickness tsilic In the case of an electrically modulating region 25 having such a structure, the steps described with reference to Figures 7A to 7D and the final step described after Figure 7G are performed without the need to perform the steps of Figures 7E to 7G or to repeat them as well.

[0096] The power device 1 can be of a different type than that previously described with reference to Fig. 1. For example, the gate structure 15 can be of the trench gate type, starting from the front surface 3a and extending in a recess present in the semiconductor body 3. Or the power device 1 can be of the DMOS, LDMOS, VMOS, etc. type.

[0097] In fact, in its most general form and as clearly known to the person skilled in the art, the MOSFET type power device 1 comprises, for each elementary cell 1′ present in the active area 7, a first source region 13a having a first conductivity type; a drain region 5 having a first conductivity type; a first source region 13a having a first conductivity type; a first body region 9a having a second conductivity type, the first body region 9a being adjacent to the drain region 5 and the first source region 13a and defining a first channel region 17a located between the first source region 13a and the drain region 5; and a gate structure 15 present along the axis Z above the drain region 5 and the first channel region 17a and capable of being electrically biased to control a first flow of charge carriers 18a through the first channel region 17a between the first source region 13a and the drain region 5, the first source region 13a, the drain region 5 and the first body region 9a being contained in a semiconductor body 3.

[0098] Furthermore, in the case where the first mask layer 52 is made of photoresist, the manufacturing method offers the following differences compared to the above: Firstly, referring to FIG. 7B, the first mask layer 52 of photoresist is formed via a photolithography technique known per se. Furthermore, referring to FIG. 7D, the one or more first heat treatments are carried out after removing, along the axis Z, the part of the first metal layer 56 lying above the first mask layer 52 and the first mask layer 52 of photoresist via a lift-off technique known per se. Although these differences are related to the steps of FIGS. 7B to 7D, they also apply to subsequent repetitions of these steps (for example the steps of FIGS. 7E to 7G).

Claims

1. In a power MOSFET device (1) that includes a semiconductor body (3) having a first main surface (3a) and a second main surface (3b) opposite to each other along the first axis (Z), and encompassing an active region (7) facing the first main surface (3a), The power MOSFET device (1) further includes an insulated gate structure (15) which comprises a gate oxide layer (12) extending over the active area (7) and composed of an insulating material, and extending over the first main surface (3a), and a gate region (24) embedded in the gate oxide layer (12) to be electrically isolated from the semiconductor body (3). The gate region (24) comprises a polysilicon gate layer (14) and at least one first silicide electrical modulation region (25a) and a second silicide electrical modulation region (25b), the gate layer (14) having an upper surface (14a) and a bottom surface (14b) opposite to each other along the first axis (Z), the bottom surface (14b) of the gate layer (14) facing the main surface (3a) of the semiconductor body (3) via the gate oxide layer (12), the first electrical modulation region (25a) and the second electrical modulation region (25b) are arranged spaced apart from each other in a first plane (XY) perpendicular to the first axis (Z) and extend within the gate layer (14) so ​​as to face the upper surface (14a) of the gate layer (14). Power MOSFET device.

2. The power MOSFET device (1) is provided with at least one first basic cell (1'), the first basic cell (1') extends within the active area (7) and A drain region (5) having a first conductivity type, A first source region (13a) having a first conductivity type, A first body region (9a) having a second conductivity type opposite to a first conductivity type, which is adjacent to the drain region (5) and the first source region (13a) and defines a first channel region (17a) interposed between the first source region (13a) and the drain region (5), The insulated gate structure (15) is located above the drain region (5) and the first channel region (17a) along the first axis (Z) and is electrically biasable to control the first flow of charge carriers (18a) through the first channel region (17a) between the first source region (13a) and the drain region (5), The source region (13a), the drain region (5), and the first body region (9a) are contained within the semiconductor body (3). The power MOSFET device according to claim 1.

3. A second source region (13b) having a first conductivity type, A second body region (9b) having a second conductivity type, adjacent to the drain region (5) and the second source region (13b), and defining a second channel region (17b) interposed between the second source region (13b) and the drain region (5), Furthermore, The insulated gate structure (15) is located above the second channel region (17b) along the first axis (Z) and is electrically biasable to control the second flow of charge carriers (18b) through the second channel region (17b) between the second source region (13b) and the drain region (5). The drain region (5) starts from the second main surface (3b) and extends within the semiconductor body (3). The first body region (9a) and the second body region (9b) extend within the semiconductor body (3) starting from the second main surface (3b) and are separated from each other orthogonal to the first axis (Z) via a portion of the drain region (5). The first source region (13a) and the second source region (13b) extend within the semiconductor body (3) starting from the second main surface (3b), and are separated from the drain region (5) perpendicular to the first axis (Z) via the first body region (9a) and the second body region (9b), respectively. The insulated gate structure (15) has a first portion facing the first body region (9a) and the first source region (13a), and a second portion facing the second body region (9b) and the second source region (13b), The first body region (9a), the first source region (13a), the drain region (5), the first portion of the insulated gate structure (15), and the first channel region (17a) form the first device portion (1a) of the first basic cell (1'), and the second body region (9b), the second source region (13b), the drain region (5), the second portion of the insulated gate structure (15), and the second channel region (17b) form the second device portion (1b) of the second basic cell (1'). The power MOSFET device according to claim 2.

4. Furthermore, at least one second basic cell (1') of the power MOSFET device (1) is provided, electrically connected to the first basic cell (1'), and the second basic cell (1') extends within the active area (7) and The drain region (5) and Each first source region (13a) having a first conductivity type, Each first body region (9a) having a second conductivity type, wherein the first body region (9a) of the second basic cell (1') is adjacent to the first source region (13a) and the drain region (5) of the second basic cell (1') and defines each first channel region (17a) interposed between the first source region (17a) and the drain region (5) of the second basic cell (1'), The insulated gate structure (15) is located above the first channel region (17a) of the second base cell (1') along the first axis (Z) and is electrically biasable to control the respective first flows of charge carriers (18a) through the first channel region (17a) of the second base cell (1') between the first source region (13a) and the drain region (5) of the second base cell (1'), It includes, The first source region (13a) and the first body region (9a) of the second base cell (1') are contained within the semiconductor body (3). The power MOSFET device according to claim 2.

5. Each of the regions between the first electrical modulation region (25a) and the second electrical modulation region (25b) has its own structural parameters, and these structural parameters are i. The shape of the first electrical modulation region (25a) and the second electrical modulation region (25b) in a plane parallel to the first plane (XY), ii. The maximum thickness (tsilic) of the first electrical modulation region (25a) and the second electrical modulation region (25b), measured along the first axis (Z), and iii The maximum expanded area (Asilican) of the first electrical modulation region (25a) and the second electrical modulation region (25b), measured on a plane parallel to the first plane (XY). It includes such that at least one of the structural parameters i to iii is different between the first electrical modulation region (25a) and the second electrical modulation region (25b). The power MOSFET device according to the preceding claim 1.

6. The power MOSFET device according to claim 5, wherein the first electrical modulation region (25a) has a first maximum thickness (tsilic), and the second electrical modulation region (25b) has a second maximum thickness (tsilic) that is even greater than the first maximum thickness.

7. The power MOSFET device according to prior claim 1, wherein the gate region (24) extends within the gate layer (14) so ​​as to face the upper surface (14a) of the gate layer (14) and further includes at least one third silicide electrical modulation region (25c) located at a certain distance from the first electrical modulation region (25a) and the second electrical modulation region (25b) on the first surface (XY).

8. The structural parameter i further includes the shape of the third electrical modulation region (25c) in a plane parallel to the first plane (XY), The structural parameter ii further includes the maximum thickness (tsilic) of the third electrical modulation region (25c) measured along the first axis (Z), The structural parameter iii further includes the maximum expanded area (Asilic) of the third electrical modulation region (25c) measured in a direction parallel to the first surface (XY), The structural parameter is further, iv Between each pair of adjacent electrical modulation regions (25a, 25b, 25c), the minimum measured distance (Disilic, parallel to the first plane (XY) is measured. It includes, At least one of the structural parameters i to iv differs among the first (25a), second (25b), and third (25c) electrical modulation regions. The power MOSFET device according to claim 5.

9. The power MOSFET device according to claim 7, wherein the first (25a), second (25b), and third (25c) electrical modulation regions are aligned with each other in the main extension direction (19) of the insulated gate structure (15) to form an array of electrical modulation regions.

10. The power MOSFET device according to claim 1, wherein the gate region (24) encompasses at least one first portion of the gate region (24) and at least one second portion of the gate region (24) that are adjacent to each other and orthogonal to the first axis (Z), and the at least one first portion of the gate region (24) encompasses a first electrical modulation region (25a) and a second electrical modulation region (25b) and provides an electrical resistance even lower than that of the at least one second portion of the gate region (24).

11. A power MOSFET device according to any one of the prior claims, wherein the semiconductor body (3) includes silicon carbide SiC.

12. In a method for manufacturing a power MOSFET device (1), The steps of forming a semiconductor body (3) having a first main surface (3a) and a second main surface (3b) that are opposite to each other along the first axis (Z), and encompassing an active region (7) facing the first main surface (3a), A step of forming an insulated gate structure (15) of a power MOSFET device (1) on an active region (7), the insulated gate structure (15) being made of an insulating material and encompassing a gate oxide layer (12) extending on a first main surface (3a) and a gate region (24) embedded in the gate oxide layer (12) to be electrically isolated from the semiconductor body (3), It includes, and the steps of forming the insulating gate structure (15) are successively, A first oxide layer (50) of an insulating material is formed on the first main surface (3a) of the semiconductor body (3). A gate layer (14) of polysilicon is formed on the first oxide layer (50), the gate layer (14) having an upper surface (14a) opposite to each other along the first axis (Z) and a bottom surface (14b) of the gate layer (14) facing the first oxide layer (50). Within the gate layer (14) and starting from the upper surface (14a) of the gate layer (14), at least one first silicide electrical modulation region (25a) and a second silicide electrical modulation region (25b) are arranged apart from and side by side in a first plane (XY) perpendicular to the first axis (Z), and together with the gate layer (14), these form the gate region (24), and A second oxide layer (50) of an insulating material is formed on the gate layer (14), the first electrical modulation region (25a), and the second electrical modulation region (25b), and together with the first oxide layer (50), the second oxide layer (50) forms a gate oxide layer (12) that surrounds the gate region (24). A method that encompasses the matter.

13. The step of forming the first electrical modulation region (25a) and the second electrical modulation region (25b) is performed successively, A first mask layer (52) is formed on the upper surface (14a) of the gate layer (14), having a first first phase opening (54) and a second first phase opening (54) which cover the first phase covering region (53'') of the upper surface (14a) of the gate layer (14) and are arranged parallel to each other in the first surface (XY) and spaced apart from each other, exposing the respective first phase exposed regions (53') of the upper surface (14a) of the gate layer (14). A first metal layer (56) of metal or a metallograph is formed on the first mask layer (52) and on the first phase exposed region (53') exposed by the first and second first phase openings (54), and One or more first heat treatments are performed at the interface between the gate layer (14) and the first metal layer (56) in each first phase exposed region (53') to form a first first phase silicide region (58a) and a second first phase silicide region (58b), which are respectively contained within a first electrical modulation region (25a) and a second electrical modulation region (25b). The method according to claim 12, which includes the following.

14. The step of forming the first electrical modulation region (25a) and the second electrical modulation region (25b) is further followed by, After performing one or more of the first heat treatments, the first metal layer (56) is removed and the first first phase silicide region (58a) and the second first phase silicide region (58b) are left on the gate layer (14), and The first mask layer (52) is removed from the gate layer (14). The method according to claim 13, which includes the fact that

15. The first phase silicide region (58a) forms the first electrical modulation region (25a), The step of forming the first electrical modulation region (25a) and the second electrical modulation region (25b) is further followed by, After forming a first first phase silicide region (58a) and a second first phase silicide region (58b) on the gate layer (14), a second mask layer (62) is formed on the upper surface (14a) of the gate layer (14) and on the first first phase silicide region (58a), having a first second phase opening (64) that covers the first first phase silicide region (58a) and the first phase covering region (63") of the upper surface (14a) of the gate layer (14), and exposes the second first phase silicide region (58b). A second metal layer (66) made of a metal or metalloid is formed on the second mask layer (62) and on the second first phase silicide region (58) exposed by the first second phase opening (64), and At the interface between the second first phase silicide region (58b) and the second metal layer (66), one or more second heat treatments are performed to form the first second phase silicide region (68) above the first second phase silicide region (68) which forms the second first phase silicide region (58b), the second first phase silicide region (58b), and the second electrical modulation region (25b) along the first axis (Z). The method according to claim 13, which includes the following.

16. The step of forming the semiconductor body (3) includes forming at least one first basic cell (1') of the power MOSFET device (1') in the active region (7), A step of forming a drain region starting from a semiconductor material substrate, having a first conductivity type and having a first main surface (3a) and a second main surface (3b) opposite to each other along the first axis (Z), The steps of forming a first body region (9a) within the drain region (5) and starting from the first main surface (3a) of the drain region (5), having a second conductivity type opposite to the first conductivity type, and A step of forming a first source region (13a) having a first conductivity type in the first body region (9a) and starting from the first main surface (3a) of the drain region (5), This includes implementing the following: The first body region (9a) is adjacent to the drain region (5) and the first source region (13a), and defines the first channel region (13a) located between the first source region (13a) and the drain region (5). The insulated gate structure (15) is located above the drain region (5) and the first channel region (17a) along the first axis (Z) and can be electrically biased to control the first flow of charge carriers (18a) through the first channel region (17a) between the first source region (13a) and the drain region (5), and The first source region (13a), the drain region (5), and the first body region (9a) are contained within the semiconductor body (3), the first main surface (3a) of the drain region (5) defines the first main surface (3a) of the semiconductor body (3), and the second main surface (3b) of the drain region (5) defines the second main surface (3b) of the semiconductor body (3). The method according to any one of claims 12 to 15.

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