Photoelectric conversion device and system

Abstract

To solve the problem in which, when a control signal is applied to control a plurality of pixels simultaneously, a large transient current flows at a rising edge of the signal, causing a malfunction in the pixels and possibly damaging wiring.SOLUTION: The photoelectric conversion device includes a plurality of pixels arranged in a matrix configuration and a control circuit for controlling the plurality of pixels. The control circuit outputs a row selection pulse to select the pixels arranged in the row direction and a pixel control pulse whose rise time is longer than the row selection pulse.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a photoelectric conversion device and a system. [Background technology]

[0002] In recent years, photoelectric conversion devices in which pixels, each of which is made up of a light receiving element and multiple transistors, are arranged two-dimensionally are used in imaging devices such as digital still cameras and digital video cameras. In order to improve the quality of captured images, various driving methods have been attempted for photoelectric conversion devices.

[0003] Patent document 1 describes a method for preventing the saturation shading phenomenon and a reduction in dynamic range by making the transition time (fall time) when the voltage on the drain line common to all pixels is turned off longer than the transition time when the reset wiring and transfer wiring are turned off.

[0004] Patent Document 2 describes that in order to reduce noise and afterimages, a control signal for a transfer switch is generated that maintains a third level for a predetermined period of time when the transfer switch of a pixel is changed from an on state to an off state.

[0005] Patent Document 3 describes a method of reading out from each pixel a signal with high sensitivity but a small dynamic range and a signal with low sensitivity but a wide dynamic range by switching the readout mode. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2004-320592 A [Patent Document 2] JP 2002-77730 A [Patent Document 3] JP 2000-165754 A Summary of the Invention [Problem to be solved by the invention]

[0007] In a photoelectric conversion device, when a control signal for simultaneously controlling a plurality of pixels is applied, a large transient current flows at the rising edge of the control signal, which may cause malfunction of the pixels or damage to the wiring. [Means for solving the problem]

[0008] A first aspect of the present invention is a photoelectric conversion device comprising a plurality of pixels arranged in a matrix and a control circuit that controls the plurality of pixels, wherein the control circuit outputs a row selection pulse that selects the pixels arranged in a row direction, and a pixel control pulse that has a longer rise time than the row selection pulse.

[0009] A second aspect of the present invention is a photoelectric conversion device comprising a plurality of pixels arranged in a matrix and a control circuit that controls the plurality of pixels, wherein the control circuit outputs a row selection pulse that selects the pixels arranged in a row direction, and a pixel control pulse that has a longer rise time and fall time than the row selection pulse. Effect of the Invention

[0010] According to one embodiment of the present invention, even if a pixel control signal that controls multiple pixels simultaneously is applied, it is possible to prevent malfunctions or damage to wiring due to a transient large current flowing at the rise of the pixel control signal. [Brief description of the drawings]

[0011] [Figure 1] FIG. 2 is a diagram showing a circuit configuration of a photoelectric conversion device according to an embodiment. [Diagram 2] FIG. 2 is a diagram showing a circuit configuration of a unit pixel according to the first embodiment. [Diagram 3] 2 is a diagram showing a circuit configuration of an output stage of the pixel control circuit 120 according to the first embodiment. [Figure 4] 5 is a timing chart for explaining a cycle for reading out output signals from pixels in one row in the first embodiment. [Diagram 5] 10A and 10B are diagrams for explaining shading that occurs in a photoelectric conversion device of a reference example. [Figure 6] 1A is a diagram for explaining the variation in the rise time of the floating diffusion capacitance control signal FDINC generated in the photoelectric conversion device of the reference example, and FIG. 1B is a diagram for explaining the variation in the potential rise amount of the floating diffusion generated in the photoelectric conversion device of the reference example. [Figure 7] FIG. 4 is a diagram for explaining that shading is suppressed in the photoelectric conversion device according to the first embodiment. [Figure 8] FIG. 11 is a diagram showing a circuit configuration of a unit pixel according to a second embodiment. [Figure 9] FIG. 11 is a diagram showing a circuit configuration of an output stage of a pixel control circuit 127 according to a second embodiment. [Figure 10] 13A is a time chart showing a case where the voltage conversion gain is read out at 1 and 2 in the second embodiment; FIG. 13B is a time chart showing a case where the voltage conversion gain is read out at 2 and 8 in the second embodiment; [Figure 11] 13A is a time chart showing a case where the voltage conversion gain is read out at 1 and 8 in the second embodiment; FIG. 13B is a time chart showing a case where the voltage conversion gain is read out at 8 and 8 in the second embodiment; [Figure 12] 11 is a table showing the relationship between the voltage conversion gain and combinations of high (H) / low (L) of a floating diffusion capacitance control signal in the second embodiment. [Figure 13] FIG. 11 is a diagram showing a circuit configuration of a unit pixel according to a third embodiment. [Figure 14] FIG. 11 is a diagram showing a circuit configuration of an output stage of a pixel control circuit 128 according to a third embodiment. [Figure 15] 13A is a graph showing the relationship between an increase in FD potential and a luminance signal level, and FIG. 13B is a diagram for explaining linearity correction processing according to the fourth embodiment. [Figure 16] 1A is a schematic diagram illustrating an apparatus including a photoelectric conversion device according to an embodiment, FIG. 1B is a diagram illustrating an example of a photoelectric conversion system for an in-vehicle camera according to an embodiment, and FIG. 1C is a diagram illustrating a photoelectric conversion system for capturing an image in front of a vehicle. [Figure 17] FIG. 4 is a diagram showing another circuit configuration of the unit pixel according to the first embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] A photoelectric conversion device according to an embodiment of the present invention will be described with reference to the drawings. The photoelectric conversion device described in each embodiment described below is not limited to imaging applications. For example, it can also be applied to a distance measuring device (a device for measuring distance using focus detection or TOF (Time Of Flight)), a photometry device (a device for measuring the amount of incident light), etc. The conductivity types of the transistors described in the following embodiments are merely examples and are not limited to the conductivity types described in the examples. The conductivity types described in the embodiments can be changed as appropriate, and the potentials of the gate, source, and drain of the transistor can be changed as appropriate in accordance with this change. For example, in the case of a transistor operated as a switch, the low and high levels of the potential supplied to the gate can be reversed from those described in the embodiments in accordance with the change in conductivity type. The embodiments described below are merely examples, and those skilled in the art can appropriately modify and implement the detailed configurations, for example, without departing from the spirit and scope of the present invention.

[0013] In the drawings referred to in the following description of the embodiments, elements with the same reference numbers have the same functions unless otherwise noted. In addition, the drawings may be represented diagrammatically for convenience of illustration and explanation, and may not strictly match the actual shape, size, arrangement, etc. In the drawings, when a plurality of identical elements are arranged, the display of the symbols and their explanations may be omitted. In addition, when describing the arrangement of pixels with reference to the drawings, a "row" refers to a horizontal arrangement, and a "column" refers to a vertical arrangement.

[0014] [Embodiment 1] 1 shows the circuit configuration of a photoelectric conversion device according to this embodiment. The photoelectric conversion device includes a pixel array 20 in which pixels 10 are arranged in a matrix, and the pixels 10 arranged in rows are connected to a pixel control circuit 120 via common wiring (control signal lines) extending in the row direction. The pixels 10 arranged in columns are connected to an AD conversion circuit 160 and a current source 40 via vertical lines (output lines) extending in the column direction.

[0015] The pixel control circuit 120 outputs each control signal to each row of pixels, including FDINC, which controls the switching of the floating diffusion capacitance of the pixel, RES, which controls the ON / OFF of the reset transistor, TX, which controls the ON / OFF of the transfer transistor, and SEL, which controls the ON / OFF of the selection transistor. In Fig. 1, the pixel row number is added in parentheses after the name of the control signal.

[0016] The AD conversion circuit 160 and the current source 40 are circuits for reading out analog signals from the pixels of each column via the vertical lines and converting them into digital signals. The AD conversion circuit 160 includes a ramp signal supply circuit 50, comparators 60 to 63, first memories 70 to 73, second memories 80 to 83, and a counter 90.

[0017] The comparators 60 and 62 compare the signals of the vertical lines 30 and 32, respectively, with the ramp signal output from the ramp signal supply circuit 50. When the outputs of the comparators 60 and 62 change, the first memories 70 and 72 capture the count signal of the counter 90. When the outputs of the comparators 61 and 63 change, the first memories 71 and 73 capture the count signal of the counter 90. As a result, the signals output from the pixels 10 to the vertical lines are AD converted. The digital signals of the first memories 70 to 73 are transferred to the second memories 80 to 83, and then output to the processing circuit 95 as the AD conversion results.

[0018] The processing circuit 95 is a processing unit capable of performing signal processing (for example, correction processing) on ​​the digital signal output from the AD conversion circuit 160. The processing circuit 95 is connected to an output circuit 100 for outputting the processed digital signal to the outside. In this embodiment, a circuit configuration using a counter 90 common to a plurality of circuits is illustrated, but a configuration in which a common count clock is supplied and a counter is provided for each circuit corresponding to each vertical line may be used. In such a configuration, the counter 90 is not one, but is provided associated with each of the first memories 70 to 73. It is also possible to transmit some bits of the count clock to the memories 70 to 73 at the first position by a common counter, and generate other bits by counters provided for each circuit corresponding to each vertical line. It is also possible to use a circuit configuration having two comparators for one vertical line in this embodiment in order to make it possible to obtain output signals with different gains. It is also possible to use a circuit of another type, without being limited to the type shown in the figure. The photoelectric conversion device also includes a timing generator (TG) 161. The TG 161 controls the drive timing of the pixel control circuit 120, the AD conversion circuit 160, the processing circuit 95, and the output circuit 100.

[0019] Next, a unit pixel, which is a component of the pixel array 20, will be described with reference to Fig. 2. Fig. 2 shows the circuit configuration of pixel 10, but other pixels also have a similar circuit configuration. Pixel 10 has a photodiode 400, a transfer transistor 410, a floating diffusion 420, a source follower transistor 430, a selection transistor 440, a GND node 450, a reset transistor 455, a gain switching transistor 456, and a power supply node 460.

[0020] The photodiode 400 as a photoelectric conversion unit generates a signal charge according to the amount of received light. The transfer transistor 410 as a transfer unit is a changeover switch (transistor) that can turn on / off the conduction between the photodiode 400 and the floating diffusion 420. For example, when transferring the signal charge generated by the photodiode 400 to the floating diffusion 420, the transfer transistor 410 is turned on. The transfer transistor 410 is driven by a transfer unit control signal TX.

[0021] The floating diffusion 420 has a storage capacitance Cfd, and temporarily holds the signal charge transferred from the photodiode 400 via the transfer transistor 410, and at the same time functions as a charge-voltage converter that converts the held signal charge into a voltage signal.

[0022] A reset transistor 455 as a reset unit is a switch (transistor) that is turned on / off by a reset unit control signal RES. A gain switching transistor 456 as a capacitance switching unit is a switch (transistor) that is turned on / off by a floating diffusion capacitance control signal FDINC.

[0023] For example, when the charge of the floating diffusion 420 is reset, the reset transistor 455 and the gain switching transistor 456 are simultaneously turned on, and the floating diffusion 420 and the power supply node 460 are connected.

[0024] Moreover, by turning on the gain switching transistor 456 while the reset transistor 455 is in the off state, the gate capacitance Cinc of the capacitance switching section can be added to the storage capacitance Cfd of the floating diffusion 420. This allows the output signal to be read out in a state where the sensitivity is low but the dynamic range is large. That is, by switching the gain switching transistor 456 to the on state or the off state, the storage capacitance of the floating diffusion section can be changed, and the gain of the voltage conversion can be switched. The floating diffusion section here refers to the entire capacitance that temporarily holds the signal charge transferred from the photodiode 400. That is, when the gate capacitance Cinc is added to the floating diffusion 420, the floating diffusion 420 and the gate capacitance Cinc are the floating diffusion section. The gain switching transistor 456 is a transistor that switches the capacitance value of the floating diffusion section.

[0025] The source follower transistor 430 as an amplifier amplifies the voltage signal converted by the floating diffusion 420 and outputs it as a pixel signal. The selection transistor 440 as a selection section is an on / off switch (transistor) for outputting the pixel signal amplified by the source follower transistor 430 to the vertical line 30, and is driven by a selection section control signal SEL. Note that the source follower transistor 430 and the reset transistor 455 are connected to a common power supply node 460, but may be connected to separate power supply nodes. In this case, the power supply voltages of the source follower transistor 430 and the reset transistor 455 can be made different. All the transistors shown in Fig. 2 are formed of N-type MOS transistors. However, this is not limiting, and all the transistors may be P-type MOS transistors. Also, some of the transistors may be N-type and other transistors may be P-type. The potential of the control signal that controls each transistor is appropriately changed depending on the conductivity type of each transistor.

[0026] In the following description, for ease of reading, the transfer unit control signal TX will be referred to as the control signal TX, the reset unit control signal RES as the control signal RES, the floating diffusion capacitance control signal FDINC as the control signal FDINC, and the selection unit control signal SEL as the control signal SEL. Also, reference symbols such as SEL, RES, FDINC, and TX may be used to indicate control signals or may be used to indicate signal lines that propagate the control signals.

[0027] Next, the circuit configuration of the output stage of the pixel control circuit 120 will be described with reference to Fig. 3. The figure shows an extracted portion of the output stage of the pixel control circuit 120, and shows the portion that outputs four types of control signals, FDINC, RES, TX, and SEL, to one pixel row. The pixel control circuit 120 has circuits of similar configuration for each pixel row.

[0028] Reference numerals 121 to 124 denote buffer circuits, and the name of the signal input to each buffer circuit is the name of the control signal output from each buffer circuit with "IN" added to the end. In the following description, when a control signal turns a pixel transistor "on," the control signal is sometimes referred to as being at a "high level," and when a control signal turns a pixel transistor "off," the control signal is sometimes referred to as being at a "low level."

[0029] The buffer circuit 121 outputs a control signal FDINC for switching the gain switching transistor 456 on / off, and a current source circuit 125 and a current source circuit 126 are connected to the buffer circuit 121. The current source circuit 125 is a controlled current source whose amount of current is controlled by a control signal CONT1, and the current source circuit 126 is a controlled current source whose amount of current is controlled by the control signal CONT1. The control signals CONT1 and CONT2 may be signals output from the TG161, or may be generated inside the pixel control circuit 120.

[0030] The rise time of the control signal FDINC from a low level to a high level can be controlled by the current supplied by the current source circuit 125. As described below, to increase the rise time of the control signal FDINC, the control signal CONT1 can be set so that the current supplied by the current source circuit 125 is reduced. Also, the fall time of the control signal FDINC from a high level to a low level can be controlled by the current drawn by the current source circuit 126. For example, to increase the fall time of the control signal FDINC, the control signal CONT2 can be set so that the current drawn by the current source circuit 126 is reduced.

[0031] The buffer circuit 122 outputs a control signal RES that switches on / off the reset transistor 455. The buffer circuit 123 outputs a control signal TX that switches on / off the transfer transistor 410. The buffer circuit 124 outputs a control signal SEL (row selection pulse) that switches on / off the selection transistor 440.

[0032] In this embodiment, a current source circuit is provided only in the buffer circuit 121 that outputs the control signal FDINC, and no current source circuit is provided in the buffer circuits that output the other control signals.

[0033] Next, the transition over time of each control signal output by the pixel control circuit 120 in a cycle of reading out output signals from pixels in one row will be described with reference to the timing chart of Fig. 4. The figure shows the waveforms of the control signal RES, the control signal FDINC, the control signal SEL, and the control signal TX output from the buffer circuit of the row in which reading is performed in the pixel control circuit 120. Also shown is an example of the ramp waveform RAMP output from the ramp signal supply circuit 50 and the waveform of the pixel output signal SIG output to a vertical line from the selection transistor 440 of one pixel 10 in that row. Every time an output signal is read out from the pixels in each row, a similar control signal is output from the buffer circuit corresponding to the row in which reading is performed.

[0034] First, at time t0, the control signal RES and the control signal FDINC start to transition from low level to high level, turning on the reset transistor 455 and the gain switching transistor 456 of the pixel 10. When both transistors are turned on, the charge of the floating diffusion 420 is reset.

[0035] At time t1, the control signal SEL as a row selection pulse goes high, turning on the selection transistor 440 of each pixel in the row. The control signal SEL has a steep waveform with a rising slope of 30V / μsec or more near the output terminal of the buffer circuit 124, and the rise time TR0 is smaller than the rise time TR1 of the control signal FDINC. The rise time is the time required for the signal level to move from 10% to 90% of the maximum value, and the fall time is the time required for the signal level to move from 90% to 10% of the maximum value.

[0036] At time t2, the control signal RES becomes low level, and the reset of the floating diffusion 420 of each pixel in the row is released. As the pixel output signal SIG, a signal corresponding to the reset level of the pixel is output to the vertical line 30 via the source follower transistor 430 and the selection transistor 440. At this time, since the control signal FDINC is high level, the gain switching transistor 456 is in an on state, and the storage capacitance of the floating diffusion section is the gate capacitance Cinc + storage capacitance Cfd. That is, the low gain is selected, and the signal LGainN corresponding to the reset level of the pixel at the low gain appears as the pixel output signal SIG. The AD conversion circuit 160 compares the signal LGainN with the ramp waveform RAMP, and obtains digital data of the reset level of the pixel at the low gain from the comparison result. The digital data is sent to the processing circuit 95 as data for CDS.

[0037] Next, at time t3, the control signal FDINC becomes low level, and the gain switching transistor 456 is turned off. As a result, the storage capacitance becomes the storage capacitance Cfd of the floating diffusion 420, and the conversion gain is switched from low gain to high gain. As the pixel output signal SIG, a signal HGainN corresponding to the reset level of the pixel in the high gain is output to the vertical line 30. The AD conversion circuit 160 compares the signal HGainN with the ramp waveform RAMP, and obtains digital data of the reset level of the pixel in the high gain from the comparison result. The digital data is sent to the processing circuit 95 as data for CDS.

[0038] Here, the fall time TF1 when the control signal FDINC transitions from a high level to a low level can be controlled by the current source circuit 126 of the buffer circuit 121. In this embodiment, as shown in the figure, the pixel control circuit 120 is configured so that the fall time TF1 of the control signal FDINC is longer than the fall time TF0 of the control signal SEL as a row selection pulse.

[0039] These control signals are propagated through row-direction wiring for commonly connecting pixels arranged in the row direction, and all of the wiring extends in the row direction in a substantially similar manner, and the wiring resistance and parasitic capacitance are distributed to the same extent. The parasitic capacitance includes the capacitance between the wirings extending in parallel and the capacitance associated with each pixel connected to the wiring (for example, in the case of the signal line FDINC, the gate-source capacitance Cgs of the gain switching transistor 456 shown in FIG. 2). If the falling edge of the control signal is made steep, the signal waveform is deformed as it travels away from the output section (buffer circuit) of the pixel control circuit 120 while propagating through the row-direction wiring, and the waveform of the control signal applied to the pixel may differ depending on the position in the row direction.

[0040] As for the control signal SEL, the transition to low level starts after the acquisition (AD conversion) of the output signal of the row is completed, so the potential level of the vertical line is not used as a signal until t1 (rising) in the cycle for reading the next row. Therefore, even if the falling waveform (falling time) of the control signal SEL applied to each pixel varies depending on the position in the row direction, it is unlikely to cause any problems in the readout operation.

[0041] On the other hand, for the control signal FDINC, after switching the pixel gain from low gain to high gain at time t3, it is necessary to read out the reset level at high gain from each pixel in the row. If the fall of the control signal FDINC is made steep like the control signal SEL, the signal waveform applied to the pixel may differ depending on the position in the row direction due to the influence of the resistance and parasitic capacitance of the row-direction wiring. Then, the gain switching timing differs for each pixel, and the readout condition of the reset level of the pixel at high gain becomes non-uniform for each pixel. Therefore, in this embodiment, the fall time TF1 of the control signal FDINC output from the buffer circuit 121 is configured to be longer than the fall time TF0 of the control signal SEL output from the buffer circuit 124. This makes it possible to read out the reset level of the pixel at high gain under uniform conditions from each pixel regardless of the position in the row direction.

[0042] After acquiring a digital signal of a reset level at high gain at time t4, the control signal TX goes high for a predetermined period at a predetermined timing. The transfer transistor 410 is turned on, and the photocharge photoelectrically converted in the photodiode 400 is transferred to the floating diffusion 420.

[0043] During the period from time t5 to t6, the pixel output signal SIG read out to the vertical line 30 through the source follower transistor 430 and the selection transistor 440 in a high gain state is AD converted by the AD conversion circuit 160. That is, the ramp waveform RAMP output from the ramp signal supply circuit 50 is compared with the waveform of the pixel output signal SIG output to the vertical line from the selection transistor 440 of the pixel, and digital data is acquired. After the control signal TX becomes low level at time t5, photocharges are accumulated again in the photodiode 400.

[0044] Next, at time t6, the control signal FDINC is transitioned from low level to high level. The gain switching transistor 456 is turned on, and the storage capacitance of the floating diffusion portion becomes the gate capacitance Cinc+storage capacitance Cfd. That is, switching from high gain to low gain is performed.

[0045] The rise time TR1 when the control signal FDINC transitions from a low level to a high level can be controlled by the current source circuit 125 of the buffer circuit 121. In this embodiment, as shown in the figure, the pixel control circuit 120 is configured so that the rise time TR1 of the control signal FDINC is longer than the rise time TR0 of the control signal SEL as a row selection pulse. In other words, the circuit is configured so that the rise time TR1 of the control signal FDINC output from the buffer circuit 121 is longer than the rise time TR0 of the control signal SEL output from the buffer circuit 124.

[0046] As a comparison with this embodiment, a case will be described with reference to FIG. 5 where the control signal FDINC is a waveform with a steep slope of 30 V / μsec or more, similar to the rise of the control signal SEL. The pixel array 20 is shown in a plan view in the lower part of FIG. 5, and in this example, pixel control circuits DRC are arranged on both the left and right sides of the pixel array. That is, the control signal is supplied from both sides of each row-directional wiring. One row-directional wiring is shown in a schematic diagram above the pixel array, which is a line with distributed resistance and parasitic capacitance, and both ends are connected to the buffer circuit of the pixel control circuit DRC. When a control signal FDINC with a steep rise is output from the buffer circuit, the rise waveform breaks down as shown in the figure as it moves away from the buffer circuit, and the transition time of gain switching varies between pixels close to the buffer circuit and pixels far from it. That is, as shown in FIG. 6(a), the rise time of the control signal FDINC varies for each pixel, and the rise time becomes longer for pixels farther from the buffer circuit.

[0047] In each pixel, the clock feedthrough phenomenon occurs when the control signal FDINC transitions from off to on. That is, the potential of the floating diffusion 420 rises due to charge injection via the gate-source capacitance Cgs (see FIG. 2) of the gain switching transistor 456. If the rise of the control signal FDINC is steep, the potential rise of the floating diffusion (swing-up from on to off) is large, and if the rise is gradual, the potential rise is small. If the rise time varies from pixel to pixel as shown in FIG. 6(a), the floating diffusion potential (i.e., the operating point of the pixel) varies from pixel to pixel as shown in FIG. 6(b). For this reason, even if the subsequent circuit (AD conversion circuit or logic circuit) performs arithmetic processing of S (signal component)-N (reset component), the operating point differs for each pixel, so some degradation of image quality occurs. That is, as shown in the upper part of FIG. 5, shading occurs at the center and both ends of the screen in the row direction.

[0048] In contrast, according to the present embodiment, the occurrence of shading can be effectively suppressed. With reference to FIG. 7, a case will be described in which the control signal FDINC is set to a waveform of less than 30 V / μsec, which has a smaller slope than the rise of the control signal SEL. The pixel array 20 is shown in a plan view in the lower part of the figure, and in this example, the pixel control circuits 120 are arranged on both the left and right sides of the pixel array. That is, the control signal is supplied from both sides of each row-directional wiring. One row-directional wiring is shown in a schematic diagram above the pixel array, which is a line in which resistance and parasitic capacitance are distributed, and both ends are connected to the buffer circuit of the pixel control circuit 120. Since the control signal FDINC with a large rise time is output from the buffer circuit, the distortion of the rising waveform when propagating through the row-directional wiring is small, and the difference in waveform occurring between pixels close to the buffer circuit and pixels far from the buffer circuit is suppressed. Therefore, the variation in the potential rise due to the transition time of gain switching and the clock feedthrough phenomenon is suppressed, and a highly uniform image signal with suppressed shading can be obtained, and the effective dynamic range can also be expanded. In this example, the pixel control circuit DRC is disposed on both the left and right sides of the pixel array, but the same problem occurs even if the pixel control circuit DRC is provided on only one side of the pixel array. That is, when the control signal FDINC has the above-mentioned steep waveform, the transition time of gain switching varies between pixels close to the buffer circuit of the pixel control circuit DRC and pixels far from it. In contrast, when the control signal FDINC has the above-mentioned waveform with a small slope, the difference in waveform between pixels close to the buffer circuit and pixels far from it is suppressed. Therefore, even if the pixel control circuit DRC is provided on only one side of the pixel array, the above-mentioned effect can be obtained.

[0049] Returning to FIG. 4, during the period from time t6 to t7, the control signal TX becomes high level for a predetermined period, the transfer transistor 410 is turned on, and the photoelectric charge photoelectrically converted in the photodiode 400 is transferred to the floating diffusion 420. A voltage corresponding to the photoelectric charge signal appears on the vertical line via the source follower transistor and the selection transistor. As described above, the control signal FDINC has already transitioned to a high level, and the conversion gain is low, so that the output signal at low gain appears on the vertical line. Note that in FIG. 4, the control signal TX is at a high level for a predetermined period during the period from time t6 to t7, but it may remain at a low level. In this case, the exposure timing corresponding to the high gain signal and the low gain signal can be made the same. On the other hand, when the control signal TX is at a high level for a predetermined period during the period from time t6 to t7 as in FIG. 4, even more signal charges can be read out. Therefore, the sensitivity in low gain signal generation can be improved.

[0050] In the period from time t7 to t8, the pixel output signal SIG read out to the vertical line 30 via the source follower transistor 430 and the selection transistor 440 in a low gain state is AD converted by the AD conversion circuit 160. That is, the ramp waveform RAMP output from the ramp signal supply circuit 50 and the waveform of the pixel output signal SIG output to the vertical line from the selection transistor 440 of the pixel are compared, and digital data is obtained.

[0051] Thereafter, the processing circuit 95 performs so-called digital CDS (Correlated Double Sampling) processing by calculating the difference between the output signal corresponding to the photoelectric charge and the reset level for each of the high gain and low gain digital data.

[0052] As described above, by switching the control signal FDINC from on to off and off to on in sequence and converting the output signal into analog-to-digital form, it is possible to obtain the high-gain and low-gain reset signal components and the optical signal components as digital signals. By enabling readout at high and low gains, it is possible to read out signals over a wider brightness range.

[0053] In this embodiment, the transition time from off to on of the control signal FDINC as a pixel control signal (pixel control pulse) is lengthened by limiting the current supplied to the buffer in the pixel control circuit. This makes it possible to obtain good low-gain image data with reduced variation between pixels. For example, when synthesizing one HDR image from images with different gains by post-processing, the dynamic range of images that can be obtained by the solid-state imaging element can be expanded by synthesizing the images using a high-gain image on the low-illuminance side and a low-gain image on the high-luminance side.

[0054] In addition, the slope of the rising waveform when the control signal FDINC output from the pixel control circuit 120 transitions from off to on is preferably less than 30V / μsec (a transition of 3V in 100nsec). The current source circuit 125 has been described as being capable of variably controlling the amount of current by the control signal CONT1, but it is not necessarily required to have a circuit configuration capable of variably controlling the amount of current by the control signal. In short, it is sufficient if the circuit can limit the current supplied to the output stage in order to increase the rise time of the control signal FDINC to an extent that shading can be suppressed. Therefore, for example, the current source circuit may be a current source circuit using an active element such as a transistor, or a simple current limiting circuit using a current limiting resistor. Alternatively, the control signal FDINC may be configured to have a longer rise time than the control signal SEL by using output stage transistors with different L / W for the buffer circuit 121 and the buffer circuit 124. The same can be said about the control of the fall time of the control signal FDINC and the configuration of the current source circuit 126. In this embodiment, an example has been described in which the reset transistor 455 and the gain switching transistor 456 are provided in series in the electrical path between the power supply node 460 and the floating diffusion 420. The present invention is not limited to this example, and may be an example in which the gain switching transistor 456 and the reset transistor 455 are each connected to the floating diffusion 420 as shown in FIG. 17. In this case, the reset transistor 455 is connected to the floating diffusion 420 without passing through the gain switching transistor 456. The configuration shown in FIG. 17 can also be driven by the same operation as that shown in FIG. 4. The effect described in this embodiment can also be obtained in the configuration shown in FIG. 17.

[0055] [Embodiment 2] A photoelectric conversion device according to a second embodiment will be described with reference to the drawings. However, the description of matters common to the first embodiment will be simplified or omitted, and the description will focus on the differences from the first embodiment. In this embodiment, each pixel has two gain switching transistors, and the pixel control circuit supplies floating diffusion capacitance control signals to the two gain switching transistors independently. Note that each pixel may be provided with three or more gain switching transistors, and each pixel may be configured to supply a floating diffusion capacitance control signal independently.

[0056] A unit pixel according to this embodiment will be described with reference to Fig. 8. Fig. 8 shows the circuit configuration of a pixel 110, but other pixels constituting the pixel array also have a similar circuit configuration. The pixel 110 has a photodiode 400, a transfer transistor 410, a floating diffusion 420, a source follower transistor 430, a selection transistor 440, a GND node 450, a reset transistor 455, a gain switching transistor 456A, a gain switching transistor 456B, and a power supply node 460.

[0057] The gain switching transistor 456A is driven by a control signal FDINC-A, and the gain switching transistor 456B is driven by a control signal FDINC-B. For example, when resetting the charge of the floating diffusion 420, the reset transistor 455, the gain switching transistor 456A, and the gain switching transistor 456B are simultaneously turned on, and the floating diffusion 420 and the power supply node 460 are connected.

[0058] In this embodiment, the gain of the voltage conversion can be switched between three levels by switching the gain switching transistor 456A and the gain switching transistor 456B on / off during signal readout. Fig. 12 is a table showing the relationship between the high (H) / low (L) combination of the floating diffusion capacitance control signal and the voltage conversion gain.

[0059] For example, when the control signals FDINC-A and FDINC-B are both L, the gain switching transistor 456A and the gain switching transistor 456B are both turned off. Since the gate capacitance of neither of the gain switching transistors is connected to the storage capacitance of the floating diffusion 420, the voltage conversion gain is 8 times. Also, when the control signal FDINC-A is H and the control signal FDINC-B is L, the gain switching transistor 456A is turned on and the gain switching transistor 456B is turned off. The gate capacitance of the gain switching transistor 456A is connected to the storage capacitance of the floating diffusion 420, and the voltage conversion gain is doubled. Also, when the control signals FDINC-A and FDINC-B are both H, the gain switching transistor 456A and the gain switching transistor 456B are both turned on. Therefore, the gate capacitance of both gain switching transistors is connected to the storage capacitance of the floating diffusion 420, and the voltage conversion gain is 1 time.

[0060] Next, the circuit configuration of the output stage of the pixel control circuit 127 will be described with reference to FIG. 9. The figure shows a part of the output stage of the pixel control circuit 127, and shows a part that outputs five types of control signals, FDINC-A, FDINC-B, RES, TX, and SEL, to one pixel row. 121 to 124 are buffer circuits, and the name of the signal input to each buffer circuit is the name of the control signal output from each buffer circuit with "IN" added to the end. The buffer circuits 121 of FDINC-A and FDINC-B each include a current source circuit 125 and a current source circuit 126 at each power supply node. By adjusting the current of the current source circuit, it is possible to adjust the transition time from off to on and from on to off of the control pulse as in the first embodiment.

[0061] Next, the read sequence when the voltage conversion gain is set to each of magnifications of 1x, 2x, and 8x will be described. Fig. 10(a) to Fig. 11(b) are time charts showing the read sequence of one row when the voltage conversion gain is set to various values. Fig. 10(a) shows the cases where the voltage conversion gain is read out at 1x and 2x, and Fig. 10(b) shows the cases where the voltage conversion gain is read out at 2x and 8x. Fig. 11(a) shows the cases where the voltage conversion gain is read out at 1x and 8x, and Fig. 11(b) shows the cases where the voltage conversion gain is read out at 8x and 8x.

[0062] The rise time / fall time of the control signal FDINC-A and the control signal FDINC-B as pixel control signals (pixel control pulses) are set to be longer than the rise time / fall time of the control signal SEL (not shown). Therefore, as in the first embodiment, an output signal and a reset level signal in which shading is suppressed can be read out from each pixel regardless of the position in the row direction. According to this embodiment, which allows three-stage gain switching, the optimal gain is selected to synthesize one HDR image, thereby making it possible to further expand the dynamic range of images that can be acquired by a solid-state imaging element.

[0063] [Embodiment 3] A photoelectric conversion device according to embodiment 3 will be described with reference to the drawings, but the description of matters common to embodiment 1 will be simplified or omitted, and differences from embodiment 1 will be mainly described. In this embodiment, each pixel has a photodiode and a plurality of transfer transistors (eight in the example), and a pixel control circuit supplies a transfer unit control signal independently to each transfer transistor. Note that the number of photodiodes and transfer transistors included in one pixel is not limited to eight, and may be any other number.

[0064] A unit pixel according to this embodiment will be described with reference to FIG. 13. FIG. 13 shows the circuit configuration of the pixel 200, but the other pixels arranged in a matrix also have the same circuit configuration. The pixel 200 includes photodiodes 400A to 400H, transfer transistors 410-1 to 410-8, a floating diffusion 420, a source follower transistor 430, a selection transistor 440, a reset transistor 455, a gain switching transistor 456, and a power supply node 460. The photodiodes 400A to 400H are configured so as to be connectable to the floating diffusion 420 by the transfer transistors 410-1 to 410-8. That is, a shared pixel structure is configured in which a floating diffusion is shared by a plurality of photodiodes. The gates of the transfer transistors 410-1 to 410-8 are individually connected to control lines TX1 to TX8 for supplying transfer control signals.

[0065] The circuit configuration of the output stage of the pixel control circuit 128 according to this embodiment will be described with reference to Fig. 14. The figure shows an extracted portion of the output stage of the pixel control circuit 128, illustrating a portion that outputs eleven types of control signals, FDINC, RES, TX1 to TX8, and SEL, to one pixel row. Numerals 121 to 124 denote buffer circuits, and the names of the signals input to each buffer circuit are the names of the control signals output from each buffer circuit with "IN" added to the end.

[0066] In the pixel control circuit 128 according to the present embodiment, not only the buffer circuit for the control signal FDINC, but also the buffer circuits for the control signals TX1 to TX8 and the buffer circuit for the control signal RES are provided with current source circuits on the side of each power supply node. That is, the pixel control circuit 128 is provided with a configuration that can make the OFF-to-ON transition time of the pulse waveforms of the control signals FDINC, TX1 to TX8, and RES as pixel control pulses longer than the OFF-to-ON transition time of the selection control signal SEL. The pixel control circuit 128 is also provided with a configuration that can make the ON-to-OFF transition time of the pulse waveforms of the control signals FDINC, TX1 to TX8, and RES longer than the ON-to-OFF transition time of the selection control signal SEL.

[0067] According to this embodiment, in addition to the shading suppression effect similar to that of the first embodiment, it is possible to suppress the instantaneous current of the reset control signal and the instantaneous current of the transfer control signal. For example, it is possible to suppress the instantaneous current during a collective reset operation of all pixels, and to suppress the instantaneous current during a simultaneous transfer operation of multiple pixels. This makes it possible to prevent problems such as the electromigration phenomenon of wiring caused by instantaneous overcurrent in a photoelectric conversion device with an ultra-high number of pixels, that is, disconnection, increased wiring resistance, or breakage of bonding wires in an IC package. In this embodiment, the control signal FDINC, the control signals TX1 to TX8, and the control signal RES are all configured to have a longer transition time from OFF to ON of the pulse waveform than the transition time from OFF to ON of the selection control signal SEL. However, the present invention is not limited to this example. The variation in the floating diffusion potential due to the clock feedthrough phenomenon described in the first embodiment is caused by a change in the control signal of the transistor having a parasitic capacitance with respect to the floating diffusion. Therefore, the transition time from OFF to ON of the control signal that controls at least one of the transistors having a parasitic capacitance with respect to the floating diffusion is made longer than the transition time from OFF to ON of the selection control signal SEL. This makes it possible to obtain an image signal with high uniformity in which shading is suppressed. That is, in this embodiment, it is sufficient to make the transition time from OFF to ON of at least one of the control signals FDINC, the control signals TX1 to TX8, and the control signal RES longer than the transition time from OFF to ON of the selection control signal SEL. This makes it possible to obtain an image signal with high uniformity in which shading is suppressed.

[0068] [Embodiment 4] A photoelectric conversion device according to embodiment 4 will be described, but this embodiment can be implemented in combination with embodiments 1 to 3. In embodiments 1 to 3, the rise time of the control signal FDINC is configured to be longer than the rise time of the control signal SEL, thereby suppressing variations (shading) in the potential rise of the floating diffusion due to the clock feedthrough phenomenon.

[0069] In this embodiment, a linearity correction process for correcting the nonlinearity of the luminance signal level (output signal level) with respect to the floating diffusion potential is further performed in the processing circuit 95 (FIG. 1) downstream of the AD conversion circuit 160. This linearity correction process is a process for correcting the nonlinearity of the sensitivity caused by the rise in the FD potential due to the transition of FDINC from off to on.

[0070] FIG. 15(a) is a graph showing the relationship between the rise in FD potential and the luminance signal level, and it can be seen that nonlinearity occurs due to the swing-up by the control signal FDINC. In this embodiment, as shown in FIG. 15(b), a correction process for improving linearity is performed by a processing circuit 95 (processing unit). Specifically, a correction table for correcting linearity is acquired in advance, and correction process is performed on the digital luminance signal after CDS processing. The correction process may be software processing or hardware processing using a dedicated processing circuit. According to this embodiment, it is possible to obtain a high-quality image in which shading is suppressed and the linearity of the output signal of each pixel is excellent.

[0071] [Embodiment 5] As embodiment 5, a system including a photoelectric conversion device according to the present invention will be described. Fig. 16(a) is a schematic diagram for explaining an apparatus 9191 including a semiconductor device 930. The semiconductor device 930 includes a photoelectric conversion device according to any one of the above-mentioned embodiments as a semiconductor device 910. The apparatus 9191 including the semiconductor device 930 will be described in detail.

[0072] The semiconductor device 930 may include, in addition to the semiconductor device 910, a package 920 that houses the semiconductor device 910. The package 920 may include a base to which the semiconductor device 910 is fixed, and a lid such as glass that faces the semiconductor device 910. The package 920 may further include bonding members such as bonding wires and bumps that connect terminals provided on the base and terminals provided on the semiconductor device 910.

[0073] The device 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 is provided corresponding to the semiconductor device 930, and is, for example, a lens, a shutter, or a mirror. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0074] The processing device 960 processes the signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0075] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) included in the device 9191. For this purpose, the device 9191 preferably further includes a memory device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit included in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0076] The device 9191 is also suitable for electronic devices such as information terminals (e.g., smartphones and wearable devices) with a photographing function and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for vibration isolation operation.

[0077] The device 9191 may be a transport device such as a vehicle, a ship, or an aircraft. The mechanical device 990 in the transport device may be used as a moving device. The device 9191 as a transport device is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) by using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0078] According to the above-described embodiment, it is possible to obtain an image with good characteristics, thereby increasing the value of the semiconductor device. In this case, increasing the value corresponds to at least one of adding a function, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental load, reducing costs, making the device smaller, and reducing weight.

[0079] Therefore, if the semiconductor device 930 according to this embodiment is used in the equipment 9191, the value of the equipment can be improved. For example, by mounting the semiconductor device 930 on a transport equipment, excellent performance can be obtained when photographing the outside of the transport equipment and measuring the external environment. Therefore, in manufacturing and selling the transport equipment, it is advantageous to decide to mount the semiconductor device according to this embodiment on the transport equipment in order to improve the performance of the transport equipment itself. In particular, the semiconductor device 930 is suitable for transport equipment that uses information obtained by the semiconductor device to perform driving assistance and / or automatic driving of the transport equipment. Note that the implementation in vehicles, ships, aircraft, etc. is not limited to application to equipment used for transportation purposes, and can also be suitably implemented in drones and the like that perform aerial photography for various purposes including inspection of buildings and agricultural facilities and monitoring of natural phenomena. Moreover, the photoelectric conversion system and the moving object of this embodiment will be described with reference to FIG. 16(b) and FIG. 16(c).

[0080] FIG. 16(b) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 8 has a photoelectric conversion device 800, which is the photoelectric conversion device described in any of the above embodiments. The photoelectric conversion system 8 has an image processing unit 801 that performs image processing on a plurality of image data acquired by the photoelectric conversion device 800, and a parallax acquisition unit 802 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the photoelectric conversion system 8. The photoelectric conversion system 8 also has a distance acquisition unit 803 that calculates a distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire distance information to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 804 may determine the possibility of collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware or a software module, or may be realized by a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or the like.

[0081] The photoelectric conversion system 8 is connected to a vehicle information acquisition device 810, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 8 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 804. The photoelectric conversion system 8 is also connected to an alarm device 830 that issues an alarm to the driver based on the judgment result of the collision judgment unit 804. For example, when the judgment result of the collision judgment unit 804 indicates that there is a high possibility of a collision, the control ECU 820 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., and vibrating the seat belt or steering wheel.

[0082] In this embodiment, the surroundings of the vehicle, for example the front or rear, are imaged by the photoelectric conversion system 8. Fig. 16(c) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 850). A vehicle information acquisition device 810 sends an instruction to the photoelectric conversion system 8 or the photoelectric conversion device 800. This configuration can further improve the accuracy of distance measurement. Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from lanes, etc. Furthermore, the photoelectric conversion system is not limited to vehicles such as the vehicle itself, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies, but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0083] [Other embodiments] The present invention is not limited to the above-described embodiment and examples, and many modifications are possible within the technical concept of the present invention. For example, the above-described different embodiments may be combined to implement the present invention.

[0084] Further, the photoelectric conversion device to which the present invention can be applied is not limited to a specific form, and for example, the light receiving portion may be either a front-illuminated type or a back-illuminated type. Also, a stacked type photoelectric conversion device in which a semiconductor chip having a light receiving portion and a semiconductor chip having a logic portion are stacked may be used. In this case, the pixel array of the pixel 10 shown in FIG. 1 is provided on one semiconductor chip. Then, the AD conversion circuit 160, the pixel control circuit 120, the TG 161, the processing circuit 95, and the output circuit 100 may be provided on another semiconductor chip. Also, the stacked type photoelectric conversion device may include three or more semiconductor chips. Examples of the three semiconductor chips include a semiconductor chip having a light receiving portion, a semiconductor chip having a logic portion, and a semiconductor chip having a memory portion. On the other hand, the photoelectric conversion device may be provided with all the configurations shown in FIG. 1 on one semiconductor chip. Although the case where the image signal output from the photoelectric conversion device is a digital signal has been described, the image signal may be output in the form of an analog signal.

[0085] The disclosure of this embodiment includes the following configuration. [Configuration 1] A plurality of pixels arranged in a matrix; A control circuit for controlling the plurality of pixels, the control circuit outputs a row selection pulse for selecting the pixels arranged in a row direction, and a pixel control pulse having a rise time longer than that of the row selection pulse. A photoelectric conversion device comprising: [Configuration 2] A plurality of pixels arranged in a matrix; A control circuit for controlling the plurality of pixels, the control circuit outputs a row selection pulse for selecting the pixels arranged in a row direction, and a pixel control pulse having a rise time and a fall time longer than those of the row selection pulse. A photoelectric conversion device comprising: [Configuration 3] The pixel control pulse includes a control signal for controlling a transistor for switching a capacitance value of a floating diffusion portion included in the pixel. 3. The photoelectric conversion device according to configuration 1 or 2. [Configuration 4] a processing unit that corrects nonlinearity of an output signal level of the pixel caused by an increase in potential of the floating diffusion unit; 4. The photoelectric conversion device according to configuration 3. [Configuration 5] The pixel control pulse includes a plurality of control signals for controlling a plurality of transistors for switching a capacitance value of a floating diffusion portion included in the pixel. 5. The photoelectric conversion device according to any one of configurations 1 to 4. [Configuration 6] The pixel control pulse includes a signal for controlling a transfer transistor that transfers a signal charge from a photodiode included in the pixel to a floating diffusion portion. 6. The photoelectric conversion device according to any one of configurations 1 to 5. [Configuration 7] The pixel control pulse includes a plurality of signals for controlling a plurality of transfer transistors that transfer signal charges from a plurality of photodiodes included in the pixel to a floating diffusion portion. 7. The photoelectric conversion device according to any one of configurations 1 to 6. [Configuration 8] The pixel control pulse includes a signal for controlling a reset transistor that resets a floating diffusion portion provided in the pixel. 8. The photoelectric conversion device according to any one of configurations 1 to 7. [Configuration 9] the control circuit includes a current source circuit at an output section of the pixel control pulse for making a rise time of the pixel control pulse slower than a rise time of the row selection pulse; 9. The photoelectric conversion device according to any one of configurations 1 to 8. [Configuration 10] the control circuit includes at least one of a current limiting resistor and a transistor at an output section of the pixel control pulse for making the rise time of the pixel control pulse slower than the rise time of the row selection pulse; 9. The photoelectric conversion device according to any one of configurations 1 to 8. [Configuration 11] the control circuit includes a current source circuit at an output section of the pixel control pulse for making the fall time of the pixel control pulse slower than the fall time of the row selection pulse; 11. The photoelectric conversion device according to any one of configurations 1 to 10. [Configuration 12] the control circuit includes at least one of a current limiting resistor and a transistor at an output section of the pixel control pulse for making a fall time of the pixel control pulse slower than a fall time of the row selection pulse; 11. The photoelectric conversion device according to any one of configurations 1 to 10. [Configuration 13] The rising slope of the pixel control pulse is less than 30V / μsec. 13. The photoelectric conversion device according to any one of configurations 1 to 12. [Configuration 14] The falling slope of the pixel control pulse is less than 30V / μsec. 14. The photoelectric conversion device according to any one of configurations 1 to 13. [Configuration 15] 15. A system comprising: a photoelectric conversion device according to any one of configurations 1 to 14; and a processing device that processes image data output from the photoelectric conversion device. [Explanation of symbols]

[0086] 10···pixel / 20···pixel array / 30, 32···vertical line / 40···current source / 50···ramp signal supply circuit / 60~63···comparator / 70~73···first memory / 80~83···second memory / 90···counter / 95···processing circuit / 100···output circuit / 110···pixel / 120···pixel control circuit / 121~124···buffer circuit / 125···current source circuit / 126···current source circuit / 127, 128···pixel control circuit / 1 30···Vertical line / 160···AD conversion circuit / 200···Pixel / 400, 400A~400H···Photodiode / 410, 410-1~410-8···Transfer transistor / 420···Floating diffusion / 430···Source follower transistor / 440···Selection transistor / 450···GND node / 455···Reset transistor / 456, 456A, 456B···Gain switching transistor / 460···Power supply node

Claims

1. A plurality of pixels arranged in a matrix, and a control circuit for controlling the plurality of pixels, wherein each of the plurality of pixels has a photoelectric conversion unit that generates signal charges, a floating diffusion unit, a transfer transistor that transfers the signal charges to the floating diffusion unit, and a transistor electrically connected to the floating diffusion unit, the control circuit outputs a row selection pulse for selecting the pixels arranged in the row direction and a pixel control pulse having a rise time longer than that of the row selection pulse, and the pixel control pulse is input to the gate of the transistor, characterized in that it is a photoelectric conversion device.

2. A plurality of pixels arranged in a matrix, and a control circuit for controlling the plurality of pixels, wherein the control circuit outputs a row selection pulse for selecting the pixels arranged in the row direction and a pixel control pulse having a rise time and a fall time longer than those of the row selection pulse, characterized in that it is a photoelectric conversion device.

3. The transistor is a transistor that switches the capacitance value of the floating diffusion unit included in the pixel. The photoelectric conversion device according to claim 1, characterized in that.

4. The pixel control pulse includes a control signal for controlling a transistor that switches the capacitance value of the floating diffusion unit included in the pixel. The photoelectric conversion device according to claim 2, characterized in that.

5. It comprises a processing unit for correcting the non-linearity of the output signal level of the pixel caused by the rise in the potential of the floating diffusion unit. The photoelectric conversion device according to claim 3, characterized in that.

6. It comprises a processing unit for correcting the non-linearity of the output signal level of the pixel caused by the rise in the potential of the floating diffusion unit. The photoelectric conversion device according to claim 4, characterized in that.

7. The pixel has a plurality of transistors including the transistor, each of the plurality of transistors is a transistor that switches the capacitance value of the floating diffusion unit included in the pixel, and the pixel control pulse includes a plurality of control signals for controlling the plurality of transistors. The photoelectric conversion device according to claim 1, characterized in that.

8. The pixel control pulse includes a plurality of control signals for controlling a plurality of transistors that switch the capacitance value of a floating diffusion section included in the pixel. The photoelectric conversion device according to claim 2, characterized in that.

9. The transistor is a transfer transistor that transfers signal charges from the photoelectric conversion section included in the pixel to the floating diffusion section. The photoelectric conversion device according to claim 1, characterized in that.

10. The pixel control pulse includes a signal for controlling a transfer transistor that transfers signal charges from a photodiode included in the pixel to a floating diffusion section. The photoelectric conversion device according to claim 2, characterized in that.

11. The pixel has a first transistor that is the transistor, a second transistor, a first photodiode and a second photodiode as the photoelectric conversion section. The first transistor is a transistor that transfers signal charges from the first photodiode to the floating diffusion section. The second transistor is a transistor that transfers signal charges from the second photodiode to the floating diffusion section. The pixel control pulse includes a plurality of signals for controlling the first transistor and the second transistor. The photoelectric conversion device according to claim 1, characterized in that.

12. The pixel control pulse includes a plurality of signals for controlling a plurality of transfer transistors that transfer signal charges from a plurality of photodiodes included in the pixel to a floating diffusion section. The photoelectric conversion device according to claim 2, characterized in that.

13. The transistor is a reset transistor that resets the floating diffusion section included in the pixel. The photoelectric conversion device according to claim 1, characterized in that.

14. The pixel control pulse includes a signal for controlling a reset transistor that resets the floating diffusion section included in the pixel. The photoelectric conversion device according to claim 2, characterized in that.

15. The control circuit includes a current source circuit for making the rise time of the pixel control pulse longer than the rise time of the row selection pulse at an output section of the pixel control pulse. The photoelectric conversion device according to claim 1, characterized in that.

16. The control circuit includes a current source circuit for making the rise time of the pixel control pulse longer than the rise time of the row selection pulse, at an output section of the pixel control pulse. The photoelectric conversion device according to claim 2, characterized in that.

17. The control circuit includes at least one of a current limiting resistor and a transistor for making the rise time of the pixel control pulse longer than the rise time of the row selection pulse, at an output section of the pixel control pulse. The photoelectric conversion device according to claim 1, characterized in that.

18. The control circuit includes at least one of a current limiting resistor and a transistor for making the rise time of the pixel control pulse longer than the rise time of the row selection pulse, at an output section of the pixel control pulse. The photoelectric conversion device according to claim 2, characterized in that.

19. The control circuit includes a current source circuit for making the fall time of the pixel control pulse longer than the fall time of the row selection pulse, at an output section of the pixel control pulse. The photoelectric conversion device according to claim 2, characterized in that.

20. The control circuit includes at least one of a current limiting resistor and a transistor for making the fall time of the pixel control pulse longer than the fall time of the row selection pulse, at an output section of the pixel control pulse. The photoelectric conversion device according to claim 2, characterized in that.

21. The slope of the rise of the pixel control pulse is less than 30 V / μsec. The photoelectric conversion device according to claim 1, characterized in that.

22. The slope of the rise of the pixel control pulse is less than 30 V / μsec. The photoelectric conversion device according to claim 2, characterized in that.

23. The slope of the fall of the pixel control pulse is less than 30 V / μsec. The photoelectric conversion device according to claim 2, characterized in that.

24. A system, comprising: the photoelectric conversion device according to any one of claims 1 to 23; and a processing device that processes image data output from the photoelectric conversion device.

Images