Termination structure

Abstract

To provide a metal oxide film field effect transistor (MOSFET) device, a method of manufacturing the same, and a method of using the same.SOLUTION: A MOSFET device has a termination structure having a plurality of mutually parallel and mutually separated gate structures and a first edge portion adjacent to the plurality of gate structures, and the termination structure has a second edge portion on the side of the termination structure opposite to the first edge portion. Each of the plurality of gate structures has a curved edge portion adjacent to the first edge portion of the termination structure, and the second edge portion of the termination structure is curved concavely relative to the curved edge portions of the plurality of gate structures.SELECTED DRAWING: None

Description

[Technical field]

[0001] The present invention relates to metal oxide semiconductor field effect transistor (MOSFET) devices, and more particularly to termination structures for MOSFET devices. [Background technology]

[0002] 1A and 1B are perspective views of an exemplary conventional MOSFET device. As shown, a corner of a MOSFET 100 is shown in these perspective views. The MOSFET 100 can incorporate one or more source regions 105, one or more gate regions 110, one or more gate insulator regions 115, one or more gate shield regions 120, one or more gate shield insulator regions 125, one or more body regions 130, one or more drift regions 135, one or more drain regions 140, one or more drain contact terminals 145, one or more termination regions 150, and one or more termination insulator regions 155. Other regions not shown can include one or more trace layers, one or more vias, one or more insulator layers, one or more passivation layers, one or more gate contacts, one or more termination contacts, one or more gate shield contacts, one or more source / body contacts, etc.

[0003] In one embodiment, the drift region 135 can be disposed between the drain region 140 and the body region 130. The body region 130 can include a plurality of source regions 105, a plurality of gate regions 110, a plurality of gate insulator regions 115, a plurality of gate shield regions 120, and a plurality of gate shield insulator regions 125. The gate regions 110 and the gate shield regions 120 can be formed as a plurality of elongated parallel structures (e.g., strip-like cell structures). The gate region 110 is surrounded by the gate insulator region 115, and the gate shield region 120 is surrounded by the gate shield insulator region 125. Thus, the gate region 110 and the gate shield region 120 can be electrically isolated from the surrounding source region 105, body region 130, and drift region 135 by the gate insulator region 115 and the gate shield insulator region 125. The plurality of gate regions 110 can be electrically coupled by one or more gate contacts (not shown). The source region 105 can be formed along the periphery of the gate insulator region 115. The source region 105 can be separated from the drift region 135 and the drain region 140 by the body region 130. The source region 105 and the body region 130 can be electrically coupled by one or more source / body contacts (not shown). A drain contact 145 can be disposed on the drain region 140. One or more trace layers, one or more vias, one or more dielectric layers, and one or more passivation layers (not shown) can be disposed on the gate region 110, the source region 105, and the body region 130.

[0004] 1A and 1B show a portion of a MOSFET having three elongated parallel structures, commonly referred to as cell structures, consisting of source region 105, gate region 110, gate insulator region 115, gate shield region 120, and gate shield insulator region 125, although it should be noted that MOSFET embodiments typically have four or more such cell structures.

[0005] In one embodiment, the source region 105 and drain region 140 can be a heavily n-doped (N+) semiconductor such as silicon doped with phosphorus or arsenic, and the drift region 135 can be a lightly n-doped (N-) semiconductor doped with phosphorus or arsenic. The body region 130 can be a p-doped (P) semiconductor such as silicon doped with boron. The gate region 110, gate shield region 120, and termination region 150 can be a heavily n-doped (N+) semiconductor such as polysilicon doped with phosphorus, and the gate insulator region 115, gate shield insulator region 125, and termination insulator region 155 can be an insulator such as silicon dioxide.

[0006] If the potential of gate region 110 relative to source region 105 exceeds the threshold voltage of MOSFET 100, a conductive channel can be introduced into body region 130 around the periphery of gate insulator region 115. Current then flows through MOSFET 100 between drain region 130 and source region 105. Thus, MOSFET 100 is in an on state.

[0007] When the potential of the gate region 110 is lower than the threshold voltage, a channel is no longer induced. As a result, a voltage potential applied between the drain region 140 and the source region 105 does not allow current to flow between them. Thus, the MOSFET 100 is in an off state, and the junction formed by the body region 130 and the drain region 140 can support the voltage applied to the source and drain. The presence of the lightly n-doped (N-) drift region 135 creates a depletion region that extends into both the body region 130 and the drain region 140, suppressing the punch-through effect in the off state. Thus, the lightly n-doped (N-) drift region 135 increases the breakdown voltage of the MOSFET 100.

[0008] The channel width of MOSFET 100 is a function of the length of the plurality of source regions 105 along the periphery of gate insulator region 110. The channel length of MOSFET 100 is a function of the width of body region 130 along the periphery of gate insulator region 115 between source region 105 and drift region 135. As such, MOSFET 100 can achieve a large channel width / length ratio, which allows MOSFET device 100 to be advantageously used in power MOSFET applications, such as the switching element in a pulse width modulated (PWM) voltage regulator.

[0009] The termination region 150 and termination insulator region 155 may be disposed within a peripheral region surrounding a core region having one or more source regions 105, one or more gate regions 110, one or more gate insulator regions 115, one or more gate shield regions 120, one or more gate shield insulator regions 125, and one or more body regions 130. The termination region 150 may be electrically coupled (not shown) to the gate shield regions 120, the body regions 130, and the source regions 105. In one embodiment, as shown in FIG. 1A, the one or more gate regions 110 and the gate shield regions 120 extend substantially to the peripheral termination region 150. In another embodiment, as shown in FIG. 1B, a gap having one or more body regions 130 is disposed between the ends of the one or more gate regions 110 and the gate shield regions 120 and the peripheral termination region 150.

[0010] The concept of charge balancing can be applied to semiconductor devices such as MOSFET 100 to improve the breakdown voltage, lower the on-state resistance, and increase the switching speed and / or efficiency of the semiconductor device. A high doping concentration of the n-doped silicon drift region 135 between two adjacent gate shield regions 120 results in a low on-state resistance of the device. On the other hand, when a reverse voltage is applied, the shielding effect is lost from the charges in the n-doped drift region between the adjacent gate shield regions 120, so a high breakdown voltage can be obtained despite the high impurity concentration in the n-doped drift region 135. However, the bigger technical challenge here is to balance the charges for high cell density, especially at the edges and corners of the active area close to the termination region 150, the termination region 150, and the deep gate shield region 120.

[0011] 2A and 2B, a partial view of an exemplary MOSFET is shown illustrating the electric field in mesa region 210 adjacent gate structure 220 and termination region 230. Portions of the source, body, and drift regions may be located in mesa region 210, and the gate and gate shield regions of the MOSFET may be located in gate structure 220. In FIG. 2A, gate structure 220 substantially abuts termination region 230, and the width of mesa region 210 between gate structures 220 is a substantially uniform width w m As shown in FIG. 2A, when a reverse bias is applied to the MOSFET, the charge in the drift region at the corner of the mesa region 210 between the termination region 230 and the gate shield region of the gate structure 220 is depleted more quickly than the charge along the mesa region 210 away from the corner. Thus, the breakdown voltage at the corner is limited to a small extent by the overshielding effect from the termination region 230 and the gate structure 220. Referring to FIG. 2B, the gate structure 220 is separated from the termination region 230 by a portion of the mesa region 210 with a width w g As one moves away from the end of the gate structure 220, the mesa region 210 is separated by a gap of m2B, when a reverse bias is applied to the MOSFET, the charge residing along the mesa region 210 away from the edge of the gate structure 220 is balanced by an opposing charge from the parallel gate structure 220. The gap w from the termination region 230 to the mesa region 210 m At the end of the gate structure 220, which is separated by w, charge balance can be achieved at location x between the end of the gate structure 220 and the termination region 230, but at location y, the charge in the mesa region 210 is balanced by the shielding effect from only one side of the termination region 230 and the corner of the gate structure 220. Thus, the shielding effect is weaker and the local breakdown voltage is lower. To improve the breakdown voltage at location y, m For w g y and provides better shielding effect for the charge at location y in mesa region 210, but at the expense of overshielding at location x due to the narrower gap. Thus, both the undershielding at location y and the overshielding at location x have lower breakdown voltages than the balanced charge scenario, as shown in Figure 3. This is why there continues to be a need for charge-balanced termination designs that can solve the charge imbalance problem and improve the breakdown voltage in such devices. [Brief description of the drawings]

[0012] A more detailed understanding may be had from the following description, taken in conjunction with the accompanying drawings, in which:

[0013] [Figure 1A-B] 1A and 1B are perspective views of an exemplary metal-oxide-semiconductor field effect transistor (MOSFET) according to the prior art. [Figure 2A-B] 2A and 2B are partial diagrams of an exemplary MOSFET according to the prior art. [Diagram 3] FIG. 3 is a graph showing the relationship between termination proximity shielding and breakdown voltage for a prior art MOSFET. [Figure 4] FIG. 4 is a perspective view illustrating an exemplary metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the present invention. [Diagram 5] FIG. 5 illustrates a top view of an exemplary MOSFET according to an embodiment of the present invention. [Figure 6] FIG. 6 illustrates a top view of an exemplary MOSFET according to an embodiment of the present invention. [Figure 7] FIG. 7 illustrates a side view of an exemplary MOSFET in accordance with an embodiment of the present invention. [Figure 8] FIG. 8 illustrates a side view of an exemplary MOSFET in accordance with an embodiment of the present invention. [Figure 9] FIG. 9 illustrates a side view of an exemplary MOSFET in accordance with an embodiment of the present invention. [Figure 10] FIG. 10 illustrates a side view of an exemplary MOSFET in accordance with an embodiment of the present invention. [Figure 11] FIG. 11 illustrates a side view of an exemplary MOSFET in accordance with an embodiment of the present invention. [Figure 12] FIG. 12 illustrates a side view of an exemplary MOSFET in accordance with an embodiment of the present invention. [Figure 13] FIG. 13 illustrates a top view of an exemplary MOSFET in accordance with an embodiment of the present invention. [Figure 14] FIG. 14 illustrates a top view of an exemplary MOSFET in accordance with an embodiment of the present invention. [Figure 15] FIG. 15 illustrates a top view of an exemplary MOSFET in accordance with an embodiment of the present invention. [Figure 16] FIG. 16 illustrates a top view of an exemplary MOSFET in accordance with an embodiment of the present invention. [Figure 17A-B] 17A and 17B illustrate a method for fabricating a MOSFET according to an embodiment of the present invention. [Figure 18] FIG. 18 is a top view illustrating an intermediate structure of a MOSFET fabricated by the method shown in the accompanying drawings and described with reference to FIGS. 17A and 17B. [Figure 19] FIG. 19 is a top view showing a MOSFET according to another embodiment. [Figure 20] FIG. 20 is a top view showing an intermediate structure of the MOSFET of FIG. [Figure 21] FIG. 21 is an enlarged view of the intermediate structure of FIG. [Figure 22] FIG. 22 is a cross-sectional view showing the intermediate structure of FIG. [Figure 23] FIG. 23 is a cross-sectional view showing another section of the intermediate structure of FIG. Summary of the Invention

[0014] The present invention relates to MOSFET devices, and methods of making and using the devices. In some embodiments, the MOSFET device includes a plurality of gate structures parallel to and spaced apart from one another, a termination structure having a first edge adjacent the plurality of gate structures and a second edge on a side of the termination structure opposite the first edge, each of the plurality of gate structures having a curved edge adjacent the first edge of the termination structure, and the second edge of the termination structure being concavely curved relative to the curved edge of the plurality of gate structures. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Some embodiments provide a metal oxide semiconductor field effect transistor (MOSFET) device having a plurality of gate structures parallel to and spaced apart from one another, a termination structure having a first edge adjacent the plurality of gate structures and a second edge on a side of the termination structure opposite the first edge, each of the plurality of gate structures having a curved edge adjacent the first edge of the termination structure, the second edge of the termination structure being concavely curved in the same direction as the curved edges of the plurality of gate structures.

[0016] In some embodiments, the second edge of the termination structure is parallel to the curved edges of the plurality of gate structures. In some embodiments, the second edge of the termination structure is scalloped in shape. In some embodiments, the MOSFET device comprises a mesa structure having a first edge proximate the second edge of the termination structure and a second edge on a side of the mesa structure opposite the first edge of the mesa structure. In some embodiments, in a cross section of the mesa structure, the first edge of the mesa structure is curved and the second edge of the mesa structure is straight. In some embodiments, the width of the mesa structure varies along the length of the mesa structure. In some embodiments, the mesa structure is floating and not tied to a fixed voltage. In some embodiments, the mesa structure is not electrically connected to the termination structure. In some embodiments, the termination structure comprises a termination trench. In some embodiments, the plurality of gate structures comprises a plurality of gate trenches.

[0017] Hereinafter, the embodiments of the present invention will be described in detail, examples of which are shown in the accompanying drawings. The present invention will be described with reference to these embodiments, but the present invention is not limited to these embodiments. In other words, the present invention is intended to cover all modifications, alterations, and equivalents that fall within the scope of the invention as defined in the appended claims. Furthermore, in the following detailed description of the invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced without these specific details. Additionally, well-known methods, procedures, components, elements, and circuits have not been described in detail in order to avoid unnecessarily obscuring aspects of the present invention.

[0018] Certain embodiments of the present invention described below are described in terms of routines, modules, logic blocks, and other symbolic representations of operations on data within one or more electronic devices. These descriptions and representations are the means used by those skilled in the art to most effectively convey the substance of their work to others skilled in the art. It should be understood that the routines, modules, logic blocks, and the like, employed herein are generally self-consistent sequences of processes or instructions leading to a desired result. These processes involve physical manipulations of physical quantities. Usually, though not necessarily, these physical manipulations take the form of electrical or magnetic signals capable of being stored, transferred, compared, and otherwise manipulated in electronic devices. In describing embodiments of the present invention, for convenience, and with reference to common usage, these signals will be referred to as data, bits, values, elements, symbols, characters, terms, numbers, strings, or the like.

[0019] It should be noted that all of these terms should be construed as referring to physical operations and physical quantities and are simply convenient labels and terms commonly used in the art. As will become apparent from the following description, unless otherwise indicated, throughout the description of the present invention, the use of "receive" and the like refers to the operations and processes of electronic devices, such as electronic computing devices, that manipulate and transform data. Data may be represented as physical quantities (e.g., electronic quantities) within the logic circuits, registers, memory, and the like of the electronic device. This data may also be converted to other data that are similarly represented as physical quantities within the electronic device.

[0020] In this specification, the use of disjunctive conjunctions is inclusive of conjunctions. The use of definite or indefinite articles is not intended to indicate cardinality or cardinality. References to "the" or "an" specifically refer to one of a plurality of possible instances. Furthermore, the phraseology and terminology used herein are for purposes of description and should not be regarded as limiting. Furthermore, in this specification, alphabetical portions of a reference number refer to different or related parts / instances of an element or feature.

[0021] Referring to FIG. 4, a perspective view shows an exemplary vertical transistor according to an embodiment of the present invention. In one embodiment, the vertical transistor can be a metal-oxide-semiconductor field effect transistor (MOSFET) 400. The MOSFET 400 can include one or more source regions 405, one or more gate regions 410, one or more gate insulator regions 415, one or more gate shield regions 420, one or more gate shield insulator regions 425, one or more body regions 430, one or more drift regions 435, one or more drain regions 440, one or more drain contacts 445, one or more termination regions 450, and one or more termination insulator regions 455. Other regions not shown include one or more trace layers, one or more vias, one or more insulator layers, one or more passivation layers, one or more gate contacts, one or more ring structure contacts, one or more source / body contacts, etc.

[0022] In one embodiment, the drift region 435 can be disposed between the drain region 440 and the body region 430. The source regions 405, the gate regions 410, the gate insulator regions 415, the gate shield regions 420, and the gate shield insulator regions 425 can be disposed within the body region 430 and the drift region 435. The gate regions 410 and the gate shield regions 420 can be formed as a plurality of elongated parallel cell structures. The gate insulator region 415 can surround the gate region 410, and the gate shield insulator region 425 can surround the gate shield region 415. In this manner, the gate regions 410 and the gate shield regions 420 are electrically isolated from the source regions 405, the body region 430, and the drift region 435 that they surround by the gate insulator region 415 and the gate shield insulator region 425. The source region 405 can be formed along the periphery of the gate insulator region 415 and can be separated from the drift region 435 and the drain region 440 by the body region 430. The source region 405, the body region 430 and the gate shield region 420 can be electrically coupled to a termination region 450 (not shown). A drain contact 445 can be disposed in the drain region 440. A drain terminal 445 can be disposed on the drain region 440. One or more trace layers, one or more vias, one or more insulator layers, one or more passivation layers (not shown) can be disposed on the gate region 410, the source region 405, the body region 430, and one or more termination regions 450.

[0023] The termination region 450 and termination insulator region 455 can be disposed within a perimeter region surrounding a core region having one or more source regions 405, one or more gate regions 410, one or more gate insulator regions 415, one or more gate shield regions 420, one or more gate shield insulator regions 425, and one or more body regions 430. The gate regions 410 and gate shield regions 420 can extend to the termination region 450 in a predetermined pattern. In one embodiment, a first set of gate shield regions 420a can extend completely to the termination region 450, and a second set of gate shield regions 420b can be spaced apart from the termination region 450 by a predetermined gap. For example, all of the gate shield regions 420a can extend to the termination region 450, while the other gate shield regions 420b can be spaced apart by a predetermined width w m Only the end region 450 can be separated from the end region 450 .

[0024] Reference is now made to Figure 5, which is a top view of an exemplary MOSFET in accordance with an embodiment of the present invention. Again, the MOSFET 400 can include one or more source regions 405, one or more gate regions 410, one or more gate shield regions 420, and one or more termination regions 450. As shown in Figure 5, the gate shield regions 420 can be raised at the ends of the gate region 410. A first set of gate shield regions 420a can extend completely to the termination region 450, with a gap between the second set of gate shield regions 420b and the termination region 450.

[0025] 5 also shows a number of body contacts 460 that provide a low impedance connection to the source region 405 and the body region 430. The number of source-body contacts may be electrically coupled to a source pad (not shown). Also shown are a number of gate contacts 465 that provide a low impedance connection to the gate region 410. The number of gate contacts 465 may be electrically coupled to gate line traces (not shown). The MOSFET 400 may also be provided with a number of termination contacts 470, a number of source / body contacts 475, and a number of gate shield contacts 480. The termination contacts 470, the number of source / body contacts 475, and the number of gate shield contacts 480 may be electrically coupled to termination / source / body / gate shield pick-up traces (not shown).

[0026] Figure 6 illustrates a top view of an exemplary MOSFET according to an embodiment of the present invention. The MOSFET illustrated in Figure 6 is substantially similar to the MOSFET of Figure 5, with the addition that Figure 6 illustrates a source pad 485, a gate line trace 490, and a termination / source / body / gate shield pick-up trace 495 (not shown) that electrically couples each set of contacts. The termination / source / body / gate shield pick-up trace 495 electrically connects the gate shield region 415, the source region 405, the body region 425, the termination region 450, and the source pad 485 through the source region 405.

[0027] FIG. 7 shows a side view of an exemplary MOSFET according to an embodiment of the present invention. FIG. 7 shows a MOSFET having one or more gate regions 410, one or more gate insulator regions 415, one or more gate shield regions 420, one or more gate shield insulator regions 425, one or more drift regions 435, one or more termination regions 450, and one or more termination insulator regions 455, as viewed along cut line AA in FIG. 5. As shown in FIG. 7, the gate shield regions 420a, 420b provided along cut line AA extend all the way to the termination region 450. These gate shield regions 420a, 420b rise to the surface and connect to the termination / source / body / gate shield pick-up trace 495 through the gate shield contact 480. Also shown in FIG. 7 are the source pad 485, the gate contact 465, and the gate line trace 490.

[0028] FIG 8 illustrates a side view of an exemplary MOSFET according to an embodiment of the invention, taken along cut line BB of FIG 5, having one or more source regions 405, one or more body regions 430, one or more drift regions 435, one or more termination regions 450, and one or more termination insulator regions 455. Also illustrated in FIG 8 are source / body contact 460, source pad 485, gate line trace 490, source / body contact 475, and termination / source / body / gate shield pick-up trace 495.

[0029] FIG. 9 illustrates a side view of an exemplary MOSFET according to an embodiment of the present invention. FIG. 9 illustrates a MOSFET having one or more gate regions 410, one or more gate insulator regions 415, one or more gate shield regions 420, one or more gate shield insulator regions 425, one or more body regions 430, one or more drift regions 435, one or more termination regions 450, and one or more termination insulator regions 455, as viewed along cut line CC in FIG. 5. As shown in FIG. 9, a given gate shield region 420 along cut line CC does not extend completely to the termination region 450. A mesa gap exists between a given gate shield region 420 and the termination region 450. The gate shield region 420 rises to the surface at the end of the gate region 410 and connects to a termination / source / body / gate shield pick-up trace 495 via a gate shield contact 480. Also shown in FIG. 9 is a source pad 485, a gate contact 460, and a gate line trace 490.

[0030] FIG. 10 illustrates a side view of an exemplary MOSFET according to an embodiment of the present invention. FIG. 10 shows a MOSFET having one or more source regions 405, one or more gate shield regions 420, one or more gate shield insulator regions 425, one or more body regions 430, one or more drift regions 435, one or more termination regions 450, and one or more termination insulator regions 455, as viewed along cut line DD in FIG. 5. The gate shield regions 420 rise to the surface and connect to a termination / source / body / gate shield pick-up trace 495 via a gate shield contact 480, regardless of whether the gate shield regions 420 extend all the way to the termination region 450. FIG. 10 also shows a number of termination contacts 470 and source / body contacts 475 coupled to the termination / source / body / gate shield pick-up trace 495.

[0031] FIG 11 illustrates a side view of an exemplary MOSFET according to an embodiment of the present invention, taken along cut line EE of FIG 5 , with one or more source regions 405, one or more gate regions 410, one or more gate insulator regions 415, one or more gate shield regions 420, one or more gate shield insulator regions 425, one or more body regions 430, one or more drift regions 435, one or more termination regions 450, and one or more termination insulator regions 455. Also illustrated in FIG 11 are multiple gate contacts 465 and gate line traces 490.

[0032] FIG 12 illustrates a side view of an exemplary MOSFET according to an embodiment of the invention, taken along cut line FF in FIG 5, having one or more source regions 405, one or more gate regions 410, one or more gate insulator regions 415, one or more gate shield regions 420, one or more gate shield insulator regions 425, one or more body regions 430, one or more drift regions 435, one or more termination regions 450, and one or more termination insulator regions 455. Also illustrated in FIG 12 are multiple source-body contacts 470 and source pads 485.

[0033] In the above exemplary embodiment of the MOSFET 400, every other gate shield region 420a extends completely to the inner termination region 450 surrounding the active area, forming a T-shaped connection. Between every other fully extended gate shield region 420a, another gate shield region 420b terminates with a gap we to the adjacent upstanding termination region 450.

[0034] FIG. 13 illustrates a top view of an exemplary MOSFET according to an embodiment of the present invention. FIG. 13 illustrates a close-up view of an edge or corner of an active area having a gate shield region 420b that terminates with a gap to an adjacent termination region 450 and portions of two adjacent gate shield regions 420a that extend completely to the termination region 450. The gate shield regions 420b that do not extend completely to the termination region 450 are raised to the surface at the end of the gate region 410b. In one embodiment, the corner of the gate shield region 420b that terminates with a gap to the adjacent termination region 450 is a circular section with a radius of r1. Furthermore, the inner corner where the gate shield region 420a extends completely to the termination edge 450 is a circular section with a radius of r2. The gap between the gate shield regions 420b that do not extend completely to the adjacent termination region 450 is wg, the width of the gate region 410 is w1, and the width between the two adjacent gate regions 410 is wm. When a reverse bias is applied to the MOSFET, the doped semiconductor between the gate shield regions 420 accumulates a net charge Q n The gate shield region 420 adjacent to the gate shield insulator region 425 is depleted under the shielding effect. t Since the gate shield region 420 is highly doped and has low resistivity, the charge Q t can be equally distributed along the length of the gate shield region 420. These two types of charges Q t and Q n When the load currents are in equilibrium, the MOSFET can reach its maximum breakdown voltage.

[0035] For a diagonal spacing y between a corner of the gate shield region 420b that does not extend all the way to the termination region 450 and a corner between the upright termination region 450 and the gate shield region 420a that extends all the way to the termination region 450, the charge in the doped semiconductor between the gate shield regions is balanced by the shielding effect from the surrounding termination region 450 and gate shield regions 420a, 420b that extend all the way to the termination region 450. As the diagonal spacing y increases, the shielding effect from the corner of the gate shield region 420b that does not extend all the way to the termination region 450 decreases, while the shielding effect from the upright termination region 450 and the gate shield region 420a that extends all the way to the termination region 450 increases. And vice versa. Thus, the over- or under-shielding effect problem of the prior art can be reduced or eliminated.

[0036] The gate shield regions 420 can extend to the termination region 450 in a variety of predefined patterns. FIG. 14 is a top view of an exemplary MOSFET according to an embodiment of the present invention. In another predefined pattern, as shown in FIG. 14, multiple gate regions 410 and gate shield regions 420 can be arranged in parallel in the core area. In the area adjacent to the termination region 450, a given gate region 410c and gate shield region 420c can be surrounded by one or more other gate regions 410d and gate shield regions. The gap between the end of a given gate shield region 420c and the surrounding other gate regions 410d and gate shield regions is substantially equal to the distance between adjacent parallel portions in the core area. The pattern of surrounding gate structures can also be used with an alternating pattern of fully extending and not fully extending gate shield regions 420a and 420b, as described with reference to FIGS. 4-12, and / or with rounded corners, as described with reference to FIG. 13.

[0037] 15 and 16 are top views of an exemplary MOSFET according to an embodiment of the present invention. As shown in FIG. 15, another predetermined pattern can be arranged in the corner regions of the MOSFET with a curved termination region 450 and one or more curved gate regions 410e, 410f. The curved termination region 450 and one or more curved gate shield regions 420e, 420f can be configured to suppress the electric field that is packed in the device corner. The gap between adjacent gate field regions 420 and the gap between adjacent portions of the gate shield region 420 and the termination region 450 can be configured to be substantially equal at both ends of the gate shield region 420 and along the length of the gate shield region 420. In one embodiment, as shown in FIG. 15, the curved gate regions 410e, 410f and the curved gate shield regions 420e, 420f in the corner regions can be arranged in an alternating pattern that extends completely and does not extend completely into one of the gate regions 410g and the gate shield regions. In another embodiment, the curved gate regions 410h, 410i, 410j at the corner regions and the curved gate shield regions within the corner regions can be arranged in a surrounding pattern as shown in Figure 16. The pattern of curved gate regions 410, curved gate shield regions 420 and curved termination regions 450 at the corner regions of the MOSFET can be used in conjunction with the alternating patterns of fully and not fully extended gate structures described with reference to Figures 4-12, the curved corner pattern described with reference to Figure 13, and / or the surrounding gate structure pattern described with reference to Figure 14.

[0038] 17A and 17B illustrate a method for fabricating a MOSFET according to an embodiment of the invention. The method begins with various initial steps in the fabrication of a semiconductor wafer, such as cleaning, deposition, doping, and etching steps. In one embodiment, the wafer can be a heavily n-doped (N+) semiconductor, such as silicon doped with phosphorus or arsenic, which forms the drain region. In step 1705, a drift region can be formed in the drain region. In one embodiment, the drift region can be formed by epitaxial deposition (evaporation) of a moderately or lightly n-doped (N or N-) semiconductor, such as silicon doped with phosphorus or arsenic, in the drain region.

[0039] A body region can be formed in the drift region at step 1710. In one embodiment, a dopant, such as boron, can be implanted into an upper portion of an epitaxially deposited semiconductor layer to form a p-doped (P) semiconductor body region over the drift region, if desired.

[0040] At 1715, a plurality of gate trenches and one or more termination trenches can be formed through the body region. The plurality of gate trenches and one or more termination trenches can extend partially into the drift region. In one embodiment, a trench mask can be formed over the body region. Portions of the body region exposed by the trench mask can be etched to form a plurality of gate trenches and one or more termination trenches in the body region. In another embodiment, separate gate and termination trench masks and etch steps can be used to form gate and termination trenches having different widths and / or different depths. In one embodiment, the width and / or depth of the termination trench can be 100%-120% of the gate trench.

[0041] The gate trenches can be arranged as parallel trenches separated from one another by a first predetermined distance wm. In one embodiment, the termination trench can be formed in a ring surrounding the gate trenches. In one embodiment, the first set of gate trenches can extend completely to the termination trench and the ends of the second set of trenches can be separated from the termination trench by a second predetermined distance wg. The first and second sets of trenches can be arranged in an alternating pattern. In one embodiment, the second predetermined distance wg can be set to 100%-60% of the first predetermined distance wm. The alternating arrangement of fully and not fully extending gate trenches can form the gate regions shown in Figures 4-12.

[0042] In another embodiment, the corners at the ends of gate trenches that do not extend completely into the termination trench can be rounded. Additionally, the inside corners of the intersections of termination trenches with gate trenches that do extend completely into the termination trench can also be rounded. Because the trench corners are rounded, a gate region and a termination region can be used together, as shown in FIG.

[0043] In another embodiment, the gate trenches can be arranged in parallel in the core area. In the area adjacent to the termination trench, each of the first set of gate trenches can be surrounded by one or more of the second set of gate trenches. As a result of the pattern surrounding the gate trenches, the gate region shown in FIG. 14 can be realized.

[0044] In another embodiment, the termination trenches can be curved in the corner regions of the MOSFET. The gate trenches can also be curved in the corner regions. In one embodiment, the gate trenches in the corner regions can be curved in an alternating pattern of gate trenches that extend completely and not completely into another gate trench. The alternating pattern of curved trenches that extend completely and not completely into the corner regions can provide the gate and termination regions shown in FIG. 15. In another embodiment, the gate trenches in the corner regions can be arranged as one or more gate trenches that surround one or more other trenches in the corner regions. As a result of surrounding the gate trenches in the corner regions, a combined gate and termination region can be used, as shown in FIG. 16.

[0045] Step 1720 can form a first dielectric region on walls and floors of the plurality of gate trenches and the one or more termination trenches. In one embodiment, surfaces of the gate trench and the one or more termination trenches can be oxidized to form a gate shield dielectric region in the plurality of gate trenches and a termination dielectric region in the one or more termination trenches.

[0046] Step 1725 can form a first semiconductor layer on the insulator regions within the plurality of gate trenches and the one or more termination trenches. In one embodiment, a heavily n-doped polysilicon, such as phosphorus or arsenic doped polysilicon, can be formed. - A doped (N+) semiconductor can be deposited into the plurality of gate trenches and one or more termination trenches and on a surface of the body region, and excess portions of the oxide layer formed on the surface of the deposited semiconductor and body region can be removed by etching until only the portions of the oxide layer located in the deposited semiconductor and gate trenches remain.

[0047] At step 1730, portions of the first semiconductor layer in the core areas of the plurality of gate trenches can be removed. In one embodiment, photoresist can be deposited and patterned to form a gate region mask to expose areas of the first semiconductor layer in the core area. The portions of the first semiconductor layer in the core area exposed by the mask can be etched back to form gate shield regions in the plurality of gate trenches in the core area, the gate shield regions extending to tops of the gate trenches adjacent the termination trench. The gate region mask can be removed after the first semiconductor layer in the core area is etched back.

[0048] At step 1735, a second semiconductor layer can be formed on the remaining portion of the first semiconductor layer. In one embodiment, a relatively thick insulator can be formed on a surface of the remaining portion of the first semiconductor layer and on the walls of the exposed portion of the trench. The relatively thick insulator can be removed from the walls of the exposed portion of the trench, after which a relatively thin insulator can be formed on the sidewalls to form a gate insulator region.

[0049] At step 1740, a second semiconductor layer can be formed in the second insulator region where the portions of the first semiconductor layer in the core areas of the plurality of gate trenches have been removed. In one embodiment, a heavily n-doped (N+) semiconductor, such as phosphorus or arsenic doped polysilicon, can be deposited in the plurality of gate trenches where the portions of the first semiconductor layer in the core areas have been removed, and on the surfaces of the termination and body regions. Excess portions of the second semiconductor and second oxide layer can then be removed until portions of the deposited second semiconductor and oxide layer remain located in portions of the gate trenches. The portions of the second semiconductor layer remaining in the plurality of gate trenches where the portions of the first semiconductor layer in the core areas have been removed can form the plurality of gate regions.

[0050] At step 1745, a plurality of source regions can be formed in the body region adjacent to the gate region. The source regions can be separated from the gate region by a gate insulator region. The source regions can also be separated from the drift region by a portion of the body region. In one embodiment, a dopant such as phosphorous or arsenic can be embedded into an upper portion of the body region to form a heavily n-doped (+N) semiconductor source region.

[0051] The wafer may undergo subsequent steps in the method of fabricating a MOSFET, such as cleaning, deposition, doping, etching, etc. Subsequent steps may form various other structures, such as contacts, traces, vias, encapsulation layers, etc. The additional steps that follow are not necessarily helpful to an understanding of the aspects of the invention, and therefore will not be discussed further herein.

[0052] Figure 18 illustrates a top view of an intermediate structure 1800 of a MOSFET fabricated according to the method described with reference to Figures 17A and 17B following step 1725. Intermediate structure 1800 has gate trench 1802, termination trenches 1804, 1806, 1808, and mesas 1810, 1812, 1814.

[0053] Also shown in this view is defect 1816. Defect 1816 is a hole or other deformation in the polysilicon of termination trench 1808. Defect 1816 may arise, for example, during the formation of polysilicon into termination trench 1808 (e.g., during step 1725 described with reference to Figures 17A and 17B). Defect 1816 may also be due to the shape of termination trench 1808 and / or mesa 1816. For example, in some embodiments, an area of ​​termination trench 1808 having one of defects 1816 may be too large to be filled during the formation of polysilicon into the termination trench (e.g., during step 1725), resulting in the formation of a void.

[0054] It may be desirable to modify one or more features of the MOSFET. In some embodiments, step 1715 may be modified to incorporate curved, wavy, scalloped, and / or radiused edge(s) in the geometry of one or more of the termination trenches, as described further below, which can provide benefits that can help prevent manufacturing defects.

[0055] Figure 19 illustrates a top view of another MOSFET embodiment. The exemplary MOSFET 1900 of Figure 19 is substantially similar to the exemplary MOSFET of Figure 13, except that termination region 1950 and mesa 1960 have different shapes.

[0056] 19 is a close-up view of an edge or corner of an active area having a gate shield region 1920b that terminates at a gap to an adjacent termination region 1950 and portions of two adjacent gate shield regions 1920a that extend completely to the termination region 1950. The gate shield region 1920b that does not extend completely to the termination region 1950 is raised to the surface at the end of the gate region 1910b. In one embodiment, the corner of the gate shield region 1920b that terminates at a gap to the adjacent termination region 1950 can be rounded and have a radius of r1. Additionally, the inner corner where the gate shield region 1920a extends completely to the termination region 1950 can also be rounded and have a radius of r2.

[0057] Mesa 1960 is disposed adjacent termination region 1950. In some implementations, mesa 1960 is floating. As shown, second termination trench 1970 is adjacent mesa 1960 on the side opposite termination region 1950. Second termination trench 1970 corresponds to termination trench 1806 similar to MOSFET 1800 described with reference to FIG. 18. In some implementations, additional mesas and termination trenches (not shown) can be added.

[0058] The edge of termination region 1950 facing mesa 1960 is curved in some areas. The curved edge of termination region 1950 may be referred to as a scalloped or wavy edge. In some embodiments, the edge of termination region facing mesa 1960 may be curved, scalloped, or wavy with a radius r3. In some embodiments, r3 is equal in curvature to radii r2 and / or r1.

[0059] In some embodiments, the curved, scalloped, or wavy edges of termination region 1950 can provide the advantage of reducing manufacturing defects such as defect 1816 described with reference to FIG. 18.

[0060] Radius r3 may be a compound radius or a simple radius, as desired. In some embodiments, r2 and / or r1 are also compound radii or simple radii, as desired. In some embodiments, r3 is equal to r2 and / or r1.

[0061] Mesa 1960 may be scalloped (or "toothed" as opposed to termination region 1950) and radius r3 corresponds to the scalloped structure of termination region 1950. When configured in this manner, the edge of mesa 1960 facing termination region 1950 is parallel to the edge of termination region 1950 facing mesa 1960 and may be referred to as a scalloped edge or a wavy edge.

[0062] In some embodiments, as shown, the width w of termination region 1950 at radius r (i.e., at the scalloped structure of termination region 1950) is z is the width w of the termination region between radii r3 (i.e., between the scalloped structures of the termination region 1950) x In some cases, this can serve the purpose of improving the charge balance within the MOSFET.

[0063] The gap between the not fully extended gate shield region 1920b and the adjacent termination region 1950 is wg , the width of the gate region 1910 is wl, and the width between two adjacent gate regions 1910 is w m When a reverse bias is applied to the MOSFET, the shielding effect from the gate shield regions 1920 depletes the doped semiconductor between the gate shield regions 1920, causing a net charge of Q n Correspondingly, an opposite charge Q t Since the gate shield region 1920 is highly doped and has low resistivity, a charge Q t These two types of charges Q t and Q n When these two conditions are balanced, the breakdown voltage of the MOSFET can be maximized.

[0064] For a diagonal spacing y between the corner of the gate shield region 1920b that does not extend all the way to the termination region 1950 and the corner between the right angle termination region 1950 and the gate shield region 1920a that extends all the way to the termination region, the charge in the doped semiconductor between the gate shield regions is balanced by the shielding effect from the surrounding termination region 1950 and the gate shield regions 1920a, 1920b that extend all the way to the termination region 1950. As the diagonal spacing y increases, the shielding effect from the corner of the gate shield region 1920b that does not extend all the way to the termination region 1950 decreases, while the shielding effect from the upright termination region 1950 and the gate shield region 1920a that extends all the way to the termination region 1950 increases. And vice versa. Thus, in some embodiments, the over or under shielding effect problem of the prior art can be reduced or eliminated.

[0065] The gate shield regions 1920 can extend to the termination region 1950 in a variety of predetermined patterns. FIG. 19 is a top view of an exemplary MOSFET according to an embodiment of the present invention. As shown in FIG. 19, in another predetermined pattern, multiple gate regions 1910 and gate shield regions 1920 can be arranged in parallel in the core area. In the area adjacent to the termination region 1950, a given gate region 1910c and gate shield region 1920c can be surrounded by one or more other gate regions 1910d and gate shield regions. The gap between the end of a given gate shield region 1920c and the surrounding other gate regions 1910d and gate shield regions is substantially equal to the distance between adjacent parallel portions in the core area. The pattern of surrounding gate structures can also be used with alternating patterns of fully extending gate shield regions 1920a and not fully extending gate shield regions 1920b, as described with reference to FIGS. 4-12 and / or rounded corners as described with reference to FIG. 13.

[0066] 20 is a top view showing an intermediate structure 2000 of MOSFET 1900. The intermediate structure 2000 has a gate trench 2002, termination trenches 2004, 2006, 2008, and mesas 2010, 2012, 2014.

[0067] Intermediate structure 2000 is substantially similar to intermediate structure 1800 described with reference to Figure 18, except that opposing edges of termination trench 2008 and mesa 2014 are curved, wavy or scalloped, while opposing edges of termination trench 1808 and mesa 1814 are straight. In some embodiments, termination trench 2008 and mesa 2014 are curved, wavy or scalloped, as are termination region 1950 and mesa 1960, as recited in claim 19.

[0068] In some embodiments, the curved, wavy, or scalloped edges of termination trench 2008 and mesa 2014 form scalloped region 2050 such that the shape of termination trench 2008 eliminates the occurrence of defects such as defect 1816 described with reference to Figure 18. For example, in some embodiments, the area of ​​termination trench 2008 that is in scalloped region 2050 is not large enough to allow polysilicon to fill in the termination trench as it is formed.

[0069] Figure 21 is a top view of a cross section of an intermediate structure 2000 similar to that described with reference to Figure 20, with the addition of a termination trench 2100. It should be noted that in some embodiments, any suitable number of termination trenches and mesas may be used. Cut line CC' is shown passing through scallop 2050, and cut line AA' is shown passing through a region of termination trench 2008 and mesa 2014 that is non-scalloped, or has the least amount of scalloping, or is at its narrowest portion of mesa 2014.

[0070] Figure 22 is a cross-sectional view of intermediate structure 2000 corresponding to cut line CC' described with reference to Figure 21. Yet another mesa 2200 is shown in Figure 22.

[0071] 22, the mesas 2010, 2012, 2014, 2200 are formed from P-type material and are disposed within a drift region 2206 formed from N-type material. Each of the termination trenches 2200, 2004, 2006, 2008 disposed within the drift region 2206 has a polysilicon material 2202, 2204, 2206, 2208 separated from the drift region 2206 and adjacent mesas by a shield oxide layer 2210, 2212, 2214, 2216.

[0072] In this embodiment, polysilicon material 2202, 2204, 2206, 2208 of termination trenches 2100, 2004, and 2006, respectively, connect to an adjacent outer one of mesas 2200, 2010, 2012, respectively. Mesa 2014 does not connect to a termination trench and is left floating. In some embodiments, floating mesa 2014 has the effect of facilitating charge balancing within the MOSFET. In some embodiments, termination trenches 2200, 2004, 2006, 2008 have different widths and do not need to be fixed at a potential when biasing the MOSFET, except in the case where termination trench 2008 can be connected to a source potential.

[0073] In a cross-sectional view of intermediate structure 2000 corresponding to cut line C-C', as shown in FIG. 22, mesa 2014 has a width w corresponding to the widest portion of mesa 2014 and scalloped region 2050, as described with reference to FIG. s has.

[0074] FIG. 23 is a cross-sectional view showing intermediate structure 2000 corresponding to cut line A-A' described with reference to FIG.

[0075] In a cross-sectional view of intermediate structure 2000 corresponding to cut line A-A', as shown in FIG. 23, mesa 2014 corresponds to the narrowest portion of mesa 2014 and scalloped region 2050, as described with reference to FIG. 20, and the width w between the scalloped regions. n has.

[0076] Advantageously, embodiments of the present invention provide charge balancing simultaneously in the active and termination areas of a MOSFET device, thereby increasing the breakdown voltage of the MOSFET device. The present invention and its embodiments are also applicable to vertical trench structure power devices such as trench diodes, trench IGBTs, etc.

[0077] The above description of specific embodiments of the present invention is for illustrative purposes only. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many obvious variations are possible in light of the above description. The embodiments have been selected and described to best explain the invention and its practical application, and thereby to enable those skilled in the art to best utilize the invention and various embodiments with various modifications to fit the specific intended use. The scope of the present invention is defined by the claims set forth at the beginning of this specification and their equivalents.

[0078] It should be understood that various modifications are possible based on this disclosure, and although features and elements have been described in specific combinations, each feature or element can be used alone without the other features or elements, or can be combined in various ways with other features or elements, or without combinations. [Explanation of symbols]

[0079] 100 MOSFET 105 Source Region 110 Gate Area 115 Gate Insulator Region 120 Gate Shield Area 125 Gate shield insulator area 130 Body Region 135 Drift Region 140 Drain Region 145 Drain contact terminal 150 Termination area 155 Termination Insulator Area 210 Mesa Region 220 Gate Structure 230 Termination area 405 Source Area 410 Gate Area 410b Gate area 410c Gate Area 410d Gate Area 410e Gate Area 410f Gate Area 410g Gate Area 410h Gate Area 410i Gate Area 410j Gate Area 415 Gate Insulator Region 420 Gate Shield Area 420a first set of gate shield regions 420b second set of gate shield regions 420c Gate Shield Area 420e Gate shield area 420f Gate Shield Area 425 Gate shield insulator area 430 Body Region 435 Drift Region 440 Drain Region 445 Drain Contact 450 Termination area 455 Termination Insulator Area 460 Body Contact 465 Gate Contact 470 Termination Contact 475 Source / Body Contact 480 Gate Shield Contact 485 Sauce Pad 490 Gate Line Trace 495 Termination / Source / Body / Gate Shield Pickup Trace 1705 Process 1710 Process 1715 Process 1720 Process 1725 Process 1730 Process 1735 Process 1740 Process 1745 Process 1800 Intermediate structure (MOSFET) 1802 Gate Trench 1804, 1806, 1808 Termination Trench 1810, 1812, 1814 Mesa 1816 Defect 1900 MOSFET 1910 Gate Area 1910b Gate area 1910c Gate Area 1910d Gate Area 1920 Gate Shield Area 1920a Gate shield area 1920b Gate shield area 1920c Gate Shield Area 1925 Gate shield insulator area 1950 Termination area 1960 Mesa 1970 2nd Termination Trench 2000 intermediate structure 2002 Gate trench 2004, 2006, 2008 Termination Trench 2010, 2012, 2014 Mesa 2050 Scalloped Area 2100 Termination Trench 2200 Mesa 2202, 2204, 2206, 2208 Polysilicon material 2206 Drift Region 2210, 2212, 2214, 2216 Shielding oxide layer

Claims

1. a plurality of gate structures parallel to and separated from one another; and a termination structure having a first edge adjacent the plurality of gate structures, the termination structure having a second edge on a side of the termination structure opposite the first edge; A metal oxide semiconductor field effect transistor (MOSFET) having: Each of the plurality of gate structures has a curved edge adjacent to the first edge of the termination structure, and the second edge of the termination structure is concavely curved relative to the curved edges of the plurality of gate structures. MOSFET characterized by:

2. 2. The MOSFET of claim 1, wherein the second edge of the termination structure is parallel to the curved edges of the plurality of gate structures.

3. 2. The MOSFET of claim 1, wherein the second edge of the termination structure is scalloped.

4. 2. The MOSFET of claim 1 further comprising a mesa structure having a first edge adjacent to the second edge of the termination structure and a second edge on a side of the mesa structure opposite the first edge of the mesa structure.

5. 5. The MOSFET of claim 4, wherein, with respect to a cross section of the mesa structure, the first edge of the mesa structure is curved and the second edge of the mesa structure is straight.

6. 5. The MOSFET of claim 4, wherein the width of the mesa structure varies along the length of the mesa structure.

7. 5. The MOSFET of claim 4, wherein said mesa is floating and not tied to a fixed voltage.

8. 5. The MOSFET of claim 4, wherein the mesa structure does not electrically connect to the termination structure.

9. The MOSFET of claim 1 wherein the termination structure comprises a termination trench.

10. 2. The MOSFET of claim 1, wherein the plurality of gate structures comprises a plurality of gate trenches.

11. 1. A method of manufacturing a metal oxide semiconductor field effect transistor (MOSFET), comprising: forming a plurality of gate structures parallel to and separated from one another; forming a termination structure having a first edge adjacent to the plurality of gate structures, the termination structure having a second edge opposite the first edge; Each of the plurality of gate structures has a curved edge adjacent the first edge of the termination structure, and the second edge of the termination structure is concavely curved relative to the curved edges of the plurality of gate structures. MOSFET manufacturing method.

12. The method of claim 11 , wherein the second edge of the termination structure is parallel to the curved edges of the plurality of gate structures.

13. The method of claim 11 , wherein the second edge of the termination structure is scalloped.

14. 12. The method of claim 11 further comprising a mesa structure having a first edge adjacent the second edge of the termination structure and a second edge on a side of the mesa structure opposite the first edge of the mesa structure.

15. 15. The method of claim 14, wherein, with respect to a cross section of the mesa structure, the first edge of the mesa structure is curved and the second edge of the mesa structure is straight.

16. The method of claim 14 wherein the width of the mesa structure varies along the length of the mesa structure.

17. The method of claim 14 wherein the mesa is floating and not tied to a fixed voltage.

18. The method of claim 14 , wherein the mesa structure does not electrically connect to the termination structure.

19. The method of claim 11 , wherein the termination structure comprises a termination trench.

20. The method of claim 11 , wherein the plurality of gate structures comprises a plurality of gate trenches.

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