Photoelectric conversion device and method for driving the same

Abstract

To provide a photoelectric conversion device that can effectively prevent variations in the potential between output lines according to a driving mode.SOLUTION: A photoelectric conversion device has: a plurality of pixels that are arranged to form a plurality of rows and a plurality of columns, and each have a photoelectric conversion part; a plurality of output lines at least two of which are arranged on each of the plurality of columns, and are connected with pixels in the corresponding columns; and a selection circuit that includes a scan circuit configured to sequentially select some partial rows of the plurality of rows and an input unit to which a control signal which is different from the other control signal input to the scan circuit is input, and is configured to select other partial rows of the plurality of rows.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a photoelectric conversion device and a driving method thereof. [Background technology]

[0002] There is known a photoelectric conversion device that is configured to provide multiple output lines for each column of a pixel area and simultaneously read out pixel signals from multiple pixel rows to the multiple output lines, thereby reading out pixel signals at high speed. In such a photoelectric conversion device, the amount of the read signal varies due to potential variations between the output lines, which can cause degradation of image quality. Patent Document 1 describes an imaging element that is configured to fix the output lines to a predetermined potential before reading out a pixel reset signal, thereby suppressing potential variations between the output lines and preventing differences in the amount of signals read out between the output lines. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2015 / 151793 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the imaging element described in Patent Document 1, depending on the driving mode, it may not be possible to sufficiently suppress the potential variation between the output lines.

[0005] An object of the present invention is to provide a photoelectric conversion device and a driving method thereof that can effectively suppress potential variations between output lines depending on the driving mode. [Means for solving the problem]

[0006] According to one disclosure of the present specification, there is provided a photoelectric conversion device having a plurality of pixels arranged in a plurality of rows and a plurality of columns, each having a photoelectric conversion unit, a plurality of output lines, at least two of which are arranged in each of the plurality of columns, each of which is connected to the pixels in the corresponding column, a scanning circuit configured to sequentially select a portion of the plurality of rows, and a selection circuit having an input unit to which a control signal other than the control signal input to the scanning circuit is input, and configured to select another portion of the plurality of rows.

[0007] According to another disclosure of the present specification, there is provided a method for driving a photoelectric conversion device having a plurality of pixels arranged in a plurality of rows and a plurality of columns, each having a photoelectric conversion unit, a plurality of output lines, at least two of which are arranged in each of the plurality of columns, each connected to a pixel in a corresponding column, a scanning circuit that sequentially selects a portion of the plurality of rows, and a selection circuit that selects another portion of the plurality of rows, wherein, during a period in which the scanning circuit selects a first row of the portion of the plurality of rows and outputs a signal of a pixel of the first row to a first output line of the plurality of output lines, the selection circuit selects a second row of the other portion of rows, and outputs a signal of a pixel of the second row to a second output line arranged in the same column as the first output line. Effect of the Invention

[0008] According to the present invention, it is possible to effectively suppress potential variations between output lines in accordance with the drive mode, and to output a high-quality signal with reduced noise. [Brief description of the drawings]

[0009] [Figure 1] 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to a first embodiment of the present invention. [Diagram 2] 1 is an equivalent circuit diagram showing an example of the configuration of a unit pixel in a photoelectric conversion device according to a first embodiment of the present invention. [Diagram 3]2 is an equivalent circuit diagram showing an example of the configuration of a null pixel in the photoelectric conversion device according to the first embodiment of the present invention. [Figure 4] 2 is a schematic diagram showing an example of a connection between unit pixels and null pixels in the photoelectric conversion device according to the first embodiment of the present invention. [Diagram 5] 2 is a block diagram showing an example of the configuration of a vertical drive circuit in the photoelectric conversion device according to the first embodiment of the present invention. FIG. [Figure 6] 2 is a circuit diagram showing an example of the configuration of a control circuit in the photoelectric conversion device according to the first embodiment of the present invention. FIG. [Figure 7] 4 is a timing chart showing the operation of a control circuit in the photoelectric conversion device according to the first embodiment of the present invention. FIG. [Figure 8] FIG. 3 is a timing chart (part 1) showing an example of driving the photoelectric conversion device according to the first embodiment of the present invention. [Figure 9] FIG. 2 is a timing chart (part 2) showing an example of driving the photoelectric conversion device according to the first embodiment of the present invention. [Figure 10] FIG. 11 is a block diagram showing an example of the configuration of a vertical drive circuit in a photoelectric conversion device according to a second embodiment of the present invention. [Figure 11] FIG. 13 is a block diagram showing a schematic configuration of an imaging system according to a third embodiment of the present invention. [Figure 12] FIG. 13 is a diagram showing an example of the configuration of an imaging system and a moving object according to a fourth embodiment of the present invention. [Figure 13] FIG. 13 is a block diagram showing a schematic configuration of an apparatus according to a fifth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] [First embodiment] A photoelectric conversion device according to a first embodiment of the present invention will be described with reference to Figs. 1 to 5. Fig. 1 is a block diagram showing a schematic configuration of the photoelectric conversion device according to this embodiment. Fig. 2 is an equivalent circuit diagram showing an example of the configuration of a unit pixel in the photoelectric conversion device according to this embodiment. Fig. 3 is an equivalent circuit diagram showing an example of the configuration of a null pixel in the photoelectric conversion device according to this embodiment. Fig. 4 is a schematic diagram showing an example of connection of unit pixels and null pixels in the photoelectric conversion device according to this embodiment. Fig. 5 is a block diagram showing an example of the configuration of a vertical drive circuit in the photoelectric conversion device according to this embodiment.

[0011] As shown in FIG. 1, the photoelectric conversion device 100 according to this embodiment has pixel regions 10 and 20, a vertical drive circuit 30, a column circuit section 50, a horizontal drive circuit 60, a signal processing section 70, an output circuit 80, and a system control section 90.

[0012] The pixel region 10 includes a plurality of unit pixels 12 arranged in a matrix across a plurality of rows and a plurality of columns. Each of the unit pixels 12 includes a photoelectric conversion unit formed of a photoelectric conversion element such as a photodiode, and outputs a pixel signal according to the amount of incident light. In addition to effective pixels that output pixel signals according to the amount of incident light, the pixel region 10 may also include optical black pixels in which the photoelectric conversion unit is shielded from light, dummy pixels that do not output signals, and the like.

[0013] A plurality of null pixels 22 arranged in a matrix across a plurality of rows and a plurality of columns are provided in the pixel region 20. Each of the plurality of null pixels 22 does not include a photoelectric conversion unit, and outputs a predetermined pixel signal according to a given voltage.

[0014] The multiple null pixels 22 constituting the pixel region 20 are arranged in different rows from the columns in which the multiple unit pixels 12 constituting the pixel region 10 are arranged. For example, the pixel region 10 may have multiple unit pixels 12 arranged in a matrix of M rows by N columns, and the pixel region 20 may have multiple null pixels 22 arranged in a matrix of K rows by N columns. In this case, assuming that the top row of the pixel region 20 is the first row, N null pixels 22 may be arranged in each of the first row to the Kth row, and N unit pixels 12 may be arranged in each of the (K+1)th row to the (K+M)th row. K null pixels 22 and M unit pixels 12 may be arranged in each of the first column to the Nth column. The number of rows and columns of the pixel arrays arranged in the pixel regions 10 and 20 are not particularly limited.

[0015] In each row of the pixel region 10, a control line 14 is arranged to extend in a first direction (horizontal direction in FIG. 1). Each of the control lines 14 is connected to the unit pixels 12 arranged in the first direction, and serves as a common signal line for these unit pixels 12. In each row of the pixel region 20, a control line 24 is arranged to extend in the first direction. Each of the control lines 24 is connected to the null pixels 22 arranged in the first direction, and serves as a common signal line for these null pixels 22. The first direction in which the control lines 14, 24 extend may be called the row direction or horizontal direction. Each of the control lines 14, 24 may include a plurality of signal lines. The control lines 14, 24 are connected to a vertical drive circuit 30.

[0016] In each column of the pixel regions 10, 20, a vertical output line 16 is arranged extending in a second direction (vertical direction in FIG. 1) intersecting the first direction. Each of the vertical output lines 16 is connected to the unit pixels 12 and null pixels 22 aligned in the second direction, and serves as a common signal line for these unit pixels 12 and null pixels 22. The second direction in which the vertical output lines 16 extend may be called the column direction or vertical direction. Each of the vertical output lines 16 includes a plurality of output lines. The vertical output lines 16 are connected to a column circuit section 50. The specific connection relationship between the unit pixels 12 and null pixels 22 and the vertical output lines 16 will be described later.

[0017] The vertical drive circuit 30 is a control circuit having a function of receiving a control signal supplied from the system control unit 90, generating a control signal for driving the unit pixels 12 and the null pixels 22, and supplying the control signal to the unit pixels 12 and the null pixels 22 via the control lines 14, 24. The vertical drive circuit 30 may include logic circuits such as a shift register and an address decoder. The vertical drive circuit 30 sequentially supplies control signals to the control lines 14, 24 of each row, and sequentially drives the unit pixels 12 and the null pixels 22 of the pixel regions 10, 20 row by row. Signals read out from the unit pixels 12 and the null pixels 22 row by row are input to the column circuit section 50 via the vertical output lines 16 provided in each column of the pixel regions 10, 20.

[0018] The column circuit section 50 has a plurality of column circuits, each of which includes a processing circuit and a signal holding circuit, and is provided corresponding to each of a plurality of output lines constituting the vertical output line 16 of each column of the pixel regions 10 and 20. The processing circuit has a function of performing a predetermined signal processing on the pixel signal output via the corresponding output line. Examples of the signal processing performed by the processing circuit include amplification processing, correction processing using correlated double sampling (CDS), and analog-to-digital conversion (AD conversion). The signal holding circuit functions as a memory for holding the pixel signal processed by the processing circuit.

[0019] The horizontal drive circuit 60 is a control circuit having a function of receiving a control signal supplied from the system control unit 90, generating a control signal for reading out pixel signals from the column circuit unit 50, and supplying the control signal to the column circuit unit 50. The horizontal drive circuit 60 sequentially scans the column circuits of each column of the column circuit unit 50, and sequentially outputs the pixel signals held in each of them to the signal processing unit 70. The horizontal drive circuit 60 may include logic circuits such as a shift register and an address decoder.

[0020] The signal processing unit 70 has a function of performing predetermined signal processing on pixel signals transferred from the column circuit unit 50. Examples of the processing performed by the signal processing unit 70 include arithmetic processing, amplification processing, and correction processing using CDS.

[0021] The output circuit 80 has an external interface circuit, and is a circuit for outputting the signal processed by the signal processing unit 70 to the outside of the photoelectric conversion device 100. The external interface circuit included in the output circuit 80 is not particularly limited. For example, a SerDes (SERializer / DESerializer) transmission circuit such as an LVDS (Low Voltage Differential Signaling) circuit or an SLVS (Scalable Low Voltage Signaling) circuit can be applied to the external interface circuit.

[0022] The system control unit 90 is a control circuit that generates control signals for controlling the operation of the vertical drive circuit 30, the column circuit unit 50, the horizontal drive circuit 60, etc., and supplies them to each functional block. Note that the control signals for controlling the operation of the vertical drive circuit 30, the column circuit unit 50, the horizontal drive circuit 60, etc. do not necessarily need to be supplied from the system control unit 90, and at least some of them may be supplied from outside the photoelectric conversion device 100.

[0023] Next, a configuration example of a unit pixel 12 in the photoelectric conversion device according to this embodiment will be described with reference to Fig. 2. Fig. 2 shows a unit pixel 12(m,n) arranged in the mth row and nth column out of the multiple unit pixels 12 constituting the pixel region 10. Here, m is an integer from 1 to M, and n is an integer from 1 to N. The circuit configuration of the other unit pixels 12 constituting the pixel region 10 may be similar to that of the unit pixel 12(m,n).

[0024] As shown in Fig. 2, the unit pixel 12(m,n) may be composed of photoelectric conversion elements PD1, PD2, transfer transistors M11, M12, a reset transistor M2, an amplification transistor M3, and a selection transistor M4. The unit pixel 12(m,n) may have a microlens and a color filter arranged on an optical path from incident light to the photoelectric conversion elements PD1, PD2. The microlens focuses the incident light on the photoelectric conversion elements PD1, PD2. The color filter selectively transmits light of a predetermined color.

[0025] The photoelectric conversion elements PD1 and PD2 are, for example, photodiodes. The photoelectric conversion element PD1 has an anode connected to a reference voltage node and a cathode connected to the source of the transfer transistor M11. The photoelectric conversion element PD2 has an anode connected to a reference voltage node and a cathode connected to the source of the transfer transistor M12. The drains of the transfer transistor M11 and the transfer transistor M12 are connected to the source of the reset transistor M2 and the gate of the amplification transistor M3. A node FD to which the drains of the transfer transistor M11, the transfer transistor M12, the source of the reset transistor M2, and the gate of the amplification transistor M3 are connected is a so-called floating diffusion part. The floating diffusion part includes a capacitance component (floating diffusion capacitance) and has a function as a charge holding part. The floating diffusion capacitance may include a pn junction capacitance, a wiring capacitance, and the like. The drains of the reset transistor M2 and the amplification transistor M3 are connected to a node to which a power supply voltage (voltage VDD) is supplied. The source of the amplification transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to a vertical output line 16n. A current source 18 is connected to the vertical output line 16n.

[0026] In the case of the circuit configuration of FIG. 2, the control line 14_m of the mth row includes four signal lines connected to the gate of the transfer transistor M11, the gate of the transfer transistor M12, the gate of the reset transistor M2, and the gate of the selection transistor M4. A control signal TX1m is supplied from the vertical drive circuit 30 to the gate of the transfer transistor M11 of the unit pixel 12 of the mth row. A control signal TX2m is supplied from the vertical drive circuit 30 to the gate of the transfer transistor M12 of the unit pixel 12 of the mth row. A control signal RSTm is supplied from the vertical drive circuit 30 to the gate of the reset transistor M2 of the unit pixel 12 of the mth row. A control signal SELm is supplied from the vertical drive circuit 30 to the gate of the selection transistor M4 of the unit pixel 12 of the mth row. When each transistor is an N-type MOS transistor, when a high-level control signal is supplied from the vertical drive circuit 30, the corresponding transistor is turned on. Also, when a low-level control signal is supplied from the vertical drive circuit 30, the corresponding transistor is turned off.

[0027] In this embodiment, the description will be made on the assumption that, of the electron-hole pairs generated in the photoelectric conversion elements PD1 and PD2 by the incidence of light, the electrons are used as signal charges. When electrons are used as signal charges, each transistor constituting the unit pixel 12 may be composed of an N-type MOS transistor. However, the signal charges are not limited to electrons, and holes may be used as signal charges. When holes are used as signal charges, the conductivity type of each transistor is the opposite conductivity type to that described in this embodiment. The names of the source and drain of a MOS transistor may differ depending on the conductivity type of the transistor and the function of interest. Some or all of the names of the source and drain used in this embodiment may be called by the opposite names.

[0028] The photoelectric conversion elements PD1 and PD2 convert the incident light into an electric charge according to the amount of light (photoelectric conversion) and accumulate the generated electric charge. When the transfer transistor M11 is turned on, it transfers the electric charge held by the photoelectric conversion element PD1 to the node FD. When the transfer transistor M12 is turned on, it transfers the electric charge held by the photoelectric conversion element PD2 to the node FD. The electric charge transferred from the photoelectric conversion elements PD1 and PD2 is held in the capacitance (floating diffusion capacitance) of the node FD. As a result, the node FD has a potential according to the amount of the electric charge transferred from the photoelectric conversion elements PD1 and PD2 by charge-voltage conversion by the floating diffusion capacitance.

[0029] When the selection transistor M4 is turned on, it connects the amplification transistor M3 to the vertical output line 16n. The amplification transistor M3 has a configuration in which a voltage VDD is supplied to its drain and a bias current is supplied to its source from the current source 18 via the vertical output line 16n and the selection transistor M4, forming an amplification section (source follower circuit) with the gate as an input node. As a result, the amplification transistor M3 outputs a signal based on the voltage of the node FD to the vertical output line 16n via the selection transistor M4. In this sense, the amplification transistor M3 and the selection transistor M4 are an output section that outputs a pixel signal according to the amount of charge held in the node FD.

[0030] The reset transistor M2 has a function of controlling the supply of a voltage (voltage VDD) to the FD node for resetting the node FD as a charge storage unit. The reset transistor M2 resets the node FD to a voltage corresponding to the voltage VDD by turning on. At this time, it is also possible to reset the photoelectric conversion element PD1 to a voltage corresponding to the voltage VDD by simultaneously turning on the transfer transistor M11. In addition, it is also possible to reset the photoelectric conversion element PD2 to a voltage corresponding to the voltage VDD by simultaneously turning on the transfer transistor M12.

[0031] By appropriately controlling the transfer transistors M11, M12, the reset transistor M2, and the selection transistor M4, a signal corresponding to the reset voltage of the node FD and a signal corresponding to the amount of light incident on the photoelectric conversion elements PD1, PD2 are read out from each unit pixel 12. Hereinafter, the signal corresponding to the reset voltage of the node FD is referred to as a noise signal (N signal), and the signal corresponding to the amount of light incident on the photoelectric conversion elements PD1, PD2 is referred to as a photoelectric conversion signal (S signal).

[0032] In the unit pixel 12 of this embodiment, two photoelectric conversion elements PD1 and PD2 share one floating diffusion region (node ​​FD). From such a unit pixel 12, it is possible to separately read out a pixel signal based on the charge generated by the photoelectric conversion element PD1 and a signal based on the charge generated by the photoelectric conversion element PD2. In this case, first, an N signal and an S signal based on the charge generated by the photoelectric conversion element PD1 can be read out, and then an N signal and an S signal based on the charge generated by the photoelectric conversion element PD2 can be read out.

[0033] Next, a configuration example of the null pixel 22 in the photoelectric conversion device according to this embodiment will be described with reference to Fig. 3. Fig. 3 shows a null pixel 22(k,n) arranged in the kth row and nth column out of the multiple null pixels 22 constituting the pixel region 20. Here, k is an integer from 1 to K, and n is an integer from 1 to N. The other null pixels 22 constituting the pixel region 20 may have the same circuit configuration as the null pixel 22(k,n).

[0034] 3, the null pixel 22(k,n) may be composed of a reset transistor M5, an amplification transistor M6, and a selection transistor M7. That is, the null pixel 22 differs from the unit pixel 12 in that it does not include photoelectric conversion elements PD1, PD2 and transfer transistors M11, M12. The physical configurations of the reset transistor M5, the amplification transistor M6, and the selection transistor M7 may be similar to those of the reset transistor M2, the amplification transistor M3, and the selection transistor M4 of the unit pixel 12.

[0035] The source of the reset transistor M5 is connected to the gate of the amplification transistor M6. A node FDn to which the source of the reset transistor M5 and the gate of the amplification transistor M6 are connected is a floating diffusion portion similar to the node FD of the unit pixel 12. The drain of the reset transistor M5 and the drain of the amplification transistor M6 are connected to a node to which a power supply voltage (voltage VDD) is supplied. The source of the amplification transistor M6 is connected to the drain of the selection transistor M7. The source of the selection transistor M7 is connected to the vertical output line 16n.

[0036] 3, the control line 24_k of the kth row includes two signal lines connected to the gate of the reset transistor M5 and the gate of the selection transistor M7. A control signal NRSTk is supplied from the vertical drive circuit 30 to the gate of the reset transistor M5 of the null pixel 22 of the kth row. A control signal NSELk is supplied from the vertical drive circuit 30 to the gate of the selection transistor M7 of the null pixel 22 of the kth row.

[0037] As described above, the reset transistor M5, the amplification transistor M6, and the selection transistor M7 of the null pixel 22 have the same configurations as the reset transistor M2, the amplification transistor M3, and the selection transistor M4 of the unit pixel 12. Therefore, an N signal obtained by removing the effects of the photoelectric conversion elements PD1 and PD2 and the transfer transistors M11 and M12 from the N signal of the unit pixel 12 is read out from the null pixel 22.

[0038] Next, an example of the connection between the unit pixels 12 and the null pixels 22 and the vertical output lines 16 will be described with reference to Fig. 4. Note that, as an example in this embodiment, the vertical output lines 16 of each column include four output lines, but the number of output lines included in the vertical output lines 16 of each column is not limited to four.

[0039] When the vertical output line 16 of each column is composed of four output lines, the vertical output line 16n of the n-th column includes an output line 16n1, an output line 16n2, an output line 16n3, and an output line 16n4, as shown in Fig. 4. The pixel region 20 includes at least the same number of rows as the number of output lines constituting the vertical output line 16 of each column.

[0040] Each unit pixel 12 is connected to one of the four output lines of the vertical output line 16 arranged in the corresponding column. For example, as shown in FIG. 4, the unit pixel 12(K+1,n) arranged in the (K+1)th row and nth column is connected to the output line 16n1 constituting the vertical output line 16n of the nth column. The unit pixel 12(K+2,n) arranged in the (K+2)th row and nth column is connected to the output line 16n2 constituting the vertical output line 16n of the nth column. The unit pixel 12(K+3,n) arranged in the (K+3)th row and nth column is connected to the output line 16n3 constituting the vertical output line 16n of the nth column. The unit pixel 12(K+4,n) arranged in the (K+4)th row and nth column is connected to the output line 16n4 constituting the vertical output line 16n of the nth column. Similarly to the unit pixels 12 in the first to fourth rows, the unit pixels 12 in the fifth and subsequent rows are connected to one of the output lines 16n1 to 16n4 at a cycle of four rows.

[0041] The unit pixels 12 arranged in the (K+m)th row are supplied with control signals RSTm, TX1m, TX2m, and SELm from the vertical drive circuit 30. For example, the unit pixels 12 arranged in the (K+1)th row are supplied with control signals RST1, TX11, TX21, and SEL1 from the vertical drive circuit 30. The unit pixels 12 arranged in the second row are supplied with control signals RST2, TX12, TX22, and SEL2 from the vertical drive circuit 30. The same applies to the unit pixels 12 in the third and subsequent rows.

[0042] In the unit pixel 12 of the present embodiment, the pixel including the photoelectric conversion element PD1 and the transfer transistor M11 and the pixel including the photoelectric conversion element PD2 and the transfer transistor M12 share the reset transistor M2, the amplification transistor M3, and the selection transistor M4. By configuring the unit pixel 12 in this way, the number of transistors per pixel can be reduced compared to a pixel configuration in which the reset transistor M2, the amplification transistor M3, and the selection transistor M4 are not shared. Therefore, for example, assuming a layout in which the area of ​​the photoelectric conversion element is the same, it is possible to miniaturize the pixel compared to a pixel configuration in which the reset transistor M2, the amplification transistor M3, and the selection transistor M4 are not shared.

[0043] Each null pixel 22 is connected to one of the four output lines of the vertical output line 16 arranged in the corresponding column. For example, as shown in FIG. 4, the null pixel 22(1,n) arranged in the first row and n-th column is connected to the output line 16n1 constituting the vertical output line 16n of the n-th column. The null pixel 22(2,n) arranged in the second row and n-th column is connected to the output line 16n2 constituting the vertical output line 16n of the n-th column. The null pixel 22(3,n) arranged in the third row and n-th column is connected to the output line 16n3 constituting the vertical output line 16n of the n-th column. The null pixel 22(4,n) arranged in the fourth row and n-th column is connected to the output line 16n4 constituting the vertical output line 16n of the n-th column.

[0044] The null pixels 22 arranged in the k-th row are supplied with control signals NRSTk and NSELk from the vertical drive circuit 30. For example, the null pixels 22 arranged in the first row are supplied with control signals NRST1 and NSEL1 from the vertical drive circuit 30. The null pixels 22 arranged in the second row are supplied with control signals NRST2 and NSEL2 from the vertical drive circuit 30. The same applies to the null pixels 22 in the third row and onwards.

[0045] Next, a configuration example of the vertical drive circuit 30 in the photoelectric conversion device according to the present embodiment will be described with reference to FIG. 5, the vertical drive circuit 30 in the photoelectric conversion device according to the present embodiment has a vertical scanning section 32 and a vertical logic section 34. The vertical logic section 34 has M unit vertical logic sections 36 corresponding to the M rows constituting the pixel region 10, and K unit vertical logic sections 42 corresponding to the K rows constituting the pixel region 20. Each unit vertical logic section 36 has a logic generation section 38 and a calculation section 40. Each unit vertical logic section 42 has a logic generation section 44 and a calculation section 46.

[0046] The vertical scanning section 32 serves as a selection circuit that selects unit vertical logic sections 36, 42 corresponding to a plurality of rows constituting the pixel regions 10, 20. The vertical scanning section 32 outputs a row selection signal DEC corresponding to each row of the pixel region 10 in response to a control signal from the system control section 90.<K+1> ~DEC<K+M> and a row selection signal DEC corresponding to each row of the pixel region 20. <1> ~DEC <k>and generate a row selection signal DEC<K+1> ~DEC<K+M> is a selection signal for selecting a unit vertical logic unit 36, and is input to the unit vertical logic unit 36 ​​of the corresponding row. The vertical scanning unit 32 may be configured with an address decoder and a shift register. When the vertical scanning unit 32 is configured with an address decoder, the control signal input from the system control unit 90 is an address signal, and the row selection signal DEC <1> ~DEC <k>,DEC<K+1> ~DEC<K+M> is a decoded signal obtained by decoding the address signal.

[0047] Row selection signal DEC <1> ~DEC <k>is a selection signal for selecting a unit vertical logic unit 42, and is input to the unit vertical logic unit 42 of the corresponding row. The vertical scanning unit 32 is also a scanning circuit configured to sequentially select a portion of a plurality of rows corresponding to the unit vertical logic unit 36 ​​out of the plurality of rows constituting the pixel regions 10, 20. The configuration in which each row is selected by the row selection signal DEC is the same in the unit vertical logic units 42, 36. In addition, a control signal VLSELk generated by a control circuit 92 under the control of the system control unit 90 is input to the unit vertical logic unit 42 of each row.

[0048] The logic generation unit 44 of the unit vertical logic unit 42 in the kth row outputs the row selection signal DEC <k>and outputs a logical value corresponding to a control signal from the system control unit 90. The arithmetic unit 46 of the unit vertical logic unit 42 of the kth row generates control signals NRSTk, NSELk in response to the logical value input from the logic generation unit 44, the control signal from the system control unit 90, and the control signal VLSELk from the control circuit 92. The generated control signals NRSTk, NSELk are output to the null pixel 22(k,n) via the control line 24_k. Here, the control signal VLSELk is a signal for determining whether it is a horizontal scanning period in which a pixel signal is read out to the output line 16nk or a horizontal scanning period in which a pixel signal is not read out to the output line 16nk.

[0049] When the control signal VLSELk is at a high level and it is a horizontal scanning period in which no pixel signal is read out to the output line 16nk, the calculation unit 46 outputs the row selection signal DEC <k>The control signals NRSTk, NSELk are allowed to be output to the null pixels 22(k, n) regardless of the input signal VLSELk. The logic circuit constituting the arithmetic unit 46 is not particularly limited, but may be configured to include, for example, an OR circuit that receives the output of the logic generation unit 44 and the control signal VLSELk, and an AND circuit that receives the output of the OR circuit and a control signal from the system control unit 90.

[0050] The logic generating unit 38 of the unit vertical logic unit 36 ​​in the (K+m)th row outputs the row selection signal DEC<K+m> and outputs a logical value according to a control signal from the system control unit 90. The arithmetic unit 40 of the unit vertical logic unit 36 ​​in the (K+m)th row generates control signals RSTm, SELm, TX11m, and TX21m according to the logical value input from the logic generation unit 38 and the control signal from the system control unit 90. The generated control signals RSTm, SELm, TX11m, and TX21m are output to the unit pixel 12(K+m,n) via the control line 14_m. The unit vertical logic unit 36 ​​outputs a row selection signal DEC<K+m> In response to the row selection signal DEC, the unit vertical logic unit 36 ​​controls the output of the control signals RSTm, SELm, TX11m, and TX21m to the unit pixel 12(K+m, n).<K+m> The control signals RSTm, SELm, TX11m, and TX21m are not supplied to the control line 14_m except during the period selected by the command.

[0051] The control circuit 92 has a role as a selection circuit to select some of the rows corresponding to the unit vertical logic unit 42 among the multiple rows constituting the pixel regions 10 and 20. The control circuit 92 has an input unit to which a control signal other than the control signal (e.g., address signal) input to the vertical scanning unit 32 is input. The control circuit 92 can be configured as a circuit that receives pulse signals P1 and P2 and an enable signal EN from the system control unit 90 as input signals and outputs control signals VLSEL1, VLSEL2, VLSEL3, and VLSEL4, as shown in FIG. 6, for example. The logic circuit constituting such a control circuit 92 is not particularly limited, but can be configured to include logic circuits NOT1, NOT2, AND1, AND2, AND3, and AND4, as shown in FIG. 6, for example.

[0052] A pulse signal P1 is input to an input node of the logic circuit NOT1. A pulse signal P2 is input to an input node of the logic circuit NOT2. An output signal of the logic circuit NOT1 and an enable signal EN are input to two input nodes of the logic circuit AND1. The output signal of the logic circuit AND1 becomes a control signal VLSEL1. A pulse signal P1 and an enable signal EN are input to two input nodes of the logic circuit AND2. An output signal of the logic circuit AND2 becomes a control signal VLSEL3. An output signal of the logic circuit NOT2 and an enable signal EN are input to two input nodes of the logic circuit AND3. An output signal of the logic circuit AND3 becomes a control signal VLSEL2. A pulse signal P2 and an enable signal EN are input to two input nodes of the logic circuit AND4. An output signal of the logic circuit AND4 becomes a control signal VLSEL4.

[0053] Next, the operation of the control circuit 92 will be described with reference to Fig. 7. Fig. 7 shows an example of the operation of the control circuit 92 in four consecutive horizontal scanning periods (first horizontal scanning period 1HD to fourth horizontal scanning period 4HD). The operation of generating the control signals VLSEL1 to VLSEL4 by the pulse signals P1 and P2 can be repeated with the four horizontal scanning periods shown in Fig. 7 as one cycle.

[0054] The pulse signal P1 is at a high level during the first horizontal scanning period 1HD and the fourth horizontal scanning period 4HD, and at a low level during the second horizontal scanning period 2HD and the third horizontal scanning period 3HD. The pulse signal P2 is at a high level during the first horizontal scanning period 1HD and the second horizontal scanning period 2HD, and at a low level during the third horizontal scanning period 3HD and the fourth horizontal scanning period 4HD. The enable signal EN is at a high level during the first horizontal scanning period 1HD to the fourth horizontal scanning period 4HD.

[0055] 7, when the enable signal EN is at a high level, an inverted pulse of the pulse signal P1 becomes the control signal VLSEL1, and an in-phase pulse of the pulse signal P1 becomes the control signal VLSEL3. Also, when the enable signal EN is at a high level, an inverted pulse of the pulse signal P2 becomes the control signal VLSEL2, and an in-phase pulse of the pulse signal P2 becomes the control signal VLSEL4.

[0056] Therefore, when the pulse signals P1 and P2 transition as shown in FIG. 7, in the first horizontal scanning period 1HD, the control signals VLSEL1 and VLSEL2 are at low level, and the control signals VLSEL3 and VLSEL4 are at high level. In the second horizontal scanning period 2HD, the control signals VLSEL2 and VLSEL3 are at low level, and the control signals VLSEL1 and VLSEL4 are at high level. In the third horizontal scanning period 3HD, the control signals VLSEL3 and VLSEL4 are at low level, and the control signals VLSEL1 and VLSEL2 are at high level. In the fourth horizontal scanning period 4HD, the control signals VLSEL1 and VLSEL4 are at low level, and the control signals VLSEL2 and VLSEL3 are at high level.

[0057] Next, a method for driving the photoelectric conversion device according to this embodiment will be described with reference to Fig. 8 and Fig. 9. Fig. 8 and Fig. 9 are timing charts showing the method for driving the photoelectric conversion device according to this embodiment.

[0058] First, a basic driving example of the photoelectric conversion device according to this embodiment will be described with reference to Fig. 8. Here, an operation in the case of reading out pixel signals from unit pixels 12(K+1,n), 12(K+2,n), 12(K+3,n), and 12(K+4,n) shown in Fig. 4 will be described.

[0059] In the following description, for convenience, among the components of the unit pixel 12, the part that contributes to reading out the signal from the photoelectric conversion element PD1 and the part that contributes to reading out the signal from the photoelectric conversion element PD2 are sometimes called "pixels". Specifically, for the unit pixel 12(K+1,n), the pixel element that contributes to reading out the signal from the photoelectric conversion element PD1 is called pixel A, and the pixel element that contributes to reading out the signal from the photoelectric conversion element PD2 is called pixel B. For the unit pixel 12(K+2,n), the pixel element that contributes to reading out the signal from the photoelectric conversion element PD1 is called pixel C, and the pixel element that contributes to reading out the signal from the photoelectric conversion element PD2 is called pixel D. For the unit pixel 12(K+3,n), the pixel element that contributes to reading out the signal from the photoelectric conversion element PD1 is called pixel E, and the pixel element that contributes to reading out the signal from the photoelectric conversion element PD2 is called pixel F. Regarding the unit pixel 12(K+4,n), the pixel element that contributes to reading out a signal from the photoelectric conversion element PD1 is pixel G, and the pixel element that contributes to reading out a signal from the photoelectric conversion element PD2 is pixel H.

[0060] The pixel elements that contribute to reading out a signal from the photoelectric conversion element PD1 are the photoelectric conversion element PD1, the transfer transistor M11, the reset transistor M2, the amplification transistor M3, and the selection transistor M4. The pixel elements that contribute to reading out a signal from the photoelectric conversion element PD2 are the photoelectric conversion element PD2, the transfer transistor M12, the reset transistor M2, the amplification transistor M3, and the selection transistor M4.

[0061] Fig. 8 is a timing diagram showing a driving mode in which all output lines constituting the vertical output line 16 at any given time are used to read out pixel signals. More specifically, this is a mode in which each of the four output lines constituting the vertical output line 16 of each column is connected to a unit pixel 12 during each horizontal scanning period, and pixel signals are read out from each of the four output lines. Fig. 8 shows control signals RST1 to RST4, TX11 to TX42, and SEL1 to SEL4 supplied from the vertical driving circuit 30. In this driving example, signals are not read out from the null pixels 22 in the pixel area 20.

[0062] The period from time t0 to time t1 is the state before the start of reading. During this period, all the control signals RST1 to RST4, TX11 to TX42, and SEL1 to SEL4 are at low level, that is, in the inactive state.

[0063] The period from time t1 to time t6 corresponds to one horizontal scanning period during which the N signals and S signals are read out from each of pixels B, C, F and G.

[0064] At time t2, the vertical drive circuit 30 changes the control signals RST1, RST2, RST3, RST4, SEL1, SEL2, SEL3, and SEL4 from low level to high level. This turns on the selection transistors M4 of the unit pixels 12(K+1,n) to 12(K+4,n), and connects the unit pixels 12(K+1,n) to 12(K+4,n) to the output lines 16n1 to 16n4. In addition, the reset transistors M2 of the unit pixels 12(K+1,n) to 12(K+4,n) turn on, and a reset operation of the node FD is started.

[0065] At the next time t3, the vertical drive circuit 30 controls the control signals RST1, RST2, RST3, and RST4 to change from high level to low level. This turns off the reset transistors M2 of the unit pixels 12(K+1,n) to 12(K+4,n), and releases the reset state of the node FD. When the reset transistor M2 turns off, the potential of the node FD drops to a predetermined potential due to coupling with the gate of the reset transistor M2. The voltage of the node FD that becomes static after the reset transistor M2 turns off is the reset voltage of the node FD.

[0066] As a result, a signal corresponding to the reset voltage of the node FD of the unit pixel 12(K+1,n) is output to the output line 16n1 via the amplification transistor M3 and the selection transistor M4. Similarly, signals corresponding to the reset voltage of the node FD of the unit pixels 12(K+2,n) to 12(K+4,n) are output to the output lines 16n2 to 16n3.

[0067] The signal output from the unit pixel 12(K+1,n) to the output line 16n1 is processed by the subsequent column circuit section 50 and read out as the N signal of pixel B. Similarly, the signals output from the unit pixels 12(K+2,n) to 12(K+4,n) to the output lines 16n2 to 16n4 are read out as the N signals of pixels C, F, and G.

[0068] At the next time t4, the vertical drive circuit 30 controls the control signals TX12, TX21, TX32, and TX41 to change from low to high. This causes the transfer transistors M11 of the unit pixels 12(K+2,n) and 12(K+4,n) to turn on, and the charges accumulated in the photoelectric conversion elements PD1 of the unit pixels 12(K+2,n) and 12(K+4,n) during the predetermined exposure period are transferred to the node FD. In addition, the transfer transistors M12 of the unit pixels 12(K+1,n) and 12(K+3,n) to turn on, and the charges accumulated in the photoelectric conversion elements PD2 of the unit pixels 12(K+1,n) and 12(K+3,n) during the predetermined exposure period are transferred to the node FD.

[0069] As a result, a signal corresponding to the amount of charge generated in the photoelectric conversion element PD2 of the unit pixel 12(1,n) is output to the output line 16n1 via the amplification transistor M3 and the selection transistor M4. Similarly, a signal corresponding to the amount of charge generated in the photoelectric conversion element PD1 of the unit pixel 12(2,n) is output to the output line 16n2 via the amplification transistor M3 and the selection transistor M4. Also, a signal corresponding to the amount of charge generated in the photoelectric conversion element PD2 of the unit pixel 12(3,n) is output to the output line 16n3 via the amplification transistor M3 and the selection transistor M4. Also, a signal corresponding to the amount of charge generated in the photoelectric conversion element PD1 of the unit pixel 12(4,n) is output to the output line 16n4 via the amplification transistor M3 and the selection transistor M4.

[0070] At the next time t5, the vertical drive circuit 30 controls the control signals TX12, TX21, TX32, and TX41 to change from high level to low level. This ends the period of charge transfer from the photoelectric conversion elements PD1 and PD2 in the unit pixels 12(K+1,n) to 12(K+4,n) to the node FD. The signal output from the unit pixel 12(K+1,n) to the output line 16n1 is processed in the subsequent column circuit section 50 after settling, and is read out as the S signal of pixel B. Similarly, the signals output from the unit pixels 12(K+2,n) to 12(K+4,n) to the output lines 16n2 to 16n4 are read out as the S signals of pixels C, F, and G.

[0071] At the next time t6, the vertical drive circuit 30 changes the control signals SEL1, SEL2, SEL3, and SEL4 from high to low, thereby turning off the selection transistors M4 of the unit pixels 12(K+1,n) to 12(K+4,n) from which data has been read, and disconnecting the unit pixels 12(K+1,n) to 12(K+4,n) from the output lines 16n1 to 16n4.

[0072] The subsequent period from time t7 to time t11 corresponds to one horizontal scanning period in which N signals and S signals are read out from each of pixels A, D, E and H, similarly to the period from time t2 to time t6.

[0073] In this way, after two horizontal scanning periods from time t1 to time t11, pixel signals are read out from eight pixels, namely pixel A, pixel B, pixel C, pixel D, pixel E, pixel F, pixel G, and pixel H. After that, the pixel region 10 is sequentially scanned in units of four rows starting from the fifth row using a similar procedure, and pixel signals are read out from the entire pixel region 10.

[0074] Next, a driving example in which two of the four output lines constituting the vertical output line 16 of each column are connected to the unit pixels 12 and pixel signals are read out from each of the unit pixels 12 connected to the output lines will be described with reference to Figure 9.

[0075] Parasitic capacitance exists between adjacent output lines of a plurality of output lines constituting one column of vertical output lines. In the solid-state imaging device described in Patent Document 1, when pixel signals are read out from some of the output lines constituting one column of vertical output lines, the other output lines are fixed to a predetermined voltage before reading out. Therefore, the influence through the parasitic capacitance between the output line that reads out the pixel signal and the output line that does not read out the pixel signal differs depending on the potential state of the adjacent output line. As a result, the amount of coupling from the vertical output line to the node FD when reading out the reset signal and the settling time of the reset signal may vary between the output lines constituting the vertical output line. When an image with the same black level is captured, the amount of signal read out between the output lines differs, causing a step in the image and deteriorating the image quality. In order to improve such a problem, in this driving example, a signal from a null pixel 22 is output to an output line that does not output a signal from the unit pixel 12.

[0076] Fig. 9 is a timing diagram showing a drive mode in which some of the output lines constituting the vertical output line 16 are not used for reading out pixel signals at any time. Fig. 9 shows control signals RST1-RST4, TX11-TX42, SEL1-SEL4, NRST1-NRST4, and NSEL1-NSEL4 supplied from the vertical drive circuit 30. Fig. 9 also shows control signals VLSEL1-VLSEL4 supplied from the control circuit 92 to the vertical drive circuit 30. Each control signal is in an active state when at a high level and in an inactive state when at a low level.

[0077] The period from time t20 to time t21 is the state before the start of reading. During this period, all the control signals RST1-4, TX11-42, SEL1-4, NRST1-4, and NSEL1-NSEL4 are at low level, i.e., inactive. In addition, the enable signal EN (not shown) is at low level, and the control signals VLSEL1-VLSEL4 are also at low level.

[0078] The period from time t21 to time t26 corresponds to one horizontal scanning period during which the N signals and the S signals are read out from each of pixels B and C. This one horizontal scanning period corresponds to the first horizontal scanning period 1HD in FIG.

[0079] At time t21, the system control unit 90 controls the enable signal EN and the pulse signals P1, P2 supplied to the control circuit 92 to change from low level to high level, causing the control signals VLSEL1, VLSEL2 to go to low level and the control signals VLSEL3, VLSEL4 to go to high level.

[0080] At the next time t22, the vertical drive circuit 30 changes the control signals RST1, RST2, SEL1, and SEL2 from low level to high level. This turns on the selection transistors M4 of the unit pixels 12(K+1,n) and 12(K+2,n), connecting the unit pixels 12(K+1,n) to the output line 16n1 and the unit pixels 12(K+2,n) to the output line 16n2. In addition, the reset transistors M2 of the unit pixels 12(K+1,n) and 12(K+2,n) turn on, starting the reset operation of the node FD.

[0081] Also, at time t22, the vertical drive circuit 30 controls the control signals NRST3, NRST4, NSEL3, and NSEL4 from low level to high level in response to the control signals VLSEL3 and VLSEL4 being at high level. As a result, the selection transistors M7 of the null pixels 22(3,n) and 22(4,n) are turned on, and the null pixels 22(3,n) and 22(4,n) are connected to the output line 16n3 and the null pixels 22(4,n) are connected to the output line 16n4, respectively. Also, the reset transistors M5 of the null pixels 22(3,n) and 22(4,n) are turned on, and the reset operation of the node FDn is started.

[0082] At the next time t23, the vertical drive circuit 30 controls the control signals RST1, RST2, NRST3, and NRST4 from high level to low level. This turns off the reset transistors M2 of the unit pixels 12(K+1,n) and 12(K+2,n), and the reset state of the node FD is released. When the reset transistor M2 turns off, the potential of the node FD drops to a predetermined potential due to coupling with the gate of the reset transistor M2. The voltage of the node FD that is statically determined after the reset transistor M2 turns off is the reset voltage of the node FD. In addition, the reset transistors M5 of the null pixels 22(3,n) and 22(4,n) turn off, and the reset state of the node FDn is released. When the reset transistor M5 turns off, the potential of the node FDn drops to a predetermined potential due to coupling with the gate of the reset transistor M5. The voltage of the node FDn that is statically determined after the reset transistor M5 turns off is the reset voltage of the node FDn.

[0083] As a result, a signal corresponding to the reset voltage of the node FD of the unit pixel 12(K+1,n) is output to the output line 16n1, and a signal corresponding to the reset voltage of the node FD of the unit pixel 12(K+2,n) is output to the output line 16n2. Also, a signal corresponding to the reset voltage of the node FDn of the null pixel 22(3,n) is output to the output line 16n3, and a signal corresponding to the reset voltage of the node FDn of the null pixel 22(4,n) is output to the output line 16n4.

[0084] The transient potential change of the output lines constituting the vertical output line 16n is affected by parasitic capacitance components such as coupling between the output lines constituting the vertical output line 16n and parasitic resistance components of the wiring, etc. For example, the output line 16n1 is coupled to the adjacent output line 16n2, and the output line 16n2 is coupled to the adjacent output lines 16n1 and 16n3.

[0085] In the period from time t22 to time t24, a potential change occurs in the output line 16n1 due to the reading of the N signal of pixel B, and a potential change occurs in the output line 16n2 due to the reading of the N signal of pixel C. At this time, the N signals of the pixels that constitute the unit pixel 12 are not read out to the output lines 16n3 and 16n4. However, a potential change occurs in the output line 16n3 due to the reading of the N signal of the null pixel 22(3,n), and a potential change occurs in the output line 16n4 due to the reading of the N signal of the null pixel 22(4,n).

[0086] In this manner, the potentials of the four output lines 16n1 to 16n4 constituting the vertical output line 16n change in the same manner at the same timing by reading out the N signals from the null pixels 22 to the output lines that do not read out the N signals from the unit pixels 12. This allows the effects of the parasitic capacitances between the output lines 16n1 to 16n4 to be roughly uniform.

[0087] At the next time t24, the vertical drive circuit 30 controls the control signals TX12 and TX21 to change from low level to high level. This turns on the transfer transistor M12 of the unit pixel 12(K+1,n), and the charge accumulated in the photoelectric conversion element PD2 of the unit pixel 12(K+1,n) during the predetermined exposure period is transferred to the node FD. Also, the transfer transistor M11 of the unit pixel 12(K+2,n) turns on, and the charge accumulated in the photoelectric conversion element PD1 of the unit pixel 12(K+2,n) during the predetermined exposure period is transferred to the node FD.

[0088] As a result, a signal corresponding to the amount of charge generated in the photoelectric conversion element PD2 of the unit pixel 12(K+1,n) is output to the output line 16n1 via the amplification transistor M3 and the selection transistor M4. Similarly, a signal corresponding to the amount of charge generated in the photoelectric conversion element PD1 of the unit pixel 12(K+2,n) is output to the output line 16n2 via the amplification transistor M3 and the selection transistor M4.

[0089] At the next time t25, the vertical drive circuit 30 controls the control signals TX12 and TX21 to change from high level to low level, thereby ending the charge transfer period from the photoelectric conversion element PD2 in the unit pixel 12(K+1,n) to the node FD and the charge transfer period from the photoelectric conversion element PD1 in the unit pixel 12(K+2,n) to the node FD.

[0090] At the next time t26, the vertical drive circuit 30 controls the control signals SEL1, SEL2, NSEL3, and NSEL4 to change from high to low. As a result, the selection transistors M4 of the unit pixels 12(K+1,n) and 12(K+2,n) from which data has been read are turned off, and the unit pixels 12(K+1,n) and 12(K+2,n) are disconnected from the output lines 16n1 and 16n2. In addition, the selection transistors M7 of the null pixels 22(3,n) and 22(4,n) are turned off, and the null pixels 22(3,n) and 22(4,n) are disconnected from the output lines 16n3 and 16n4.

[0091] The period from time t26 to time t41 is a period in which the N signals and S signals are read out from pixels A, D, E, F, G, and H in the same manner as the N signals and S signals are read out from pixels B and C during the period from time t21 to time t26.

[0092] The period from time t26 to time t31 corresponds to one horizontal scanning period during which the N signal and the S signal are read out from each of pixel D and pixel E. This one horizontal scanning period corresponds to the second horizontal scanning period 2HD in Fig. 7. When pixel D is read out, the control signal SEL2 is activated, and the N signal and the S signal are read out to the output line 16n2. When pixel E is read out, the control signal SEL3 is activated, and the N signal and the S signal are read out to the output line 16n3.

[0093] During the period from time t26 to time t31, the control signals VLSEL1 and VLSEL4 are at high level, and accordingly the control signals NSEL1 and NSEL4 are in an active state. As a result, the N signal of the null pixel 22(1,n) is read out to the output line 16n1, and the N signal of the null pixel 22(4,n) is read out to the output line 16n4. In this manner, by reading out the N signal from the null pixel 22 to an output line that does not read out the N signal from the unit pixel 12, the potentials of the four output lines 16n1 to 16n4 constituting the vertical output line 16n change in the same manner at the same timing. As a result, the influence through the parasitic capacitance between the output lines 16n1 to 16n4 can be roughly uniformed.

[0094] The period from time t31 to time t36 corresponds to one horizontal scanning period during which the N signal and the S signal are read out from each of pixel F and pixel G. This one horizontal scanning period corresponds to the third horizontal scanning period 3HD in Fig. 7. When pixel F is read out, the control signal SEL3 is set to an active state, and the N signal and the S signal are read out to the output line 16n3. When pixel G is read out, the control signal SEL4 is set to an active state, and the N signal and the S signal are read out to the output line 16n4.

[0095] During the period from time t31 to time t36, the control signals VLSEL1 and VLSEL2 are at high level, and accordingly the control signals NSEL1 and NSEL2 are in an active state. As a result, the N signal of the null pixel 22(1,n) is read out to the output line 16n1, and the N signal of the null pixel 22(2,n) is read out to the output line 16n2. In this manner, by reading out the N signal from the null pixel 22 to an output line that does not read out the N signal from the unit pixel 12, the potentials of the four output lines 16n1 to 16n4 constituting the vertical output line 16n change in the same manner at the same timing. As a result, the influence through the parasitic capacitance between the output lines 16n1 to 16n4 can be roughly uniformed.

[0096] The period from time t36 to time t41 corresponds to one horizontal scanning period during which the N signal and the S signal are read out from each of pixel A and pixel H. This one horizontal scanning period corresponds to the fourth horizontal scanning period 4HD in Fig. 7. When pixel A is read out, the control signal SEL1 is set to an active state, and the N signal and the S signal are read out to the output line 16n1. When pixel H is read out, the control signal SEL4 is set to an active state, and the N signal and the S signal are read out to the output line 16n4.

[0097] During the period from time t36 to time t41, the control signals VLSEL2 and VLSEL3 are at high level, and accordingly the control signals NSEL2 and NSEL3 are in an active state. As a result, the N signal of the null pixel 22(2,n) is read out to the output line 16n2, and the N signal of the null pixel 22(3,n) is read out to the output line 16n3. In this manner, by reading out the N signal from the null pixel 22 to an output line that does not read out the N signal from the unit pixel 12, the potentials of the four output lines 16n1 to 16n4 constituting the vertical output line 16n change in the same manner at the same timing. As a result, the influence through the parasitic capacitance between the output lines 16n1 to 16n4 can be roughly uniformed.

[0098] In this way, after four horizontal scanning periods from time t21 to time t41, pixel signals are read out from eight pixels, namely pixel A, pixel B, pixel C, pixel D, pixel E, pixel F, pixel G, and pixel H. After that, using a similar procedure, the pixel area 10 is sequentially scanned in units of four rows starting from the fifth row, and pixel signals are read out from the entire pixel area 10.

[0099] In this manner, in this embodiment, the N signals of the null pixels 22 are read out to unselected output lines, thereby harmonizing the influence of each output line on other output lines through parasitic capacitance among the multiple output lines constituting the vertical output line 16 of the same column. Therefore, according to this embodiment, it is possible to effectively suppress potential variations between the output lines and output a high-quality signal with reduced noise.

[0100] [Second embodiment] A photoelectric conversion device according to a second embodiment of the present invention will be described with reference to Fig. 10. The same components as those in the photoelectric conversion device according to the first embodiment are given the same reference numerals, and their description will be omitted or simplified. Fig. 10 is a block diagram showing an example of the configuration of a vertical drive circuit 30 in the photoelectric conversion device according to this embodiment.

[0101] The photoelectric conversion device according to this embodiment is similar to the photoelectric conversion device according to the first embodiment, except for the location of the control circuit 92. That is, in the photoelectric conversion device according to the first embodiment, the control circuit 92 is provided outside the vertical drive circuit 30 as a circuit independent of the vertical drive circuit 30. In contrast, in the photoelectric conversion device according to this embodiment, as shown in FIG. 10, the control circuit 92 is disposed inside the vertical scanning unit 32 of the vertical drive circuit 30. By configuring the photoelectric conversion device in this manner, it is no longer necessary to route wiring for supplying the control signals VLSEL1 to VLSEL4 from other functional blocks, and an efficient wiring layout is possible. In addition, it is also possible to configure logic inside the vertical scanning unit 32 and simplify the configuration of the unit vertical logic unit 36. For example, when the row selection signal DEC <k>The vertical scanning unit 32 may be configured to output a signal obtained by performing a logical operation on the control signal VLSELk and the signal VLSELk. The circuit configuration in the vertical scanning unit 32 is not limited to that shown in FIG.

[0102] As described above, according to the present embodiment, it is possible to effectively suppress potential variations between output lines and output a high-quality signal with reduced noise. In addition, an efficient wiring layout is possible, and the circuit configuration can be simplified.

[0103] [Third embodiment] An imaging system according to a third embodiment of the present invention will be described with reference to Fig. 11. Fig. 11 is a block diagram showing a schematic configuration of the imaging system according to this embodiment.

[0104] The photoelectric conversion device 100 described in the first and second embodiments is applicable to various imaging systems. Examples of applicable imaging systems include digital still cameras, digital camcorders, security cameras, copiers, fax machines, mobile phones, car-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in the imaging system. FIG. 11 illustrates a block diagram of a digital still camera as an example of these.

[0105] 11 includes an imaging device 201, a lens 202 that forms an optical image of a subject on the imaging device 201, an aperture 204 that varies the amount of light passing through the lens 202, and a barrier 206 that protects the lens 202. The lens 202 and the aperture 204 form an optical system that focuses light on the imaging device 201. The imaging device 201 is the photoelectric conversion device 100 described in either the first or second embodiment, and converts the optical image formed by the lens 202 into image data.

[0106] The imaging system 200 also includes a signal processing unit 208 that processes an output signal output from the imaging device 201. The signal processing unit 208 generates image data from a digital signal output from the imaging device 201. The signal processing unit 208 also performs various corrections and compression as necessary to output image data. The imaging device 201 may include an AD conversion unit that generates a digital signal to be processed by the signal processing unit 208. The AD conversion unit may be formed in a semiconductor layer (semiconductor substrate) in which a photoelectric conversion unit of the imaging device 201 is formed, or may be formed in a semiconductor substrate different from the semiconductor layer in which the photoelectric conversion unit of the imaging device 201 is formed. The signal processing unit 208 may also be formed in the same semiconductor substrate as the imaging device 201.

[0107] The imaging system 200 further includes a memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. The imaging system 200 further includes a recording medium 214 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading out on the recording medium 214. The recording medium 214 may be built into the imaging system 200, or may be removable.

[0108] Furthermore, the imaging system 200 has an overall control / calculation unit 218 that performs various calculations and controls the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the imaging device 201 and the signal processing unit 208. Here, the timing signals and the like may be input from outside, and the imaging system 200 only needs to have at least the imaging device 201 and the signal processing unit 208 that processes the output signal output from the imaging device 201.

[0109] The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201, and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

[0110] In this way, according to this embodiment, it is possible to realize an imaging system to which the photoelectric conversion device 100 according to the first embodiment is applied.

[0111] [Fourth embodiment] An imaging system and a moving object according to a fourth embodiment of the present invention will be described with reference to Fig. 12. Fig. 12 is a diagram showing the configuration of the imaging system and the moving object according to this embodiment.

[0112] FIG. 12(a) shows an example of an imaging system related to an in-vehicle camera. The imaging system 300 has an imaging device 310. The imaging device 310 is the photoelectric conversion device 100 described in any one of the first and second embodiments. The imaging system 300 has an image processing unit 312 that performs image processing on a plurality of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the imaging device 310. The imaging system 300 also has a distance acquisition unit 316 that calculates a distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire distance information to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 318 may determine the possibility of a collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination of these.

[0113] The imaging system 300 is connected to a vehicle information acquisition device 320, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 318. The imaging system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the judgment result of the collision judgment unit 318. For example, when the judgment result of the collision judgment unit 318 indicates that there is a high possibility of a collision, the control ECU 330 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 340 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., and vibrating the seat belt or steering wheel.

[0114] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the imaging system 300. Fig. 12(b) shows an imaging system for imaging the area in front of the vehicle (imaging range 350). A vehicle information acquisition device 320 sends instructions to the imaging system 300 or imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0115] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from lanes, etc. Furthermore, the imaging system is not limited to vehicles such as the vehicle itself, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies, but also to devices that use object recognition widely, such as intelligent transport systems (ITS).

[0116] [Fifth embodiment] A device according to a fifth embodiment of the present invention will be described with reference to Fig. 13. Fig. 13 is a block diagram showing a schematic configuration of the device according to this embodiment.

[0117] FIG. 13 is a schematic diagram showing an apparatus EQP including a photoelectric conversion device APR. The photoelectric conversion device APR has the functions of the photoelectric conversion device 100 described in either the first or second embodiment. All or a part of the photoelectric conversion device APR is a semiconductor device IC. The photoelectric conversion device APR of this example can be used as, for example, an image sensor, an AF (Auto Focus) sensor, a photometry sensor, or a distance measurement sensor. The semiconductor device IC has a pixel area PX in which pixel circuits PXC including photoelectric conversion units are arranged in a matrix. The semiconductor device IC can have a peripheral area PR around the pixel area PX. Circuits other than pixel circuits can be arranged in the peripheral area PR.

[0118] The photoelectric conversion device APR may have a structure (a chip stacking structure) in which a first semiconductor chip provided with a plurality of photoelectric conversion units and a second semiconductor chip provided with peripheral circuits are stacked. The peripheral circuits in the second semiconductor chip may be column circuits corresponding to the pixel columns of the first semiconductor chip. The peripheral circuits in the second semiconductor chip may be matrix circuits corresponding to the pixels or pixel blocks of the first semiconductor chip. The first and second semiconductor chips may be connected to each other by through-hole vias (TSVs), inter-chip wiring by direct bonding of a conductor such as copper, connection by microbumps between chips, connection by wire bonding, or the like.

[0119] The photoelectric conversion device APR may include a package PKG that houses the semiconductor device IC in addition to the semiconductor device IC. The package PKG may include a base to which the semiconductor device IC is fixed, a cover such as glass that faces the semiconductor device IC, and connection members such as bonding wires and bumps that connect terminals provided on the base and terminals provided on the semiconductor device IC.

[0120] The equipment EQP may further include at least one of an optical device OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric conversion device APR as a photoelectric conversion device, and is, for example, a lens, a shutter, or a mirror. The control device CTRL controls the photoelectric conversion device APR, and is, for example, a semiconductor device such as an ASIC. The processing device PRCS processes a signal output from the photoelectric conversion device APR, and constitutes an AFE (analog front end) or a DFE (digital front end). The processing device PRCS is a semiconductor device such as a CPU (central processing unit) or an ASIC (application specific integrated circuit). The display device DSPL is an EL display device or a liquid crystal display device that displays information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is a magnetic device or a semiconductor device that stores information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN has a moving part or a propulsion part such as a motor or an engine. In the device EQP, the signal output from the photoelectric conversion device APR is displayed on the display device DSPL, and is transmitted to the outside by a communication device (not shown) provided in the device EQP. For this purpose, the device EQP preferably further includes a memory device MMRY and a processing device PRCS in addition to the memory circuit unit and the arithmetic circuit unit provided in the photoelectric conversion device APR.

[0121] The device EQP shown in FIG. 13 may be an electronic device such as an information terminal having a photographing function (e.g., a smartphone or a wearable device) or a camera (e.g., an interchangeable lens camera, a compact camera, a video camera, or a surveillance camera). The mechanical device MCHN in the camera can drive components of the optical device OPT for zooming, focusing, and shutter operation. The device EQP may also be a transportation device (moving object) such as a vehicle, a ship, or an aircraft. The device EQP may also be a medical device such as an endoscope or a CT scanner. The device EQP may also be a medical device such as an endoscope or a CT scanner.

[0122] The mechanical device MCHN in the transportation equipment can be used as a moving device. The device EQP as a transportation equipment is suitable for transporting the photoelectric conversion device APR and for assisting and / or automating driving (operation) by using a photographing function. The processing device PRCS for assisting and / or automating driving (operation) can perform processing for operating the mechanical device MCHN as a moving device based on information obtained by the photoelectric conversion device APR.

[0123] The photoelectric conversion device APR according to this embodiment can provide high value to its designer, manufacturer, seller, purchaser and / or user. Therefore, if the photoelectric conversion device APR is installed in equipment EQP, the value of the equipment EQP can also be increased. Therefore, when manufacturing and selling equipment EQP, deciding to install the photoelectric conversion device APR of this embodiment in the equipment EQP is advantageous in increasing the value of the equipment EQP.

[0124] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible.

[0125] For example, an example in which part of the configuration of any of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is substituted therefor, is also an embodiment of the present invention.

[0126] In addition, in the above embodiment, the vertical output line 16 of each column of the pixel regions 10 and 20 is composed of four output lines, but the number of output lines constituting the vertical output line 16 of each column is not limited to four, and may be two or more.

[0127] In the above embodiment, the reset transistor M5 and the selection transistor M7 are operated when the null pixel 22 drives an unused output line, but the configuration for driving an unused output line with the null pixel 22 is not limited to this. For example, the configuration may be such that only the selection transistor M7 is operated, or the null pixel 22 may be provided with a transfer transistor similar to that of the unit pixel 12 and driven in the same manner as the unit pixel 12. By bringing the configuration of the null pixel 22 closer to that of the unit pixel 12, the loads of the vertical lines can be made more uniform. The configuration of the null pixel 22 can be changed as appropriate depending on the circuit area required to achieve this and the effect of reducing image quality degradation.

[0128] In the above embodiment, an example is shown in which unused output lines are driven by the null pixels 22, but it is also possible to configure the unused output lines to be driven using components other than the null pixels 22, for example, light-shielded pixels (optical black pixels) whose photoelectric conversion units are shielded from light. It is also possible to configure the unused output lines to output signals for purposes other than image formation signals, such as signals from focus detection pixels or signals from failure detection pixels.

[0129] Also, the circuit configuration of the unit pixel 12 shown in FIG. 2 is an example, and can be modified as appropriate. For example, the number of photoelectric conversion elements included in each unit pixel 12 may be one. Also, the number of photoelectric conversion elements included in each unit pixel 12 may be three or more. In this case, a configuration in which a plurality of photoelectric conversion elements share one FD node may be used. Also, a configuration in which a plurality of photoelectric conversion elements are a pupil division pixel sharing one microlens and a phase difference can be detected may be used. Also, the unit pixel 12 does not necessarily have to have a selection transistor M4. Also, a configuration in which the capacitance value of the node FD is switchable may be used.

[0130] Furthermore, the imaging systems shown in the third and fourth embodiments are examples of imaging systems to which the photoelectric conversion device of the present invention can be applied, and imaging systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 11 and 12.

[0131] The present invention can also be realized by a process in which a program for implementing one or more of the functions of the above-described embodiments is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. The present invention can also be realized by a circuit (e.g., ASIC) that implements one or more of the functions.

[0132] It should be noted that the above-mentioned embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be interpreted as being limited by these embodiments. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features.

[0133] The disclosure of the above embodiment includes the following configurations and methods. (Configuration 1) A plurality of pixels arranged in a plurality of rows and a plurality of columns, each having a photoelectric conversion unit; a plurality of output lines, at least two of which are arranged in each of the plurality of columns, each of which is connected to pixels in a corresponding column; a scanning circuit configured to sequentially select a portion of the plurality of rows; a selection circuit including an input section to which a control signal different from the control signal input to the scanning circuit is input, the selection circuit being configured to select other rows of the plurality of rows; A photoelectric conversion device comprising: (Configuration 2) A control circuit for controlling the scanning circuit and the selection circuit is further provided. The control circuit includes: During a period in which a first row of the partial plurality of rows is selected by the scanning circuit and signals of pixels of the first row are output to a first output line of the plurality of output lines, A second row of the other part of rows is selected by the selection circuit, and a signal of a pixel in the second row is output to a second output line arranged in the same column as the first output line. 2. The photoelectric conversion device according to configuration 1. (Configuration 3) The first output line and the second output line are adjacent to each other. 3. The photoelectric conversion device according to configuration 2. (Configuration 4) The pixels arranged in the other part of rows are null pixels that do not include a photoelectric conversion unit. 4. The photoelectric conversion device according to configuration 2 or 3. (Configuration 5) The pixels arranged in the other part of rows are light-shielded pixels whose photoelectric conversion units are shielded from light. 4. The photoelectric conversion device according to configuration 2 or 3. (Configuration 6) The signal output to the second output line is the N signal output from the pixels in the second row. 6. The photoelectric conversion device according to configuration 4 or 5. (Configuration 7) The purpose of the signal output to the first output line is different from the purpose of the signal output to the second output line. 4. The photoelectric conversion device according to configuration 2 or 3. (Configuration 8) The control signal input to the selection circuit includes information regarding output lines to which signals from the pixels in the partial rows are not output, among the output lines arranged in the same column. 8. The photoelectric conversion device according to any one of configurations 1 to 7. (Configuration 9) The selection circuit is provided outside the scanning circuit. 9. The photoelectric conversion device according to any one of configurations 1 to 8. (Configuration 10) The selection circuit is provided in the scanning circuit. 9. The photoelectric conversion device according to any one of configurations 1 to 8. (Configuration 11) Each of the pixels arranged in the plurality of rows has a plurality of photoelectric conversion units. 11. The photoelectric conversion device according to any one of configurations 1 to 10. (Method 1) A method for driving a photoelectric conversion device having a plurality of pixels arranged in a plurality of rows and a plurality of columns, each having a photoelectric conversion unit, a plurality of output lines arranged in each of the plurality of columns, at least two of which are connected to the pixels in the corresponding column, a scanning circuit that sequentially selects a portion of the plurality of rows, and a selection circuit that selects another portion of the plurality of rows, During a period in which a first row of the partial plurality of rows is selected by the scanning circuit and signals of pixels of the first row are output to a first output line of the plurality of output lines, A second row of the other part of rows is selected by the selection circuit, and a signal of a pixel in the second row is output to a second output line arranged in the same column as the first output line. A method for driving a photoelectric conversion device comprising the steps of: (Configuration 12) A photoelectric conversion device according to any one of structures 1 to 11, a signal processing device that processes a signal output from the photoelectric conversion device; An imaging system comprising: (Configuration 13) A mobile object, A photoelectric conversion device according to any one of structures 1 to 11, a distance information acquiring means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device; a control means for controlling the moving object based on the distance information; A moving object comprising: (Configuration 14) A photoelectric conversion device according to any one of structures 1 to 11, an optical device corresponding to the photoelectric conversion device; A control device for controlling the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a mechanical device controlled based on information obtained by the photoelectric conversion device; A display device that displays information obtained by the photoelectric conversion device; and a storage device for storing information obtained by the photoelectric conversion device; An apparatus comprising: [Explanation of symbols]

[0134] 10,20...pixel area 12...Unit pixel 16...Vertical output line 22...Null pixel 30...Vertical drive circuit 32...Vertical scanning section 34...Vertical logic section 36,42...Unit vertical logic section 92...Control circuit 100...Photoelectric conversion device< / k> < / k> < / k> < / k> < / k> < / k>

Claims

1. a plurality of pixels arranged in a plurality of rows and a plurality of columns, each having a photoelectric conversion unit; a plurality of output lines, at least two of which are arranged in each of the plurality of columns, each of which is connected to pixels in a corresponding column; a scanning circuit configured to sequentially select a portion of the plurality of rows; a selection circuit including an input unit to which a control signal different from the control signal input to the scanning circuit is input, the selection circuit being configured to select other rows of the plurality of rows; A photoelectric conversion device comprising:

2. a control circuit for controlling the scanning circuit and the selection circuit; The control circuit During a period in which a first row of the partial plurality of rows is selected by the scanning circuit and signals of pixels in the first row are output to a first output line of the plurality of output lines, A second row of the other part of rows is selected by the selection circuit, and a signal of a pixel in the second row is output to a second output line arranged in the same column as the first output line.

2. The photoelectric conversion device according to claim 1.

3. The first output line and the second output line are adjacent to each other.

3. The photoelectric conversion device according to claim 2.

4. The pixels arranged in the other part of rows are pixels that do not include a photoelectric conversion unit.

4. The photoelectric conversion device according to claim 2 or 3.

5. The pixels arranged in the other part of rows are light-shielded pixels whose photoelectric conversion units are shielded from light.

4. The photoelectric conversion device according to claim 2 or 3.

6. The signal output to the second output line is the N signal output from the pixel in the second row.

5. The photoelectric conversion device according to claim 4.

7. The signal output to the first output line and the signal output to the second output line have different uses.

4. The photoelectric conversion device according to claim 2 or 3.

8. The control signal input to the selection circuit includes information about output lines to which signals from pixels in the plurality of rows are not output, among the output lines arranged in the same column.

4. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

9. The selection circuit is provided outside the scanning circuit.

4. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

10. The selection circuit is provided in the scanning circuit.

4. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

11. Each of the pixels arranged in the plurality of rows has a plurality of photoelectric conversion units.

4. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

12. A method for driving a photoelectric conversion device including: a plurality of pixels arranged in a plurality of rows and a plurality of columns, each having a photoelectric conversion unit; a plurality of output lines, at least two of which are arranged in each of the plurality of columns, each connected to a pixel in a corresponding column; a scanning circuit that sequentially selects some of the plurality of rows; and a selection circuit that selects other some of the plurality of rows, During a period in which a first row of the partial plurality of rows is selected by the scanning circuit and signals of pixels in the first row are output to a first output line of the plurality of output lines, A second row of the other part of rows is selected by the selection circuit, and a signal of a pixel in the second row is output to a second output line arranged in the same column as the first output line. A method for driving a photoelectric conversion device.

13. The photoelectric conversion device according to any one of claims 1 to 3, a signal processing device that processes a signal output from the photoelectric conversion device; An imaging system comprising:

14. A mobile object, The photoelectric conversion device according to any one of claims 1 to 3, a distance information acquisition means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device; a control means for controlling the moving object based on the distance information; A moving object characterized by having:

15. The photoelectric conversion device according to any one of claims 1 to 3, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a mechanical device controlled based on the information obtained by the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; and a storage device that stores information obtained by the photoelectric conversion device; An apparatus characterized by comprising:

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