Method of manufacturing multilayer electronic component

Abstract

To provide a method of manufacturing a multilayer electronic component, in which, in the process of opening side margin portion attachment surfaces of a plurality of unit chips, there is no need to concentrate stress at a specific portion of the plurality of unit chips and occurrence of damages of the unit chips can be suppressed, so that the reliability and manufacturing yield of a multilayer electronic component with a side margin portion formed thereto are improved.SOLUTION: A method includes: a stacked body production step of producing a stacked body by stacking, on a support film 310, a plurality of ceramic green sheets on which conductive patterns are disposed; a stacked body cutting step of cutting the stacked body in a second direction perpendicular to a first direction which is a stacking direction of the plurality of ceramic green sheets and in a third direction perpendicular to the first and second directions, to obtain a plurality of unit chips; an arrangement step of, after separating the unit chip from the support film, arranging the unit chip such that a second side surface S2 of the unit chip is in contact with an adhesive tape; and a first side margin portion formation step of attaching a first side surface S1 to a ceramic green sheet for a side margin portion, and forming a first side margin portion.SELECTED DRAWING: Figure 12

Description

[Technical field]

[0001] The present invention relates to a method for producing a multilayer electronic component. [Background technology]

[0002] Multi-layered ceramic capacitors (MLCCs), which are one type of multi-layered electronic component, are chip-type capacitors that are mounted on printed circuit boards of various electronic products such as visual devices such as liquid crystal displays (LCDs) and plasma display panels (PDPs), computers, smartphones, and mobile phones, and serve to charge and discharge electricity.

[0003] Conventionally, in order to miniaturize a multilayer ceramic capacitor while increasing its capacitance, the internal electrodes are exposed in the width direction of the body, thereby maximizing the area of ​​the internal electrodes in the width direction through a margin-free design, and after the unit chips are manufactured and before firing, a process is applied in which a side margin portion is separately attached to the exposed surface of the internal electrodes in the width direction of the unit chips.

[0004] In particular, Patent Document 1 discloses a technique in which the surfaces on which side margins of a plurality of stacked chips are formed are simultaneously exposed in the same direction (upward) by using an adhesive sheet and an elastic pad.

[0005] Specifically, according to the method of forming side margins disclosed in the above-mentioned Patent Document 1, a plurality of green chips arranged in row and column directions are tumblingly separated at regular intervals to uniformly open the cut sides, and then a step of attaching side ceramic green sheets to the cut sides of the plurality of green chips is included.

[0006] In particular, in the rolling method disclosed in Patent Document 1, a strong shear force is applied to the green chips by the support and the rolling plate, which may cause stress to concentrate on the corners of the green chips acting on the center of rotation, which may damage the corners of the green chips and reduce the reliability and manufacturing yield of the multilayer electronic component.

[0007] In addition, according to the method of forming a side margin portion disclosed in Patent Document 1, multiple green chips must be rotated simultaneously, which can cause problems such as adjacent stacked chips sticking to each other, and there is also a risk of defects such as non-movement and non-rotation due to the dispersion of sizes of the multiple green chips.

[0008] Therefore, the present invention aims to suppress the phenomenon of stress concentration at the corners of unit chips in the process of exposing the forming surfaces of the side margins of unit chips in order to form the side margins of multilayer electronic components, and to reduce defects such as non-movement and non-rotation that may occur when multiple unit chips are exposed simultaneously, thereby improving the reliability and manufacturing yield of multilayer electronic components. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] U.S. Patent Publication No. 2012-0234462 Summary of the Invention [Problem to be solved by the invention]

[0010] One of the various objects of the present invention is to solve the problem of stress concentration at corners of a plurality of unit chips in the process of opening the attachment surfaces of the side margin portions of a plurality of unit chips in order to form the side margin portions.

[0011] One of the various objects of the present invention is to solve the problem that unit chips do not move or rotate when a plurality of unit chips are rolled to form a side margin portion and the attachment surface of the side margin portion is opened, which may occur due to size dispersion between the plurality of unit chips.

[0012] One of the various objects of the present invention is to solve the problem that when a side margin portion is formed by punching a ceramic green sheet onto the attachment surface of the side margin portion of a plurality of unit chips, the adhesive strength of the side margin portion decreases due to rapid drying of the ceramic green sheet.

[0013] One of the various objects of the present invention is to solve the problem that, when a side margin portion is formed by punching a ceramic green sheet on an attachment surface of the side margin portion of a plurality of unit chips, a separate adhesive component must be coated on the surface of the ceramic green sheet to ensure the adhesive strength of the side margin portion due to rapid drying of the ceramic green sheet.

[0014] However, the object of the present invention is not limited to the above-mentioned contents, and can be more easily understood in the course of describing specific embodiments of the present invention. [Means for solving the problem]

[0015] According to an embodiment of the present invention, a method for manufacturing a multilayer electronic component may include a laminate fabricating step of fabricating a laminate by stacking a plurality of ceramic green sheets, each having a conductive pattern disposed thereon, on a support film; a laminate cutting step of cutting the laminate in a second direction perpendicular to the first direction and in a third direction perpendicular to the first and second directions to obtain a plurality of unit chips, where a cut surface of the conductive pattern is exposed on one side of the unit chip in the second direction, and first and second side surfaces facing the third direction, and a second internal electrode pattern is exposed on another side of the unit chip in the second direction, and the first and second side surfaces, in the unit chips; an arrangement step of separating the unit chips from the support film and arranging the unit chips such that second side surfaces of the unit chips are in contact with an adhesive tape; and a first side margin forming step of attaching the first side surface to a ceramic green sheet for a side margin to form a first side margin.

[0016] According to another embodiment of the present invention, a method for manufacturing a multilayer electronic component includes a laminate fabricating step of fabricating a laminate by stacking a plurality of ceramic green sheets, each having a conductive pattern disposed thereon, on a support film; a laminate cutting step of cutting the laminate in a second direction perpendicular to the first direction and in a third direction perpendicular to the first and second directions to obtain a plurality of unit chips, where a cut surface of the conductive pattern is exposed on one side of the unit chip in the second direction, and first and second side surfaces facing the third direction, and a second internal electrode pattern is exposed on another side of the unit chip in the second direction, and the first and second side surfaces, in the unit chips; an arrangement step of separating the unit chips from the support film without rotating the unit chips, and arranging the unit chips such that second side surfaces of the unit chips are in contact with an adhesive tape; and a first side margin forming step of attaching the first side surface to a ceramic green sheet for a side margin to form a first side margin. Effect of the Invention

[0017] One of the various advantages of the present invention is that, in the process of releasing the attachment surfaces of the side margin portions of a plurality of unit chips, there is no need to concentrate stress on specific portions of the plurality of unit chips, thereby suppressing damage to the unit chips and improving the reliability and manufacturing yield of stacked electronic components having side margin portions.

[0018] One of the various advantages of the present invention is that it suppresses the phenomenon of cracks occurring at the boundary between the capacitance forming portion and the cover portion of the multilayer electronic component by replacing a process that concentrates stress on a specific portion of the unit chip.

[0019] One of the various advantages of the present invention is that even when there is size dispersion among a plurality of unit chips, the unit chips are prevented from being left unmoved and unrotated, thereby improving the manufacturing yield of multilayer electronic components.

[0020] One of the various advantages of the present invention is that when a ceramic green sheet is punched onto the attachment surface of the side margin portions of multiple unit chips to form the side margin portions, rapid drying of the ceramic green sheet is suppressed, thereby ensuring sufficient adhesive strength of the side margin portions.

[0021] However, the various and beneficial advantages and effects of the present invention are not limited to the above, and can be more easily understood in the course of describing specific embodiments of the present invention. [Brief description of the drawings]

[0022] [Figure 1] 1 is a schematic perspective view of a multilayer electronic component that can be manufactured by a method for manufacturing a multilayer electronic component according to an embodiment of the present invention; [Diagram 2] 2 is a cross-sectional view taken along the line II' of FIG. [Diagram 3] 2 is a cross-sectional view taken along line II-II' of FIG. [Figure 4]10 is a schematic diagram showing a method for manufacturing a multilayer electronic component according to a comparative example. [Diagram 5] 1A to 1C are schematic diagrams illustrating steps of a method for producing a multilayer electronic component according to an embodiment of the present invention. [Figure 6] 2 is an exploded perspective view showing a schematic diagram of a laminate manufacturing step according to an embodiment of the present invention; FIG. [Figure 7] 2 is a perspective view illustrating a laminate cutting step according to an embodiment of the present invention; FIG. [Figure 8] 1 is a perspective view showing a schematic shape of a bar immediately after a laminate cutting step according to an embodiment of the present invention; FIG. [Figure 9] 1 is a plan view of a bar viewed from a first direction immediately after another laminate cutting step is performed in one embodiment of the present invention. FIG. [Figure 10] 1 is a perspective view showing a schematic shape of a unit chip according to an embodiment of the present invention; [Figure 11] 1 is a perspective view illustrating a support film rotating step according to an embodiment of the present invention; [Figure 12] 2 is a plan view generally illustrating an arrangement step according to an embodiment of the present invention; [Figure 13] 4 is a plan view illustrating a state in which a first side surface of a unit chip is attached to a ceramic green sheet for a side margin portion in a step of forming a first side margin portion according to an embodiment of the present invention. FIG. [Figure 14] 4 is a plan view illustrating a state in which a ceramic green sheet for a side margin portion attached to a first side surface of a unit chip is punched in a step of forming a first side margin portion according to an embodiment of the present invention. FIG. [Figure 15] 1 is a perspective view illustrating an arrangement step according to an embodiment; [Figure 16a] 1 is a perspective view illustrating an arrangement step according to an embodiment; [Figure 16b] 1 is a perspective view illustrating an arrangement step according to an embodiment; [Figure 17]1 is a perspective view illustrating a state of a body having first and second side margin portions formed in a unit chip according to an embodiment of the present invention before firing; [Figure 18] 18 is a cross-sectional view taken along line III-III' of FIG. 17. [Figure 19] 4 is a cross-sectional view taken along line IV-IV' of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] Hereinafter, the embodiments of the present invention will be described with reference to specific embodiments and the accompanying drawings. However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, the embodiments of the present invention are provided to more completely explain the present invention to ordinary skilled artisans. Therefore, the shapes and sizes of elements in the drawings may be enlarged or reduced (or highlighted or simplified) for clearer explanation, and elements indicated by the same reference numerals in the drawings are the same elements.

[0024] In order to clearly explain the present invention in the drawings, parts that are not relevant to the explanation are omitted, and the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, so the present invention is not necessarily limited to those shown. Components having the same function within the same concept are described using the same reference numerals. Furthermore, throughout the specification, when a part "includes" a certain component, this does not mean that other components are excluded, but that the part may further include other components, unless otherwise specified to the contrary.

[0025] In the drawings, a first direction is defined as a direction in which a plurality of ceramic green sheets are stacked or a thickness T direction, and among second and third directions perpendicular to the first direction, the second direction can be defined as a length L direction and the third direction can be defined as a width W direction.

[0026] FIG. 4 is a schematic diagram showing a method for manufacturing a multilayer electronic component according to a comparative example, FIG. 5 is a schematic diagram showing the procedure of a method for manufacturing a multilayer electronic component according to one embodiment of the present invention, FIG. 6 is an exploded perspective view showing a laminate manufacturing step according to one embodiment of the present invention, FIG. 7 is a perspective view showing a laminate cutting step according to one embodiment of the present invention, FIG. 8 is a perspective view showing a bar shape immediately after performing a laminate cutting step according to one embodiment of the present invention, FIG. 9 is a plan view of a bar seen from a first direction immediately after performing another laminate cutting step according to one embodiment of the present invention, FIG. 10 is a perspective view showing a shape of a unit chip according to one embodiment of the present invention, FIG. 11 is a perspective view showing a support film rotating step according to one embodiment of the present invention, FIG. 12 is a plan view showing an arrangement step according to one embodiment of the present invention, and FIG. 13 is a plan view showing a first side of a unit chip being attached to a ceramic green sheet for a side margin portion in a first side margin portion forming step according to one embodiment of the present invention.

[0027] Hereinafter, a method for manufacturing a multilayer electronic component according to one embodiment of the present invention, another embodiment, and various embodiments will be described in detail with reference to FIGS. 5 to 14, the method for manufacturing a multilayer electronic component 100 according to an embodiment of the present invention includes a laminate preparation step (P1) of preparing a laminate 200 by stacking a plurality of ceramic green sheets 201, 202, each having a conductive pattern 221', 222' arranged thereon, on a support film 310; a step (P2) of cutting the laminate 200 in a second direction perpendicular to the first direction and in a third direction perpendicular to the first and second directions, where the direction in which the plurality of ceramic green sheets 201, 202 are stacked is defined as a first direction, and cutting the laminate 200 in a third direction perpendicular to the first and second directions to obtain a plurality of unit chips 210, in which the cut surfaces of the conductive patterns 221', 222' face one side 3 of the unit chip in the second direction and a third direction facing one side 3 in the third direction. The method may include a laminate cutting step (P2) of cutting the laminate so that the first internal electrode pattern 221 exposed to the first and second sides S1, S2 and the cut surfaces of the conductive patterns 221', 222' are included in the unit chip 210, and the second internal electrode pattern 222 exposed to the other side 4 in the second direction of the unit chip, the first and second sides S1, S2 are included in the unit chip 210; an arranging step (P3) of separating the unit chip 210 from the support film 310 and arranging the unit chip 210 so that the second side S2 of the unit chip 210 contacts the adhesive tape 320; and a first side margin forming step (P4) of attaching the first side S1 to a ceramic green sheet 140 for the side margin portion to form the first side margin portion 214.

[0028] [P1: Laminate production stage] As shown in FIG. 6, in the production step (P1) of the laminate 200, first, a plurality of ceramic green sheets 201, 202 having conductive patterns 221', 222' arranged thereon are laminated on a support film 310.

[0029] The support film 310 can serve to support the laminate 200 in which the conductive patterns 221' and 222' and the plurality of ceramic green sheets 201 and 202 are laminated. At this time, the support film 310 can contain adhesive substances such as Latex, starch, cellulose, protein, IR (Isoprene Rubber), NBR (Nitrile Butadiene Rubber), SBR (Styrene Butadiene Rubber), CR (Chloroprene Rubber), Silicon Rubber, Silicon-based, Urethane-based, Acryl-based, and mixtures thereof in order to effectively support and adhere the laminate 200.

[0030] The plurality of ceramic green sheets 201 and 202 can be formed of a ceramic paste containing ceramic powder, an organic solvent, a dispersant, and a binder. The above-mentioned ceramic powder can be a barium titanate-based material, a lead composite perovskite-based material, a strontium titanate-based material, etc. as a raw material for forming the dielectric layer 111 of the multilayer electronic component 100. The above-mentioned barium titanate-based material can contain BaTiO3-based ceramic powder. As an example of the above-mentioned ceramic powder, BaTiO3, (Ba 1-x Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1) or Ba(Ti 1-y Zr y )O3 (0 < y < 1), etc. can be mentioned. When the plurality of ceramic green sheets 201 and 202 are fired, they become the dielectric layer 111 constituting the main body 110.

[0031] Meanwhile, in an embodiment, the laminate 200 may further include a ceramic green sheet 203 for a cover portion forming the cover portions 112, 113. The ceramic green sheet 203 for a cover portion may be made of the same material and components as the ceramic green sheets 201, 202, but is not limited thereto, and may form the upper and lower cover portions 112, 113 of the body 110 through a firing process. At this time, the ceramic green sheet 203 for a cover portion may be formed on one surface and the other surface in the first direction of the laminate, and may be formed as a single layer or multiple layers.

[0032] The conductive patterns 221', 222' may be formed on the ceramic green sheets 201, 202 by an internal electrode paste containing a conductive metal. The conductive metal contained in the conductive patterns 221', 222' is not particularly limited, and any material having excellent electrical conductivity may be used. For example, the conductive metal may include one or more of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof. The method of forming the conductive patterns 221', 222' on the ceramic green sheets 201, 202 is not particularly limited. For example, the conductive patterns 221', 222' may be formed by screen printing or gravure printing the internal electrode conductive paste containing the conductive metal on the ceramic green sheets 201, 202.

[0033] The conductive patterns 221' and 222' may be stripe-shaped. Specifically, the internal electrode patterns may be formed to contact both ends of the ceramic green sheets 201 and 202 in the third direction at regular intervals in the second direction.

[0034] The conductive patterns 221', 222' may include a first conductive pattern 221' formed on a ceramic green sheet 201 and a second conductive pattern 222' formed on another ceramic green sheet 202. In this case, the ceramic green sheet on which the first conductive pattern 221' is formed may be referred to as the first ceramic green sheet 201, and the ceramic green sheet on which the second conductive pattern 222' is formed may be referred to as the second ceramic green sheet 202.

[0035] 6, a plurality of ceramic green sheets 201, 202 may be alternately laminated such that the first conductive pattern 221' and the second conductive pattern 222' are cross-laminated. Thus, when forming a unit chip 210 described later, the first conductive pattern 221' may form a first internal electrode pattern 221 exposed to the first side surface S1, the second side surface S2, and the third surface 3, and the second conductive pattern 222' may form a second internal electrode pattern 222 exposed to the first side surface S1, the second side surface S2, and the fourth surface 4. The first internal electrode pattern 221 may become the first internal electrode 121 after firing, and the second internal electrode pattern 222 may become the second internal electrode 122 after firing.

[0036] Meanwhile, in the present invention, for convenience of explanation, the direction in which the plurality of ceramic green sheets arranged on the support film 310 are stacked will be described as a first direction.

[0037] [P2: Laminate cutting stage] 7 to 9, with the direction in which the multiple ceramic green sheets are stacked based on the laminate 200 as a first direction, the laminate 200 is cut in a second direction perpendicular to the first direction and then cut in a third direction perpendicular to the first and second directions to obtain multiple unit chips 210, and the cut surfaces of the conductive patterns 221', 222' are cut so that the first internal electrode pattern 221 exposed to one surface 3 in the second direction of the unit chip 210 and the first and second side surfaces S1, S2 facing the third direction, the cut surfaces of the conductive patterns 221', 222' are cut so that the other surface 4 in the second direction of the unit chip, and the second internal electrode pattern 222 exposed to the first and second side surfaces S1, S2 are included in the unit chip 210.

[0038] 7, the laminate 200 may be cut along cutting lines C1-C1 and C2-C2 that are perpendicular to each other. The C1-C1 cutting lines are parallel to the second direction and are arranged at substantially equal intervals in the third direction, and the C2-C2 cutting lines are parallel to the third direction and are arranged at substantially equal intervals in the second direction. The C1-C1 cutting lines may form unit chips 210 having a substantially constant size in the third direction, and the C2-C2 cutting lines may form unit chips 210 having a substantially constant size in the second direction.

[0039] In particular, the C2-C2 cutting line is formed to cut the centers of the first and second conductive patterns 221', 222' in the second direction and the space between the first and second conductive patterns 221', 222' in the second direction, so that the first internal electrode pattern 221 of the unit chip 210 can be exposed to the first side S1, the second side S2, and the third side 3, which is one side in the second direction, and the second internal electrode pattern 222 can be exposed to the first side S1, the second side S2, and the fourth side 4, which is the other side in the second direction.

[0040] There is no particular limitation on the means for cutting the laminate 200. For example, the laminate 200 can be cut using a blade cutting method such as a doctor blade or a dicing blade, a guillotine cutting method, or a laser cutting method.

[0041] 8 and 9, it can be seen that immediately after performing the laminate cutting step (P2), the laminate 200 is formed of a plurality of unit chips 210. The plurality of unit chips 210 can be adhered to the support film 310 even after cutting due to the adhesiveness of the support film 310.

[0042] Although Figures 8 and 9 show the multiple unit chips 210 spaced apart from one another at regular intervals due to cutting, the multiple unit chips 210 may be substantially in contact with one another with weak adhesive force between them due to the viscosity of the multiple ceramic green sheets 201, 202 and the internal electrode patterns 221, 222.

[0043] However, this does not exclude the unit chips from being separated from each other, and they may be arranged to be partially separated by cutting means, but the size of the space between the unit chips may be narrower than the size that allows adjacent unit chips to rotate without touching each other.

[0044] 10, the first and second internal electrode patterns 221, 222 of the unit chips 210 according to an embodiment of the present invention are simultaneously exposed to first and second side surfaces S1, S2 facing each other of the unit chips 210. This maximizes the area in which the internal electrode patterns 221, 222 can be formed, thereby improving the capacitance per unit volume of the multilayer electronic component 100. However, the first and second side surfaces S1, S2 to which the first and second internal electrode patterns 221, 222 are simultaneously exposed are vulnerable to the penetration of external moisture, and if external electrodes, which will be described later, are formed extending to the first and second side surfaces S1, S2, a short circuit may occur.

[0045] In the first side margin portion forming step (P4) of one embodiment of the present invention described below, the ceramic green sheet for the side margin portion is attached to the first side S1 and punched to form the first side margin portion, thereby solving the above-mentioned moisture resistance reliability problem and the risk of short circuit occurrence.

[0046] 6 to 9, the laminate preparation step (P1) and the laminate cutting step (P2) are performed in a state where the support film 310 is disposed substantially horizontally to the ground, but the present invention is not limited thereto. That is, in one embodiment, the laminate preparation step (P1) and the laminate cutting step (P2) may be performed in a state where the support film 310 is disposed substantially vertically to the ground, and the adhesive tape 320 described below may be disposed substantially horizontally to the ground, and an arrangement step (P3) described below may be performed to open one of the first and second side surfaces S1 and S2.

[0047] [P3: Sequencing stage] Referring to FIG. 4, Patent Document 1, which is a comparative example, discloses a method for forming a ceramic protective layer 22 on a first cut side surface 20 of a plurality of green chips 19.

[0048] Specifically, in Patent Document 1, green chips 19 are placed on a support table 40 together with an adhesive sheet 38, and a rolling plate 41 is placed on the top surface of the green chips 19 (FIG. 4(a)). Thereafter, the support table 40 is moved in the direction of the arrow 42 relative to the rolling plate 41 to perform a tumbling process in which multiple green chips 19 are rotated 90 degrees at once (FIG. 4(b)).

[0049] Thereafter, the rolling plate 41 is removed, and the first cut side surfaces 20 of the green chips 19 are uniformly opened. Then, a ceramic green sheet 47 for a side surface is placed facing the opened first cut side surfaces 20, and the ceramic green sheet 47 for a side surface is placed on an elastic pad 48 for adhesion placed on a fixed table 49 (FIG. 4(c)). Next, an adhesive is applied to the ceramic green sheet 47 for a side surface or the opened first cut side surfaces 20, and the ceramic green sheet 47 for a side surface is pressed against the first cut side surfaces 20 of the green chips 19 to such an extent that the elastic pad 48 for adhesion is deformed (FIG. 4(d)). A punching process is performed in which a shear force acts on the ceramic green sheet 47 for a side surface and the ceramic green sheet 47 is punched out to the size of the first cut side surfaces 20 (FIG. 4(e)).

[0050] According to the above-mentioned Patent Document 1, in order to expose the cut side surfaces 20 of the plurality of green chips 19 upward, it is necessary to move the support table 40 in the direction of the arrow relative to the rolling operation plate 41, so that shear stress is generated in the plurality of green chips 19. In particular, in the process of rotating the green chip 19 around one corner as the rotation axis, excessive stress may be concentrated at the corner that becomes the rotation axis of the green chip 19. In particular, the green chip on which the ceramic protective layer 22 is formed undergoes a firing process at 900 to 1300°C, and the corner of the green chip 19 on which excessive stress is concentrated may be easily damaged by such thermal shock, and cracks may occur between the capacitance forming part of the main body and the cover part after firing, deteriorating the reliability of the multilayer electronic component.

[0051] In addition, the grip chip 19 of Patent Document 1 can be smoothly rotated if it contacts the support base 40 and the rolling plate 41 at the same time, but due to the dispersion of sizes of the multiple green chips 19, some of the multiple green chips 19 may not contact the support base 40 or the rolling plate 41. In this case, the green chips 19 that do not contact the support base 40 or the rolling plate 41 may not be rotated even after the rotation process, which may cause a problem that the ceramic protective layer 22 cannot be formed on the green chips 19.

[0052] FIG. 12 is a plan view generally illustrating an arrangement step according to an embodiment of the present invention.

[0053] In the arrangement step (P3) according to an embodiment of the present invention, after the unit chips 210 are separated from the support film 310, the unit chips are arranged such that the second side S2 of the unit chips contacts the adhesive tape 320.

[0054] Through this, when the unit chip 210 is separated from the support film 310, it can be separated without a specific rotation axis, so the phenomenon in which part of the unit chip 210 rotates while in contact with the support film 310 as disclosed in Patent Document 1 does not occur.

[0055] This makes it possible to prevent the occurrence of a phenomenon in which stress is concentrated at one corner of unit chip 210 due to rotation with part of unit chip 210 attached to support film 10. This makes it possible to suppress the occurrence of a phenomenon in which cracks are generated at the boundaries between capacitance forming portion Ac and cover portions 112, 113 when multilayer electronic component 100 is manufactured through the steps described below.

[0056] In addition, according to one embodiment of the present invention, when the unit chip 210 is separated from the support film 310 in the first direction, which is the direction in which the ceramic green sheets 201, 202 are stacked, there is no need to apply pressure to the exposed portions of the internal electrode patterns 221, 222, so damage to the first and second sides S1, S2 of the unit chip 210, which are vulnerable to moisture penetration, can be prevented.

[0057] In addition, since the unit chips 210 can be separated from the support film 310 without being rotated, it is possible to prevent adjacent unit chips 210 from sticking together and the unit chips 210 from being moved or rotated due to size dispersion.

[0058] That is, the method for manufacturing a multilayer electronic component according to one embodiment of the present invention includes an arrangement step (P3) of separating unit chips 210 from a support film 310 and then arranging the unit chips 210 so that the second side S2 of the unit chips 210 contacts the adhesive tape 320. This can prevent damage, non-movement, and non-rotation of the multiple unit chips 210 during the process of attaching the ceramic green sheet 140 for the side margin portion to the first side S1, thereby improving the manufacturing yield of the multilayer electronic component.

[0059] In one embodiment, the arrangement step (P3) may be performed by separating the unit chips 210 in a first direction, which is the direction in which the ceramic green sheets 201 and 202 are stacked, and then moving the unit chips 210 in a direction perpendicular to the separation direction so that the second side S2 of the unit chips 210 is arranged in contact with the adhesive tape 320.

[0060] As a result, the unit chips 210 do not rotate when they are separated from the support film 310, and also do not rotate during the process of moving and arranging the unit chips 210 on the adhesive tape 320.

[0061] From a similar perspective, in another embodiment of the present invention, after performing the laminate fabrication step (P1) and the laminate cutting step (P2), an arrangement step may be included in which the unit chips 210 are separated from the support film 310 without being rotated, and then the second side S2 of the unit chips 210 is arranged so as to contact the adhesive tape 320.

[0062] As a result, the unit chips 210 themselves do not rotate during the process of separating the unit chips 210 from the support film 310, thereby minimizing the phenomenon of stress concentrating on one corner of the unit chips 210 due to the rotation of the unit chips 210 or friction occurring between the unit chips 210 and the support film 310. As a result, it is possible to prevent the phenomenon that occurs in Patent Document 1, in which stress concentrates on one corner of the unit chips 210 when the unit chips 210 rotate while attached to the support film 10. As a result, it is possible to suppress the phenomenon that cracks occur at the boundaries between the capacitance forming portion Ac and the cover portions 112 and 113 when the multilayer electronic component 100 is manufactured through the process described below.

[0063] At this time, in the above arrangement process, the unit chips 210 separated from the support film 310 may be arranged so that the second side S2 contacts the adhesive tape 320 described below without being rotated. That is, according to one embodiment, the unit chips 210 do not need to be rotated at the moment when the unit chips 210 are separated from the support film 310, nor while the separated unit chips 210 are moved to be arranged on the adhesive tape 320. As a result, even when several unit chips 210 are moved simultaneously to be arranged on the adhesive tape 320, damage to the unit chips 210 due to rotation can be prevented and the process can be simplified.

[0064] Thereafter, the separated unit chips 210 are moved in a direction perpendicular to the first direction to arrange the second side 6 of the unit chips 210 in contact with the adhesive tape 320. Thus, the first side S1 of the unit chips 210 can be opened upward or downward without interference with the adjacent unit chips 210.

[0065] In the process of moving the separated unit chips 210 in a direction perpendicular to the first direction and arranging them on the adhesive tape 320, the arrangement of the unit chips 210 formed on the support film 310 may be different from the arrangement of the unit chips 210 formed on the adhesive tape 320. For example, the interval between the unit chips 210 formed on the adhesive tape 320 may be wider than the interval between the unit chips 210 formed on the support film 310. This can minimize interference between adjacent unit chips 210 when performing the first side margin portion forming step (P4) described below. In addition, since there is no need to perform a separate process for widening the interval between the unit chips 210, the method for manufacturing a multilayer electronic component can be simplified.

[0066] The method of moving unit chips 210 in a direction perpendicular to the first direction and arranging them so that second side surfaces 6 of unit chips 210 come into contact with adhesive tape 320 is not particularly limited.

[0067] 11 is a perspective view showing a support film rotating step according to an embodiment of the present invention. Referring to FIG. 11, in one embodiment, the method for manufacturing a multilayer electronic component may further include a support film rotating step of rotating the support film between the laminate cutting step (P2) and the arrangement step (P3). At this time, the laminate fabricating step (P1) and the laminate cutting step (P2) are performed in a state in which the support film 310 is arranged substantially parallel to the ground, and the support film rotating step may arrange the support film 310 substantially perpendicular to the ground. As a result, the support film 310 and the unit chips 210 are not separated, and the bar 300 is rotated as a whole, so that the first side S1 or the second side S2 may be aligned in a direction looking at the adhesive tape 320 described below without damaging the unit chips 210.

[0068] Meanwhile, immediately after the laminate cutting step (P1), the intervals between the unit chips 210 may be so narrow that they may be said to be in a substantially contacting state as described above. In this case, if the method for manufacturing a multilayer electronic component according to an embodiment further includes the support film rotating step immediately after the laminate cutting step (P2), the separation distances between the unit chips may be substantially the same during the support film rotating step immediately after the laminate cutting step (P1). As a result, when the unit chips 210 are simultaneously separated into several pieces in the arranging step (P3), the phenomenon in which the unit chips 210 are not separated and remain on the support film 310 can be reduced.

[0069] However, the support film rotating step is not an essential element of the present invention, and even if the adhesive tape 320 described below is arranged perpendicular to the support film 310 without the support film rotating step, the first side S1 or the second side S2 can be aligned in the direction of looking at the adhesive tape 320.

[0070] In addition, the support film rotating step does not necessarily have to be performed between the laminate cutting step (P2) and the arrangement step (P3). For example, the method for manufacturing a multilayer electronic component according to an embodiment may further include a support film rotating step of rotating the support film 310 between the laminate fabricating step (P1) and the laminate cutting step (P2).

[0071] Meanwhile, the rotation in the above-mentioned support film 310 rotating step is performed by rotating the support film 310 90 degrees in a clockwise or counterclockwise direction based on the initial support film 310, so that the support film 310 and the adhesive tape 320 described later can be arranged vertically, but is not limited thereto.

[0072] Meanwhile, in the process of moving the separated unit chips 210 in a direction perpendicular to the first direction and arranging the adhesive tape 320 so as to contact the second side S2 of the unit chips 210, the position of the adhesive tape 320 is not particularly limited. However, in order to simplify the process and more effectively prevent the unit chips 210 from rotating, the position of the adhesive tape 320 may be adjusted to be close to the second side S2 of the unit chips 210. That is, in one embodiment, the arranging step (P3) may be a step of arranging the unit chips 210 in the first direction, and then arranging the unit chips 210 so that the second side S2 of the unit chips 210 contacts the adhesive tape 320 arranged parallel to the first and second sides S1 and S2 of the unit chips 210 and arranged close to the second side S2 of the first and second sides S1 and S2.

[0073] As described above, the tumbling process disclosed in Patent Document 1 is a process in which the green chip 19 rotates around one corner as a rotation axis. During this process, a problem occurs in that excessive stress is concentrated at the corner of the green chip 19 that contacts the adhesive sheet 38 or the rolling plate 41.

[0074] However, in one embodiment, the unit chip 210 may be separated from the support film 310 so that the unit chip 210 is completely separated from the support film 310. In this way, the first or second side surface S1 or S2 of the unit chip 210 can be opened without a process of rotating the unit chip 210 while one corner of the unit chip 210 is in contact with the support film 310, so that the phenomenon of stress concentration at one corner of the unit chip 210 can be suppressed.

[0075] Hereinafter, a specific method for arranging a plurality of unit chips 210 on the adhesive tape 320 in the arranging step (P3) will be described.

[0076] 15 to 16b, the unit chips 210 may be arranged in row (i1, i2, i3, i4, i5, i6,...) and column (j1, j2, j3, j4, j5, j6,...) directions immediately after the laminate cutting step (P2). The arrangement of the unit chips 210 arranged on the support film 310 immediately after the laminate cutting step (P2) may be different from the arrangement of the unit chips 210 arranged on the adhesive tape 320 immediately after the arrangement step (P3). The different arrangement may mean that the distance between the unit chips 210 is different before and after the arrangement step (P3) and that the exposed surfaces of the unit chips 210 are different before and after the arrangement step (P3).

[0077] FIG. 15 is a perspective view that illustrates a schematic arrangement step according to an embodiment.

[0078] Referring to FIG. 15, the arrangement step (P3) according to one embodiment may be a step of separating unit chips 210 arranged in even columns of the same row from unit chips 210 arranged in odd columns of the same row and arranging them on an adhesive tape 320.

[0079] For example, the arranging step (P3) may be a step of first separating unit chips 210 arranged in even-numbered columns j2, j4, j6,..., of the same row, i6, and arranging them on adhesive tape 320, and then separately separating unit chips 210 arranged in odd-numbered columns i1, i3, i5,..., of the same row, i6, and arranging them on adhesive tape 320. The same row may refer to all rows forming an array of a plurality of unit chips 210, and there is no particular restriction on the order of the procedure of separating unit chips 210 arranged in an even-numbered column of the same row from unit chips 210 arranged in an odd-numbered column of the same row.

[0080] 16a and 16b are perspective views that are schematic diagrams illustrating an arrangement step according to one embodiment.

[0081] 16a, the arranging step (P3) according to an embodiment may be a step of simultaneously separating the unit chips 210 arranged in one row and arranging them on an adhesive tape 320. As shown in FIG.

[0082] For example, the arranging step (P3) may be a step of simultaneously separating unit chips 210 arranged in one row, i1 row, and arranging them on adhesive tape 320. That is, the step of separating all unit chips 210 arranged in one row, i1 row, and arranging them on adhesive tape 320, and then separating all unit chips 210 arranged in any one row among the remaining rows and arranging them on adhesive tape 320 may be repeated.

[0083] When all the unit chips 210 arranged on the support film 310 are arranged on the adhesive tape 320 by this method, the interval between the unit chips 210 belonging to one row may not be suitable for performing the first side margin forming step (P4) described below. For example, when the unit chips arranged in i1 rows are simultaneously separated and arranged on the adhesive tape 320, the interval between the unit chips 210 originating from the i1 row arranged on the adhesive tape 320 may be substantially the same as the interval between the unit chips 210 arranged on the support film 310. Therefore, when performing the first side margin forming step (P4) described below, the interval between adjacent unit chips 210 is not sufficient, which may cause a problem that punching cannot be performed smoothly, and interference may occur between adjacent unit chips 210.

[0084] 16b, the arranging step according to an embodiment may be a step of pulling the adhesive tape 320 on which the unit chips 210 arranged in one row are arranged in the column direction to separate the unit chips 210 arranged in one row from each other, thereby ensuring a sufficient separation distance between the unit chips 210 arranged on the adhesive tape 320.

[0085] [P4: First side margin formation stage] According to an embodiment of the present invention, a method for manufacturing a multilayer electronic component includes a first side margin forming step (P4) of forming a first side margin portion 214 by attaching a first side surface to the ceramic green sheet for the side margin portion after the arranging step (P3).

[0086] Hereinafter, with reference to Figures 13, 14 and 17, the first side margin portion forming step (P4) will be described based on the case where the first side S1 of the unit chip 210 is opened, but it can also be applied to the case where the second side S2 is opened.

[0087] The ceramic green sheet 140 for the side margin portion may be formed of a ceramic paste including a ceramic powder including a barium titanate-based material, a lead complex perovskite-based material, or a strontium titanate-based material, an organic solvent, a dispersant, and a binder, like the above-mentioned ceramic green sheets 201 and 202. However, the composition of the ceramic green sheet 140 for the side margin portion does not necessarily have to be the same as that of the above-mentioned ceramic green sheets 201 and 202, and may have a different composition. As a result, the margin portions 114 and 115 after firing may have a different average dielectric particle size, density, or hardness from that of the dielectric layer 111.

[0088] The method of attaching the ceramic green sheet 140 for the side margin portion to the first side S1 of the unit chip 210 is not particularly limited. For example, the elastic pad 360 may be used to apply pressure. Specifically, referring to FIG. 13, the upper support 330 may be disposed on one side of the adhesive tape 320 on which the unit chips 210 are not disposed, and the elastic pad 360 and the ceramic green sheet 140 for the side margin portion may be laminated in order on the lower support 340, and the ceramic green sheet 140 for the side margin portion may be attached to the first side S1 by applying pressure. At this time, in one embodiment, the ceramic green sheet 140 for the side margin portion may be attached to the first side S1 at a temperature of 50 to 150° C. to prevent the ceramic green sheet 140 for the side margin portion from being deformed or cracked.

[0089] The method of forming the side margin portion 214 from the side margin portion ceramic green sheet 140 attached to the first side surface S1 of the unit chip 210 is not particularly limited.

[0090] For example, after attaching the ceramic green sheet 140 for the side margin portion, pressure is applied to the ceramic green sheet 140 for the side margin portion so that the elastic pad 360 is elastically deformed, and punching is performed to cut the ceramic green sheet 140 for the side margin portion to a portion corresponding to the first side surface S1. By punching in this manner, the ceramic green sheet 140 for the side margin portion can be cut to a portion corresponding to the first side surface S1 to form the first side margin portion 214. The first side margin portion 214 can later be subjected to a firing process to form the margin portion 114 of the multilayer electronic component.

[0091] In one embodiment, in the first side margin portion forming step (P4), the attachment and punching of the ceramic green sheet 140 for the side margin portion may be performed in a state in which the ceramic green sheet 140 for the side margin portion is attached to the carrier film 350. This prevents the ceramic green sheet 140 for the side margin portion from drying rapidly and ensures sufficient adhesive strength for the ceramic green sheet 140 for the side margin portion to be attached to the first side surface S1 without applying a separate adhesive to the first side surface S1 or the ceramic green sheet 140 for the side margin portion. That is, in one embodiment, the surface of the ceramic green sheet 140 for the side margin portion that contacts the first side surface S1 may not be coated with an adhesive component.

[0092] In one embodiment, the side margin ceramic green sheet 140 can be prevented from drying out too quickly, so punching can be performed at a temperature of 50° C. or less. This eliminates the need to maintain a high temperature to form the side margin, and reduces damage to the unit chips 210 or the side margin ceramic green sheet 140 caused by thermal shock.

[0093] Meanwhile, the components of the carrier film 350 are not particularly limited. In one embodiment, the carrier film 350 may include PET (polyethylene terephthalate), PO (polyolefin), PP (polypropylene), and silicone (Si). This can effectively prevent the side margin ceramic green sheet 140 attached to the carrier film 350 from drying rapidly. In addition, the thickness of the carrier film 350 is not particularly limited, but is preferably 10 μm or more for proper formation of the side margin, and is preferably 30 μm or less for easy punching of the side margin ceramic green sheet.

[0094] According to one embodiment, the method for manufacturing a multilayer electronic component may further include, after the first side margin portion forming step (P4), a second side margin portion forming step of attaching and punching a second side surface S2 of the unit chip 210 to the ceramic green sheet 140 for the side margin portion to form a second side margin portion 215.

[0095] The second side margin portion forming step may be performed in the same process as the first side margin portion forming step (P4), except that the ceramic green sheet 140 for the side margin portion is attached and punched on the second side surface S2 of the unit chip 210.

[0096] Specifically, after the first side margin forming step (P4), the cut ceramic green sheet 140 for the side margin except for the first side margin 214 may be removed, and the carrier film 350, the elastic pad 360, and the lower support 340 may be removed. Thereafter, another adhesive tape may be attached to the surface on which the first side margin 214 is formed, and then the existing adhesive tape 320 and the upper support 330 may be removed to open the second side surface S2 of the unit chip 210. By applying the first side margin forming step (P4) to the second side surface S2 thus opened, the unit chip 210 having the first and second side margins 214 and 215 may be formed.

[0097] Meanwhile, in the first and second side margin portion forming steps, the ceramic green sheet for the side margin portion is punched with the carrier film attached thereto, so that the second side margin portion forming step is performed, and after the body forming step and the external electrode forming step described below are performed, the margin portions 114 and 115 may be arranged in a form surrounding the body 110. That is, the margin portions 114 and 115 may be arranged to extend to parts of the third and fourth surfaces 3 and 4 of the body 110, or may be arranged to cover corners of the body 110. As a result, it is possible to improve the moisture resistance reliability of the multilayer electronic component 100 by blocking the penetration of external moisture.

[0098] Similarly, in the step of forming the first and second side margins, the ceramic green sheet for the side margins is punched with the carrier film attached, so that the corners of the first and second side margins can be curved, which has the advantage that there is no need to separately polish the corners of the laminated chip 210 before firing.

[0099] The method for manufacturing a multilayer electronic component according to an embodiment may include a body forming step of firing the unit chip 210 having the first and second side margin portions 214 and 215 formed thereon after the second side margin portion forming step. The firing temperature is not particularly limited, but may be, for example, 1000 to 1300° C. Also, the firing may be performed in a reducing atmosphere.

[0100] Thereafter, the external electrodes 131 and 132 are formed on the third and fourth surfaces 3 and 4 of the body 110, respectively, so that the multilayer electronic component 100 can be manufactured.

[0101] Meanwhile, the unit chip 210 having the first and second side margin portions 214, 215 formed thereon can be fired without any additional process to form the main body 110, but is not limited thereto. A conductive paste containing a metal having excellent electrical conductivity can be disposed on the third and fourth surfaces 3, 4, respectively, and fired simultaneously with the main body 110 to form the external electrodes 131, 132, thereby manufacturing the multilayer electronic component 100.

[0102] FIG. 18 is a cross-sectional view taken along line III-III' of FIG. 17, and roughly illustrates cross-sections taken along the second and third directions of the unit chip 210 to which the first and second side margin portions 214 and 215 are attached.

[0103] FIG. 19 is a cross-sectional view taken along line IV-IV' of FIG. 1, and generally illustrates cross-sectional views in the second and third directions of the multilayer electronic component 100 according to one embodiment of the present invention.

[0104] 18, first and second side margin portions are disposed on the first side surface S1 and the second side surface S2 of the unit chip 210. At this time, the ceramic green sheet 140 for the side margin portions is punched while being disposed on the above-mentioned carrier film 350, so that the first and second side margin portions 214 and 215 can be disposed extending from the first and second side surfaces S1 and S2 of the unit chip 210 to a part of at least one of the first to fourth surfaces 1, 2, 3, and 4.

[0105] Meanwhile, in one embodiment, when the average value of the vertical distance between the extension line E3 of the third surface of the unit chip 210 and the second direction ends of the first and second side margin portions 214, 215 adjacent to the third surface is defined as d1, and the average value of the vertical distance between the extension line ES1 of the first side surface of the unit chip 210 and the ends of the first and second side margin portions 214, 215 contacting the third surface 3 or the fourth surface 4 is defined as d2, d1 / d2 may satisfy a value greater than 0.4 and less than 0.8.

[0106] 19, a first margin portion 114 is disposed on a first side surface S1 of a body 110 of a multilayer electronic component 100, and a second margin portion 115 is disposed on a second side surface S2. The first and second margin portions 114, 115 may be formed by firing the first and second side margin portions 214, 215 of FIG. 18. Meanwhile, the values ​​of d1 and d2 of FIG. 18 may change as a result of a firing process for manufacturing the multilayer electronic component 100. That is, in one embodiment, when the average value of the vertical distance between the extension line E3' of the third surface of the main body 110 and the end adjacent to the third surface in the second direction of the first and second margin portions 114, 115 is d1', and the average value of the vertical distance between the extension line ES1' of the first side surface of the main body 110 and the end where the first and second margin portions 114, 115 contact the third surface 3 or the fourth surface 4 is d2', d1' / d2' may be greater than 0.3 and less than 0.6. When the d1' / d2' is greater than 0.3 and less than 0.6, the margin portions 114, 115 are arranged in a form that sufficiently surrounds the main body 110, thereby blocking the penetration of external moisture, thereby improving the reliability of the multilayer electronic component 100.

[0107] On the other hand, d1, d2, d1', and d2', which represent the average values ​​of the vertical distances, can be measured as follows.

[0108] d1 and d2 may correspond to values ​​measured in the unit chip 210. The cross sections in the second and third directions of the unit chip 210 before firing may be polished so that the internal electrode pattern is not exposed, and the cross sections may be observed and measured using an optical microscope (OM) or a scanning electron microscope (SEM). In this case, the cross sections in the second and third directions may be selected from 10 cross sections obtained by polishing the cover part at equal intervals in the first direction, and the values ​​of d1 and d2 measured in each cross section may be averaged to further generalize the values.

[0109] d1' and d2' may correspond to values ​​measured in the main body 110. The cross sections in the second and third directions of the multilayer electronic component 100 may be polished so that the internal electrode patterns are not exposed, and the cross sections may be observed and measured using an optical microscope (OM) or a scanning electron microscope (SEM). In this case, the cross sections in the second and third directions may be selected from 10 cross sections obtained by polishing the cover part at equal intervals in the first direction, and the values ​​of d1' and d2' measured in each cross section may be averaged to further generalize the values.

[0110] FIG. 1 is a schematic perspective view of a multilayer electronic component 100 that can be manufactured by a method for manufacturing a multilayer electronic component according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along line II' of FIG. 1, and FIG. 3 is a cross-sectional view taken along line II' of FIG. 1.

[0111] Hereinafter, a multilayer electronic component 100 that can be manufactured by a manufacturing method according to an embodiment of the present invention will be described with reference to Figures 1 to 3. However, the multilayer electronic component 100 is not limited to the first to third forms, and the form and number of the internal electrodes and external electrodes can vary depending on the mounting position or application.

[0112] The multilayer electronic component 100 may include a body 110 including a dielectric layer 111 and first and second internal electrodes 121, 122 arranged alternately on either side of the dielectric layer, and external electrodes 131, 132 arranged on the body 110.

[0113] The main body 110 has a dielectric layer 111 and internal electrodes 121 and 122 laminated alternately.

[0114] There is no particular limitation on the specific shape of the main body 110. As shown in the figure, the main body 110 can be formed in a hexahedron shape or a shape similar thereto. Due to the shrinkage of the ceramic powder contained in the main body 110 during the firing process, the main body 110 can have a substantially hexahedron shape although it does not have a hexahedron shape with perfect straight lines.

[0115] The main body 110 can have a first and a first surface 1 and 2 facing each other in a first direction, a third and a fourth surface 3 and 4 facing each other in a second direction and connected to the first and second surfaces 1 and 2, and a first and a second side surface S1 and S2 facing each other in a third direction and connected to the first to fourth surfaces.

[0116] The plurality of dielectric layers 111 forming the main body 110 are in a fired state, and the boundary between adjacent dielectric layers 111 can be integrated so as to be difficult to confirm without using a scanning electron microscope (SEM).

[0117] According to an embodiment of the present invention, the raw material for forming the dielectric layer 111 is not particularly limited as long as sufficient capacitance can be obtained. For example, a barium titanate-based material, a lead composite perovskite-based material, or a strontium titanate-based material can be used. The barium titanate-based material can include BaTiO3-based ceramic powder. As an example of the ceramic powder, BaTiO3, (Ba 1-x Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1), or Ba(Ti 1-y Zry ) Examples include O3 (0 < y < 1).

[0118] In addition, various ceramic additives, organic solvents, binders, dispersants, etc. can be added to the raw materials for forming the dielectric layer 111 according to the purpose of the present invention, such as powders of barium titanate (BaTiO3).

[0119] The main body 110 includes a capacitance forming portion Ac that is disposed inside the main body 110 and includes a first internal electrode 121 and a second internal electrode 122 that are alternately disposed with the dielectric layer 111 interposed therebetween to form a capacitance, and cover portions 112 and 113 formed on the upper and lower portions of the capacitance forming portion Ac in the first direction.

[0120] In addition, the capacitance forming portion Ac is a portion that contributes to the formation of the capacitance of the capacitor, and can be formed by repeatedly laminating a plurality of first and second internal electrodes 121 and 122 with the dielectric layer 111 interposed therebetween.

[0121] The cover portions 112 and 113 can include an upper cover portion 112 disposed on the upper portion of the capacitance forming portion Ac in the first direction, and a lower cover portion 113 disposed on the lower portion of the capacitance forming portion Ac in the first direction.

[0122] The upper cover portion 112 and the lower cover portion 113 can be formed by laminating a single dielectric layer or two or more dielectric layers in the thickness direction on the upper and lower surfaces of the capacitance forming portion Ac, respectively, and can basically serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0123] The upper cover portion 112 and the lower cover portion 113 do not include internal electrodes and can include the same material as the dielectric layer 111.

[0124] That is, the upper cover portion 112 and the lower cover portion 113 can include a ceramic material, for example, can include a barium titanate (BaTiO3)-based ceramic material.

[0125] Moreover, margin portions 114 and 115 can be disposed on the side surfaces of the capacitance forming portion Ac.

[0126] The margin portions 114, 115 may include a margin portion 114 disposed on a first side surface S1 of the body 110 and a margin portion 115 disposed on a second side surface S2 of the body 110. That is, the margin portions 114, 115 may be disposed on both end surfaces of the body 110 in a third direction.

[0127] The margin portions 114, 115 may refer to the regions between both ends of the first and second internal electrodes 121, 122 and the boundary surface of the body 110 in a cross-section of the body 110 cut in the width-thickness (WT) direction, as shown in FIG. 3.

[0128] The margins 114 and 115 basically serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0129] According to one embodiment of the present invention, in order to suppress steps caused by the internal electrodes 121 and 122, after lamination, the internal electrodes are cut so as to be exposed to the first and second side surfaces S1 and S2 of the body, and then a single dielectric layer or two or more dielectric layers can be laminated in the third direction on both side surfaces of the capacitance forming portion Ac to form margin portions 114 and 115.

[0130] The width of the margin parts 114 and 115 is not particularly limited. However, in order to more easily achieve miniaturization and volumetric capacity of the multilayer electronic component, the average thickness of the margin parts 114 and 115 may be 30 μm or less. In addition, according to an embodiment of the present invention, the method includes the steps of separating the unit chips from the support film in the direction in which the ceramic green sheets are laminated, and then moving the unit chips in a direction perpendicular to the separation direction to arrange the second sides of the unit chips in contact with the adhesive tape, thereby manufacturing a multilayer electronic component with improved reliability. Therefore, even when the average thickness of the margin parts 114 and 115 is 30 μm or less, excellent reliability can be ensured.

[0131] The average width of the margin portions 114, 115 may mean the average size of the margin portions 114, 115 in the third direction, and may be the average value of the sizes of the margin portions 114, 115 in the third direction measured at five equally spaced points on the side of the capacitance forming portion Ac.

[0132] The multiple internal electrodes 121, 122 can be arranged alternately with the dielectric layer 111 in between.

[0133] The plurality of internal electrodes 121, 122 may include first and second internal electrodes 121, 122. The first and second internal electrodes 121, 122 may be alternately arranged to face each other with the dielectric layer 111 constituting the body 110 interposed therebetween, and may be connected to third and fourth surfaces 3, 4 of the body 110, respectively.

[0134] Specifically, one end of the first internal electrode 121 may be connected to the third surface 3 , and one end of the second internal electrode 122 may be connected to the fourth surface 4 .

[0135] The first internal electrode 121 may be spaced apart from the fourth surface 4 and exposed through the third surface 3, and the second internal electrode 122 may be spaced apart from the third surface 3 and exposed through the fourth surface 4. A first external electrode 131 may be disposed on the third surface 3 of the body and connected to the first internal electrode 121, and a second external electrode 132 may be disposed on the fourth surface 4 of the body and connected to the second internal electrode 122.

[0136] That is, the first internal electrode 121 is connected to the first external electrode 131 but not to the second external electrode 132, and the second internal electrode 122 is connected to the second external electrode 132 but not to the first external electrode 131. Thus, the first internal electrodes 121 may be formed at a certain distance apart on the fourth surface 4, and the second internal electrodes 122 may be formed at a certain distance apart on the third surface 3.

[0137] At this time, the first and second internal electrodes 121 and 122 may be electrically isolated from each other by the dielectric layer 111 disposed therebetween.

[0138] The body 110 may be formed by alternately stacking the ceramic green sheets 201 on which the first internal electrode patterns 221 are printed and the ceramic green sheets 202 on which the second internal electrode patterns 222 are printed, and then firing the stacked ceramic green sheets.

[0139] There are no particular limitations on the material forming the internal electrodes 121 and 122, and any material having excellent electrical conductivity can be used. For example, the internal electrodes 121 and 122 can include one or more of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

[0140] The internal electrodes 121 and 122 may be formed by printing a conductive paste for internal electrodes, including at least one of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof, on the ceramic green sheet. The method for printing the conductive paste for internal electrodes may be a screen printing method or a gravure printing method, but the present invention is not limited thereto.

[0141] The external electrodes 131 and 132 are disposed on the third surface 3 and the fourth surface 4 of the body 110, respectively, and the first external electrode 131 may be electrically connected to the first internal electrode 121, and the second external electrode 132 may be electrically connected to the second internal electrode 122.

[0142] In this embodiment, the multilayer electronic component 100 has a structure including two external electrodes 131 and 132. However, the number and shapes of the external electrodes 131 and 132 may be changed according to the shape of the internal electrodes 121 and 122 and other purposes.

[0143] Meanwhile, the external electrodes 131 and 132 may be formed using any material having electrical conductivity, such as a metal, and the specific material may be determined in consideration of electrical characteristics, structural stability, etc., and may further have a multi-layer structure.

[0144] For example, the external electrodes 131 and 132 may include an electrode layer disposed on the surface of the body 110 and in direct contact with the internal electrodes 121 and 122, and a plating layer formed on the electrode layer.

[0145] More specifically, the electrode layer may be a fired electrode containing a conductive metal and glass, or a resin-based electrode containing a conductive metal and resin.

[0146] The electrode layer may be formed by sequentially forming a fired electrode and a resin-based electrode on the main body, and may be formed by transferring a sheet containing a conductive metal onto the main body, or by transferring a sheet containing a conductive metal onto the fired electrode.

[0147] The conductive metal contained in the electrode layer may be a material having excellent electrical conductivity, and is not particularly limited. For example, the conductive metal may be one or more of nickel (Ni), copper (Cu), and alloys thereof.

[0148] The plating layer serves to improve mounting characteristics. The type of plating layer is not particularly limited, and may be a plating layer containing one or more of Ni, Sn, Pd, and alloys thereof, and may be formed of a plurality of layers.

[0149] More specifically, the plating layer may be a Ni plating layer or a Sn plating layer, and may be a form in which a Ni plating layer and a Sn plating layer are sequentially formed on an electrode layer, or a form in which a Sn plating layer, a Ni plating layer and a Sn plating layer are sequentially formed. Also, the plating layer may include a plurality of Ni plating layers and / or a plurality of Sn plating layers.

[0150] (Embodiment) A laminate was fabricated on a support film using dielectric ceramic green sheets made of BaTiO3 powder and minor components and a conductive pattern made of Ni powder, and then the laminate was cut in a second direction perpendicular to the first direction, with the direction in which the ceramic green sheets were stacked being defined as a first direction, and then cut in a third direction perpendicular to the second direction to form a plurality of unit chips. In the cutting process, the unit chips were cut so that a first internal electrode pattern in which the cut surface of the conductive pattern is exposed to one surface, first and second sides in the second direction of the unit chip, and a second internal electrode pattern in which the cut surface of the conductive pattern is exposed to the other surface, first and second sides in the second direction of the unit chip, were included in the unit chip.

[0151] Thereafter, the unit chips were separated from the support film and then arranged so that the second side of each chip was in contact with the adhesive tape.

[0152] Thereafter, the first side surface was attached to a ceramic green sheet for a side margin portion, which was made of BaTiO3 powder and auxiliary components, to form a first side margin portion, and a second side margin portion was formed in the same manner.

[0153] Thereafter, the unit chip having the first and second side margin portions formed thereon was fired under conditions of a firing temperature of 1300°C or less and a hydrogen concentration of 2.0% H2 or less to form a main body, and a conductive paste was applied onto the main body to form external electrodes, thereby forming a sample of a multilayer electronic component according to an embodiment.

[0154] (Comparative Example) A laminate was fabricated on a support film using dielectric ceramic green sheets made of BaTiO3 powder and minor components and a conductive pattern made of Ni powder, and then the laminate was cut in a second direction perpendicular to the first direction, with the direction in which the ceramic green sheets were stacked being defined as a first direction, and then cut in a third direction perpendicular to the second direction to form a plurality of unit chips. In the cutting process, the unit chips were cut so that a first internal electrode pattern in which the cut surface of the conductive pattern is exposed to one surface, first and second sides in the second direction of the unit chip, and a second internal electrode pattern in which the cut surface of the conductive pattern is exposed to the other surface, first and second sides in the second direction of the unit chip, were included in the unit chip.

[0155] Then, as disclosed in Patent Document 1, a tumbling process was performed in which a rolling plate was placed on the top surface of the unit chips, and the support film and the rolling plate were moved in parallel in opposite directions to rotate multiple unit chips 90 degrees at once.

[0156] Thereafter, the first side surface was attached to a ceramic green sheet for a side margin portion, which was made of BaTiO3 powder and auxiliary components, to form a first side margin portion, and a second side margin portion was formed in the same manner.

[0157] Thereafter, the unit chip having the first and second side margin portions formed thereon was fired at a firing temperature of 1300°C or less and a hydrogen concentration of 2.0% H2 or less to form a main body, and a conductive paste was applied onto the main body to form external electrodes, thereby forming a sample of a multilayer electronic component according to the comparative example.

[0158] Table 1 below was created by evaluating whether or not cracks occurred at the boundary between the capacitance forming portion and the cover portion in the multilayer electronic components manufactured according to the examples and the multilayer electronic components manufactured according to the comparative examples.

[0159] Meanwhile, a group of unit chips manufactured in one run of the manufacturing method for multilayer electronic components is defined as 1 lot, and in Table 1 below, approximately 1,000,000 or more unit chips were manufactured per lot.

[0160] In the following Table 1, 50 samples of multilayer electronic components were randomly selected for each lot of the multilayer electronic components manufactured according to the examples and comparative examples.

[0161] Thereafter, the assembled samples were molded and then polished to the center point in the third direction of the first and second directional surfaces and the center point in the second direction of the first and third directional surfaces. The boundaries between the cover portion and the capacitance forming portion on the first and second directional surfaces and the first and third directional surfaces were then observed with an optical microscope (OM) at a magnification of 25 to 100 times, and any cracks observed were judged to be defective.

[0162] [Table 1]

[0163] Referring to Table 1, it can be seen that the multilayer electronic component according to the comparative example including the rolling process according to Patent Document 1 had a crack occurrence rate of 2000 PPM for a total of 20 lots.

[0164] In addition, it can be confirmed that the multilayer electronic component according to the embodiment including the arrangement step (P3) according to one embodiment of the present invention instead of the rolling process according to Patent Document 1 had a crack occurrence rate of only 370 PPM in a total of 27 lots.

[0165] Therefore, according to Table 1, an embodiment including the arrangement step (P3) according to one embodiment of the present invention instead of the rolling process of Patent Document 1 can suppress damage caused to the corners of the unit chips due to the tumbling process of Patent Document 1, and can suppress the phenomenon of cracks occurring at the boundary between the capacitance forming portion and the cover portion of the completed multilayer electronic component, thereby improving the reliability of the multilayer electronic component.

[0166] Table 2 below shows the evaluation results of the composite reliability of the multilayer electronic components manufactured according to the embodiment and the multilayer electronic components manufactured according to the comparative example.

[0167] In Table 2, 20 samples were randomly selected from each of the multilayer electronic components manufactured according to the examples and comparative examples, and a composite reliability test was carried out under the following conditions: 40°C, 4.8V for 1 hour (section 1), 85°C, 4.8V for 1 hour (section 2), and 85°C, 2.8V, 65% relative humidity for 2 hours (section 3). Samples with insulation resistance (IR) values ​​of the multilayer electronic components below 1.0E^+05 for each section were evaluated as defective, and the rest were evaluated as normal. Meanwhile, sections 1 to 3 in the composite reliability test were carried out continuously.

[0168] [Table 2]

[0169] Referring to Table 2, it can be seen that, for the multilayer electronic components manufactured according to the comparative example, two defective products were generated in which the insulation resistance value fell to below the initial value of 1.0E^+05 after proceeding through sections 1 to 3, whereas, for the multilayer electronic components manufactured according to the examples, no samples had an insulation resistance value that fell to below the initial value of 1.0E^+05 after proceeding through sections 1 to 3. In addition, for the multilayer electronic components manufactured according to the examples, no samples had an insulation resistance value that fell by an order of 1.0E^+02 or more in section 1.

[0170] Therefore, according to Table 2, the embodiment including the arrangement step (P3) according to one embodiment of the present invention instead of the rolling process according to Patent Document 1 can prevent a decrease in insulation resistance of the multilayer electronic component in a hot and humid environment by suppressing the phenomenon in which stress is concentrated and damaged at one corner of the unit chip, thereby improving the reliability of the multilayer electronic component.

[0171] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments and the accompanying drawings, but is limited by the scope of the accompanying claims. Therefore, various substitutions, modifications and changes can be made by a person having ordinary knowledge in the art within the scope of the technical idea of ​​the present invention described in the claims, and these also belong to the scope of the present invention.

[0172] In addition, the expression "one embodiment" used in the present invention does not mean the same embodiment, but is provided to emphasize and describe each unique feature different from each other. However, the above-presented one embodiment does not exclude being realized in combination with the features of another embodiment. For example, even if a matter described in a specific embodiment is not described in another embodiment, it can be understood as a description related to the other embodiment, unless there is a description that is opposite or contradictory to the matter in the other embodiment.

[0173] The terms used in the present invention are merely used to describe one embodiment and are not intended to limit the present invention. In this case, a singular expression includes a plural expression unless a clearly different expression is used in the context. [Explanation of symbols]

[0174] 100: Multilayer electronic components 110: Main unit 111: Dielectric layer 112, 113: Cover part 114, 115: Margin 121, 122: Internal electrode 131, 132: External electrode 140: Ceramic green sheet for side margin 200: Laminate 201, 202: Ceramic green sheet 203: Ceramic green sheet for cover 210: Unit chip 214, 215: Side margin 221, 222: Internal electrode pattern 221', 222': Conductive patterns 310: Support film 320: Adhesive tape 330, 340: Support stand 350: Carrier film 360: Elastic pad

Claims

1. The process involves a laminate manufacturing stage in which multiple ceramic green sheets, each with a conductive pattern arranged on a support film, are stacked to create a laminate, When the direction in which the plurality of ceramic green sheets are stacked is defined as the first direction with respect to the laminate, the laminate is cut in a second direction perpendicular to the first direction, and in a third direction perpendicular to the first and second directions to obtain a plurality of unit chips, and the laminate is cut such that the unit chip contains a first internal electrode pattern whose cut surface of the conductive pattern is exposed on one face in the second direction of the unit chip, a first side and a second side facing the third direction, and a second internal electrode pattern whose cut surface of the conductive pattern is exposed on the other face in the second direction of the unit chip, a first side and a second side. After separating the unit chip from the support film in the first direction, the unit chip is moved in the third direction and arranged so that its second side contacts the adhesive tape positioned closer to the second side of the first side and the second side of the unit chip. A method for manufacturing a stacked electronic component, comprising: a first side margin forming step of attaching the first side surface to a ceramic green sheet for the side margin to form the first side margin.

2. The method for manufacturing a stacked electronic component according to claim 1, wherein the separation is performed such that all surfaces of the unit chip are separated from the support film.

3. A method for manufacturing a laminated electronic component according to claim 1 or 2, further comprising a support film rotation step of rotating the support film between the laminate cutting step and the arrangement step.

4. The method for manufacturing a laminated electronic component according to claim 3, wherein the laminate manufacturing step and the laminate cutting step are performed with the support film positioned substantially parallel to the ground, and the support film rotation step is performed so that the support film is positioned substantially perpendicular to the ground.

5. The method for manufacturing a laminated electronic component according to claim 3, wherein immediately after the laminate cutting step, the separation distance between the plurality of unit chips is substantially the same during the support film rotation step.

6. The method for manufacturing a laminated electronic component according to claim 1 or 2, wherein the laminate manufacturing step and the laminate cutting step are performed with the support film positioned substantially perpendicular to the ground, and the adhesive tape is positioned substantially horizontally to the ground.

7. A method for manufacturing a laminated electronic component according to claim 1 or 2, further comprising a support film rotation step of rotating the support film between the laminate manufacturing step and the laminate cutting step.

8. The method for manufacturing a stacked electronic component according to claim 1 or 2, wherein the arrangement step is performed by separately separating the unit chips arranged in even columns of the same row from the unit chips arranged in odd columns of the same row and arranging them on the adhesive tape.

9. The method for manufacturing a stacked electronic component according to claim 1 or 2, wherein the arrangement step is performed by simultaneously separating unit chips arranged in one row and placing them on the adhesive tape.

10. The method for manufacturing a stacked electronic component according to claim 9, wherein the arrangement step is performed by pulling an adhesive tape on which the unit chips arranged in one row are arranged in the row direction to separate the unit chips arranged in one row from each other.

11. The method for manufacturing a laminated electronic component according to claim 1 or 2, wherein the first side margin formation step is performed by punching a ceramic green sheet for the side margin to which the first side surface is attached.

12. The method for manufacturing a laminated electronic component according to claim 11, wherein the adhesion and punching are performed with the ceramic green sheet for the side margin portion positioned on the carrier film.

13. The method for manufacturing a laminated electronic component according to claim 12, wherein the thickness of the carrier film is 10 μm or more and 30 μm or less.

14. The method for manufacturing a laminated electronic component according to claim 12, wherein the carrier film is arranged on an elastic pad.

15. The method for manufacturing a laminated electronic component according to claim 12, wherein the surface of the ceramic green sheet for the side margin that is in contact with the first side surface is not coated with an adhesive component.

16. A second side margin forming step in which the second side surface is attached to the ceramic green sheet for the side margin to form the second side margin, A body forming step in which the unit chip on which the first side margin portion and the second side margin portion are formed is fired to form the main body, A method for manufacturing a stacked electronic component according to claim 1 or 2, further comprising the step of forming an external electrode on the main body.

17. The method for manufacturing a laminated electronic component according to claim 16, wherein in the first side margin formation step and the second side margin formation step, the adhesion and punching are performed with the ceramic green sheet for the side margin positioned on the carrier film.

18. When one face of the unit chip in the second direction is designated as the third face, and the other face of the unit chip in the second direction is designated as the fourth face, A method for manufacturing a stacked electronic component according to claim 17, wherein, when d1 is the average value of the vertical distance from the extension line of the third surface of the unit chip to the end adjacent to the third surface at the end of the first side margin portion and the second side margin portion in the second direction, and d2 is the average value of the vertical distance from the extension line of the first side surface of the unit chip to the end of the first side margin portion and the second side margin portion that is in contact with the third surface or the fourth surface, the condition that d1 / d2 is greater than 0.4 and less than 0.8 is satisfied.

19. When one face of the unit chip in the second direction is designated as the third face, and the other face of the unit chip in the second direction is designated as the fourth face, The first side margin portion and the second side margin portion are fired to form the first margin portion and the second margin portion, A method for manufacturing a stacked electronic component according to claim 17, wherein when d1' is the average of the vertical distances from the extension of the third surface of the main body to the ends of the first margin portion and the second margin portion in the second direction, and d2' is the average of the vertical distances from the extension of the first side surface of the main body to the ends of the first margin portion and the second margin portion that are in contact with the third surface or the fourth surface, the condition that d1' / d2' is greater than 0.3 and less than 0.6 is satisfied.

20. The first side margin portion and the second side margin portion are fired to form the first margin portion and the second margin portion, The method for manufacturing a stacked electronic component according to claim 16, wherein the first margin portion and the second margin portion are arranged to surround the main body.

21. The first side margin portion and the second side margin portion are fired to form the first margin portion and the second margin portion, The method for manufacturing a stacked electronic component according to claim 16, wherein the corners of the first margin portion and the second margin portion form a curved surface.

22. The first side margin portion and the second side margin portion are fired to form the first margin portion and the second margin portion, The method for manufacturing a stacked electronic component according to claim 16, wherein the first margin portion and the second margin portion are arranged to cover the corners of the main body.

23. The first side margin portion and the second side margin portion are fired to form the first margin portion and the second margin portion, The method for manufacturing a stacked electronic component according to claim 16, wherein the average thickness of the first margin portion and the second margin portion is 30 μm or less.

24. The process involves a laminate manufacturing stage in which multiple ceramic green sheets, each with a conductive pattern arranged on a support film, are stacked to create a laminate, When the direction in which the plurality of ceramic green sheets are stacked is defined as the first direction with respect to the laminate, the laminate is cut in a second direction perpendicular to the first direction, and in a third direction perpendicular to the first and second directions to obtain a plurality of unit chips, and the laminate is cut such that the unit chip contains a first internal electrode pattern whose cut surface of the conductive pattern is exposed on one face in the second direction of the unit chip, a first side and a second side facing the third direction, and a second internal electrode pattern whose cut surface of the conductive pattern is exposed on the other face in the second direction of the unit chip, a first side and a second side. The arrangement step involves separating the unit chip from the support film without rotating the unit chip, and arranging the unit chip so that its second side surface is in contact with the adhesive tape. The process includes a first side margin forming step of attaching the first side surface to a ceramic green sheet for the side margin to form the first side margin, Manufacturing method for multilayer electronic components.

25. The method for manufacturing a stacked electronic component according to claim 24, wherein the arrangement is configured such that the second side surface of the separated unit chips is in contact with the adhesive tape without rotating them.

26. The method for manufacturing a stacked electronic component according to claim 24, wherein the separation is carried out so that the unit chip is completely separated from the support film.

27. A method for manufacturing a laminated electronic component according to any one of claims 24 to 26, further comprising a support film rotation step of rotating the support film between the laminate cutting step and the arrangement step.

28. The method for manufacturing a laminated electronic component according to claim 27, wherein the laminate manufacturing step and the laminate cutting step are performed with the support film positioned substantially parallel to the ground, and the support film rotation step is performed so that the support film is positioned substantially perpendicular to the ground.

29. The method for manufacturing a laminated electronic component according to claim 27, wherein immediately after the laminate cutting step, the separation distance between the plurality of unit chips is substantially the same during the support film rotation step.

30. The method for manufacturing a laminated electronic component according to any one of claims 24 to 26, wherein the laminate manufacturing step and the laminate cutting step are performed with the support film positioned substantially perpendicular to the ground, and the adhesive tape is positioned substantially horizontally to the ground.

31. A method for manufacturing a laminated electronic component according to any one of claims 24 to 26, further comprising a support film rotation step of rotating the support film between the laminate manufacturing step and the laminate cutting step.

32. The method for manufacturing a stacked electronic component according to any one of claims 24 to 26, wherein the arrangement step is performed by separately separating the unit chips arranged in even columns of the same row and the unit chips arranged in odd columns of the same row and arranging them on the adhesive tape.

33. The method for manufacturing a stacked electronic component according to any one of claims 24 to 26, wherein the arrangement step is performed by simultaneously separating unit chips arranged in one row and placing them on the adhesive tape.

34. The method for manufacturing a stacked electronic component according to claim 33, wherein the arrangement step is performed by pulling the adhesive tape on which the unit chips arranged in one row are arranged in the row direction to separate the unit chips arranged in one row from each other.

35. The method for manufacturing a stacked electronic component according to any one of claims 24 to 26, wherein the first side margin formation step is performed by punching a ceramic green sheet for the side margin to which the first side surface is attached.

36. The method for manufacturing a laminated electronic component according to claim 35, wherein the adhesion and punching are performed with the ceramic green sheet for the side margin portion arranged on the carrier film.

37. The method for manufacturing a laminated electronic component according to claim 35, wherein the surface of the ceramic green sheet for the side margin that is in contact with the first side surface is not coated with an adhesive component.

38. A second side margin forming step, in which the second side surface is attached to and punched on a ceramic green sheet for the side margin to form the second side margin, A body forming step in which the unit chip on which the first side margin portion and the second side margin portion are formed is fired to form the main body, A method for manufacturing a stacked electronic component according to any one of claims 24 to 26, further comprising the step of forming an external electrode on the main body.

39. The method for manufacturing a laminated electronic component according to claim 38, wherein in the first side margin formation step and the second side margin formation step, the adhesion and punching are performed with the ceramic green sheet for the side margin positioned on the carrier film.

Images