Semiconductor device and method of manufacturing the same

Abstract

To provide techniques for suppressing the accumulation of holes in a P-type floating region and improving the switching time of a semiconductor device such as an insulated gate type bipolar transistor.SOLUTION: A semiconductor device includes a trench gate and a trench emitter formed in a semiconductor substrate, and a floating region of a first conductivity type formed in the semiconductor substrate sandwiched between the trench gate and the trench emitter. The bottom of the floating region is located below the bottom of the trench gate and the trench emitter, and the floating region has a crystal defect formation region on the surface side of the floating region.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, and to a technique that is effective when applied to a power semiconductor device such as an insulated gate bipolar transistor (IGBT) having a trench gate and a P-type floating region. [Background technology]

[0002] As an insulated gate bipolar transistor (IGBT), an IE (Injection Enhancement) type IGBT that can utilize the IE effect has been developed. The IE effect is an effect that reduces the on-voltage of the IGBT by increasing the concentration of charges accumulated in the drift region by making it difficult for holes to be discharged when the IGBT is in the on-state. Such IE type IGBTs include a GG type structure, a GGEE type structure, and a GE-S type structure (see JP 2019-029434 A). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-029434 A Summary of the Invention [Problem to be solved by the invention]

[0004] In IE-type IGBTs of GG, GGEE, and GE-S structures, a P-type floating region may be present between the gate trenches (between GG in the GG structure) or between the gate trench and the emitter trench (between GE in the GGEE and GE-S structures). The ease of discharging holes accumulated in the P-type floating region between the GG and GE trenches as well as the drift region also affects the switching time of the IGBT. To further improve the switching characteristics, it is necessary to control the hole accumulation effect on the P-type floating region. A gate trench is a trench region in which an electrode formed in a trench is connected to a gate electrode and functions as a gate electrode. An emitter trench is a trench region in which an electrode formed in a trench is connected to an emitter electrode and functions as an emitter electrode.

[0005] The present disclosure provides a technique for suppressing hole accumulation in a P-type floating region to improve the switching time of a semiconductor device such as an insulated gate bipolar transistor.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A brief summary of representative aspects of this disclosure is as follows.

[0008] A semiconductor device according to one embodiment includes: a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; a first trench and a second trench formed in the semiconductor substrate; a first trench emitter embedded in the first trench via a first gate insulating film; a first trench gate embedded in the second trench via a second gate insulating film; a floating region formed in the semiconductor substrate between the first trench emitter and the first trench gate; and a crystal defect region containing crystal defects, which is locally formed in the floating region at a position close to the first main surface.

[0009] In a cross-sectional view, the floating region is formed to cover a bottom surface of the first trench and a bottom surface of the second trench, In plan view and cross-sectional view, the crystal defect region is provided spaced apart from the first trench and the second trench. Effect of the Invention

[0010] According to the semiconductor device of the above embodiment, hole accumulation in the P-type floating region can be suppressed, and the switching time can be improved. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is an overall plan view of a semiconductor chip according to an embodiment. [Diagram 2] FIG. 2 is a cross-sectional view of a main part of the cell region RR shown in FIG. [Diagram 3] FIG. 3 is a plan view of a main part of the cell region RR in FIG. [Figure 4] FIG. 4 is a flow diagram illustrating a method for manufacturing a p-type floating region according to the embodiment. [Diagram 5] FIG. 5 is a cross-sectional view of a main part according to another configuration example of the cell region RR shown in FIG. [Figure 6] FIG. 6 is a diagram for explaining the configuration of the crystal defect region in FIG. 2 and FIG. [Figure 7] FIG. 7 is a diagram illustrating switching characteristics. [Figure 8] FIG. 8 is a diagram illustrating the evaluation results of crystal defects according to the embodiment. [Figure 9] FIG. 9 is a diagram illustrating a method for manufacturing a semiconductor device according to the embodiment. [Figure 10] FIG. 10 is a diagram illustrating the method of manufacturing the semiconductor device following FIG. [Figure 11] FIG. 11 is a diagram illustrating the method of manufacturing the semiconductor device subsequent to FIG. [Figure 12] FIG. 12 is a diagram for explaining the method of manufacturing the semiconductor device subsequent to FIG. [Figure 13] FIG. 13 is a diagram for explaining the method of manufacturing the semiconductor device subsequent to FIG. [Figure 14] FIG. 14 is a diagram illustrating the method of manufacturing the semiconductor device subsequent to FIG. [Figure 15] FIG. 15 is a diagram for explaining the method of manufacturing the semiconductor device subsequent to FIG. [Figure 16] FIG. 16 is a diagram illustrating the method of manufacturing a semiconductor device subsequent to FIG. [Figure 17] FIG. 17 is a diagram for explaining the method of manufacturing the semiconductor device subsequent to FIG. [Figure 18] FIG. 18 is a diagram illustrating the method of manufacturing a semiconductor device subsequent to FIG. [Figure 19] FIG. 19 is a diagram for explaining the method of manufacturing the semiconductor device subsequent to FIG. [Figure 20] FIG. 20 is a diagram illustrating the method of manufacturing a semiconductor device subsequent to FIG. [Figure 21] FIG. 21 is a diagram for explaining the method of manufacturing the semiconductor device subsequent to FIG. [Figure 22] FIG. 22 is a cross-sectional view of a main part according to another configuration example of the cell region RR shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] In the following embodiments, when necessary for convenience, the description will be divided into a plurality of sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. In addition, in the following embodiments, when the number of elements (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, except when specifically specified or when it is clearly limited to a specific number in principle, and it may be more than or less than the specific number. Furthermore, in the following embodiments, the components (including element steps, etc.) are not essential, except when specifically specified or when it is clearly considered to be essential in principle. Similarly, in the following embodiments, when the shape, positional relationship, etc. of the components, etc. are mentioned, it is considered to include those that are substantially similar to or similar to the shape, etc., except when specifically specified or when it is clearly considered not to be essential in principle. This also applies to the above numerical values ​​and ranges.

[0013] Hereinafter, the embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, the same reference numerals are used for the members having the same functions, and the repeated explanations are omitted. In addition, the drawings may be shown in a schematic manner compared to the actual embodiment in order to clarify the explanation, but they are merely examples and do not limit the interpretation of the present invention. In addition, in the following embodiments, the explanations of the same or similar parts will not be repeated as a rule unless it is particularly necessary.

[0014] Furthermore, in the drawings used in the embodiments, hatching may be omitted in order to make the drawings easier to understand.

[0015] In this specification, the conductivity type of a semiconductor is p-type means that the concentration of holes is higher than the concentration of electrons, and holes are the main charge carriers. Also, p-type semiconductor means a region of a semiconductor containing impurities such as boron or gallium. In this specification, the conductivity type of a semiconductor is n-type means that the concentration of electrons is higher than the concentration of holes, and electrons are the main charge carriers. Also, n-type semiconductor means a region of a semiconductor containing impurities such as phosphorus or arsenic.

[0016] In this specification, the switching operation of the IGBT switching from an off state to an on state is referred to as “turn on,” and the switching operation of the IGBT switching from an on state to an off state is referred to as “turn off.” Note that these switching operations do not occur instantly, but may include multiple steps with a time sequence relationship, including an external circuit to which the IGBT is connected.

[0017] (Embodiment) DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment will now be described in detail with reference to the drawings. A semiconductor device 100 according to the present embodiment has, for example, a semiconductor chip CHP equipped with an IGBT.

[0018] FIG. 1 is a plan view of the entire semiconductor chip CHP according to the present embodiment. As shown in FIG. 1, most of the semiconductor chip CHP of the semiconductor device 100 is covered with an emitter potential electrode EE. A gate potential electrode GE is formed on the outer periphery of the emitter potential electrode EE so as to surround the emitter potential electrode EE. The area surrounded by a dashed line near the center of the emitter potential electrode EE is the emitter pad EP, and the area surrounded by the dashed line of the gate potential electrode GE is the gate pad GP. The upper surface of the semiconductor chip CHP is covered with a protective film PIQ (not shown in FIG. 1), but the protective film PIQ is removed from the upper surfaces of the emitter pad EP and the gate pad GP. External connection terminals such as wire bonding or clips are connected to the emitter pad EP and the gate pad GP, and the semiconductor chip CHP is electrically connected to another chip or a wiring board through the external connection terminals.

[0019] (Configuration example 1 of a semiconductor device including an IE type IGBT: GGEE type structure) Fig. 2 is a cross-sectional view of a main part of the cell region RR shown in Fig. 1. Fig. 3 is a plan view of a main part of the cell region RR in Fig. 1. Fig. 4 is a flow chart for explaining a method for manufacturing a p-type floating region FL according to the embodiment.

[0020] As shown in FIG. 2, the semiconductor device 100 including the IE type IGBT has a GGEE type cell structure. The GGEE type cell structure has a trench gate TG, a trench emitter TE, a p-type base region BL, an n-type emitter region EL, a p-type floating region FL, and an n-type hole barrier region HBL on a first main surface US of a semiconductor substrate SUB. The IE type IGBT 100 further has an n-type drift region DL arranged below the n-type hole barrier region HBL, an n-type field stop layer FSL arranged below the n-type drift region DL, a p-type collector layer CL arranged below the n-type field stop layer FSL, and a collector electrode CE arranged below the p-type collector layer CL. An emitter electrode EE is electrically connected to the p-type base region BL and the n-type emitter region EL through a contact member or plug in a connection hole CH1 formed in an interlayer insulating film IL. The symbol BC is a high-concentration p-type base contact layer formed on the surface of the p-type base region BL. The emitter electrode EE is electrically connected to the p-type base region BL formed between the trench emitters TE and the trench emitter TE via a contact member or plug in a connection hole CH2 formed in the interlayer insulating film IL. An insulating film FPF is formed on the upper side of the emitter electrode EE. The insulating film FPF is a final passivation film made of an organic insulating film whose main component is, for example, polyimide. If the p-type is the first conductive type, the n-type can be said to be the second conductive type opposite to the first conductive type.

[0021] In the p-type floating region FL, a crystal defect region CDR is formed in which crystal defects are locally formed, as indicated by a dotted rectangular line. When the depth of the p-type floating region FL is, for example, about 6 μm, the crystal defect region CDR is provided in a region 0 to 1 μm deep from the surface of the p-type floating region FL. Here, the crystal defect density in the range of 0 to 1 μm deep from the surface is, for example, 1×10 3 pieces / cm 2 When the IGBT is turned off and a reverse bias is applied between the emitter and the drain, the crystal defect density in the region of the p-type floating region FL that is depleted, i.e., the region of the p-type floating region FL that is 3 μm to 6 μm deep from the first main surface US, is approximately the same as the crystal defect density of the semiconductor substrate SUB.

[0022] The IE type IGBT 100 includes a parasitic P-channel MOSFET with the p-type floating region FL as the source region, the p-type base region BL as the drain region, and the trench emitter TE as the gate electrode. The n-type hole barrier region HBL constitutes the channel formation region of the parasitic P-channel MOSFET. The collector electrode CE acts as a backgate of the parasitic P-channel MOSFET via the p-type collector layer CL, the n-type field stop layer FSL, the n-type drift region DL, and the n-type hole barrier region HBL. This parasitic P-channel MOSFET allows holes accumulated in the p-type floating region FL during switching of the IGBT to be discharged to the emitter electrode EE via a short path, thereby shortening the switching time. In addition, since the potential fluctuation of the p-type floating region FL is suppressed, the potential of the trench gate TG is stabilized, and switching loss during switching can be suppressed.

[0023] The configuration of the IE type IGBT 100 will be described below.

[0024] First, the semiconductor substrate SUB is made of single crystal silicon doped with n-type impurities such as phosphorus (P). The impurity concentration of the semiconductor substrate SUB is the same as the impurity concentration of the drift region DL.

[0025] The n-type hole barrier region HBL is formed by introducing an n-type impurity from the front surface US side of the semiconductor substrate SUB. The introduction of the n-type impurity can be exemplified by using, for example, phosphorus as an ion species. The n-type hole barrier region HBL functions as a barrier against holes by preventing holes from reaching the p-type base region BL and being discharged during operation of the IE-type IGBT. The impurity concentration of the n-type hole barrier region HBL is set to be higher than the n-type impurity concentration in the n-type drift region DL and lower than the n-type impurity concentration in the n-type emitter region EL described later.

[0026] The p-type floating region FL is formed by introducing p-type impurities from the front surface US side of the semiconductor substrate SUB. As shown in Fig. 4, the p-type floating region FL can be preferably manufactured by a multi-stage ion implantation method using a first ion implantation step S1, a second ion implantation step S2, and an annealing step S3. The ion implantations in the first ion implantation step S1 and the second ion implantation step S2 are performed on the same region (desired region) of the front surface US of the semiconductor substrate SUB.

[0027] In the first ion implantation step S1, for example, the ion species (ion species of the first conductivity type) is boron (B) and the dose amount is 6.0×10 12 / cm 2 From 1.25 × 10 13 / cm 2 The implantation energy is set to 300 keV to 1.25 MeV.

[0028] In the second ion implantation step S2, for example, the ion species is boron (B) and the dose amount is 1.0×10 13 / cm 2 From 2.75 × 10 13 / cm 2 The implantation energy is set to 300 keV to 1.25 MeV.

[0029] Then, the annealing step S3 is performed after the first ion implantation step S1 and the second ion implantation step S2. The annealing step S3 is, for example, a heat treatment at 900° C. for about 30 seconds. As a result, the ions implanted in the first ion implantation step S1 and the second ion implantation step S2 are activated by the heat treatment, and the p-type floating region FL in which the crystal defect region CDR described above is formed is formed. In addition, since the annealing step S3 can be performed only once, it is possible to reduce costs by eliminating the annealing step.

[0030] If the thickness of the p-type floating region FL is insufficient, the ion-implanted impurity (boron) may be diffused by additional heat treatment. Alternatively, the heat treatment step for diffusing the ion-implanted impurity (boron) may also serve as the annealing step S3.

[0031] The trench gate TG and the trench emitter TE are composed of an n-type impurity doped polycrystalline silicon layer formed so as to be embedded in a trench formed by etching in the first main surface of the semiconductor substrate SUB. The trench gate TG and the trench emitter TE are electrically isolated from the semiconductor layer formed in the semiconductor substrate SUB by a gate insulating film GI. The thickness of the gate insulating film GI is, for example, 0.10 to 0.12 μm.

[0032] The depth of the trench can be, for example, 3.0 to 3.5 μm, and the width of the trench can be, for example, 0.5 to 1.0 μm. The trench is formed in a stripe shape in a plan view, and the trench gate TG and the trench emitter TE are arranged to face each other with the hole barrier region HBL in between. A floating region FL is arranged between the trench gate TG and the trench emitter TE. The thickness (or depth) of the p-type floating region FL can be, for example, 5 to 6 μm, and the bottom portion of the p-type floating region FL is formed to cover the bottom portion of the trench, thereby reducing electric field concentration at the bottom of the trench gate TG.

[0033] The p-type base region BL is formed by introducing a p-type impurity from the front surface US side of the semiconductor substrate SUB. The p-type impurity is, for example, boron. Since the acceleration energy of the ion implantation of the p-type base region BL is set low, the ion implantation damage is small and crystal defects are unlikely to remain.

[0034] The p-type base region BL is formed on the n-type hole barrier region HBL so as to be in contact with one side surface of the trench gate TG via the gate insulating film GI. The p-type base region BL is also formed on the n-type hole barrier region HBL so as to be in contact with one side surface of the trench emitter TE via the gate insulating film GI.

[0035] Moreover, the ion implantation for forming the p-type base region BL may be performed not only on the n-type hole barrier region HBL but also on the p-type floating region FL. In this case, however, only the concentration of the surface of the p-type floating region FL increases, and the function of the p-type floating region FL remains unchanged. Compared with the case where ions are implanted only on the n-type hole barrier region HBL, this has the advantage that a fine mask pattern is not required.

[0036] The n-type emitter region EL is formed by introducing an n-type impurity into the surface of the p-type base region BL. The p-type impurity is, for example, arsenic.

[0037] The interlayer insulating film IL is formed on the first main surface of the semiconductor substrate SUB so as to cover the n-type emitter region EL, the p-type base region BL, and the p-type floating region FL. The interlayer insulating film IL is, for example, a silicon oxide film or a PSG (Phosphorus Silicate Glass) film formed by a CVD method or the like. The thickness of the interlayer insulating film IL is, for example, about 0.6 μm. Suitable examples of materials for this interlayer insulating film IL include a silicon oxide film, a PSG film, a BPSG (Boron Phosphorus Silicate Glass) film, an NSG (Non-doped Silicate Glass) film, an SOG (Spin On Glass) film, and composite films thereof.

[0038] The interlayer insulating film IL has contact holes CH1 and CH2 formed therein. The contact holes CH1 and CH2 can be formed by anisotropic dry etching. By the anisotropic dry etching, a part of the first main surface of the semiconductor substrate SUB exposed from the contact holes CH1 and CH2 is etched, and the contact holes CH1 and CH2 reaching halfway through the p-type base region BL and the trench emitter TE are formed.

[0039] The p-type base contact layer BC can be formed by introducing p-type impurities into the surface of the semiconductor substrate SUB through the contact holes CH1 and CH2. The p-type impurities are, for example, boron.

[0040] The emitter electrode EE is formed on the interlayer insulating film IL including the insides of the contact holes CH1 and CH2. The emitter electrode EE can be formed of an aluminum film by a sputtering method. Alternatively, the emitter electrode EE may be formed as a laminated film, for example, by the following procedure. First, a titanium tungsten film is formed as a barrier metal film on the first main surface of the semiconductor substrate SUB by, for example, a sputtering method. The thickness of the titanium tungsten film is, for example, about 0.2 μm.

[0041] Next, after performing silicide annealing, an aluminum-based metal film is formed on the entire surface of the titanium tungsten film by, for example, sputtering so as to fill the insides of the contact holes CH1 and CH2. The aluminum-based metal film is made of, for example, an aluminum film with a few percent of silicon and / or copper added, and has a thickness of about 5 μm. The aluminum-based metal film filled in the contact holes CH1 and CH2 becomes a contact member or a plug.

[0042] Next, by processing into a predetermined pattern by dry etching using the resist pattern as a mask, an emitter electrode EE made of a laminated film of a titanium tungsten film and an aluminum-based metal film can be formed.

[0043] The emitter electrode EE is electrically connected to each of the n-type emitter region EL, the p-type base contact layer BC, and the trench emitter TE.

[0044] Next, a final passivation film FPF is formed on the emitter electrode EE and the interlayer insulating film IL. The final passivation film FPF is, for example, an organic film whose main component is polyimide, and has a thickness of, for example, about 10 μm. The final passivation film FPF is formed by coating this organic film entirely on the emitter electrode EE and the interlayer insulating film IL, and then opening the emitter pad EP portion and the gate pad GP portion using normal lithography technology.

[0045] After the final passivation film FPF is formed, a backgrinding process is performed on a second main surface (back surface) BS opposite to the first main surface of the semiconductor substrate SUB, thereby thinning the semiconductor substrate SUB. The backgrinding process thins the semiconductor substrate SUB from a thickness of about 800 μm to, for example, 30 μm to 200 μm.

[0046] Next, an n-type field stop layer FSL is formed by selectively introducing an n-type impurity into the second main surface (back surface) BS of the thinned semiconductor substrate SUB by ion implantation. The n-type impurity is, for example, phosphorus.

[0047] Next, a p-type collector layer CL is formed by introducing a p-type impurity into the second main surface (rear surface) BS of the thinned semiconductor substrate SUB by ion implantation. The p-type impurity is, for example, boron. Alternatively, an n-type field stop layer FSL and a p-type collector layer CL may be formed by introducing an n-type impurity and a p-type impurity in sequence and performing laser annealing on the second main surface (rear surface) BS of the semiconductor substrate SUB.

[0048] Next, a collector electrode CE is formed on the surface of the p-type collector layer CL by, for example, a sputtering method. The collector electrode CE can be formed, for example, by a laminated film of an aluminum (Al) layer, a titanium (Ti) layer, a nickel (Ni) layer, a gold (Au) layer, etc., in this order from the second main surface (back surface) BS of the semiconductor substrate SUB. The collector potential electrode CE may be a metal film, such as a titanium nitride film, formed by a sputtering method or a CVD method.

[0049] The above manufacturing process makes it possible to manufacture the IE type IGBT shown in Fig. 2. Here, in order to more specifically illustrate the device structure, an example of the main dimensions of each part of the device will be shown.

[0050] The trench pitch distance between the pair of trench gates TG is 1.8 μm to 2.0 μm, the trench pitch distance between the pair of trench emitters TE is 0.9 μm to 1.1 μm, the width WFL of the p-type floating region FL (see FIG. 6) is 5.5 to 7 μm, and the depth of the p-type floating region FL is 4.5 to 6 μm.

[0051] Fig. 3 is a diagram for explaining a cell formation region, and is a schematic enlarged plan view of a region RR in Fig. 1. Fig. 2 is a schematic cross-sectional view taken along line BB in Fig. 3.

[0052] The cell formation region RR includes an active cell region RCa, a non-active region Ria, and a hole collector cell region RCc. Each of the active cell region RCa, the non-active region Ria, and the hole collector cell region RCc is provided to extend in a stripe shape along the first direction Y. The active cell region RCa, the non-active region Ria, the hole collector cell region RCc, and the non-active region Ria are arranged in this order as one layout unit, and are repeatedly arranged in a second direction X perpendicular to the first direction Y.

[0053] In the active cell region RCa, an active cell Ca is formed. In FIG. 3, a pair of trench gates TG formed in a stripe shape in the first direction Y and an n-type emitter region EL provided between the pair of trench gates TG are illustrated as the active cell Ca. In the hole collector cell region RCc, a hole collector cell Cc is formed. As described in FIG. 2, the hole collector cell Cc is a parasitic P-channel MOSFET having a p-type floating region FL as a source region, a p-type base region BL as a drain region, an n-type hole barrier region HBL as a channel forming region, and a trench emitter TE as a gate electrode. In FIG. 3, a pair of trench emitters TE formed in a stripe shape in the first direction Y and a connecting trench emitter TEa connecting between the pair of trench emitters TE are illustrated as the hole collector cell Cc. In FIG. 3, a p-type floating region FL is illustrated as the inactive region Ria. 2, when the connection hole CH2 is formed so as to contact both of the pair of trench emitters TE, the connection trench emitter TEa may be unnecessary. When the connection hole CH2 is formed so as to contact only one of the pair of trench emitters TE, it is preferable to provide the connection trench emitter TEa. Here, the trench gate TG and the trench emitter TE can be considered to extend in a first direction Y in a plan view and to be adjacent to each other in a second direction X that is perpendicular to (or intersects) the first direction Y in a plan view.

[0054] (Configuration example 2 of a semiconductor device including an IE type IGBT: GE type structure) Fig. 5 is a cross-sectional view of a main part according to another configuration example of the cell region RR shown in Fig. 1. While Fig. 2 shows a cell structure of a GGEE type structure, Fig. 5 is a cross-sectional view explaining a cell structure of a GE type structure (or an EG type structure or a GE-S type structure).

[0055] The cell structure of the GE type structure in FIG. 5 differs from the cell structure of the GGEE type structure in FIG. 2 in that the trench emitter TE and the trench gate TG are paired, and the pair of trench emitters TE and trench gates TG are formed in a plurality of pairs. The emitter electrode EE is electrically connected to each of the n-type emitter region EL, the p-type base contact layer BC, and the trench emitter TE between the pair of trench emitters TE and trench gates TG via a contact member or plug in a connection hole (contact hole) CH3 formed in the interlayer insulating film IL. The other configurations of the cell structure of the GE type structure in FIG. 5 are the same as those of the cell structure of the GGEE type structure in FIG. 2, and therefore the overlapping description will be omitted. The p-type floating region FL and the crystal defect region CDR in FIG. 2 and FIG. 5 are formed by the same manufacturing method and have the same configuration.

[0056] (Configuration example 3 of a semiconductor device including an IE type IGBT: GG type structure) FIG. 22 is a cross-sectional view of a main part according to another configuration example of the cell region RR shown in FIG. 1. FIG. 22 is a cross-sectional view for explaining a cell structure of a GG type structure. The cell structure of the GG type structure of FIG. 22 differs from the cell structure of the GGEE type structure of FIG. 2 in that the EE side portion (a pair of trench emitters TE portion) of the GGEE type structure of FIG. 2 has the same structure (p-type base region BL, n-type emitter region EL, p-type base contact layer BC, and contact hole CH1) as the GG side portion (a pair of trench gates TG portion) of the GGEE type structure of FIG. 2. The other configurations of the cell structure of the GG type structure of FIG. 22 are the same as those of the cell structure of the GGEE type structure of FIG. 2, and the overlapping description will be omitted. The p-type floating region FL and the crystal defect region CDR of FIG. 2, FIG. 5, and FIG. 22 are formed by the same manufacturing method and have the same configuration.

[0057] (Example of the configuration of crystal defect region CDR) Fig. 6 is a diagram for explaining the configuration of the crystal defect region CDR in Fig. 2 and Fig. 5. Fig. 6 shows a cross-sectional view between the trench gate TG and the trench emitter TE in the cell structure of the GGEE type structure in Fig. 2 or the cell structure of the GE type structure in Fig. 5, and a graph of the crystal defect density in the depth direction and the lateral direction of the crystal defect region CDR formed in the p-type floating region FL. Here, an example will be described in which the depth of the p-type floating region FL is, for example, about 6 μm. A crystal defect region CDR in which crystal defects are selectively formed is provided in a region of 0 to 1 μm in the depth direction from the surface of the p-type floating region FL.

[0058] 6, for example, depth 0 indicates the upper end of the p-type floating region FL or the upper end of the crystal defect region CDR, depth d1 indicates the lower end of the crystal defect region CDR, depth d2 indicates the upper end (or upper part) of the depletion layer DEP in the off state (at rated voltage, or more preferably, in the avalanche state), and depth d3 indicates the lower end of the p-type floating region FL. The area below depth d3 is the drift region DL.

[0059] The depletion layer DEP expands as the voltage applied to the collector increases, but even if the avalanche state is not reached, there is no problem in terms of leakage as long as the crystal defect region CDR does not enter the depletion layer DEP when the rated voltage is applied.

[0060] The bottom of the p-type floating region FL is located below the bottom of the trench gate and the trench emitter. The p-type floating region FL has a crystal defect region CDR on the surface side of the p-type floating region FL. The crystal defect region CDR is provided on the surface side of the p-type floating region FL between the surface (0) of the p-type floating region FL and the upper end (d2) of the depletion layer DEP. The crystal defect region CDR is formed between the surface of the p-type floating region FL and the upper part of the depletion layer DEP, in a region where the depletion layer DEP is not formed. By configuring the crystal defect region CDR to exist in a region not included in the depletion layer DEP even when the device is off, deterioration of electrical characteristics such as an increase in leakage current when the device is off can be suppressed.

[0061] The crystal defect density CDD1 in the depth direction (dp) of the crystal defect region CDR has the following characteristics. (1) The crystal defect density is relatively high in the upper part of the p-type floating region FL, for example, within a range of 0 to 1 μm from the surface to a depth d1 (for example, 1 μm) (i.e., within a range of 0 to 1 μm, the crystal defect density is maximum), and in regions of the p-type floating region FL deeper than the depth d1 (1 μm), the crystal defect density is reduced. (2) The density of crystal defects within a range of 0 to 1 μm from the surface of the p-type floating region FL is, for example, 1×10 3 pieces / cm 2 The following is the result. (3) In the p-type floating region FL, a region having a depth that becomes a depletion layer DEP when a gate voltage is applied (during avalanche) when the IGBT is turned off, for example, a region having a depth in the range of approximately d2 (e.g., 3 μm) to d3 (e.g., 6 μm), has a relatively low defect density that is approximately the same as the defect density of the original semiconductor crystal substrate.

[0062] The crystal defect density CDD2 in the lateral direction (wd) of the crystal defect region CDR has the following characteristics. (4) Crystal defects are formed (that is, the lateral width of the formation region of the crystal defect region CDR) only within the formation width WFL of the p-type floating region FL. (5) The crystal defect region CDR is formed so as not to contact the trenches (TE, TG) or penetrate the gate insulating film GI. In other words, it is preferable that there are no crystal defects on the side surfaces of the trenches (TE, TG) or on the gate insulating film GI. This configuration makes it possible to suppress deterioration of electrical characteristics such as a decrease in the reliability of the gate insulating film GI. As the number of crystal defects increases, the possibility that the crystal defects will penetrate the gate insulating film GI increases, so the crystal defect density is 1×10 3 (pcs / cm 2 It is preferable to keep it below that. (6) The crystal defect region CDR is provided apart from the trench gate TG and the trench emitter TE without contacting them. The distance w1 between the trench (TE, TG) and the crystal defect region CDR is, for example, 0.1 μm to 0.3 μm, and more preferably, about 0.2 μm.

[0063] (Explanation of the improvement in switching characteristics: Effect of crystal defect region CDR) Fig. 7 is a diagram for explaining switching characteristics. Fig. 7(A) shows the state of holes (holes h) when starting to apply a gate bias to the gate electrode of the IGBT from the OFF state in the case where the crystal defect region CDR is not formed. With the application of the gate bias, the potential in the p-type floating region FL rises and holes h are induced, but since a high voltage is applied to the collector, the parasitic P-channel MOSFET, which has the p-type floating region FL as the source region, the p-type base region BL as the drain region, and the trench emitter TE as the gate electrode, is in the OFF state due to the substrate bias effect, so the induced holes h cannot escape and are accumulated in the p-type floating region FL.

[0064] FIG. 7B1 shows the state of holes (holes h) when a gate bias starts to be applied to the gate electrode of an IGBT when a crystal defect region CDR is formed, and some of the accumulated holes h are captured by crystal defects (recombination centers).

[0065] 7B2 shows the state of holes (holes h) after the IGBT is turned off and the collector voltage drops when the crystal defect region CDR is formed. A parasitic P-channel MOSFET, which has the p-type floating region FL as the source region, the p-type base region BL as the drain region, and the trench emitter TE as the gate electrode, starts to operate and begins to discharge holes h.

[0066] In other words, immediately after the gate bias is applied (before the turn-off progresses and the collector voltage drops), the holes h cannot be discharged in the parasitic P-channel MOSFET, and so the holes h accumulate in the p-type floating region FL. The crystal defects in the crystal defect region CDR are used as a site for the recombination of the holes h. After that, the bias applied to the NW (n-type hole barrier region HBL) gradually weakens, and the parasitic P-channel MOSFET begins to operate. As a result, the holes h are discharged from near the trench emitter TE to the emitter electrode EE.

[0067] In the cell structure of the GG type structure in Figure 22, since there is no parasitic P-channel MOSFET, holes h cannot be actively discharged to the emitter electrode EE side, and it is necessary to wait for holes h to be released by diffusion. However, since the crystal defects in the crystal defect region CDR are also used in this structure, it is possible to reduce the effect of the accumulation of holes h. In addition, although the switching speed of the GG type structure shown in Figure 22 is inferior to that of the GGEE structure shown in Figure 21, holes h do not escape from the pair of trench emitter TE parts, and holes h can be efficiently accumulated in the drift region, so that V CE(sat) In addition, since the density of the trench gate TG is high, there is an advantage that the saturation current in the on-state can be increased.

[0068] The ease of discharging holes (h) accumulated in the p-type floating region FL between the trench gate TG and the trench emitter TE affects the switching time of the IGBT. To further improve the switching characteristics, it is necessary to suppress the hole accumulation effect in the p-type floating region FL. The hole accumulation effect is suppressed by utilizing crystal defects in the crystal defect region CDR. This makes it possible to improve the ease of discharging holes (h) accumulated in the p-type floating region FL. As a result, the turn-on characteristics are improved, and the switching speed of the IGBT can be increased.

[0069] On the other hand, in the on state, holes are accumulated in the drift region. However, if there are more recombination centers than necessary in the p-type floating region FL, the holes that should be accumulated in the drift region will diffuse into the p-type floating region FL according to the concentration gradient and recombine at the recombination centers. This reduces the hole accumulation effect in the drift region, and V CE(sat) From this viewpoint, the density of crystal defects in the p-type floating region FL is at most 1×10 3 (pcs / cm 2 It is preferable to keep it to about .

[0070] (Explanation of crystal defect evaluation results) FIG. 8 is a diagram for explaining the evaluation results of crystal defects according to the embodiment. Specifically, FIG. 8 shows the evaluation results of crystal defects in the depth direction of the p-type floating region FL. The p-type floating region FL is formed by the manufacturing method described in FIG. 4. Here, the evaluation method of the crystal defects uses the "Standard according to the Japanese Industrial Standards (JIS H 0609)". In "JIS H 0609", JIS-G liquid is used as an etching liquid. The JIS-G liquid has a composition of 126 ml of water, 254 ml of 70% nitric acid, and 20 ml of 50% hydrofluoric acid. The etching rate of Si by the JIS-G liquid is about 1 μm / min.

[0071] In the crystal defect evaluation result Evr shown in Figure 8, the p-type floating region FL is etched using JIS-G liquid to check for crystal defects. The approximate etching amount (etching depth: depth ds from the semiconductor substrate surface) is calculated from the Si etching rate using JIS-G liquid and the cumulative etching time Tte. In the crystal defect evaluation result Evr, if there are crystal defects, they are observed as diagonal black streaks. The observed black streaks are the total number of crystal defects that exist from the surface to the etching depth in question, so by repeating etching and observation, the depth at which the crystal defects have occurred can be estimated.

[0072] In the example of the evaluation result Evr in FIG. 8, the evaluation result Evr of crystal defects is shown for three cumulative etching times Tte: 1 min (depth ds from the semiconductor substrate surface: about 1 μm), 2 min (depth ds from the semiconductor substrate surface: about 2 μm), and 3 min (depth ds from the semiconductor substrate surface: about 3 μm). (1) The evaluation result Evr for the cumulative etching time Tte of 1 min shows that a small amount of crystal defects are formed within about 1 μm from the surface. (2) The evaluation result Evr for the cumulative etching time Tte of 2 min shows that no new crystal defects are formed within about 1 μm to 2 μm. (3) The evaluation result Evr for the cumulative etching time Tte of 3 min shows that no new crystal defects are formed within 2 μm to 3 μm.

[0073] Since no new crystal defect formation was observed after 3 min, it suggests that crystal defects were selectively formed only in the shallow region of the p-type floating region FL. Calculations based on the evaluation results with a cumulative etching time of 1 min showed that the crystal defect density (CCD1) was 1×10 2 ~1×10 3 (pcs / cm 2 ) was confirmed. That is, it was found that in the p-type floating region FL formed by the manufacturing method described in Fig. 4, crystal defects (crystal defect region CDR) can be selectively formed in a shallow region (region 0 to 1 µm from the surface) of the p-type floating region FL. This makes it possible to obtain the effects described above.

[0074] (Method of manufacturing a semiconductor device including an IE type IGBT) Next, a method for manufacturing a semiconductor device including an IE type IGBT will be described with reference to Fig. 9 to Fig. 21. Here, as an example, a method for manufacturing an IE type IGBT having the cell structure of the GGEE type structure described in Fig. 2 will be described.

[0075] As shown in Fig. 9, an n-type drift region DL is formed in a semiconductor substrate SUB. The drift region DL is formed by preparing a semiconductor substrate SUB into which an n-type impurity has been introduced in advance and using the n-type semiconductor substrate SUB as the n-type drift region DL, or by preparing a p-type semiconductor substrate SUB and forming the n-type drift region DL on the p-type semiconductor substrate SUB by an epitaxial method. Note that in this embodiment, the drift region DL may also be described as the semiconductor substrate SUB.

[0076] Next, as shown in Fig. 10, an n-type hole barrier region HBL is formed on the surface of the drift region DL by photolithography and ion implantation. The hole barrier region HBL has a higher impurity concentration than the drift region DL. The impurity for forming the hole barrier region HBL is, for example, phosphorus (P), and this ion implantation may be performed multiple times.

[0077] Next, as shown in FIG. 11, photolithography and ion implantation are used to implant boron (B) ions into the surface of the drift region DL to form a p-type floating region FL. A mask MK1 is selectively formed in a desired region of the surface US of the semiconductor substrate SUB. The mask MK1 is selectively formed on the surface US of the semiconductor substrate SUB so as to cover the region where the hole barrier region HBL is to be formed and both sides thereof, and so as to perform ion implantation into the region where the p-type floating region FL is to be formed. The ion implantation for forming the p-type floating region FL is carried out by introducing boron (B) into the inside of the drift region DL from the surface US side of the semiconductor substrate SUB in two separate steps using the first ion implantation step S1 and the second ion implantation step S2 described in FIG. 4. Here, in the first ion implantation step S1, for example, the ion species is boron (B) and the dose amount is 6.0×10 12 / cm 2 From 1.25 × 10 13 / cm 2 The second ion implantation step S2 is performed with an ion species of boron (B) and a dose of 1.0×10 13 / cm 2 From 2.75 × 10 13 / cm 2 The implantation energy is set to 300 keV to 1.25 MeV.

[0078] Next, as shown in Fig. 12, the annealing step described in Fig. 4 is performed to form a p-type floating region FL. Here, a crystal defect region CDR is formed on the front surface US side of the p-type floating region FL.

[0079] If the thickness of the p-type floating region FL (the depth at which the bottom exists) is insufficient, boron may be diffused by an additional heat treatment thereafter (not necessarily immediately after). Also, the above-mentioned annealing may not be performed in this process, and the heat treatment for diffusing boron may serve as the above-mentioned annealing.

[0080] 13, an insulating film such as a silicon oxide film is formed on the semiconductor substrate SUB by, for example, a CVD (Chemical Vapor Deposition) method, and the insulating film is patterned by photolithography and dry etching to form a mask MK2. The mask MK2 is used as a mask for forming a first trench T1 (a trench for TG) and a second trench T2 (a trench for TE) in the semiconductor substrate SUB, and is therefore selectively formed on the surface of the semiconductor substrate SUB so that the formation regions of the first trench T1 and the second trench T2 on the surface of the semiconductor substrate SUB are exposed.

[0081] Next, as shown in Fig. 14, a trench formation process is performed. The semiconductor substrate SUB is etched using the patterned mask MK2 as a hard mask to form a first trench T1 and a second trench T2 in the semiconductor substrate SUB. Thereafter, the mask MK2 is removed by a wet etching process or the like.

[0082] Here, if necessary, a heat treatment may be performed to diffuse boron so that the thickness of the p-type floating region FL is set to a desired value. By performing the diffusion after the trench formation process, the diffusion process can be used even when the gap between the pair of trenches is narrow and it is difficult to form the p-type floating region FL in the gap.

[0083] The heat treatment for diffusing boron does not necessarily have to follow this process flow, and the above-mentioned advantages can be obtained as long as it is performed after the trench formation process. For example, the heat treatment may be performed after forming the conductive film FG inside the first trench T1 and the second trench T2, or may be performed separately in both processes. In this way, if there are other heat treatment processes such as sacrificial oxidation for removing damage in the trench formation process and heat treatment for incorporating a gate protection diode (not specifically described in this specification), they can be combined, and the number of processes can be reduced.

[0084] 15, a thermal oxidation process is performed on the semiconductor substrate SUB to form an insulating film, for example, a silicon oxide film, on the inner walls of the trenches T1 and T2, the upper surface of the floating region FL, and the upper surface of the hole barrier region HBL. The insulating film formed on the inner walls of the trenches T1 and T2 is a gate insulating film GI. The thickness of the gate insulating film GI is, for example, 100 nm.

[0085] 16, a conductive film FG made of, for example, a polycrystalline silicon film doped with n-type impurities is formed by, for example, a CVD method so as to fill the insides of trenches T1 and T2. The conductive film FG inside trench T1 becomes a gate potential electrode (also called a first electrode) of trench gate TG. The conductive film FG inside trench T2 becomes an emitter potential electrode (also called a second electrode) of trench emitter TE. Next, as shown in FIG. 17, a process for forming a base region (also called a channel region) BL and an emitter region (also called a source region) EL is performed. First, a process for forming the base region BL is performed. After removing or thinning the gate insulating film GI exposed on the surface of the semiconductor substrate SUB by, for example, dry etching or wet etching as appropriate, a p-type base region BL is formed on each surface of the floating region FL and the hole barrier region HBL by using photolithography and ion implantation. The base region BL is an impurity region having a higher impurity concentration than the floating region FL. The impurity for forming the base region BL is, for example, boron (B).

[0086] Next, a process of forming an emitter region EL is performed. By using a photolithography method and an ion implantation method, an n-type emitter region EL is formed on the surface of the base region BL of the active cell region. The emitter region EL is an impurity region having a higher impurity concentration than the hole barrier region HBL. At this time, the emitter region EL is not formed in the base region BL of the hole collector cell region. The impurity for forming the emitter region EL is, for example, arsenic (As).

[0087] 18, a step of forming an interlayer insulating film IL is performed. First, an interlayer insulating film IL such as a silicon oxide film is formed by, for example, a CVD method on the insulating film on the upper surface of the floating region FL, the insulating film on the upper surface of the hole barrier region HBL, and the trench gate TG and trench emitter TE.

[0088] Next, as shown in FIG. 19, the steps of forming the contact hole (connection hole) CH1, the contact hole (connection hole) CH2, and the base contact layer BC are performed.

[0089] By using a photolithography method and a dry etching process (e.g., anisotropic dry etching), a contact hole CH1 is formed in the active cell region, penetrating the interlayer insulating film IL and the emitter region EL and reaching the base region BL. Also, in the hole collector cell region, a contact hole CH2 is formed, penetrating the interlayer insulating film IL and including a recess recessed from the first main surface US toward the second main surface (back surface) BS of the semiconductor substrate, so as to straddle the trench emitter TE and the base region BL.

[0090] Next, a p-type base contact layer BC is formed in the base region BL below each of the contact holes CH1 and CH2 by using photolithography and ion implantation. The base contact layer BC is an impurity region having a higher impurity concentration than the base region BL. The base contact layer BC in the active cell region is formed so as not to contact the n-type emitter region EL. The impurity for forming the base contact layer BC is, for example, boron, and then a heat treatment is performed to activate each impurity region. Note that, if necessary, a heat treatment may be performed after (not necessarily immediately after) some or all of the ion implantation steps to activate each impurity region and diffuse it to a predetermined depth.

[0091] Next, as shown in FIG. 20, a process of forming an emitter potential electrode EE and a final passivation film FPF is carried out.

[0092] First, for example, an aluminum film is formed on the insulating film IL by, for example, a sputtering method so as to fill the contact holes CH1 and CH2. The aluminum film filled in each of the contact holes CH1 and CH2 becomes a contact member. Thereafter, the aluminum film is patterned using a photolithography method and a dry etching process to form the emitter potential electrode EE. At the same time, the gate potential electrode GE shown in FIG. 1 is also formed by patterning the aluminum film. In addition, before the formation of the aluminum film, a barrier metal film made of, for example, a titanium nitride film or a titanium tungsten film may be formed, and the aluminum film may be formed on the barrier metal film. That is, the emitter potential electrode EE may be a laminated film of a barrier metal film and an aluminum film.

[0093] Next, a process for forming a final passivation film FPF is performed. The final passivation film FPF is formed on the upper side of the emitter electrode EE and on the upper side of the interlayer insulating film IL. The final passivation film FPF is, for example, an organic film whose main component is polyimide, and has a thickness of, for example, about 10 μm. The final passivation film FPF is formed by applying this organic film to the entire upper side of the emitter electrode EE and the upper side of the interlayer insulating film IL, and opening the emitter pad EP portion and the gate pad GP portion by normal lithography.

[0094] Next, as shown in FIG. 21, a field stop layer FSL, a collector layer CL, and a collector potential electrode CE are formed on the second main surface (rear surface) BS side of the semiconductor substrate SUB.

[0095] First, if necessary, a polishing process is performed on the second main surface (rear surface) of the semiconductor substrate SUB to reduce the thickness of the semiconductor substrate SUB. Next, ion implantation is performed from the second main surface (rear surface) side of the semiconductor substrate SUB. By this ion implantation, an n-type field stop region FSL and a p-type collector region CL are formed. The field stop region FSL is an impurity region having a higher impurity concentration than the drift region DL. The impurity for forming the field stop region FSL is, for example, phosphorus (P). The impurity for forming the collector region PC is, for example, boron (B).

[0096] Next, a collector potential electrode CE made of a laminated film of, for example, an aluminum (Al) layer, a titanium (Ti) layer, a nickel (Ni) layer, and a gold (Au) layer, etc., is formed on the surface of the collector region CL exposed on the second main surface (rear surface) of the semiconductor substrate SUB, for example by a sputtering method or a CVD method.

[0097] The invention made by the inventor has been specifically described above based on examples. However, it goes without saying that the present invention is not limited to the above-mentioned embodiments and examples, and various modifications are possible. [Explanation of symbols]

[0098] 100 Semiconductor device CHP Semiconductor Chip FL Floating Area TG Trench Gate TE Trench Emitter CDR Crystal Defect Region CE Collector potential electrode CH1, CH2 contact holes EE Emitter potential electrode EP Emitter Pad GE Gate potential electrode GI Gate Insulator GP Gate Pad IL insulating film EL Emitter Area HBL Hole Barrier Region FSL Field Stop Layer DL Drift Region BL Base Region CL Collector Layer BC Base contact layer SUB Semiconductor Substrate

Claims

1. A semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, A first trench and a second trench formed in the semiconductor substrate, A first trench emitter is embedded in the first trench via a first gate insulating film, The second trench is embedded with a first trench gate via a second gate insulating film, A floating region formed on the semiconductor substrate between the first trench emitter and the first trench gate, The floating region includes a crystal defect region containing crystal defects, which is locally formed near the first main surface within the floating region. In a cross-sectional view, the floating region is formed to cover the bottom surface of the first trench and the bottom surface of the second trench. A semiconductor device in which, in a plan view and a cross-sectional view, the crystal defect region is provided spaced apart from the first trench and the second trench.

2. The semiconductor device according to claim 1, wherein the crystal defect region is located within the floating region and is not in contact with the first trench and the second trench.

3. In a plan view, the third trench formed in the semiconductor substrate is in the direction opposite to the direction in which the second trench of the first trench was formed, A second trench emitter is embedded in the third trench via a third gate insulating film, A first base region formed on the first main surface between the first trench emitter and the second trench emitter, An interlayer insulating film formed on the first main surface so as to cover the first trench emitter, the second trench emitter, the first trench gate, the first base region, and the crystal defect region, A first contact member that penetrates the interlayer insulating film and reaches the first main surface, An emitter electrode formed on the interlayer insulating film, Furthermore, The semiconductor device according to claim 1, wherein the first contact member is connected to the first trench emitter, the second trench emitter, the first base region, and the emitter electrode.

4. The semiconductor device according to claim 1, wherein the location where the density of crystal defects is maximum within the crystal defect region is located near the first main surface.

5. The maximum density of the aforementioned crystal defects is 10 ３ pieces / cm 2 The semiconductor device according to claim 1, wherein the semiconductor device is as follows:

6. The semiconductor device according to claim 1, wherein, in a plan view, the first trench emitter and the first trench gate extend in a first direction and are arranged side by side in a second direction intersecting the first direction.

7. A contact hole that penetrates the interlayer insulating film and reaches the first main surface, Within the contact hole, a recess is further formed extending from the first main surface to the second main surface, and in a plan view, is formed to span the first trench emitter, the first base region, and the second trench emitter. The semiconductor device according to claim 3, wherein the first contact member is formed by being embedded in the contact hole and the recess.

8. In a plan view, the fourth trench formed in the semiconductor substrate is in the direction opposite to the direction in which the first trench was formed in the second trench, The fourth trench is embedded with a second trench gate via a fourth gate insulating film, A second base region formed on the semiconductor substrate between the first trench gate and the second trench gate, An emitter region formed on the first main surface of the second base region, A second contact member penetrates the interlayer insulating film and reaches the first main surface, Furthermore, The semiconductor device according to claim 3, wherein the second contact member connects to the second base region and the emitter region.

9. A gate electrode formed on the first main surface and electrically connected to the first trench gate and the second trench gate, The device further comprises a collector electrode formed on the second main surface, The emitter electrode is electrically connected to the first trench emitter, the second trench emitter, the first base region, the second base region, and the emitter region. The semiconductor device according to claim 8, wherein the emitter electrode, the gate electrode, and the collector electrode constitute an IGBT.

10. The semiconductor device according to claim 9, wherein the crystal defect region is formed in a region where the floating region does not become depleted when the IGBT is in the off state.

11. (a) A step of forming a first hole barrier region of a second conductivity type and a second hole barrier region of the second conductivity type on a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface. (b) A step of forming a floating region of the first conductivity type opposite to the second conductivity type on the semiconductor substrate between the first hole barrier region and the second hole barrier region, (c) A step of forming a crystal defect region containing crystal defects, which is locally formed in the floating region near the first main surface, (d) A step of forming a first trench and a second trench that are formed so as to sandwich the floating region in a plan view, (e) After step (d), a step of forming a first gate insulating film and a second gate insulating film on the side surface of the first trench and the side surface of the second trench, respectively. (f) After step (e), a first trench emitter is formed in the first trench via the first gate insulating film, and a first trench gate is formed in the second trench via the second gate insulating film, In a cross-sectional view, the floating region is formed to cover the bottom surface of the first trench and the bottom surface of the second trench. A method for manufacturing a semiconductor device, wherein, in a plan view and a cross-sectional view, the crystal defect region is provided spaced apart from the first trench and the second trench.

12. The method for manufacturing a semiconductor device according to claim 11, wherein the crystal defect region is located within the floating region and is not in contact with the first trench and the second trench.

13. (g) After step (f), a step of forming the first base region of the second conductivity type on the first main surface on the first hole barrier region, (h) After step (g), a step of forming an interlayer insulating film formed on the first main surface so as to cover the first trench emitter, the first trench gate, and the crystal defect region, (i) After step (h), a step of forming a first contact hole that penetrates the interlayer insulating film on the first base region and reaches the first main surface, (j) After step (i), a step of forming a first contact member in the first contact hole, (k) The step of forming an emitter electrode on the interlayer insulating film after step (j) is further included, In step (d) above, a third trench is further formed so as to sandwich the first hole barrier region with the first trench in a plan view. In step (e) above, a third gate insulating film is further formed on the side surface of the third trench, In step (f) above, a second trench emitter is further formed in the third trench via the third gate insulating film, The method for manufacturing a semiconductor device according to claim 11, wherein the first contact member is connected to the first trench emitter, the first base region, the second trench emitter, and the emitter electrode.

14. In step (d) above, a fourth trench is further formed so as to sandwich the second hole barrier region with the second trench, In step (e) above, a fourth gate insulating film is further formed in the fourth trench, In step (f) above, a second trench gate is further formed in the fourth trench via the fourth gate insulating film, In step (g) above, a second base region of the second conductivity type is further formed on the first main surface on the second hole barrier region, In step (i) above, a second opening is further formed that penetrates the interlayer insulating film on the second base region and reaches the first main surface, In step (j) above, a second contact member is further formed in the second opening, In step (h) above, the interlayer insulating film is further formed on the first main surface so as to cover the second trench gate, (l) After step (g) and before step (h), a step of forming an emitter region of a first conductivity type on the first main surface on the second base region, further comprising The method for manufacturing a semiconductor device according to claim 13, wherein the second contact member is connected to the second base region, the emitter region, and the emitter electrode.

15. The above step (i) is, (i1) The first contact hole further comprises a recess formed in the semiconductor substrate from the first main surface toward the second main surface, which, in a plan view, spans the first trench emitter, the first base region, and the second trench emitter. The method for manufacturing a semiconductor device according to claim 13, wherein the first contact member is formed by being embedded in the first contact hole and the recess.

16. In step (b) above, the ionic species is boron, and the dose is 6.0 × 10 １２ / cm 2 from 1.25 × 10 １３ / cm 2 The implantation is performed by ion implantation, with an implantation energy ranging from 300 keV to 1.25 MeV. The above step (c) is, (c1) The ion species is boron, and the dose amount is 1.0×10 １３ / cm 2 to 2.75×10 １３ / cm 2 and the implantation energy is from 300 keV to 1.25 MeV, an ion implantation step, and (c2) A method for manufacturing a semiconductor device according to claim 11, comprising an annealing step in which the processing temperature is 900°C.

17. The method for manufacturing a semiconductor device according to claim 11, wherein the location where the density of crystal defects is maximum within the crystal defect region is located on the first main surface side in the direction from the first main surface toward the second main surface.

18. The density of crystal defects in the crystal defect region is 10 ３ pieces / cm 2 The method for manufacturing a semiconductor device according to claim 11, which is as follows:

19. The method for manufacturing a semiconductor device according to claim 14, wherein, in a plan view, the first trench emitter, the second trench emitter, the first trench gate, and the second trench gate extend in a first direction and are arranged side by side in a second direction intersecting the first direction.

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